Searched refs:ROR (Results 1 - 25 of 90) sorted by relevance

1234

/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-operand-rn-ror-amount-t32.cc102 {{al, r0, r0, ROR, 0}, false, al, "al r0 r0 ROR 0", "al_r0_r0_ROR_0"},
103 {{al, r0, r0, ROR, 8}, false, al, "al r0 r0 ROR 8", "al_r0_r0_ROR_8"},
104 {{al, r0, r0, ROR, 16}, false, al, "al r0 r0 ROR 16", "al_r0_r0_ROR_16"},
105 {{al, r0, r0, ROR, 24}, false, al, "al r0 r0 ROR 24", "al_r0_r0_ROR_24"},
106 {{al, r0, r1, ROR, 0}, false, al, "al r0 r1 ROR
[all...]
H A Dtest-assembler-cond-rd-operand-rn-ror-amount-a32.cc102 {{vc, r2, r5, ROR, 0}, false, al, "vc r2 r5 ROR 0", "vc_r2_r5_ROR_0"},
103 {{eq, r5, r7, ROR, 0}, false, al, "eq r5 r7 ROR 0", "eq_r5_r7_ROR_0"},
104 {{ge, r3, r2, ROR, 8}, false, al, "ge r3 r2 ROR 8", "ge_r3_r2_ROR_8"},
105 {{cc, r11, r3, ROR, 16}, false, al, "cc r11 r3 ROR 16", "cc_r11_r3_ROR_16"},
106 {{cs, r13, r6, ROR, 0}, false, al, "cs r13 r6 ROR
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc102 const TestData kTests[] = {{{ls, r3, r3, r13, ROR, 0},
105 "ls r3 r3 r13 ROR 0",
107 {{cs, r2, r7, r1, ROR, 16},
110 "cs r2 r7 r1 ROR 16",
112 {{mi, r13, r0, r2, ROR, 8},
115 "mi r13 r0 r2 ROR 8",
117 {{lt, r0, r6, r1, ROR, 8},
120 "lt r0 r6 r1 ROR 8",
122 {{al, r6, r4, r8, ROR, 16},
125 "al r6 r4 r8 ROR 1
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc102 const TestData kTests[] = {{{al, r4, r0, r8, ROR, 16},
105 "al r4 r0 r8 ROR 16",
107 {{al, r14, r13, r12, ROR, 24},
110 "al r14 r13 r12 ROR 24",
112 {{al, r9, r10, r5, ROR, 16},
115 "al r9 r10 r5 ROR 16",
117 {{al, r11, r13, r14, ROR, 8},
120 "al r11 r13 r14 ROR 8",
122 {{al, r3, r12, r11, ROR, 16},
125 "al r3 r12 r11 ROR 1
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc121 {{al, r7, r8, r10, ROR, 21},
124 "al r7 r8 r10 ROR 21",
126 {{al, r5, r5, r3, ROR, 12},
129 "al r5 r5 r3 ROR 12",
136 {{al, r9, r10, r11, ROR, 2},
139 "al r9 r10 r11 ROR 2",
151 {{al, r2, r11, r1, ROR, 9},
154 "al r2 r11 r1 ROR 9",
161 {{al, r6, r13, r3, ROR, 1},
164 "al r6 r13 r3 ROR
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc136 {{cc, r10, r5, r1, ROR, 10},
139 "cc r10 r5 r1 ROR 10",
141 {{ge, r3, r14, r7, ROR, 7},
144 "ge r3 r14 r7 ROR 7",
171 {{cs, r12, r3, r0, ROR, 20},
174 "cs r12 r3 r0 ROR 20",
176 {{vs, r1, r6, r9, ROR, 14},
179 "vs r1 r6 r9 ROR 14",
186 {{vc, r14, r13, r10, ROR, 7},
189 "vc r14 r13 r10 ROR
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc104 {{vc, r5, r5, ROR, 10}, false, al, "vc r5 r5 ROR 10", "vc_r5_r5_ROR_10"},
105 {{ne, r3, r4, ROR, 17}, false, al, "ne r3 r4 ROR 17", "ne_r3_r4_ROR_17"},
106 {{cs, r9, r10, ROR, 16}, false, al, "cs r9 r10 ROR 16", "cs_r9_r10_ROR_16"},
107 {{lt, r0, r2, ROR, 29}, false, al, "lt r0 r2 ROR 29", "lt_r0_r2_ROR_29"},
108 {{al, r11, r2, ROR, 23}, false, al, "al r11 r2 ROR 2
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc104 {{al, r14, r8, ROR, 21}, false, al, "al r14 r8 ROR 21", "al_r14_r8_ROR_21"},
105 {{al, r5, r13, ROR, 4}, false, al, "al r5 r13 ROR 4", "al_r5_r13_ROR_4"},
106 {{al, r0, r3, ROR, 4}, false, al, "al r0 r3 ROR 4", "al_r0_r3_ROR_4"},
107 {{al, r3, r14, ROR, 7}, false, al, "al r3 r14 ROR 7", "al_r3_r14_ROR_7"},
111 {{al, r0, r9, ROR, 17}, false, al, "al r0 r9 ROR 1
[all...]
H A Dtest-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc602 {{al, r0, r2, plus, r14, ROR, 9, Offset},
605 "al r0 r2 plus r14 ROR 9 Offset",
617 {{al, r0, r4, plus, r12, ROR, 13, Offset},
620 "al r0 r4 plus r12 ROR 13 Offset",
627 {{al, r0, r7, plus, r0, ROR, 25, Offset},
630 "al r0 r7 plus r0 ROR 25 Offset",
647 {{al, r0, r7, plus, r12, ROR, 11, Offset},
650 "al r0 r7 plus r12 ROR 11 Offset",
677 {{al, r0, r8, minus, r7, ROR, 30, Offset},
680 "al r0 r8 minus r7 ROR 3
[all...]
H A Dtest-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc350 {{al, r4, r12, plus, r9, ROR, 12, Offset},
351 "al r4 r12 plus r9 ROR 12 Offset",
380 {{al, r0, r11, plus, r4, ROR, 2, Offset},
381 "al r0 r11 plus r4 ROR 2 Offset",
390 {{al, r2, r11, plus, r9, ROR, 29, Offset},
391 "al r2 r11 plus r9 ROR 29 Offset",
410 {{al, r5, r1, plus, r3, ROR, 19, Offset},
411 "al r5 r1 plus r3 ROR 19 Offset",
430 {{al, r7, r14, plus, r0, ROR, 17, Offset},
431 "al r7 r14 plus r0 ROR 1
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-a32.cc110 {{ge, r11, r13, ROR, r2},
113 "ge r11 r13 ROR r2",
121 {{eq, r3, r0, ROR, r11}, false, al, "eq r3 r0 ROR r11", "eq_r3_r0_ROR_r11"},
127 {{ge, r14, r6, ROR, r13},
130 "ge r14 r6 ROR r13",
138 {{ge, r4, r6, ROR, r7}, false, al, "ge r4 r6 ROR r7", "ge_r4_r6_ROR_r7"},
160 {{hi, r9, r11, ROR, r13},
163 "hi r9 r11 ROR r1
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-t32.cc111 {{al, r12, r3, ROR, r5}, false, al, "al r12 r3 ROR r5", "al_r12_r3_ROR_r5"},
133 {{al, r12, r11, ROR, r7},
136 "al r12 r11 ROR r7",
143 {{al, r11, r7, ROR, r0}, false, al, "al r11 r7 ROR r0", "al_r11_r7_ROR_r0"},
144 {{al, r6, r13, ROR, r2}, false, al, "al r6 r13 ROR r2", "al_r6_r13_ROR_r2"},
155 {{al, r4, r2, ROR, r3}, false, al, "al r4 r2 ROR r
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc120 {{al, r0, r0, ROR, r0}, false, al, "al r0 r0 ROR r0", "al_r0_r0_ROR_r0"},
121 {{al, r0, r0, ROR, r1}, false, al, "al r0 r0 ROR r1", "al_r0_r0_ROR_r1"},
122 {{al, r0, r0, ROR, r2}, false, al, "al r0 r0 ROR r2", "al_r0_r0_ROR_r2"},
123 {{al, r0, r0, ROR, r3}, false, al, "al r0 r0 ROR r3", "al_r0_r0_ROR_r3"},
124 {{al, r0, r0, ROR, r4}, false, al, "al r0 r0 ROR r
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc99 {{pl, r3, r3, ROR, r3}, true, pl, "pl r3 r3 ROR r3", "pl_r3_r3_ROR_r3"},
100 {{vc, r4, r4, ROR, r1}, true, vc, "vc r4 r4 ROR r1", "vc_r4_r4_ROR_r1"},
104 {{hi, r6, r6, ROR, r5}, true, hi, "hi r6 r6 ROR r5", "hi_r6_r6_ROR_r5"},
116 {{eq, r5, r5, ROR, r2}, true, eq, "eq r5 r5 ROR r2", "eq_r5_r5_ROR_r2"},
122 {{ge, r6, r6, ROR, r3}, true, ge, "ge r6 r6 ROR r
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc126 {{vs, r11, r0, r14, ROR, r1},
129 "vs r11 r0 r14 ROR r1",
131 {{vc, r5, r0, r11, ROR, r4},
134 "vc r5 r0 r11 ROR r4",
186 {{hi, r6, r3, r0, ROR, r4},
189 "hi r6 r3 r0 ROR r4",
216 {{ne, r4, r10, r9, ROR, r5},
219 "ne r4 r10 r9 ROR r5",
226 {{pl, r1, r0, r1, ROR, r1},
229 "pl r1 r0 r1 ROR r
[all...]
H A Dtest-simulator-cond-rd-operand-rn-ror-amount-a32.cc450 const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0},
451 "eq r0 r0 ROR 0",
455 {{ne, r0, r0, ROR, 0},
456 "ne r0 r0 ROR 0",
460 {{cs, r0, r0, ROR, 0},
461 "cs r0 r0 ROR 0",
465 {{cc, r0, r0, ROR, 0},
466 "cc r0 r0 ROR 0",
470 {{mi, r0, r0, ROR, 0},
471 "mi r0 r0 ROR
[all...]
H A Dtest-simulator-cond-rd-operand-rn-ror-amount-t32.cc450 const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0},
451 "eq r0 r0 ROR 0",
455 {{ne, r0, r0, ROR, 0},
456 "ne r0 r0 ROR 0",
460 {{cs, r0, r0, ROR, 0},
461 "cs r0 r0 ROR 0",
465 {{cc, r0, r0, ROR, 0},
466 "cc r0 r0 ROR 0",
470 {{mi, r0, r0, ROR, 0},
471 "mi r0 r0 ROR
[all...]
H A Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc802 {{al, r0, r0, ROR, 1},
803 "al r0 r0 ROR 1",
807 {{al, r0, r0, ROR, 2},
808 "al r0 r0 ROR 2",
812 {{al, r0, r0, ROR, 3},
813 "al r0 r0 ROR 3",
817 {{al, r0, r0, ROR, 4},
818 "al r0 r0 ROR 4",
822 {{al, r0, r0, ROR, 5},
823 "al r0 r0 ROR
[all...]
H A Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc802 {{al, r0, r1, ROR, 1},
803 "al r0 r1 ROR 1",
807 {{al, r0, r1, ROR, 2},
808 "al r0 r1 ROR 2",
812 {{al, r0, r1, ROR, 3},
813 "al r0 r1 ROR 3",
817 {{al, r0, r1, ROR, 4},
818 "al r0 r1 ROR 4",
822 {{al, r0, r1, ROR, 5},
823 "al r0 r1 ROR
[all...]
H A Dtest-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc825 const TestLoopData kTests[] = {{{eq, r0, r0, r0, ROR, 0},
826 "eq r0 r0 r0 ROR 0",
830 {{ne, r0, r0, r0, ROR, 0},
831 "ne r0 r0 r0 ROR 0",
835 {{cs, r0, r0, r0, ROR, 0},
836 "cs r0 r0 r0 ROR 0",
840 {{cc, r0, r0, r0, ROR, 0},
841 "cc r0 r0 r0 ROR 0",
845 {{mi, r0, r0, r0, ROR, 0},
846 "mi r0 r0 r0 ROR
[all...]
H A Dtest-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc825 const TestLoopData kTests[] = {{{eq, r0, r0, r0, ROR, 0},
826 "eq r0 r0 r0 ROR 0",
830 {{ne, r0, r0, r0, ROR, 0},
831 "ne r0 r0 r0 ROR 0",
835 {{cs, r0, r0, r0, ROR, 0},
836 "cs r0 r0 r0 ROR 0",
840 {{cc, r0, r0, r0, ROR, 0},
841 "cc r0 r0 r0 ROR 0",
845 {{mi, r0, r0, r0, ROR, 0},
846 "mi r0 r0 r0 ROR
[all...]
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc1219 {{al, r0, r0, r1, ROR, 1},
1220 "al r0 r0 r1 ROR 1",
1224 {{al, r0, r0, r1, ROR, 2},
1225 "al r0 r0 r1 ROR 2",
1229 {{al, r0, r0, r1, ROR, 3},
1230 "al r0 r0 r1 ROR 3",
1234 {{al, r0, r0, r1, ROR, 4},
1235 "al r0 r0 r1 ROR 4",
1239 {{al, r0, r0, r1, ROR, 5},
1240 "al r0 r0 r1 ROR
[all...]
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc1219 {{al, r0, r1, r2, ROR, 1},
1220 "al r0 r1 r2 ROR 1",
1224 {{al, r0, r1, r2, ROR, 2},
1225 "al r0 r1 r2 ROR 2",
1229 {{al, r0, r1, r2, ROR, 3},
1230 "al r0 r1 r2 ROR 3",
1234 {{al, r0, r1, r2, ROR, 4},
1235 "al r0 r1 r2 ROR 4",
1239 {{al, r0, r1, r2, ROR, 5},
1240 "al r0 r1 r2 ROR
[all...]
/external/vixl/src/aarch32/
H A Dinstructions-aarch32.cc49 case ROR:
428 case ROR:
593 case ROR:
731 case ROR:
/external/valgrind/none/tests/arm/
H A Dv6media.stdout.exp3042 sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3043 sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3044 sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3045 sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3046 sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3047 sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3048 sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3049 sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3050 sxtab r0, r1, r2, ROR #24 :: rd 0xf7b0b19c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3051 sxtab r0, r1, r2, ROR #2
[all...]

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