Searched refs:RSI (Results 1 - 25 of 44) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp81 bool operator==(const RegSeqInfo &RSI) const {
82 return RSI.Instr == Instr;
96 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
98 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
104 void trackRSI(const RegSeqInfo &RSI);
180 RegSeqInfo *RSI, const RegSeqInfo *BaseRSI,
182 unsigned Reg = RSI->Instr->getOperand(0).getReg();
183 MachineBasicBlock::iterator Pos = RSI->Instr;
190 for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(),
191 E = RSI
179 RebuildVector( RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const argument
275 tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI, std::vector<std::pair<unsigned, unsigned> > &RemapChan) argument
295 tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI, std::vector<std::pair<unsigned, unsigned> > &RemapChan) argument
308 trackRSI(const RegSeqInfo &RSI) argument
[all...]
/external/strace/linux/x86_64/
H A Duserent.h14 XLAT(8*RSI),
/external/kernel-headers/original/uapi/asm-x86/asm/
H A Dptrace-abi.h46 #define RSI 104 macro
/external/libunwind/src/x86_64/
H A Dunwind_i.h43 #define RSI 4 macro
H A Dinit.h53 c->dwarf.loc[RSI] = REG_INIT_LOC(c, rsi, RSI);
H A DGregs.c111 case UNW_X86_64_RSI: loc = c->dwarf.loc[RSI]; break;
H A DGos-freebsd.c115 c->dwarf.loc[RSI] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RSI, 0);
/external/lzma/Asm/x86/
H A D7zAsm.asm72 r6 equ RSI
/external/valgrind/coregrind/m_sigframe/
H A Dsigframe-amd64-darwin.c102 SC2(__rsi,RSI);
130 SC2(RSI,__rsi);
H A Dsigframe-amd64-linux.c354 SC2(rsi,RSI);
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp109 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP,
285 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
313 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
350 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
386 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
422 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
423 return X86::RSI;
/external/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp1042 RSI = PTI->ReadSequences.begin(), RSE = PTI->ReadSequences.end();
1043 RSI != RSE; ++RSI) {
1045 RI = RSI->begin(), RE = RSI->end(); RI != RE; ++RI) {
1279 RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end();
1280 RSI != RSE; ++RSI) {
1286 substituteVariantOperand(*RSI, /*IsRead=*/true, StartIdx);
1308 RSI
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86RegisterInfo.cpp370 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
689 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
726 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
762 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
798 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
799 return X86::RSI;
H A DX86GenRegisterInfo.inc132 RSI = 113,
301 const unsigned ESI_Overlaps[] = { X86::ESI, X86::RSI, X86::SI, X86::SIL, 0 };
361 const unsigned RSI_Overlaps[] = { X86::RSI, X86::ESI, X86::SI, X86::SIL, 0 };
363 const unsigned SI_Overlaps[] = { X86::SI, X86::ESI, X86::RSI, X86::SIL, 0 };
364 const unsigned SIL_Overlaps[] = { X86::SIL, X86::ESI, X86::RSI, X86::SI, 0 };
515 const unsigned ESI_SuperRegsSet[] = { X86::RSI, 0 };
542 const unsigned SI_SuperRegsSet[] = { X86::ESI, X86::RSI, 0 };
543 const unsigned SIL_SuperRegsSet[] = { X86::SI, X86::ESI, X86::RSI, 0 };
678 { "RSI", RSI_Overlaps, RSI_SubRegsSet, Empty_SuperRegsSet },
740 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X8
[all...]
H A DX86SelectionDAGInfo.cpp228 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
H A DX86GenCallingConv.inc516 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
635 X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
/external/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp224 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI,
253 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RSI : X86::ESI,
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h167 ENTRY(RSI) \
185 ENTRY(RSI) \
/external/google-breakpad/src/common/android/
H A Dbreakpad_getcontext_unittest.cc130 CHECK_REG(RSI);
/external/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h293 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
399 case X86::RSI: return X86::ESI;
/external/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h177 ENTRY(RSI) \
195 ENTRY(RSI) \
/external/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeView.h514 RSI = 332, member in class:llvm::codeview::CallingConvention::ClassOptions::FrameProcedureOptions::FunctionOptions::HfaKind::MemberAccess::MethodKind::MethodOptions::ModifierOptions::PointerKind::PointerMode::PointerOptions::PointerToMemberRepresentation::VFTableSlotKind::WindowsRTClassKind::ExportFlags::RegisterId
/external/clang/lib/Sema/
H A DSemaStmt.cpp3965 CapturedRegionScopeInfo *RSI = getCurCapturedRegion(); local
3966 RecordDecl *Record = RSI->TheRecordDecl;
3978 CapturedRegionScopeInfo *RSI = getCurCapturedRegion(); local
3982 buildCapturedStmtCaptureList(Captures, CaptureInits, RSI->Captures);
3984 CapturedDecl *CD = RSI->TheCapturedDecl;
3985 RecordDecl *RD = RSI->TheRecordDecl;
3988 getASTContext(), S, static_cast<CapturedRegionKind>(RSI->CapRegionKind),
/external/libunwind/src/ptrace/
H A D_UPT_reg_offset.c297 UNW_R_OFF(RSI, rsi)
/external/llvm/lib/DebugInfo/CodeView/
H A DEnumTables.cpp65 CV_ENUM_CLASS_ENT(RegisterId, RSI),

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