/external/llvm/lib/MC/MCParser/ |
H A D | MCTargetAsmParser.cpp | 15 const MCSubtargetInfo &STI) 17 STI(&STI) 26 STI = &STICopy; 31 return *STI; 14 MCTargetAsmParser(MCTargetOptions const &MCOptions, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.h | 27 const MCSubtargetInfo &STI) override; 31 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 33 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 37 const MCSubtargetInfo &STI, 41 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 45 const MCSubtargetInfo &STI, raw_ostream &O); 47 const MCSubtargetInfo &STI, raw_ostream &O); 50 const MCSubtargetInfo &STI, raw_ostream &O); 52 const MCSubtargetInfo &STI, raw_ostream &O); 54 const MCSubtargetInfo &STI, raw_ostrea [all...] |
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.h | 40 bool isMicroMips(const MCSubtargetInfo &STI) const; 41 bool isMips32r6(const MCSubtargetInfo &STI) const; 51 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, 56 const MCSubtargetInfo &STI) const override; 62 const MCSubtargetInfo &STI) const; 69 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 82 const MCSubtargetInfo &STI) const; 86 const MCSubtargetInfo &STI) const; 90 const MCSubtargetInfo &STI) cons [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.h | 28 const MCSubtargetInfo &STI) override; 32 virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 34 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 38 const MCSubtargetInfo &STI, 47 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, 50 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 52 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 54 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 60 const MCSubtargetInfo &STI, raw_ostream &O) { 65 const MCSubtargetInfo &STI, raw_ostrea 59 printPostIncOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) argument 86 printMemExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 103 printUImm12Offset(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 109 printAMIndexedWB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/Sparc/InstPrinter/ |
H A D | SparcInstPrinter.h | 29 const MCSubtargetInfo &STI) override; 30 bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 32 bool isV9(const MCSubtargetInfo &STI) const; 35 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 37 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 41 const MCSubtargetInfo &STI, raw_ostream &O); 44 void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, 46 void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, 48 void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, 50 bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, [all...] |
H A D | SparcInstPrinter.cpp | 38 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { 39 return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0; 48 StringRef Annot, const MCSubtargetInfo &STI) { 49 if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O)) 50 printInstruction(MI, STI, O); 55 const MCSubtargetInfo &STI, 76 O << "\tjmp "; printMemOperand(MI, 1, STI, O); 79 O << "\tcall "; printMemOperand(MI, 1, STI, O); 85 if (isV9(STI) 47 printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) argument 54 printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) argument 108 printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 140 printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) argument 163 printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 192 printGetPCX(const MCInst *MI, unsigned opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 33 const MCSubtargetInfo &STI; member in class:__anon18792::MipsMCCodeEmitter 38 : MCII(mcii), STI(sti) {} 49 const MCSubtargetInfo &STI, 51 return new MipsMCCodeEmitter(MCII, STI, Ctx); 48 createMipsMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 53 const MCSubtargetInfo &STI) const; 56 const MCSubtargetInfo &STI) const; 59 const MCSubtargetInfo &STI) const; 62 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 71 const MCSubtargetInfo &STI) const; 74 const MCSubtargetInfo &STI) const; 77 const MCSubtargetInfo &STI) const; 80 const MCSubtargetInfo &STI) cons [all...] |
/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 42 const MCSubtargetInfo &STI) const override; 48 const MCSubtargetInfo &STI) const; 54 const MCSubtargetInfo &STI) const; 62 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 71 const MCSubtargetInfo &STI) const; 74 const MCSubtargetInfo &STI) const; 77 const MCSubtargetInfo &STI) const; 91 const MCSubtargetInfo &STI) cons [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCShuffler.h | 30 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, argument 32 : HexagonShuffler(MCII, STI) { 35 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, argument 38 : HexagonShuffler(MCII, STI) { 56 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 58 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 60 unsigned HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
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/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
H A D | X86Disassembler.h | 111 X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode); 132 X86_16Disassembler(const MCSubtargetInfo &STI) : argument 133 X86GenericDisassembler(STI, MODE_16BIT) { 140 X86_32Disassembler(const MCSubtargetInfo &STI) : argument 141 X86GenericDisassembler(STI, MODE_32BIT) { 148 X86_64Disassembler(const MCSubtargetInfo &STI) : argument 149 X86GenericDisassembler(STI, MODE_64BIT) {
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 33 const MCSubtargetInfo &STI) const; 37 const MCSubtargetInfo &STI) const { 43 const MCSubtargetInfo &STI) const {
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/external/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRELFStreamer.h | 20 AVRELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.h | 32 const MCSubtargetInfo *&STI); 53 const MCSubtargetInfo *&STI); 55 X86AsmInstrumentation(const MCSubtargetInfo *&STI); 61 const MCSubtargetInfo *&STI; member in class:llvm::X86AsmInstrumentation
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMRegisterInfo.h | 28 ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.h | 26 AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument 27 : MCDisassembler(STI, Ctx) {}
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
H A D | AlphaFrameLowering.h | 25 const AlphaSubtarget &STI; member in class:llvm::AlphaFrameLowering 30 : TargetFrameLowering(StackGrowsDown, 16, 0), STI(sti), curgpdist(0) {
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.h | 35 MBlazeDisassembler(const MCSubtargetInfo &STI) : argument 36 MCDisassembler(STI) {
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsFrameLowering.h | 26 const MipsSubtarget &STI; member in class:llvm::MipsFrameLowering 31 STI(sti) {
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXFrameLowering.h | 26 const PTXSubtarget &STI; member in class:llvm::PTXFrameLowering 31 STI(sti) {
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
H A D | SparcFrameLowering.h | 25 const SparcSubtarget &STI; member in class:llvm::SparcFrameLowering 28 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, 0), STI(sti) {
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 53 bool isThumb(const MCSubtargetInfo &STI) const { 54 return STI.getFeatureBits()[ARM::ModeThumb]; 56 bool isThumb2(const MCSubtargetInfo &STI) const { 57 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; 59 bool isTargetMachO(const MCSubtargetInfo &STI) const { 60 const Triple &TT = STI.getTargetTriple(); 70 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 83 const MCSubtargetInfo &STI) cons 580 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) argument [all...] |
/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 50 const MCSubtargetInfo &STI) const; 56 const MCSubtargetInfo &STI) const; 64 const MCSubtargetInfo &STI) const; 70 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 82 const MCSubtargetInfo &STI) const; 88 const MCSubtargetInfo &STI) const; 95 const MCSubtargetInfo &STI) const; 101 const MCSubtargetInfo &STI) const; 107 const MCSubtargetInfo &STI) cons [all...] |
/external/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUBaseInfo.cpp | 151 bool isSI(const MCSubtargetInfo &STI) { argument 152 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands]; 155 bool isCI(const MCSubtargetInfo &STI) { argument 156 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands]; 159 bool isVI(const MCSubtargetInfo &STI) { argument 160 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 163 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) { argument 168 assert(!isSI(STI)); 169 return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi; 172 assert(!isSI(STI)); [all...] |
/external/llvm/include/llvm/MC/MCDisassembler/ |
H A D | MCDisassembler.h | 56 MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument 57 : Ctx(Ctx), STI(STI), Symbolizer(), CommentStream(nullptr) {} 86 const MCSubtargetInfo &STI; member in class:llvm::MCDisassembler 104 const MCSubtargetInfo& getSubtargetInfo() const { return STI; }
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