Searched refs:STM (Results 1 - 23 of 23) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUAsmPrinter.cpp117 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>(); local
119 if (STM.isAmdHsaOS()) {
127 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>(); local
128 if (MFI->isKernel() && STM.isAmdHsaOS()) {
159 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>(); local
161 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
163 if (!STM.isAmdHsaOS()) {
181 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
233 if (STM.dumpCode()) {
253 const R600Subtarget &STM local
311 const SISubtarget &STM = MF.getSubtarget<SISubtarget>(); local
581 const SISubtarget &STM = MF.getSubtarget<SISubtarget>(); local
640 const SISubtarget &STM = MF.getSubtarget<SISubtarget>(); local
[all...]
H A DSILoadStoreOptimizer.cpp414 const SISubtarget &STM = MF.getSubtarget<SISubtarget>(); local
415 if (!STM.loadStoreOptEnabled())
418 TII = STM.getInstrInfo();
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUAsmPrinter.cpp41 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); local
42 if (STM.dumpCode()) {
46 if (STM.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
H A DAMDILISelLowering.cpp101 const AMDGPUSubtarget &STM = getTargetMachine().getSubtarget<AMDGPUSubtarget>(); local
173 if (STM.device()->isSupported(AMDGPUDeviceInfo::LongOps)) {
187 if (STM.device()->isSupported(AMDGPUDeviceInfo::DoubleOps)) {
/external/swiftshader/third_party/LLVM/lib/Target/
H A DTargetData.cpp356 StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap); local
357 StructLayout *&SL = (*STM)[Ty];
/external/llvm/lib/IR/
H A DDataLayout.cpp560 StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap);
561 StructLayout *&SL = (*STM)[Ty];
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dthumb-diagnostics.s71 @ Invalid writeback and register lists for STM
H A Ddiagnostics.s216 @ Out of order STM registers
H A Dbasic-thumb-instructions.s467 @ STM
H A Dbasic-arm-instructions.s2016 @ STM*
/external/llvm/utils/TableGen/
H A DDAGISelMatcherEmitter.cpp761 } else if (const SwitchTypeMatcher *STM = dyn_cast<SwitchTypeMatcher>(M)) {
762 for (unsigned i = 0, e = STM->getNumCases(); i != e; ++i)
763 BuildHistogram(STM->getCaseMatcher(i), OpcodeFreq);
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DDAGISelMatcherEmitter.cpp725 } else if (const SwitchTypeMatcher *STM = dyn_cast<SwitchTypeMatcher>(M)) {
726 for (unsigned i = 0, e = STM->getNumCases(); i != e; ++i)
727 BuildHistogram(STM->getCaseMatcher(i), OpcodeFreq);
/external/libunwind_llvm/src/
H A DUnwindRegistersSave.S313 @ . the pc (r15) cannot be in the list in an STM instruction
/external/llvm/test/MC/ARM/
H A Dthumb-diagnostics.s119 @ Invalid writeback and register lists for STM
H A Ddiagnostics.s285 @ Out of order STM registers
488 @ CHECK-ERRORS: error: system STM cannot have writeback register
H A Dbasic-thumb-instructions.s518 @ STM
H A Dv8_IT_manual.s609 @ STM, encoding T1
613 @ STM, encoding T2 (32-bit)
617 @ STM, encoding T3 (32-bit)
H A Dbasic-arm-instructions.s2832 @ STM*
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp905 // Fallback to STM instruction, which has existed since the dawn of
1238 MachineInstrBuilder LDM, STM; local
1249 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1254 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1258 AddDefaultPred(STM.addOperand(MI->getOperand(2)));
1274 STM.addReg(Reg, RegState::Kill);
2999 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
/external/v8/src/s390/
H A Dconstants-s390.h842 STM = 0x90, // Store Multiple (32) enumerator in enum:v8::internal::Opcode
H A Dsimulator-s390.h603 EVALUATE(STM);
H A Dsimulator-s390.cc824 EvalTable[STM] = &Simulator::Evaluate_STM;
2870 case STM:
2888 if (op == STM) {
7205 EVALUATE(STM) {
7206 DCHECK_OPCODE(STM);
H A Dassembler-s390.cc535 rs_form(STM, r1, r2, src.rb(), src.offset());

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