| /external/llvm/test/MC/Mips/ |
| H A D | elf-N64.s | 34 sd $ra, 8($sp) # 8-byte Folded Spill
35 sd $gp, 0($sp) # 8-byte Folded Spill
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| H A D | r-mips-got-disp.s | 27 sd $ra, 8($sp) # 8-byte Folded Spill
28 sd $gp, 0($sp) # 8-byte Folded Spill
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| H A D | elf-tls.s | 34 sw $ra, 20($sp) # 4-byte Folded Spill
66 sw $ra, 20($sp) # 4-byte Folded Spill
98 sw $ra, 20($sp) # 4-byte Folded Spill
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| H A D | xgot.s | 38 sw $ra, 20($sp) # 4-byte Folded Spill
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 202 struct SpilledReg Spill; local
203 Spill.Lane = Lane;
210 return Spill;
222 Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
223 return Spill;
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| H A D | SIMachineFunctionInfo.h | 291 void setHasSpilledSGPRs(bool Spill = true) {
292 HasSpilledSGPRs = Spill;
299 void setHasSpilledVGPRs(bool Spill = true) {
300 HasSpilledVGPRs = Spill;
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| H A D | SIRegisterInfo.cpp | 528 struct SIMachineFunctionInfo::SpilledReg Spill = local
531 if (Spill.hasReg()) {
534 Spill.VGPR)
536 .addImm(Spill.Lane);
542 // Spill SGPR to a frame index.
592 struct SIMachineFunctionInfo::SpilledReg Spill = local
595 if (Spill.hasReg()) {
599 .addReg(Spill.VGPR)
600 .addImm(Spill.Lane)
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| /external/llvm/lib/CodeGen/ |
| H A D | RegAllocBasic.cpp | 163 // Spill or split all live virtual registers currently unified under PhysReg
189 // Spill each interfering vreg allocated to PhysReg or an alias.
191 LiveInterval &Spill = *Intfs[i]; local
194 if (!VRM->hasPhys(Spill.reg))
199 Matrix->unassign(Spill);
201 // Spill the extracted interval.
202 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats);
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| H A D | InlineSpiller.cpp | 123 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
125 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
973 /// spillAll - Spill all registers remaining after rematerialization.
992 // Spill around uses of all RegsToSpill.
1054 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot, argument
1057 SlotIndex Idx = LIS.getInstructionIndex(Spill);
1060 MergeableSpills[MIdx].insert(&Spill);
1066 bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill, argument
1071 SlotIndex Idx = LIS.getInstructionIndex(Spill);
1074 return MergeableSpills[MIdx].erase(&Spill);
[all...] |
| /external/v8/src/compiler/ |
| H A D | register-allocator.cc | 457 void LiveRange::Spill() { function in class:v8::internal::compiler::LiveRangeBoundArray::LiveRange
1228 // Spill ranges are created for top level, non-splintered ranges. This is so
2584 Spill(range);
2597 Spill(range);
2708 void RegisterAllocator::Spill(LiveRange* range) { function in class:v8::internal::compiler::LiveRangeBoundArray::RegisterAllocator
2716 range->Spill();
2831 Spill(range);
2840 Spill(range);
3157 Spill(current);
3416 Spill(rang
[all...] |
| H A D | register-allocator.h | 340 void Spill();
525 // Spill range management.
710 // Spill slots can be 4, 8, or 16 bytes wide.
1021 void Spill(LiveRange* range);
1091 // Spill the given life range after position pos.
1094 // Spill the given life range after position [start] and up to position [end].
1098 // Spill the given life range after position [start] and up to position [end].
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| /external/v8/src/crankshaft/ |
| H A D | lithium-allocator.h | 456 // Spill the given life range after position pos.
459 // Spill the given life range after position [start] and up to position [end].
464 // Spill the given life range after position [start] and up to position [end].
478 void Spill(LiveRange* range);
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| H A D | lithium-allocator.cc | 1537 Spill(current);
1844 Spill(current);
1899 // Spill starting part of live range up to that use.
2088 Spill(second_part);
2119 Spill(second_part);
2129 void LAllocator::Spill(LiveRange* range) { function in class:LAllocator
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