Searched refs:Src1Reg (Results 1 - 10 of 10) sorted by relevance
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
101 Src1Reg = MI.getOperand(1).getReg();
104 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
146 Src1Reg = MI.getOperand(1).getReg();
148 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
160 Src1Reg = MI.getOperand(0).getReg();
161 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)
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| H A D | HexagonMCDuplexInfo.cpp | 178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; local
317 Src1Reg = MCI.getOperand(0).getReg();
319 if (HexagonMCInstrInfo::isIntReg(Src1Reg) &&
321 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) {
325 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
333 Src1Reg = MCI.getOperand(0).getReg();
335 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
352 Src1Reg = MCI.getOperand(0).getReg();
354 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
362 Src1Reg
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1139 unsigned Src1Reg = MI.getOperand(1).getReg(); local
1141 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
1142 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
1163 unsigned Src1Reg = MI.getOperand(1).getReg(); local
1166 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
1167 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
1193 unsigned Src1Reg = MI.getOperand(1).getReg(); local
1206 .addReg(Src1Reg, Src1RegIsKill)
3304 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
3319 Src1Reg
3638 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 212 unsigned Src1Reg = MI->getOperand(2).getReg(); local
226 .addReg(Src1Reg, getKillRegState(Src1Kill))
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| /external/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 278 unsigned Src1Reg = MI->getOperand(2).getReg(); local
294 .addReg(Src1Reg, getKillRegState(Src1Kill))
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 270 unsigned Src1Reg = 0) const;
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| H A D | R600InstrInfo.cpp | 1265 unsigned Src1Reg) const {
1269 if (Src1Reg) {
1283 if (Src1Reg) {
1284 MIB.addReg(Src1Reg) // $src1
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| H A D | SIInstrInfo.cpp | 1265 unsigned Src1Reg = Src1->getReg(); local
1267 Src0->setReg(Src1Reg);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2558 unsigned Src1Reg = getRegForValue(Src1Val); local
2559 if (!Src1Reg)
2569 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1);
2572 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
2688 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); local
2694 if (!Src1Reg || !Src2Reg)
2698 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
2702 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
4483 unsigned Src1Reg local
4561 unsigned Src1Reg = getRegForValue(I->getOperand(1)); local
[all...] |
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 994 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); local
998 if (!Src1Reg || !Src2Reg || !CondReg)
1016 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1685 unsigned Src1Reg = getRegForValue(I->getOperand(1)); local
1686 if (!Src0Reg || !Src1Reg)
1689 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1690 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
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