| /external/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 556 unsigned SuperReg = 0;
559 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
560 SuperReg = Reg;
579 // All group registers should be a subreg of SuperReg.
582 if (Reg == SuperReg) continue;
583 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
598 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
603 // Check each possible rename register for SuperReg in round-robin
612 TRI->getMinimalPhysRegClass(SuperReg, MV
[all...] |
| H A D | ScheduleDAGInstrs.cpp | 1258 const unsigned SuperReg = MO.getReg(); local
1260 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 570 unsigned SuperReg = 0;
573 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
574 SuperReg = Reg;
590 // All group registers should be a subreg of SuperReg.
593 if (Reg == SuperReg) continue;
594 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
607 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
612 // Check each possible rename register for SuperReg in round-robin
621 TRI->getMinimalPhysRegClass(SuperReg, MV
[all...] |
| H A D | CriticalAntiDepBreaker.cpp | 284 unsigned SuperReg = *Super; local
285 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
| H A D | PostRASchedulerList.cpp | 416 const unsigned SuperReg = MO.getReg(); local
417 for (const unsigned *Subreg = TRI->getSubRegisters(SuperReg);
|
| H A D | LiveIntervalAnalysis.cpp | 2069 unsigned SuperReg = *AS; local
2070 if (!hasAllocatableSuperReg(SuperReg) && hasInterval(SuperReg)) {
2071 BestReg = SuperReg;
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| H A D | VirtRegRewriter.cpp | 2562 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
2563 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
2565 PhysReg = SuperReg;
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 849 unsigned SuperReg = local
852 if (VSXSelfCopyCrash && SrcReg == SuperReg)
855 DestReg = SuperReg;
858 unsigned SuperReg = local
861 if (VSXSelfCopyCrash && SrcReg == SuperReg)
864 DestReg = SuperReg;
867 unsigned SuperReg = local
870 if (VSXSelfCopyCrash && DestReg == SuperReg)
873 SrcReg = SuperReg;
876 unsigned SuperReg local
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1663 SDValue SuperReg = SDValue(VLd, 0);
1669 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1887 SDValue SuperReg; local
1892 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1894 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1901 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1903 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1905 Ops.push_back(SuperReg);
1920 SuperReg = SDValue(VLdLn, 0);
1926 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1974 SDValue SuperReg; local
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 46 MachineOperand &SuperReg,
52 MachineOperand &SuperReg,
|
| H A D | SIRegisterInfo.cpp | 520 unsigned SuperReg = MI->getOperand(0).getReg(); local
522 // SubReg carries the "Kill" flag when SubReg == SuperReg.
525 unsigned SubReg = getPhysRegSubReg(SuperReg,
552 // The last implicit use of the SuperReg carries the "Kill" flag.
556 Mov.addReg(SuperReg, RegState::Implicit | SuperKillState);
|
| H A D | SIInstrInfo.cpp | 1903 MachineOperand &SuperReg,
1912 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
1914 .addReg(SuperReg.getReg(), 0, SubIdx);
1925 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
|
| H A D | R600InstrInfo.cpp | 1120 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1121 Reserved.set(SuperReg);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1930 SDValue SuperReg = SDValue(VLd, 0); local
1937 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2166 SDValue SuperReg; local
2171 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2173 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2180 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2182 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2184 Ops.push_back(SuperReg);
2200 SuperReg = SDValue(VLdLn, 0);
2207 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2255 SDValue SuperReg; local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1146 SDValue SuperReg = SDValue(Ld, 0); local
1149 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1174 SDValue SuperReg = SDValue(Ld, 1); local
1176 ReplaceUses(SDValue(N, 0), SuperReg); local
1180 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1282 SDValue SuperReg = SDValue(Ld, 0); local
1288 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1331 SDValue SuperReg = SDValue(Ld, 1); local
1334 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg);
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6066 unsigned SuperReg = MRI->getMatchingSuperReg( local
6069 assert(SuperReg && "expected register pair");
6071 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
|