Searched refs:Swz (Results 1 - 5 of 5) sorted by relevance
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_emulate_loops.c | 52 rc_swizzle Swz; member in struct:count_inst
123 (1 << GET_SWZ(count_inst->Swz,0) != mask)){
142 inst->U.I.SrcReg[0].Swizzle == count_inst->Swz){
146 inst->U.I.SrcReg[1].Swizzle == count_inst->Swz){
231 count_inst.Swz = counter->Swizzle;
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.h | 62 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
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| H A D | R600InstrInfo.cpp | 383 R600InstrInfo::BankSwizzle Swz) {
386 switch (Swz) {
411 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
412 switch (Swz) {
437 /// Swz swizzle sequence.
440 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
447 Swizzle(IGSrcs[i], Swz[i]);
453 if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
454 Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
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| H A D | R600InstrInfo.h | 120 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
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| H A D | R600ISelLowering.cpp | 1918 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4], argument
1927 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1929 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1935 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1937 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
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