Searched refs:TGSI_OPCODE_IMAX (Results 1 - 7 of 7) sorted by relevance
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_info.c | 161 { 1, 2, 0, 0, 0, 0, COMP, "IMAX", TGSI_OPCODE_IMAX },
297 case TGSI_OPCODE_IMAX:
345 case TGSI_OPCODE_IMAX:
|
| H A D | tgsi_exec.c | 4061 case TGSI_OPCODE_IMAX:
|
| /external/mesa3d/src/gallium/include/pipe/ |
| H A D | p_shader_tokens.h | 371 #define TGSI_OPCODE_IMAX 121 macro
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | radeon_setup_tgsi_llvm.c | 1094 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
1095 bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_from_tgsi.cpp | 385 case TGSI_OPCODE_IMAX:
1760 case TGSI_OPCODE_IMAX:
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| H A D | lp_bld_tgsi_action.c | 1074 /* TGSI_OPCODE_IMAX (CPU Only) */
1583 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = imax_emit_cpu;
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| H A D | r600_shader.c | 5370 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
5544 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
5718 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
|
Completed in 150 milliseconds