Searched refs:TGSI_OPCODE_UADD (Results 1 - 7 of 7) sorted by relevance
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_info.c | 169 { 1, 2, 0, 0, 0, 0, COMP, "UADD", TGSI_OPCODE_UADD },
279 case TGSI_OPCODE_UADD:
327 case TGSI_OPCODE_UADD:
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| H A D | tgsi_exec.c | 4093 case TGSI_OPCODE_UADD:
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| /external/mesa3d/src/gallium/include/pipe/ |
| H A D | p_shader_tokens.h | 379 #define TGSI_OPCODE_UADD 129 macro
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| H A D | lp_bld_tgsi_action.c | 710 TGSI_OPCODE_UADD, tmp, emit_data->args[2]);
1420 /* TGSI_OPCODE_UADD (CPU Only) */
1614 bld_base->op_actions[TGSI_OPCODE_UADD].emit = uadd_emit_cpu;
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_from_tgsi.cpp | 369 case TGSI_OPCODE_UADD:
1753 case TGSI_OPCODE_UADD:
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | radeon_setup_tgsi_llvm.c | 1061 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
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| /external/mesa3d/src/gallium/drivers/r600/ |
| H A D | r600_shader.c | 5378 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
5552 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
5726 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
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