Searched refs:TGSI_WRITEMASK_W (Results 1 - 25 of 27) sorted by relevance

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/external/mesa3d/src/gallium/state_trackers/vega/
H A Dasm_fill.h260 ureg_writemask(temp[1], TGSI_WRITEMASK_W),
270 ureg_writemask(temp[0], TGSI_WRITEMASK_W),
373 ureg_ADD(ureg, ureg_writemask(out, TGSI_WRITEMASK_W),
540 ureg_MUL(ureg, ureg_writemask(temp[0], TGSI_WRITEMASK_W),
598 ureg_writemask(temp[0], TGSI_WRITEMASK_W),
/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_util.c298 read_mask |= TGSI_WRITEMASK_W;
H A Dtgsi_exec.c589 writemask == TGSI_WRITEMASK_W ||
2747 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2774 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2815 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2867 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2912 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2932 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2945 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2971 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2996 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
[all...]
H A Dtgsi_dump.c201 if (writemask & TGSI_WRITEMASK_W)
H A Dtgsi_text.c360 *writemask |= TGSI_WRITEMASK_W;
/external/mesa3d/src/gallium/auxiliary/vl/
H A Dvl_compositor.c111 ureg_RCP(shader, ureg_writemask(o_vtop, TGSI_WRITEMASK_W),
119 ureg_RCP(shader, ureg_writemask(o_vbottom, TGSI_WRITEMASK_W),
157 ureg_MOV(shader, ureg_writemask(texel, TGSI_WRITEMASK_W), ureg_imm1f(shader, 1.0f));
162 ureg_MOV(shader, ureg_writemask(fragment, TGSI_WRITEMASK_W), ureg_imm1f(shader, 1.0f));
207 ureg_MOV(shader, ureg_writemask(t_tc[i], TGSI_WRITEMASK_W),
246 ureg_MOV(shader, ureg_writemask(t_texel[0], TGSI_WRITEMASK_W), ureg_imm1f(shader, 1.0f));
250 ureg_MOV(shader, ureg_writemask(o_fragment, TGSI_WRITEMASK_W), ureg_imm1f(shader, 1.0f));
294 ureg_MOV(shader, ureg_writemask(fragment, TGSI_WRITEMASK_W), ureg_src(texel));
H A Dvl_idct.c236 ureg_MUL(shader, ureg_writemask(m[0][0], TGSI_WRITEMASK_W), ureg_abs(ureg_src(m[7][1])), ureg_imm1f(shader, 1 << 14));
240 ureg_CMP(shader, ureg_writemask(m[0][0], TGSI_WRITEMASK_W), ureg_negate(ureg_src(m[0][0])),
242 ureg_MUL(shader, ureg_writemask(m[0][0], TGSI_WRITEMASK_W), ureg_src(m[0][0]),
246 ureg_ADD(shader, ureg_writemask(fragment, TGSI_WRITEMASK_W), ureg_src(m[0][0]), ureg_src(m[7][1]));
H A Dvl_mc.c197 ureg_CMP(shader, ureg_writemask(fragment, TGSI_WRITEMASK_W),
272 ureg_MOV(shader, ureg_writemask(o_flags, TGSI_WRITEMASK_W), ureg_imm1f(shader, -1.0f));
293 ureg_CMP(shader, ureg_writemask(o_flags, TGSI_WRITEMASK_W),
359 ureg_MOV(shader, ureg_writemask(fragment, TGSI_WRITEMASK_W), ureg_imm1f(shader, 1.0f));
H A Dvl_zscan.c146 ureg_FLR(shader, ureg_writemask(tmp, TGSI_WRITEMASK_W), ureg_src(tmp));
157 ureg_MUL(shader, ureg_writemask(o_vtex[i], TGSI_WRITEMASK_W), ureg_src(tmp),
/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_setup_point.c196 if (usage_mask & TGSI_WRITEMASK_W) {
224 fragcoord_usage_mask |= TGSI_WRITEMASK_W;
H A Dlp_setup_line.c155 if (usage_mask & TGSI_WRITEMASK_W) {
201 fragcoord_usage_mask |= TGSI_WRITEMASK_W;
H A Dlp_bld_interp.c319 assert(bld->mask[0] & TGSI_WRITEMASK_W);
518 assert(bld->mask[0] & TGSI_WRITEMASK_W);
642 assert(bld->mask[0] & TGSI_WRITEMASK_W);
H A Dlp_state_fs.c1386 usage_mask & TGSI_WRITEMASK_W ? "w" : "");
/external/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_optimize.c83 if ( write_mask & TGSI_WRITEMASK_W && r->Register.SwizzleW != TGSI_SWIZZLE_W)
142 if ( write_mask & TGSI_WRITEMASK_W )
H A Di915_fpc_translate.c340 if (writeMask & TGSI_WRITEMASK_W)
/external/mesa3d/src/gallium/include/pipe/
H A Dp_shader_tokens.h93 #define TGSI_WRITEMASK_W 0x08 macro
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_info.c147 readmask |= TGSI_WRITEMASK_W;
/external/mesa3d/src/gallium/auxiliary/draw/
H A Ddraw_pipe_aapoint.c379 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
416 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
462 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
H A Ddraw_pipe_aaline.c310 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
/external/mesa3d/src/gallium/state_trackers/xorg/
H A Dxorg_exa_tgsi.c376 ureg_MOV(ureg, ureg_writemask(rgb, TGSI_WRITEMASK_W),
429 ureg_writemask(tmp1, TGSI_WRITEMASK_W),
449 ureg_writemask(dst, TGSI_WRITEMASK_W),
/external/mesa3d/src/gallium/drivers/svga/
H A Dsvga_tgsi_insn.c1502 writemask( tmp, TGSI_WRITEMASK_W ),
1723 if (dst.mask & TGSI_WRITEMASK_W) {
1728 writemask( dst2, TGSI_WRITEMASK_W ),
1984 if (dst.mask & TGSI_WRITEMASK_W) {
1989 writemask(dst, TGSI_WRITEMASK_W),
2146 if (dst.mask & TGSI_WRITEMASK_W) {
2148 writemask(dst, TGSI_WRITEMASK_W),
2381 if (dst.mask & TGSI_WRITEMASK_W) {
2383 writemask(dst, TGSI_WRITEMASK_W),
2779 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_W ),
[all...]
/external/mesa3d/src/gallium/state_trackers/xa/
H A Dxa_tgsi.c404 ureg_writemask(tmp1, TGSI_WRITEMASK_W),
424 ureg_writemask(dst, TGSI_WRITEMASK_W),
/external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d1x/
H A Dsm4_to_tgsi.cpp477 ureg_MOV(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_W), ureg_swizzle(_src(4), 0, 0, 0, 0));
/external/mesa3d/src/gallium/drivers/nv30/
H A Dnvfx_fragprog.c435 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_FP_MASK_W;
H A Dnvfx_vertprog.c453 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;

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