Searched refs:TGSI_WRITEMASK_XYZW (Results 1 - 20 of 20) sorted by relevance

/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_util.c252 read_mask = TGSI_WRITEMASK_XYZW;
256 read_mask = src_idx == 0 ? TGSI_WRITEMASK_XYZ : TGSI_WRITEMASK_XYZW;
290 read_mask = TGSI_WRITEMASK_XYZW;
302 read_mask = TGSI_WRITEMASK_XYZW;
308 read_mask = TGSI_WRITEMASK_XYZW;
H A Dtgsi_ureg.c252 dst.WriteMask = TGSI_WRITEMASK_XYZW;
439 return ureg_DECL_output_masked(ureg, name, index, TGSI_WRITEMASK_XYZW);
1245 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; /* FIXME! */
1275 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW;
1294 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW;
1315 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW;
1474 TGSI_WRITEMASK_XYZW);
1484 TGSI_WRITEMASK_XYZW);
H A Dtgsi_scan.c321 dst->Register.WriteMask != TGSI_WRITEMASK_XYZW)
H A Dtgsi_build.c106 declaration.UsageMask = TGSI_WRITEMASK_XYZW;
889 dst_register.WriteMask = TGSI_WRITEMASK_XYZW;
911 assert( mask <= TGSI_WRITEMASK_XYZW );
H A Dtgsi_dump.c193 if (writemask != TGSI_WRITEMASK_XYZW) {
H A Dtgsi_ureg.h985 dst.WriteMask = TGSI_WRITEMASK_XYZW;
H A Dtgsi_text.c371 *writemask = TGSI_WRITEMASK_XYZW;
/external/mesa3d/src/gallium/auxiliary/util/
H A Du_simple_shaders.c141 if (writemask != TGSI_WRITEMASK_XYZW) {
168 TGSI_WRITEMASK_XYZW );
H A Du_blit.c71 void *fs[PIPE_MAX_TEXTURE_TYPES][TGSI_WRITEMASK_XYZW + 1];
904 set_fragment_shader(ctx, TGSI_WRITEMASK_XYZW,
/external/mesa3d/src/gallium/auxiliary/postprocess/
H A Dpp_run.c63 TGSI_WRITEMASK_XYZW, 0);
H A Dpp_mlaa.c182 TGSI_WRITEMASK_XYZW, 0);
/external/mesa3d/src/gallium/drivers/r300/
H A Dr300_vs_draw.c253 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
265 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
/external/mesa3d/src/mesa/state_tracker/
H A Dst_cb_blit.c245 0.0, pFilter, TGSI_WRITEMASK_XYZW, 0);
260 0.0, pFilter, TGSI_WRITEMASK_XYZW, 0);
H A Dst_mesa_to_tgsi.c435 (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
H A Dst_cb_texture.c877 return TGSI_WRITEMASK_XYZW;
/external/mesa3d/src/gallium/include/pipe/
H A Dp_shader_tokens.h100 #define TGSI_WRITEMASK_XYZW 0x0F macro
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_info.c132 readmask = TGSI_WRITEMASK_XYZW;
H A Dlp_bld_tgsi_aos.c326 if (reg->Register.WriteMask != TGSI_WRITEMASK_XYZW) {
/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_bld_interp.c732 bld->mask[0] = TGSI_WRITEMASK_XYZW;
/external/mesa3d/src/gallium/drivers/svga/
H A Dsvga_tgsi_insn.c2271 if (dst.mask != TGSI_WRITEMASK_XYZW) {

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