Searched refs:VEX (Results 1 - 8 of 8) sorted by relevance

/external/valgrind/
H A DAndroid.mk75 external/valgrind/VEX/pub \
104 VEX/priv/main_globals.c \
105 VEX/priv/main_main.c \
106 VEX/priv/main_util.c \
107 VEX/priv/ir_defs.c \
108 VEX/priv/ir_match.c \
109 VEX/priv/ir_opt.c \
110 VEX/priv/ir_inject.c \
111 VEX/priv/guest_generic_bb_to_IR.c \
112 VEX/pri
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/external/valgrind/solaris/
H A Dbuild_solaris_package4 # directory. The Valgrind and VEX revisions are taken from that
64 svn export --quiet --ignore-externals $source_directory/VEX $SRCDIR/VEX \
66 (( $? != 0 )) && fail "Failed to export working copy from $source_directory/VEX."
72 vex_rev=$( svn info $source_directory/VEX | grep Revision | sed -e 's/Revision: //' )
75 [[ -z $vex_rev ]] && fail "Failed to find VEX revision."
77 echo "Valgrind revision: $valgrind_rev, VEX revision $vex_rev."
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h377 /// VEX - The opcode prefix used by AVX instructions
379 VEX = 1U << 0, enumerator in enum:llvm::X86II::__anon18860
395 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
401 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX
H A DX86MCCodeEmitter.cpp55 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
59 // VEX.VVVV => XMM9 => ~9
385 /// called VEX.
420 // VEX_5M (VEX m-mmmmm field):
430 // VEX_4V (VEX vvvv field): a register specifier
479 case X86II::A6: // Bypass: Not used by VEX
480 case X86II::A7: // Bypass: Not used by VEX
481 case X86II::TB: // Bypass: Not used by VEX
595 // VEX opcode prefix can have 2 or 3 bytes
608 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefi
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/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h387 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
465 // VEX - encoding using 0xC4/0xC5
466 VEX = 1 << EncodingShift,
492 /// operand 3 with VEX.vvvv.
502 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
509 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX
519 // - 11 LIG (but, in insn encoding, leave VEX.L and EVEX.L in zeros.
H A DX86MCCodeEmitter.cpp595 /// called VEX.
600 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
636 // VEX_5M (VEX m-mmmmm field):
657 // VEX_4V (VEX vvvv field): a register specifier
890 if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
891 // VEX opcode prefix can have 2 or 3 bytes
908 // Can we use the 2 byte VEX prefix?
909 if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
915 // 3 byte VEX prefix
927 && "More than 2 significant bits in VEX
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/external/llvm/utils/TableGen/
H A DX86RecognizableInstr.cpp127 VEX = 1, XOP = 2, EVEX = 3 enumerator in enum:X86Local::__anon13787
255 // Special case since there is no attribute class for 64-bit and VEX
290 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
291 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
376 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
608 // - In AVX, there is a register operand in the VEX.vvvv field here -
620 // in ModRMVEX and the one above the one in the VEX.VVVV field
629 // - In AVX, there is a register operand in the VEX.vvvv field here -
642 // in ModRMVEX and the one above the one in the VEX.VVVV field
651 // - In AVX, there is a register operand in the VEX
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/external/libvpx/libvpx/third_party/x86inc/
H A Dx86inc.asm1310 ; Instructions with both VEX and non-VEX encodings

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