Searched refs:WriteMask (Results 1 - 25 of 96) sorted by relevance

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/external/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_optimize.c165 o->WriteMask = i->WriteMask;
210 is_unswizzled(&current->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) &&
211 is_unswizzled(&current->FullInstruction.Src[1], current->FullInstruction.Dst[0].Register.WriteMask) &&
212 is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) )
218 next->FullInstruction.Dst[0].Register.WriteMask,
221 current->FullInstruction.Dst[0].Register.WriteMask = current->FullInstruction.Dst[0].Register.WriteMask |
222 next->FullInstruction.Dst[0].Register.WriteMask;
234 is_unswizzled(&current->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask)
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/external/mesa3d/src/gallium/drivers/r300/compiler/tests/
H A Drc_test_helpers.c203 struct match_info WriteMask; member in struct:dst_tokens
236 tokens.WriteMask.String = dst_str + matches[3].rm_so;
237 tokens.WriteMask.Length = match_length(matches, 3);
258 /* WriteMask */
259 if (tokens.WriteMask.Length == 0) {
260 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
263 if (tokens.WriteMask.String[0] != '.') {
267 for (i = 1; i < tokens.WriteMask.Length; i++) {
268 switch(tokens.WriteMask.String[i]) {
270 inst->U.I.DstReg.WriteMask |
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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dgen6_depthstencil.c60 ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
73 ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
79 if (ctx->Stencil.WriteMask[0] ||
80 (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
H A Dbrw_cc.c120 cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0];
134 cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
140 if (ctx->Stencil.WriteMask[0] ||
141 (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
H A Dbrw_wm_fp.c139 reg.WriteMask = WRITEMASK_XYZW;
149 reg.WriteMask &= mask;
260 if (inst0->DstReg.WriteMask == 0)
263 dst_chan = ffs(inst0->DstReg.WriteMask) - 1;
266 inst->DstReg.WriteMask = 1 << dst_chan;
268 other_channel_mask = inst0->DstReg.WriteMask & ~(1 << dst_chan);
564 if (dst.WriteMask & WRITEMASK_Y) {
576 if (dst.WriteMask & WRITEMASK_XZ) {
592 if (dst.WriteMask & WRITEMASK_W) {
626 if (dst.WriteMask
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H A Dgen7_misc_state.c115 dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
195 ((stencil_mt != NULL && ctx->Stencil.WriteMask != 0) << 27) |
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_pair_translate.c90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0;
91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0;
275 inst->DstReg.WriteMask);
286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
293 inst->DstReg.WriteMask & RC_MASK_XYZ;
295 GET_BIT(inst->DstReg.WriteMask, 3);
303 pair->RGB.WriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ;
307 pair->Alpha.WriteMask |= (GET_BIT(inst->DstReg.WriteMask,
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H A Dr3xx_fragprog.c64 if (inst->DstReg.WriteMask & RC_MASK_Z) {
65 inst->DstReg.WriteMask = RC_MASK_W;
67 inst->DstReg.WriteMask = 0;
H A Dradeon_dataflow_deadcode.c41 unsigned char WriteMask:4; member in struct:instruction_state
162 usedmask = *pused & inst->U.I.DstReg.WriteMask;
167 insts->WriteMask |= usedmask;
257 ptr->U.I.DstReg.WriteMask, srcmasks);
324 inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask;
325 if (s.Instructions[ip].WriteMask)
341 usemask = s.Instructions[ip].WriteMask;
H A Dradeon_variable.c60 if (var_ptr->Dst.WriteMask == RC_MASK_W) {
156 unsigned int mask = var->Readers[i].WriteMask;
285 new->Dst.WriteMask = DstWriteMask;
332 if (sub_inst->WriteMask) {
334 writemask = sub_inst->WriteMask;
373 inst->U.I.DstReg.WriteMask, &reader_data);
394 writemask |= var->Dst.WriteMask;
525 var->Inst->IP, var->Dst.Index, var->Dst.WriteMask);
H A Dradeon_program_tex.c92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
173 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
183 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
194 inst_mul->U.I.DstReg.WriteMask = RC_MASK_W;
210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W;
311 inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ;
333 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ;
342 inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ;
353 inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ;
368 inst_add->U.I.DstReg.WriteMask
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H A Dradeon_program.h60 unsigned int WriteMask:4; member in struct:rc_dst_register
H A Dradeon_program_pair.h74 unsigned int WriteMask:4; member in struct:rc_pair_sub_instruction
H A Dradeon_dataflow.h76 unsigned int WriteMask; member in struct:rc_reader
H A Dradeon_program_print.c164 if (dst.WriteMask != RC_MASK_XYZW) {
166 rc_print_mask(f, dst.WriteMask);
389 if (inst->RGB.WriteMask)
391 (inst->RGB.WriteMask & 1) ? "x" : "",
392 (inst->RGB.WriteMask & 2) ? "y" : "",
393 (inst->RGB.WriteMask & 4) ? "z" : "");
428 if (inst->Alpha.WriteMask)
/external/mesa3d/src/mesa/program/
H A Dprog_instruction.c54 inst[i].DstReg.WriteMask = WRITEMASK_XYZW;
307 if (inst->DstReg.WriteMask == WRITEMASK_X ||
308 inst->DstReg.WriteMask == WRITEMASK_Y ||
309 inst->DstReg.WriteMask == WRITEMASK_Z ||
310 inst->DstReg.WriteMask == WRITEMASK_W ||
311 inst->DstReg.WriteMask == 0x0) {
323 if (inst->DstReg.WriteMask & (1 << chan)) {
H A Dprog_optimize.c88 channel_mask = inst->DstReg.WriteMask & dst_mask;
134 const GLuint mask = mov->DstReg.WriteMask;
331 inst->DstReg.WriteMask & (1 << chan)) {
336 inst->DstReg.WriteMask &= ~(1 << chan);
341 if (inst->DstReg.WriteMask == 0) {
421 mask &= ~inst->DstReg.WriteMask;
523 dst_mask = mov->DstReg.WriteMask;
573 dst_mask &= ~inst2->DstReg.WriteMask;
581 src_mask &= ~inst2->DstReg.WriteMask;
613 const GLuint mask = inst->DstReg.WriteMask;
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H A Dprogramopt.c93 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i);
165 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW;
177 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW;
192 newInst[3].DstReg.WriteMask = WRITEMASK_XYZW;
324 inst->DstReg.WriteMask = WRITEMASK_X;
345 inst->DstReg.WriteMask = WRITEMASK_X;
359 inst->DstReg.WriteMask = WRITEMASK_X;
372 inst->DstReg.WriteMask = WRITEMASK_X;
384 inst->DstReg.WriteMask = WRITEMASK_XYZ;
399 inst->DstReg.WriteMask
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H A Dnvvertparse.c603 dstReg->WriteMask = 0;
606 dstReg->WriteMask |= WRITEMASK_X;
610 dstReg->WriteMask |= WRITEMASK_Y;
614 dstReg->WriteMask |= WRITEMASK_Z;
618 dstReg->WriteMask |= WRITEMASK_W;
627 dstReg->WriteMask = WRITEMASK_XYZW;
982 inst->DstReg.WriteMask = WRITEMASK_X;
/external/skia/src/gpu/
H A DGrUserStencilSettings.h118 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask> struct Init {};
128 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask>
129 constexpr static Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask> StaticInit() {
130 return Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>();
149 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask,
152 const Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>&)
156 Attrs::EffectiveWriteMask(WriteMask)}
160 Attrs::EffectiveWriteMask(WriteMask)} {
/external/mesa3d/src/mesa/main/
H A Dstencil.c259 * Updates gl_stencil_attrib::WriteMask. On change flushes the vertices and
276 if (ctx->Stencil.WriteMask[face] == mask)
279 ctx->Stencil.WriteMask[face] = mask;
290 if (ctx->Stencil.WriteMask[0] == mask &&
291 ctx->Stencil.WriteMask[1] == mask)
294 ctx->Stencil.WriteMask[0] = ctx->Stencil.WriteMask[1] = mask;
536 ctx->Stencil.WriteMask[0] = mask;
539 ctx->Stencil.WriteMask[1] = mask;
566 ctx->Stencil.WriteMask[
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/external/mesa3d/src/gallium/auxiliary/draw/
H A Ddraw_pipe_aapoint.c245 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XY;
259 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
276 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
288 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X;
301 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
334 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z;
350 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z;
363 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y;
379 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W;
395 newInst.Dst[0].Register.WriteMask
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/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_exec.c585 uint writemask = inst->Dst[0].Register.WriteMask;
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1908 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1987 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2059 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2088 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2200 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2263 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2424 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2450 if (inst->Dst[0].Register.WriteMask
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/external/mesa3d/src/mesa/drivers/dri/nouveau/
H A Dnv04_state_raster.c173 if (ctx->Stencil.WriteMask[0])
182 ctx->Stencil.WriteMask[0] << 24;
/external/mesa3d/src/mesa/state_tracker/
H A Dst_atom_depth.c118 dsa->stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
129 dsa->stencil[1].writemask = ctx->Stencil.WriteMask[back] & 0xff;

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