/external/elfutils/libelf/ |
H A D | elf_hash.c | 37 #include <dl-hash.h>
|
H A D | elf_strptr.c | 198 struct Elf_Data_List *dl = &strscn->data_list; local 199 while (dl != NULL) 201 if (offset >= (size_t) dl->data.d.d_off 202 && offset < dl->data.d.d_off + dl->data.d.d_size) 206 if (likely (memrchr ((char *) dl->data.d.d_buf 207 + (offset - dl->data.d.d_off), '\0', 208 (dl->data.d.d_size 209 - (offset - dl->data.d.d_off))) != NULL)) 210 result = ((char *) dl [all...] |
H A D | elf_gnu_hash.c | 37 #include <dl-hash.h>
|
/external/clang/test/CodeGenCXX/ |
H A D | debug-info-byval.cpp | 26 void get(int *i, unsigned dl, VAL v, VAL *p, unsigned n, EVT missing_arg) { argument 29 if (dl == n)
|
/external/syslinux/mbr/ |
H A D | adjust.h | 45 movb $0x80, %dl 50 movb $0x80, %dl
|
/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXSelectionDAGInfo.cpp | 29 PTXSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, argument 69 Loads[i] = DAG.getLoad(VT, dl, Chain, 70 DAG.getNode(ISD::ADD, dl, PointerType, Src, 77 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 81 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], 82 DAG.getNode(ISD::ADD, dl, PointerType, Dst, 88 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 108 Loads[i] = DAG.getLoad(VT, dl, Chain, 109 DAG.getNode(ISD::ADD, dl, PointerType, Src, 117 Chain = DAG.getNode(ISD::TokenFactor, dl, MV 142 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
H A D | SparcFrameLowering.cpp | 35 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); local 55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6) 61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); 63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) 65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6) 75 DebugLoc dl = MBBI->getDebugLoc(); local 78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
|
H A D | SparcISelLowering.cpp | 85 DebugLoc dl, SelectionDAG &DAG) const { 114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 128 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 129 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag); 139 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, 141 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, 153 DebugLoc dl, SelectionDAG &DAG, 176 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 188 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 198 LoVal = DAG.getLoad(MVT::i32, dl, Chai 81 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument 149 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 349 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 886 DebugLoc dl = Op.getDebugLoc(); local 907 DebugLoc dl = Op.getDebugLoc(); local 925 DebugLoc dl = Op.getDebugLoc(); local 933 DebugLoc dl = Op.getDebugLoc(); local 946 DebugLoc dl = Op.getDebugLoc(); local 978 DebugLoc dl = Op.getDebugLoc(); local 1010 DebugLoc dl = Op.getDebugLoc(); local 1027 DebugLoc dl = Node->getDebugLoc(); local 1058 DebugLoc dl = Op.getDebugLoc(); local 1075 DebugLoc dl = Op.getDebugLoc(); local 1086 DebugLoc dl = Op.getDebugLoc(); local 1117 DebugLoc dl = Op.getDebugLoc(); local 1170 DebugLoc dl = MI->getDebugLoc(); local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 255 SDLoc dl(N); 263 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); 267 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 271 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); 280 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 294 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 298 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); 305 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); 308 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 316 SDLoc dl( 2791 IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &dl) argument 2995 SDLoc dl = SDLoc(N); local [all...] |
H A D | LegalizeDAG.cpp | 97 const SDLoc &dl); 99 const SDLoc &dl); 105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl, 110 bool &NeedInvert, const SDLoc &dl); 114 unsigned NumOps, bool isSigned, const SDLoc &dl); 132 const SDLoc &dl); 144 const SDLoc &dl); 146 const SDLoc &dl); 148 const SDLoc &dl); 150 SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl); 214 ShuffleWithNarrowerEltType( EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef<int> Mask) const argument 313 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, const SDLoc &dl) argument 357 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, const SDLoc &dl) argument [all...] |
H A D | LegalizeTypesGeneric.cpp | 46 SDLoc dl(N); 63 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 64 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 75 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 76 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 89 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 90 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 97 std::tie(Lo, Hi) = DAG.SplitVector(InOp, dl, LoV [all...] |
/external/libchrome/base/ |
H A D | native_library_posix.cc | 31 void* dl = dlopen(library_path.value().c_str(), RTLD_LAZY); local 32 if (!dl && error) 35 return dl;
|
/external/ltp/tools/pounder21/ |
H A D | libpounder.sh | 58 for SERVER in voxel.dl.sourceforge.net easynews.dl.sourceforge.net umn.dl.sourceforge.net; do
|
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | SDNodeDbgValue.h | 54 SDDbgValue(MDNode *mdP, SDNode *N, unsigned R, uint64_t off, DebugLoc dl, argument 55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O), 63 SDDbgValue(MDNode *mdP, const Value *C, uint64_t off, DebugLoc dl, argument 65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { 71 SDDbgValue(MDNode *mdP, unsigned FI, uint64_t off, DebugLoc dl, unsigned O) : argument 72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
|
/external/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 48 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 88 CLI.setDebugLoc(dl).setChain(Chain) 133 Count = DAG.getIntPtrConstant(SizeVal, dl); 139 Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl); 143 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), 148 Count = DAG.getIntPtrConstant(SizeVal, dl); 149 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 153 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, 156 Chain = DAG.getCopyToReg(Chain, dl, Subtarge 47 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument 196 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
H A D | BlackfinFrameLowering.cpp | 52 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); local 63 RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize); 69 BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize); 79 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH)) 81 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH)) 83 BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP) 85 RegInfo->loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize); 86 BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP) 100 DebugLoc dl = MBBI->getDebugLoc(); local 108 RegInfo->adjustRegister(MBB, MBBI, dl, B [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 255 SDLoc dl(GA); 258 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); 263 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); 265 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); 330 SDLoc dl(CP); 340 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); 353 SDLoc dl(Op); 362 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); 365 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 366 DAG.getConstant(1, dl, MV 1043 SDLoc &dl = CLI.DL; local 1070 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument 1116 LowerCCCCallTo( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1251 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1270 LowerCCCArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1448 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const argument 1539 DebugLoc dl = MI.getDebugLoc(); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 29 ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, argument 66 Loads[i] = DAG.getLoad(VT, dl, Chain, 67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 78 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], 79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 105 Loads[i] = DAG.getLoad(VT, dl, Chain, 106 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 114 Chain = DAG.getNode(ISD::TokenFactor, dl, MV 142 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument [all...] |
/external/llvm/test/Bindings/OCaml/ |
H A D | target.ml | 45 let dl = DL.of_string layout in var 48 assert_equal (DL.as_string dl) layout; 49 assert_equal (DL.byte_order dl) Endian.Little; 50 assert_equal (DL.pointer_size dl) 4; 51 assert_equal (DL.intptr_type context dl) i32_type; 52 assert_equal (DL.qualified_pointer_size 0 dl) 4; 53 assert_equal (DL.qualified_intptr_type context 0 dl) i32_type; 54 assert_equal (DL.size_in_bits sty dl) (Int64.of_int 96); 55 assert_equal (DL.store_size sty dl) (Int64.of_int 12); 56 assert_equal (DL.abi_size sty dl) (Int6 [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 558 DebugLoc dl = Op.getDebugLoc(); local 598 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, 618 rotate = DAG.getNode(ISD::ADD, dl, PtrVT, 637 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); 638 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); 639 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); 643 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); 646 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, 653 rotate = DAG.getNode(ISD::ADD, dl, PtrVT, 659 SDValue low = DAG.getLoad(MVT::i128, dl, the_chai 763 DebugLoc dl = Op.getDebugLoc(); local 1005 DebugLoc dl = Op.getDebugLoc(); local 1037 DebugLoc dl = Op.getDebugLoc(); local 1064 DebugLoc dl = Op.getDebugLoc(); local 1088 DebugLoc dl = Op.getDebugLoc(); local 1107 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1258 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1455 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument 1646 DebugLoc dl = Op.getDebugLoc(); local 1722 LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, DebugLoc dl) argument 1828 DebugLoc dl = Op.getDebugLoc(); local 1946 DebugLoc dl = Op.getDebugLoc(); local 1996 DebugLoc dl = Op.getDebugLoc(); local 2160 DebugLoc dl = Op.getDebugLoc(); local 2195 DebugLoc dl = Op.getDebugLoc(); local 2301 DebugLoc dl = Op.getDebugLoc(); local 2354 DebugLoc dl = Op.getDebugLoc(); local 2514 DebugLoc dl = Op.getDebugLoc(); local 2651 DebugLoc dl = Op.getDebugLoc(); local 2678 DebugLoc dl = Op.getDebugLoc(); local 2716 DebugLoc dl = Op.getDebugLoc(); local 2908 DebugLoc dl = N->getDebugLoc(); local [all...] |
H A D | SPUFrameLowering.cpp | 97 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); local 119 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel); 124 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16) 128 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) 131 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) 136 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) 139 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) 141 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1) 144 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) 147 BuildMI(MBB, MBBI, dl, TI 195 DebugLoc dl = MBBI->getDebugLoc(); local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 25 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 92 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 94 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 115 CLI.setDebugLoc(dl) 129 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, 142 return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size, Align, 146 return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size, Align, 186 Dst = DAG.getNode(ARMISD::MEMCPY, dl, VTs, Chain, Dst, Src, 187 DAG.getConstant(NumRegs, dl, MVT::i32)); 212 Loads[i] = DAG.getLoad(VT, dl, Chai 24 EmitSpecializedLibcall( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, RTLIB::Libcall LC) const argument 128 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 248 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 256 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument [all...] |
H A D | ARMSelectionDAGInfo.h | 41 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, 49 EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, 56 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, 61 SDValue EmitSpecializedLibcall(SelectionDAG &DAG, const SDLoc &dl,
|
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 30 X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, argument 70 DAG, dl); 120 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 126 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 130 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 134 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 141 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 147 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, 149 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 155 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Ty 175 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSelectionDAGInfo.h | 23 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
|