Searched refs:lanes (Results 1 - 22 of 22) sorted by relevance

/external/gemmlowp/meta/generators/
H A Dzip_Nx8_neon.py29 """Prepares read lanes for the zip operation.
34 zip_lanes: number of lanes to prepare.
41 lanes = []
45 lanes.append(ZipLane(input_address,
50 lanes.append(ZipLane(address_register,
55 return lanes
67 def GenerateClearAggregators(emitter, lanes):
68 for lane in lanes:
72 def GenerateLoadAggregateStore(emitter, lanes, output_address, alignment):
73 """Emit inner loop code for reading N lanes an
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H A Dqnt_Nx8_neon.py26 def BuildName(lanes, leftovers, aligned):
27 name = 'qnt_%dx8' % lanes
35 def LoadAndDuplicateOffsets(emitter, registers, lanes, offsets):
36 if lanes == 1 or lanes == 2 or lanes == 3:
38 for unused_i in range(0, lanes):
47 raise ConfigurationError('Unsupported number of lanes: %d' % lanes)
58 """Prepare lanes fo
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H A Dmul_Nx8_Mx8_neon.py22 self.lanes = []
25 self.lanes.append(lane)
28 for i in range(0, len(self.lanes)):
29 registers.FreeRegister(self.lanes[i])
30 self.lanes[i] = None
34 lanes = MulLanes(address)
36 lanes.AddLane(registers.DoubleRegister())
37 return lanes
41 lanes = MulLanes(address)
42 lanes
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/external/v8/src/runtime/
H A Druntime-simd.cc173 #define CONVERT_SIMD_LANE_ARG_CHECKED(name, index, lanes) \
180 if (number < 0 || number >= lanes || !IsInt32Double(number)) { \
199 lane_type lanes[kLaneCount]; \
201 lanes[i] = op(a->get_lane(i)); \
203 Handle<type> result = isolate->factory()->New##type(lanes);
210 lane_type lanes[kLaneCount]; \
212 lanes[i] = op(a->get_lane(i), b->get_lane(i)); \
214 Handle<type> result = isolate->factory()->New##type(lanes);
221 bool lanes[kLaneCount]; \
223 lanes[
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/external/libhevc/common/arm/
H A Dihevc_intra_pred_luma_dc.s213 vdup.16 q12, d11[0] @3*dc + 2 (moved to all lanes)
454 vdup.16 q12, d11[0] @3*dc + 2 (moved to all lanes)
/external/mesa3d/src/gallium/drivers/nv50/codegen/
H A Dnv50_ir.cpp573 lanes = 0xf;
737 i->lanes = lanes;
H A Dnv50_ir_emit_nv50.cpp602 code[1] = 0x00200000 | (i->lanes << 14);
619 code[1] = 0x00200000 | (i->lanes << 14);
759 code[1] |= (i->lanes << 14);
1690 emitQUADOP(insn, insn->lanes, insn->subOp);
1759 if (i->join || i->lanes != 0xf || i->exit)
H A Dnv50_ir_build_util.cpp265 quadop->lanes = l;
H A Dnv50_ir.h696 unsigned lanes : 4;
H A Dnv50_ir_peephole.cpp2061 this->lanes != that->lanes ||
H A Dnv50_ir_lowering_nv50.cpp628 // The lanes of a quad are grouped by the bit in the condition register they
750 // mov coordinates from lane l to all lanes
753 // add dPdx from lane l to lanes dx
756 // add dPdy from lane l to lanes dy
769 mov->lanes = 1 << l;
/external/vixl/src/aarch64/
H A Doperands-aarch64.h198 // described. They do not consider the number of lanes that make up a vector.
201 // Check the number of lanes, ie. the format of the vector, using methods such
310 VRegister(unsigned code, unsigned size, unsigned lanes = 1)
311 : CPURegister(code, size, kVRegister), lanes_(lanes) {
379 // For consistency, we assert the number of lanes of these scalar registers,
401 VIXL_DEPRECATED("GetLanes", int lanes() const) { return GetLanes(); }
H A Dlogic-aarch64.cc1384 int lanes = LaneCountFromFormat(vform); local
1388 for (int i = 0; i < lanes; i += 2) {
1397 VIXL_ASSERT(((i >> 1) + (j * lanes / 2)) < kMaxLanesPerVector);
1398 result[(i >> 1) + (j * lanes / 2)] = dst_val;
1564 int lanes = LaneCountFromFormat(vform); local
1577 VIXL_ASSERT(((i >> 1) + (j * lanes / 2)) < kMaxLanesPerVector);
1578 result[(i >> 1) + (j * lanes / 2)] = dst_val;
/external/libvpx/libvpx/vpx_dsp/x86/
H A Dquantize_avx_x86_64.asm61 pcmpeqw m4, m4 ; All word lanes -1
208 pcmpeqw m4, m4 ; All lanes -1
/external/mesa3d/src/gallium/drivers/nvc0/codegen/
H A Dnv50_ir_emit_nvc0.cpp1508 opc |= i->lanes << 5;
1720 emitQUADOP(insn, insn->subOp, insn->lanes);
1780 if (i->op == OP_MOV && i->lanes != 0xf) {
H A Dnv50_ir_lowering_nvc0.cpp772 // mov coordinates from lane l to all lanes
775 // add dPdx from lane l to lanes dx
778 // add dPdy from lane l to lanes dy
791 mov->lanes = 1 << l;
/external/v8/src/
H A Dfactory.h439 Handle<Type> New##Type(lane_type lanes[lane_count], \
H A Dfactory.cc1280 Handle<Type> Factory::New##Type(lane_type lanes[lane_count], \
1283 isolate(), isolate()->heap()->Allocate##Type(lanes, pretenure), Type); \
/external/v8/src/heap/
H A Dheap.h1933 AllocationResult Allocate##Type(lane_type lanes[lane_count], \
H A Dheap.cc2431 AllocationResult Heap::Allocate##Type(lane_type lanes[lane_count], \
2448 instance->set_lane(i, lanes[i]); \
/external/valgrind/none/tests/arm/
H A Dneon64.stdout.exp2007 ---- VLD1 (single element to all lanes) ----
2048 ---- VLD2 (2-elements to all lanes) ----
2086 ---- VLD3 (3-elements to all lanes) ----
2124 ---- VLD4 (4-elements to all lanes) ----
2293 ---- VLD1 (single element to all lanes) ----
2334 ---- VLD2 (2-elements to all lanes) ----
2372 ---- VLD3 (3-elements to all lanes) ----
2410 ---- VLD4 (4-elements to all lanes) ----
2579 ---- VLD1 (single element to all lanes) ----
2620 ---- VLD2 (2-elements to all lanes)
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/external/vixl/src/aarch32/
H A Ddisasm-aarch32.cc84 DecodeNeonAndAlign(int lanes, SpacingType spacing, Alignment align) argument
85 : DecodeNeon(lanes, spacing), align_(align) {}
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