/external/llvm/test/MC/AArch64/ |
H A D | alias-addsubimm.s | 3 // CHECK: sub w0, w2, #2, lsl #12 4 // CHECK: sub w0, w2, #2, lsl #12 5 sub w0, w2, #2, lsl 12 6 add w0, w2, #-2, lsl 12 7 // CHECK: sub x1, x3, #2, lsl #12 8 // CHECK: sub x1, x3, #2, lsl #12 9 sub x1, x3, #2, lsl 12 10 add x1, x3, #-2, lsl 12 17 sub x1, x3, #4095, lsl 0 18 add x1, x3, #-4095, lsl [all...] |
H A D | neon-mov.s | 11 movi v15.2s, #1, lsl #8 12 movi v16.2s, #1, lsl #16 13 movi v31.2s, #1, lsl #24 15 movi v0.4s, #1, lsl #8 16 movi v0.4s, #1, lsl #16 17 movi v0.4s, #1, lsl #24 19 movi v0.4h, #1, lsl #8 21 movi v0.8h, #1, lsl #8 25 // CHECK: movi v15.2s, #{{0x1|1}}, lsl #8 // encoding: [0x2f,0x24,0x00,0x0f] 26 // CHECK: movi v16.2s, #{{0x1|1}}, lsl #1 [all...] |
H A D | arm64-optional-hash.s | 8 ; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1] 9 adds x3, x4, 1024, lsl 12 30 ; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8] 31 prfm pstl3strm, [x4, x5, lsl 3]
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H A D | arm64-aliases.s | 43 ands wzr, w1, w2, lsl #2 44 ands xzr, x1, x2, lsl #3 45 tst w3, w7, lsl #31 52 ; CHECK: tst w1, w2, lsl #2 ; encoding: [0x3f,0x08,0x02,0x6a] 53 ; CHECK: tst x1, x2, lsl #3 ; encoding: [0x3f,0x0c,0x02,0xea] 54 ; CHECK: tst w3, w7, lsl #31 ; encoding: [0x7f,0x7c,0x07,0x6a] 60 cmn w1, #3, lsl #0 70 ; CHECK: cmn x2, #0x400, lsl #12 ; encoding: [0x5f,0x00,0x50,0xb1] 82 cmp w1, #1024, lsl #12 93 cmp wsp, w9, lsl # [all...] |
H A D | arm64-arithmetic-encoding.s | 33 add w3, w4, #1024, lsl #0 35 add x3, x4, #1024, lsl #0 42 add w3, w4, #1024, lsl #12 44 add w3, w4, #0, lsl #12 45 add x3, x4, #1024, lsl #12 47 add x3, x4, #0, lsl #12 50 ; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11] 51 ; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11] 52 ; CHECK: add w3, w4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x11] 53 ; CHECK: add x3, x4, #1024, lsl #1 [all...] |
H A D | arm64-leaf-compact-unwind.s | 90 str w9, [x8, x9, lsl #2] 175 sub w8, w8, w7, lsl #1 176 sub w8, w8, w6, lsl #1 177 sub w8, w8, w5, lsl #1 178 sub w8, w8, w4, lsl #1 179 sub w8, w8, w3, lsl #1 180 sub w8, w8, w2, lsl #1 181 sub w0, w8, w1, lsl #1 210 str w11, [x8, x9, lsl #2]
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H A D | arm64-logical-encoding.s | 52 and w1, w2, w3, lsl #2 53 and x1, x2, x3, lsl #2 63 ; CHECK: and w1, w2, w3, lsl #2 ; encoding: [0x41,0x08,0x03,0x0a] 64 ; CHECK: and x1, x2, x3, lsl #2 ; encoding: [0x41,0x08,0x03,0x8a] 74 ands w1, w2, w3, lsl #2 75 ands x1, x2, x3, lsl #2 85 ; CHECK: ands w1, w2, w3, lsl #2 ; encoding: [0x41,0x08,0x03,0x6a] 86 ; CHECK: ands x1, x2, x3, lsl #2 ; encoding: [0x41,0x08,0x03,0xea] 96 bic w1, w2, w3, lsl #3 97 bic x1, x2, x3, lsl # [all...] |
H A D | basic-a64-diagnostics.s | 12 // CHECK-ERROR: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4] 15 // CHECK-ERROR: error: expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4] 29 // CHECK-ERROR: error: expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4] 32 // CHECK-ERROR: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4] 40 // CHECK-ERROR: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 63] 58 // CHECK-ERROR: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 63] 68 // Amount not optional if lsl valid and used 69 add sp, x5, x7, lsl 71 // CHECK-ERROR: add sp, x5, x7, lsl 81 add w4, w5, #-4096, lsl #1 [all...] |
/external/compiler-rt/lib/builtins/arm/ |
H A D | switch16.S | 36 add r0, lr, r0, lsl #1 // compute address of element in table 37 add ip, lr, ip, lsl #1 // compute address of last element in table 41 add ip, lr, r0, lsl #1 // compute label = lr + element*2
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H A D | switch32.S | 36 add r0, lr, r0, lsl #2 // compute address of element in table 37 add ip, lr, ip, lsl #2 // compute address of last element in table
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H A D | comparesf2.S | 47 mov r2, r0, lsl #1 48 mov r3, r1, lsl #1 114 mov r2, r0, lsl #1 115 mov r3, r1, lsl #1 138 mov r2, r0, lsl #1 139 mov r3, r1, lsl #1
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H A D | switch8.S | 39 add ip, lr, r0, lsl #1 // compute label = lr + element*2
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H A D | switchu8.S | 39 add ip, lr, r0, lsl #1 // compute label = lr + element*2
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H A D | udivmodsi4.S | 72 sub ip, ip, r3, lsl #1 76 sub ip, ip, r3, lsl #2 77 sub ip, ip, r3, lsl #3 122 cmp r0, r1, lsl IMM shift; \ 125 WIDE(subhs) r0, r0, r1, lsl IMM shift
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H A D | udivsi3.S | 72 sub ip, ip, r3, lsl #1 76 sub ip, ip, r3, lsl #2 77 sub ip, ip, r3, lsl #3 119 cmp r0, r1, lsl IMM shift; \ 122 WIDE(subhs) r0, r0, r1, lsl IMM shift
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/external/libvpx/libvpx/build/make/ |
H A D | thumb.pm | 19 # Write additions with shifts, such as "add r10, r11, lsl #8", 20 # in three operand form, "add r10, r10, r11, lsl #8". 21 s/(add\s+)(r\d+),\s*(r\d+),\s*(lsl #\d+)/$1$2, $2, $3, $4/g; 28 # This converts instructions such as "add r12, r12, r5, lsl r4" 29 # into the sequence "lsl r5, r4", "add r12, r12, r5", "lsr r5, r4". 30 s/^(\s*)(add)(\s+)(r\d+),\s*(r\d+),\s*(r\d+),\s*lsl (r\d+)/$1lsl$3$6, $7\n$1$2$3$4, $5, $6\n$1lsr$3$6, $7/g; 44 # This converts "ldrne r4, [src, -pstep, lsl #1]" into 45 # "subne src, src, pstep, lsl #1", "ldrne r4, [src]", 46 # "addne src, src, pstep, lsl # [all...] |
/external/valgrind/none/tests/arm/ |
H A D | v6intThumb.stdout.exp | 2145 adds.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 2146 adds.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 2147 adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 2148 adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000 2157 add.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ 2158 add.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ 2159 add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ 2160 add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ 2169 adds.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N 2170 adds.w r1, r2, r3, lsl # [all...] |
/external/boringssl/linux-arm/crypto/aes/ |
H A D | aes-armv4.S | 185 orr r0,r0,r4,lsl#8 187 orr r0,r0,r5,lsl#16 189 orr r0,r0,r6,lsl#24 192 orr r1,r1,r4,lsl#8 194 orr r1,r1,r5,lsl#16 196 orr r1,r1,r6,lsl#24 199 orr r2,r2,r4,lsl#8 201 orr r2,r2,r5,lsl#16 203 orr r2,r2,r6,lsl#24 206 orr r3,r3,r4,lsl# [all...] |
/external/boringssl/src/crypto/aes/asm/ |
H A D | aes-armv4.pl | 215 orr $s0,$s0,$t1,lsl#8 217 orr $s0,$s0,$t2,lsl#16 219 orr $s0,$s0,$t3,lsl#24 222 orr $s1,$s1,$t1,lsl#8 224 orr $s1,$s1,$t2,lsl#16 226 orr $s1,$s1,$t3,lsl#24 229 orr $s2,$s2,$t1,lsl#8 231 orr $s2,$s2,$t2,lsl#16 233 orr $s2,$s2,$t3,lsl#24 236 orr $s3,$s3,$t1,lsl# [all...] |
/external/boringssl/src/crypto/modes/asm/ |
H A D | ghash-armv4.pl | 184 add $Zhh,$Htbl,$nlo,lsl#4 194 eor $Zll,$Zll,$Zlh,lsl#28 197 eor $Zlh,$Zlh,$Zhl,lsl#28 199 eor $Zhl,$Zhl,$Zhh,lsl#28 204 eor $Zhh,$Zhh,$Tll,lsl#16 207 add $Thh,$Htbl,$nlo,lsl#4 213 eor $Zll,$Zll,$Zlh,lsl#28 215 eor $Zlh,$Zlh,$Zhl,lsl#28 219 eor $Zhl,$Zhl,$Zhh,lsl#28 224 eor $Zhh,$Zhh,$Tll,lsl#1 [all...] |
/external/libvpx/libvpx/vpx_dsp/arm/ |
H A D | vpx_convolve_copy_neon_asm.asm | 34 pld [r0, r1, lsl #1] 44 pld [r0, r1, lsl #1] 46 pld [r0, r1, lsl #1] 55 pld [r0, r1, lsl #1] 57 pld [r0, r1, lsl #1] 66 pld [r0, r1, lsl #1] 68 pld [r0, r1, lsl #1]
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/external/libhevc/common/arm/ |
H A D | ihevc_deblk_chroma_horz.s | 81 ldrle r1,[r3,r1,lsl #2] 88 ldrle r2,[r3,r2,lsl #2] 91 add r1,r1,r4,lsl #1 107 add r2,r2,r4,lsl #1 110 ldr r1,[r3,r1,lsl #2] 120 ldr r2,[r3,r2,lsl #2]
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H A D | ihevc_deblk_chroma_vert.s | 81 ldrle r3,[r7,r3,lsl #2] 89 ldrle r2,[r7,r2,lsl #2] 93 add r3,r3,r5,lsl #1 109 add r2,r2,r5,lsl #1 113 ldr r3,[r6,r3,lsl #2] 125 ldr r2,[r6,r2,lsl #2]
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/external/llvm/test/MC/ARM/ |
H A D | arm-aliases.s | 4 @ Shift-by-zero should canonicalize to no shift at all (lsl #0 encoding) 5 add r1, r2, r3, lsl #0 10 bic r1, r2, r3, lsl #0
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H A D | arm-shift-encoding.s | 6 ldr r0, [r0, r0, lsl #0] 7 ldr r0, [r0, r0, lsl #16] 17 @ CHECK: ldr r0, [r0, r0, lsl #16] @ encoding: [0x00,0x08,0x90,0xe7] 26 pld [r0, r0, lsl #0] 27 pld [r0, r0, lsl #16] 37 @ CHECK: [r0, r0, lsl #16] @ encoding: [0x00,0xf8,0xd0,0xf7] 46 str r0, [r0, r0, lsl #0] 47 str r0, [r0, r0, lsl #16] 57 @ CHECK: str r0, [r0, r0, lsl #16] @ encoding: [0x00,0x08,0x80,0xe7] 70 str r6, [r7], r8, lsl # [all...] |