/external/llvm/test/MC/AArch64/ |
H A D | neon-mla-mls-instructions.s | 8 mla v0.8b, v1.8b, v2.8b 9 mla v0.16b, v1.16b, v2.16b 10 mla v0.4h, v1.4h, v2.4h 11 mla v0.8h, v1.8h, v2.8h 12 mla v0.2s, v1.2s, v2.2s 13 mla v0.4s, v1.4s, v2.4s 15 // CHECK: mla v0.8b, v1.8b, v2.8b // encoding: [0x20,0x94,0x22,0x0e] 16 // CHECK: mla v0.16b, v1.16b, v2.16b // encoding: [0x20,0x94,0x22,0x4e] 17 // CHECK: mla v0.4h, v1.4h, v2.4h // encoding: [0x20,0x94,0x62,0x0e] 18 // CHECK: mla v [all...] |
H A D | neon-2velem.s | 9 mla v0.2s, v1.2s, v2.s[2] 10 mla v0.2s, v1.2s, v22.s[2] 11 mla v3.4s, v8.4s, v2.s[1] 12 mla v3.4s, v8.4s, v22.s[3] 14 // CHECK: mla v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x08,0x82,0x2f] 15 // CHECK: mla v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x08,0x96,0x2f] 16 // CHECK: mla v3.4s, v8.4s, v2.s[1] // encoding: [0x03,0x01,0xa2,0x6f] 17 // CHECK: mla v3.4s, v8.4s, v22.s[3] // encoding: [0x03,0x09,0xb6,0x6f] 19 mla v0.4h, v1.4h, v2.h[2] 20 mla v [all...] |
H A D | neon-diagnostics.s | 114 mla v0.16b, v1.8b, v2.8b 118 // CHECK-ERROR: mla v0.16b, v1.8b, v2.8b 2949 mla v0.2d, v1.2d, v16.d[1] 2950 mla v0.2s, v1.2s, v2.s[4] 2951 mla v0.4s, v1.4s, v2.s[4] 2952 mla v0.2h, v1.2h, v2.h[1] 2953 mla v0.4h, v1.4h, v2.h[8] 2954 mla v0.8h, v1.8h, v2.h[8] 2955 mla v0.4h, v1.4h, v16.h[2] 2956 mla v [all...] |
H A D | arm64-advsimd.s | 334 mla.8b v0, v0, v0 405 ; CHECK: mla.8b v0, v0, v0 ; encoding: [0x00,0x94,0x20,0x0e] 1217 mla.4h v0, v0, v0[0] 1218 mla.8h v0, v0, v0[1] 1219 mla.2s v0, v0, v0[2] 1220 mla.4s v0, v0, v0[3] 1286 ; CHECK: mla.4h v0, v0, v0[0] ; encoding: [0x00,0x00,0x40,0x2f] 1287 ; CHECK: mla.8h v0, v0, v0[1] ; encoding: [0x00,0x00,0x50,0x6f] 1288 ; CHECK: mla.2s v0, v0, v0[2] ; encoding: [0x00,0x08,0x80,0x2f] 1289 ; CHECK: mla [all...] |
/external/libavc/common/armv8/ |
H A D | ih264_inter_pred_filters_luma_vert_av8.s | 142 mla v14.8h, v12.8h, v22.8h // temp += temp1 * 20 145 mla v20.8h, v18.8h , v22.8h // temp4 += temp3 * 20 152 mla v16.8h, v12.8h , v22.8h 159 mla v14.8h, v12.8h , v22.8h 166 mla v18.8h, v12.8h , v22.8h 173 mla v16.8h, v12.8h , v22.8h 181 mla v14.8h, v12.8h , v22.8h 187 mla v18.8h, v12.8h , v22.8h 201 mla v14.8h, v12.8h , v22.8h // temp += temp1 * 20 205 mla v2 [all...] |
H A D | ih264_weighted_bi_pred_av8.s | 179 mla v4.8h, v6.8h , v2.h[2] //weight 2 mult. for rows 1,2 181 mla v8.8h, v10.8h , v2.h[2] //weight 2 mult. for rows 3,4 211 mla v4.8h, v6.8h , v2.h[2] //weight 2 mult. for row 1 215 mla v8.8h, v10.8h , v2.h[2] //weight 2 mult. for row 2 219 mla v12.8h, v14.8h , v2.h[2] //weight 2 mult. for row 3 221 mla v16.8h, v18.8h , v2.h[2] //weight 2 mult. for row 4 257 mla v20.8h, v22.8h , v2.h[2] //weight 2 mult. for row 1L 261 mla v4.8h, v6.8h , v2.h[2] //weight 2 mult. for row 1H 265 mla v24.8h, v26.8h , v2.h[2] //weight 2 mult. for row 2L 269 mla v [all...] |
H A D | ih264_inter_pred_luma_vert_qpel_av8.s | 149 mla v14.8h, v12.8h , v22.8h // temp += temp1 * 20 152 mla v20.8h, v18.8h , v22.8h // temp4 += temp3 * 20 159 mla v16.8h, v12.8h , v22.8h 166 mla v14.8h, v12.8h , v22.8h 175 mla v18.8h, v12.8h , v22.8h 182 mla v16.8h, v12.8h , v22.8h 192 mla v14.8h, v12.8h , v22.8h 198 mla v18.8h, v12.8h , v22.8h 216 mla v14.8h, v12.8h , v22.8h // temp += temp1 * 20 222 mla v2 [all...] |
H A D | ih264_inter_pred_luma_horz_hpel_vert_hpel_av8.s | 117 mla v18.8h, v20.8h , v28.8h 121 mla v20.8h, v24.8h , v28.8h 127 mla v22.8h, v24.8h , v28.8h 198 mla v18.8h, v20.8h , v28.8h 202 mla v20.8h, v24.8h , v28.8h 208 mla v22.8h, v24.8h , v28.8h 277 mla v18.8h, v20.8h , v28.8h 281 mla v20.8h, v24.8h , v28.8h 287 mla v22.8h, v24.8h , v28.8h 359 mla v1 [all...] |
H A D | ih264_inter_pred_luma_horz_hpel_vert_qpel_av8.s | 171 mla v6.8h, v8.8h , v22.8h 185 mla v8.8h, v10.8h , v22.8h 199 mla v10.8h, v12.8h , v22.8h 213 mla v12.8h, v14.8h , v22.8h 227 mla v14.8h, v16.8h , v22.8h 244 mla v16.8h, v18.8h , v22.8h 272 mla v20.8h, v2.8h , v22.8h 315 mla v8.8h, v2.8h , v22.8h 353 mla v28.8h, v2.8h , v22.8h 419 mla v [all...] |
H A D | ih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s | 179 mla v18.8h, v20.8h , v28.8h 183 mla v20.8h, v24.8h , v28.8h 189 mla v22.8h, v24.8h , v28.8h 266 mla v18.8h, v20.8h , v28.8h 270 mla v20.8h, v24.8h , v28.8h 276 mla v22.8h, v24.8h , v28.8h 350 mla v18.8h, v20.8h , v28.8h 354 mla v20.8h, v24.8h , v28.8h 360 mla v22.8h, v24.8h , v28.8h 437 mla v1 [all...] |
H A D | ih264_deblk_luma_av8.s | 369 mla v12.8h, v8.8h , v1.h[0] //(p0+q0+p1)+3*p2+2*p3 L 370 mla v4.8h, v16.8h , v1.h[0] //(p0+q0+p1)+3*p2+2*p3 H 883 mla v24.8h, v20.8h , v28.8h //p2 + X2(p1) + X2(p0) + X2(q0) + q1 L 884 mla v26.8h, v22.8h , v28.8h //p2 + X2(p1) + X2(p0) + X2(q0) + q1 H 959 mla v14.8h, v18.8h , v28.8h //p1 + X2(p0) + X2(q0) + X2(q1) + q2L 961 mla v4.8h, v26.8h , v28.8h //p1 + X2(p0) + X2(q0) + X2(q1) + q2H 994 mla v18.8h, v16.8h , v28.8h //X2(q3) + X3(q2) + q1 + q0 + p0 L 998 mla v26.8h, v4.8h , v28.8h //X2(q3) + X3(q2) + q1 + q0 + p0 H
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H A D | ih264_deblk_chroma_av8.s | 521 mla v14.8h, v18.8h , v28.8h 522 mla v16.8h, v20.8h , v28.8h //4*(q0 - p0) + (p1 - q1)
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H A D | ih264_resi_trans_quant_av8.s | 652 mla v25.4s, v2.4s, v30.4s 653 mla v26.4s, v3.4s, v30.4s
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/external/llvm/test/MC/ARM/ |
H A D | directive-arch-armv4.s | 33 mla r4, r5, r6, r3
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H A D | mul-v4.s | 14 @ ARMV4: mla r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0xe0] 18 mla r0, r1, r2, r3 label
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/external/libhevc/common/arm/ |
H A D | ihevc_weighted_pred_bi.s | 159 mla r4,r12,r8,r4 @(lvl_shift1 * wgt0) + (lvl_shift2 * wgt1)
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/external/libhevc/common/arm64/ |
H A D | ihevc_deblk_luma_vert.s | 234 mla v20.8h, v0.8h, v16.8h 286 mla v26.8h, v0.8h, v16.8h
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/external/v8/src/compiler/arm/ |
H A D | code-generator-arm.cc | 895 __ mla(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1), 1067 __ mla(i.OutputRegister(1), i.InputRegister(0), i.InputRegister(3), 1069 __ mla(i.OutputRegister(1), i.InputRegister(2), i.InputRegister(1),
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/external/v8/src/arm/ |
H A D | disasm-arm.cc | 742 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
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H A D | assembler-arm.h | 890 void mla(Register dst, Register src1, Register src2, Register srcA,
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/external/vixl/src/aarch64/ |
H A D | logic-aarch64.cc | 822 LogicVRegister Simulator::mla(VectorFormat vform, function in class:vixl::aarch64::Simulator 867 LogicVRegister Simulator::mla(VectorFormat vform, function in class:vixl::aarch64::Simulator 874 return mla(vform, dst, src1, dup_element(indexform, temp, src2, index)); 3226 mla(vform, dst, temp1, temp2); 3238 mla(vform, dst, temp1, temp2); 3250 mla(vform, dst, temp1, temp2); 3262 mla(vform, dst, temp1, temp2);
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H A D | assembler-aarch64.h | 1570 void mla(const VRegister& vd, const VRegister& vn, const VRegister& vm); 1585 void mla(const VRegister& vd,
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/external/vixl/test/aarch64/ |
H A D | test-trace-aarch64.cc | 1234 __ mla(v29.V16B(), v7.V16B(), v26.V16B()); 1235 __ mla(v6.V2S(), v4.V2S(), v14.V2S()); 1236 __ mla(v9.V2S(), v11.V2S(), v0.S(), 2); 1237 __ mla(v5.V4H(), v17.V4H(), v25.V4H()); 1238 __ mla(v24.V4H(), v7.V4H(), v11.H(), 3); 1239 __ mla(v12.V4S(), v3.V4S(), v4.V4S()); 1240 __ mla(v10.V4S(), v7.V4S(), v7.S(), 3); 1241 __ mla(v3.V8B(), v16.V8B(), v9.V8B()); 1242 __ mla(v19.V8H(), v22.V8H(), v18.V8H()); 1243 __ mla(v [all...] |
/external/valgrind/none/tests/arm64/ |
H A D | fp_and_simd.c | 3009 GEN_THREEVEC_TEST(mla_4s_4s_s0, "mla v2.4s, v11.4s, v29.s[0]", 2, 11, 29) 3010 GEN_THREEVEC_TEST(mla_4s_4s_s3, "mla v2.4s, v11.4s, v29.s[3]", 2, 11, 29) 3011 GEN_THREEVEC_TEST(mla_2s_2s_s0, "mla v2.2s, v11.2s, v29.s[0]", 2, 11, 29) 3012 GEN_THREEVEC_TEST(mla_2s_2s_s3, "mla v2.2s, v11.2s, v29.s[3]", 2, 11, 29) 3014 GEN_THREEVEC_TEST(mla_8h_8h_h1, "mla v2.8h, v11.8h, v2.h[1]", 2, 11, 9) 3015 GEN_THREEVEC_TEST(mla_8h_8h_h5, "mla v2.8h, v11.8h, v2.h[5]", 2, 11, 9) 3016 GEN_THREEVEC_TEST(mla_4h_4h_h2, "mla v2.4h, v11.4h, v2.h[2]", 2, 11, 9) 3017 GEN_THREEVEC_TEST(mla_4h_4h_h7, "mla v2.4h, v11.4h, v2.h[7]", 2, 11, 9) 3037 GEN_BINARY_TEST(mla, 4s, 4s, 4s) 3038 GEN_BINARY_TEST(mla, [all...] |
/external/valgrind/none/tests/arm/ |
H A D | v6intARM.stdout.exp | 509 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 510 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 511 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 512 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 513 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000 514 mla r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000
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