Searched refs:regR (Results 1 - 9 of 9) sorted by relevance

/external/valgrind/none/tests/amd64/
H A Dbug137714-amd64.c17 void maskmovq_mmx ( UChar* regL, UChar* regR )
31 : /*in*/ "r"(regL), "r"(regR), "r"(&dst[0])
39 void maskmovdqu_sse ( UChar* regL, UChar* regR )
53 : /*in*/ "r"(regL), "r"(regR), "r"(dst)
68 UChar* regR = malloc(8); local
70 assert(regR);
78 regR[j] = (UChar)randomUInt();
79 printf("%02x", regR[j]);
82 maskmovq_mmx( regR, regL );
90 UChar* regR local
[all...]
/external/valgrind/none/tests/x86/
H A Dbug137714-x86.c17 void maskmovq_mmx ( UChar* regL, UChar* regR )
31 : /*in*/ "r"(regL), "r"(regR), "r"(&dst[0])
39 void maskmovdqu_sse ( UChar* regL, UChar* regR )
53 : /*in*/ "r"(regL), "r"(regR), "r"(dst)
68 UChar* regR = malloc(8); local
70 assert(regR);
78 regR[j] = (UChar)randomUInt();
79 printf("%02x", regR[j]);
82 maskmovq_mmx( regR, regL );
90 UChar* regR local
[all...]
/external/valgrind/VEX/priv/
H A Dhost_arm64_isel.c1703 HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2); local
1706 addInstr(env, ARM64Instr_MovI(hregARM64_X1(), regR));
H A Dhost_mips_isel.c1352 HReg regR = iselWordExpr_R(env, e->Iex.Binop.arg2); local
1355 addInstr(env, mk_iMOVds_RR(hregMIPS_GPR5(env->mode64), regR));
H A Dhost_x86_isel.c1030 HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2); local
1031 addInstr(env, mk_iMOVsd_RR(regR,hregX86_ECX()));
H A Dhost_amd64_isel.c1073 HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2); local
1074 addInstr(env, mk_iMOVsd_RR(regR,hregAMD64_RCX()));
H A Dhost_arm_isel.c1493 HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2); local
1496 addInstr(env, mk_iMOVds_RR(hregARM_R1(), regR));
/external/sqlite/dist/orig/
H A Dsqlite3.c110056 int regR; /* Range of registers holding conflicting PK */ local
[all...]
/external/sqlite/dist/
H A Dsqlite3.c110056 int regR; /* Range of registers holding conflicting PK */ local
[all...]

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