Searched refs:tiling (Results 1 - 25 of 110) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i915/
H A Dintel_regions.c136 if (region->tiling != I915_TILING_NONE)
156 if (region->tiling != I915_TILING_NONE)
171 uint32_t tiling, drm_intel_bo *buffer)
185 region->tiling = tiling;
194 uint32_t tiling,
208 &tiling, &aligned_pitch, flags);
213 aligned_pitch / cpp, tiling, buffer);
247 uint32_t bit_6_swizzle, tiling; local
266 ret = drm_intel_bo_get_tiling(buffer, &tiling,
168 intel_region_alloc_internal(struct intel_screen *screen, GLuint cpp, GLuint width, GLuint height, GLuint pitch, uint32_t tiling, drm_intel_bo *buffer) argument
193 intel_region_alloc(struct intel_screen *screen, uint32_t tiling, GLuint cpp, GLuint width, GLuint height, bool expect_accelerated_upload) argument
411 uint32_t tiling = region->tiling; local
444 uint32_t tiling = region->tiling; local
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H A Dintel_tex_copy.c108 if (intelImage->mt->region->tiling == I915_TILING_Y) {
127 region->tiling,
131 intelImage->mt->region->tiling,
H A Dintel_clear.c126 * the tiling bits to determine how to clear. */
135 if (stencilRegion->tiling == I915_TILING_Y ||
155 if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL)
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dintel_regions.c136 if (region->tiling != I915_TILING_NONE)
156 if (region->tiling != I915_TILING_NONE)
171 uint32_t tiling, drm_intel_bo *buffer)
185 region->tiling = tiling;
194 uint32_t tiling,
208 &tiling, &aligned_pitch, flags);
213 aligned_pitch / cpp, tiling, buffer);
247 uint32_t bit_6_swizzle, tiling; local
266 ret = drm_intel_bo_get_tiling(buffer, &tiling,
168 intel_region_alloc_internal(struct intel_screen *screen, GLuint cpp, GLuint width, GLuint height, GLuint pitch, uint32_t tiling, drm_intel_bo *buffer) argument
193 intel_region_alloc(struct intel_screen *screen, uint32_t tiling, GLuint cpp, GLuint width, GLuint height, bool expect_accelerated_upload) argument
411 uint32_t tiling = region->tiling; local
444 uint32_t tiling = region->tiling; local
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H A Dintel_tex_copy.c108 if (intelImage->mt->region->tiling == I915_TILING_Y) {
127 region->tiling,
131 intelImage->mt->region->tiling,
/external/mesa3d/src/mesa/drivers/dri/intel/
H A Dintel_regions.c136 if (region->tiling != I915_TILING_NONE)
156 if (region->tiling != I915_TILING_NONE)
171 uint32_t tiling, drm_intel_bo *buffer)
185 region->tiling = tiling;
194 uint32_t tiling,
208 &tiling, &aligned_pitch, flags);
213 aligned_pitch / cpp, tiling, buffer);
247 uint32_t bit_6_swizzle, tiling; local
266 ret = drm_intel_bo_get_tiling(buffer, &tiling,
168 intel_region_alloc_internal(struct intel_screen *screen, GLuint cpp, GLuint width, GLuint height, GLuint pitch, uint32_t tiling, drm_intel_bo *buffer) argument
193 intel_region_alloc(struct intel_screen *screen, uint32_t tiling, GLuint cpp, GLuint width, GLuint height, bool expect_accelerated_upload) argument
411 uint32_t tiling = region->tiling; local
444 uint32_t tiling = region->tiling; local
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H A Dintel_tex_copy.c108 if (intelImage->mt->region->tiling == I915_TILING_Y) {
127 region->tiling,
131 intelImage->mt->region->tiling,
H A Dintel_regions.h70 uint32_t tiling; /**< Which tiling mode the region is in */ member in struct:intel_region
81 uint32_t tiling,
/external/vulkan-validation-layers/loader/
H A Dextensions.h36 VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags,
H A Dextensions.c35 VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags,
44 unwrapped_phys_dev, format, type, tiling, usage, flags,
51 VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags,
72 phys_dev->phys_dev, format, type, tiling, usage, flags,
77 phys_dev->phys_dev, format, type, tiling, usage, flags,
33 vkGetPhysicalDeviceExternalImageFormatPropertiesNV( VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags, VkExternalMemoryHandleTypeFlagsNV externalHandleType, VkExternalImageFormatPropertiesNV *pExternalImageFormatProperties) argument
49 terminator_GetPhysicalDeviceExternalImageFormatPropertiesNV( VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags, VkExternalMemoryHandleTypeFlagsNV externalHandleType, VkExternalImageFormatPropertiesNV *pExternalImageFormatProperties) argument
/external/mesa3d/src/gallium/drivers/i915/
H A Di915_screen.h50 boolean tiling; member in struct:i915_screen::__anon14541
H A Di915_winsys.h153 * the tiling mode provide in *tiling. If tiling is no possible, *tiling will
160 enum i915_winsys_buffer_tile *tiling,
172 enum i915_winsys_buffer_tile *tiling,
H A Di915_state_static.c79 buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling) argument
83 switch (tiling) {
110 buf_3d_tiling_bits(tex->tiling);
135 buf_3d_tiling_bits(tex->tiling);
219 if (is->is_i945 && tex->tiling != I915_TILE_NONE
H A Di915_resource.h69 /* tiling flags */
70 enum i915_winsys_buffer_tile tiling; member in struct:i915_texture
/external/skia/src/gpu/vk/
H A DGrVkImage.h91 void setNewResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling);
106 Resource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling) argument
107 : fImage(image), fAlloc(alloc), fImageTiling(tiling) {}
129 BorrowedResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling) argument
130 : Resource(image, alloc, tiling) {
/external/drm_gralloc/
H A Dgralloc_drm_radeon.c81 static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling) argument
86 if (tiling & RADEON_TILING_MACRO) {
92 } else if (tiling & RADEON_TILING_MICRO) {
112 if (tiling)
122 static int radeon_get_height_align(struct radeon_info *info, uint32_t tiling) argument
127 if (tiling & RADEON_TILING_MACRO)
129 else if (tiling & RADEON_TILING_MICRO)
135 if (tiling)
146 int bpe, uint32_t tiling)
148 int pixel_align = radeon_get_pitch_align(info, bpe, tiling);
145 radeon_get_base_align(struct radeon_info *info, int bpe, uint32_t tiling) argument
191 uint32_t tiling, domain; local
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H A Dgralloc_drm_intel.c71 uint32_t tiling; member in struct:intel_buffer
243 uint32_t *tiling, unsigned long *stride)
275 *tiling = I915_TILING_X;
278 *tiling = I915_TILING_NONE;
287 bpp, tiling, stride, flags);
294 if (*tiling != I915_TILING_NONE) {
296 *tiling = I915_TILING_NONE;
309 *tiling = I915_TILING_NONE;
313 *tiling = I915_TILING_X;
315 *tiling
241 alloc_ibo(struct intel_info *info, const struct gralloc_drm_handle_t *handle, uint32_t *tiling, unsigned long *stride) argument
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/external/mesa3d/src/gallium/winsys/i915/sw/
H A Di915_sw_buffer.c33 enum i915_winsys_buffer_tile *tiling,
44 buf->tiling = *tiling;
31 i915_sw_buffer_create_tiled(struct i915_winsys *iws, unsigned *stride, unsigned height, enum i915_winsys_buffer_tile *tiling, enum i915_winsys_buffer_type type) argument
H A Di915_sw_winsys.h46 enum i915_winsys_buffer_tile tiling; member in struct:i915_sw_buffer
/external/libdrm/tegra/
H A Dtegra.h61 struct drm_tegra_bo_tiling *tiling);
63 const struct drm_tegra_bo_tiling *tiling);
H A Dtegra.c341 struct drm_tegra_bo_tiling *tiling)
358 if (tiling) {
359 tiling->mode = args.mode;
360 tiling->value = args.value;
367 const struct drm_tegra_bo_tiling *tiling)
378 args.mode = tiling->mode;
379 args.value = tiling->value;
340 drm_tegra_bo_get_tiling(struct drm_tegra_bo *bo, struct drm_tegra_bo_tiling *tiling) argument
366 drm_tegra_bo_set_tiling(struct drm_tegra_bo *bo, const struct drm_tegra_bo_tiling *tiling) argument
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dradeon_mipmap_tree.h94 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target);
101 unsigned tiling);
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_mipmap_tree.h94 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target);
101 unsigned tiling);
/external/mesa3d/src/gallium/winsys/i915/drm/
H A Di915_drm_buffer.c58 enum i915_winsys_buffer_tile *tiling,
64 uint32_t tiling_mode = *tiling;
82 *tiling = tiling_mode;
94 enum i915_winsys_buffer_tile *tiling,
115 *tiling = tile;
56 i915_drm_buffer_create_tiled(struct i915_winsys *iws, unsigned *stride, unsigned height, enum i915_winsys_buffer_tile *tiling, enum i915_winsys_buffer_type type) argument
92 i915_drm_buffer_from_handle(struct i915_winsys *iws, struct winsys_handle *whandle, enum i915_winsys_buffer_tile *tiling, unsigned *stride) argument
/external/deqp/external/vulkancts/modules/vulkan/memory/
H A DvktMemoryRequirementsTests.cpp310 (info.imageType != VK_IMAGE_TYPE_2D || (info.flags & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT) || info.tiling != VK_IMAGE_TILING_OPTIMAL || info.mipLevels > 1u))
321 DE_ASSERT(info.tiling == VK_IMAGE_TILING_OPTIMAL);
415 const VkFormatFeatureFlags formatFeatures = (info.tiling == VK_IMAGE_TILING_LINEAR ? formatProperties.linearTilingFeatures
423 physDevice, info.format, info.imageType, info.tiling, info.usage, info.flags, &imageFormatProperties);
501 result.check(imageInfo.tiling == VK_IMAGE_TILING_OPTIMAL || hostVisibleCoherentMemoryFound,
518 switch (imageInfo.tiling)
537 VkImageTiling tiling; member in struct:vkt::memory::__anon3829::ImageParams
594 params.tiling, // VkImageTiling tiling;
614 // For the same tiling, transien
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