Searched refs:v0 (Results 1 - 25 of 588) sorted by relevance

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/external/llvm/test/MC/AMDGPU/regression/
H A Dbug28538.s8 v_mov_b32 v0, v0 row_bcast:0
12 v_mov_b32 v0, v0 row_bcast:13
H A Dbug28413.s6 v_cmp_eq_i32 vcc, 0.5, v0
7 // SICI: v_cmp_eq_i32_e32 vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x04,0x7d]
8 // VI: v_cmp_eq_i32_e32 vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x84,0x7d]
14 v_cmp_eq_i32 vcc, 3.125, v0
15 // SICI: v_cmp_eq_i32_e32 vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x04,0x7d,0x00,0x00,0x48,0x40]
16 // VI: v_cmp_eq_i32_e32 vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x84,0x7d,0x00,0x00,0x48,0x40]
18 v_cmpx_eq_u32 vcc, 3.125, v0
19 // SICI: v_cmpx_eq_u32_e32 vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0xa4,0x7d,0x00,0x00,0x48,0x40]
20 // VI: v_cmpx_eq_u32_e32 vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0xb4,0x7d,0x00,0x00,0x48,0x40]
22 v_mov_b32 v0, 0.
[all...]
/external/llvm/test/MC/SystemZ/
H A Dinsn-bad-zEC12.s92 #CHECK: vab %v0, %v0, %v0
94 #CHECK: vaf %v0, %v0, %v0
96 #CHECK: vag %v0, %v0, %v0
98 #CHECK: vah %v0,
[all...]
H A Dinsn-bad-z13.s23 #CHECK: vcdgb %v0, %v0, 0, -1
25 #CHECK: vcdgb %v0, %v0, 0, 16
27 #CHECK: vcdgb %v0, %v0, -1, 0
29 #CHECK: vcdgb %v0, %v0, 16, 0
31 vcdgb %v0, %v0,
[all...]
H A Dinsn-good-z13.s21 #CHECK: vab %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf3]
22 #CHECK: vab %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf3]
23 #CHECK: vab %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf3]
24 #CHECK: vab %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf3]
27 vab %v0,
[all...]
/external/llvm/test/MC/AArch64/
H A Dneon-shift-left-long.s8 sshll v0.8h, v1.8b, #3
9 sshll v0.4s, v1.4h, #3
10 sshll v0.2d, v1.2s, #3
11 sshll2 v0.8h, v1.16b, #3
12 sshll2 v0.4s, v1.8h, #3
13 sshll2 v0.2d, v1.4s, #3
15 // CHECK: sshll v0.8h, v1.8b, #3 // encoding: [0x20,0xa4,0x0b,0x0f]
16 // CHECK: sshll v0.4s, v1.4h, #3 // encoding: [0x20,0xa4,0x13,0x0f]
17 // CHECK: sshll v0.2d, v1.2s, #3 // encoding: [0x20,0xa4,0x23,0x0f]
18 // CHECK: sshll2 v0
[all...]
H A Darm64-advsimd.s5 abs.8b v0, v0
6 abs.16b v0, v0
7 abs.4h v0, v0
8 abs.8h v0, v0
9 abs.2s v0, v0
[all...]
H A Dneon-simd-shift.s8 sshr v0.8b, v1.8b, #3
9 sshr v0.4h, v1.4h, #3
10 sshr v0.2s, v1.2s, #3
11 sshr v0.16b, v1.16b, #3
12 sshr v0.8h, v1.8h, #3
13 sshr v0.4s, v1.4s, #3
14 sshr v0.2d, v1.2d, #3
15 // CHECK: sshr v0.8b, v1.8b, #3 // encoding: [0x20,0x04,0x0d,0x0f]
16 // CHECK: sshr v0.4h, v1.4h, #3 // encoding: [0x20,0x04,0x1d,0x0f]
17 // CHECK: sshr v0
[all...]
H A Dneon-sxtl.s8 sxtl v0.8h, v1.8b
9 sxtl v0.4s, v1.4h
10 sxtl v0.2d, v1.2s
12 // CHECK: sshll v0.8h, v1.8b, #0 // encoding: [0x20,0xa4,0x08,0x0f]
13 // CHECK: sshll v0.4s, v1.4h, #0 // encoding: [0x20,0xa4,0x10,0x0f]
14 // CHECK: sshll v0.2d, v1.2s, #0 // encoding: [0x20,0xa4,0x20,0x0f]
20 sxtl2 v0.8h, v1.16b
21 sxtl2 v0.4s, v1.8h
22 sxtl2 v0.2d, v1.4s
24 // CHECK: sshll2 v0
[all...]
H A Dneon-uxtl.s8 uxtl v0.8h, v1.8b
9 uxtl v0.4s, v1.4h
10 uxtl v0.2d, v1.2s
12 // CHECK: ushll v0.8h, v1.8b, #0 // encoding: [0x20,0xa4,0x08,0x2f]
13 // CHECK: ushll v0.4s, v1.4h, #0 // encoding: [0x20,0xa4,0x10,0x2f]
14 // CHECK: ushll v0.2d, v1.2s, #0 // encoding: [0x20,0xa4,0x20,0x2f]
20 uxtl2 v0.8h, v1.16b
21 uxtl2 v0.4s, v1.8h
22 uxtl2 v0.2d, v1.4s
24 // CHECK: ushll2 v0
[all...]
H A Dneon-bitwise-instructions.s8 and v0.8b, v1.8b, v2.8b
9 and v0.16b, v1.16b, v2.16b
11 // CHECK: and v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x0e]
12 // CHECK: and v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x4e]
18 orr v0.8b, v1.8b, v2.8b
19 orr v0.16b, v1.16b, v2.16b
21 // CHECK: orr v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x0e]
22 // CHECK: orr v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x4e]
28 eor v0.8b, v1.8b, v2.8b
29 eor v0
[all...]
H A Dneon-3vdiff.s17 saddl v0.8h, v1.8b, v2.8b
18 saddl v0.4s, v1.4h, v2.4h
19 saddl v0.2d, v1.2s, v2.2s
21 // CHECK: saddl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x00,0x22,0x0e]
22 // CHECK: saddl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x00,0x62,0x0e]
23 // CHECK: saddl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x00,0xa2,0x0e]
25 saddl2 v0.4s, v1.8h, v2.8h
26 saddl2 v0.8h, v1.16b, v2.16b
27 saddl2 v0.2d, v1.4s, v2.4s
29 // CHECK: saddl2 v0
[all...]
H A Dneon-mla-mls-instructions.s8 mla v0.8b, v1.8b, v2.8b
9 mla v0.16b, v1.16b, v2.16b
10 mla v0.4h, v1.4h, v2.4h
11 mla v0.8h, v1.8h, v2.8h
12 mla v0.2s, v1.2s, v2.2s
13 mla v0.4s, v1.4s, v2.4s
15 // CHECK: mla v0.8b, v1.8b, v2.8b // encoding: [0x20,0x94,0x22,0x0e]
16 // CHECK: mla v0.16b, v1.16b, v2.16b // encoding: [0x20,0x94,0x22,0x4e]
17 // CHECK: mla v0.4h, v1.4h, v2.4h // encoding: [0x20,0x94,0x62,0x0e]
18 // CHECK: mla v0
[all...]
H A Dneon-mov.s9 movi v0.2s, #1
14 movi v0.4s, #1
15 movi v0.4s, #1, lsl #8
16 movi v0.4s, #1, lsl #16
17 movi v0.4s, #1, lsl #24
18 movi v0.4h, #1
19 movi v0.4h, #1, lsl #8
20 movi v0.8h, #1
21 movi v0.8h, #1, lsl #8
23 // CHECK: movi v0
[all...]
H A Dneon-shift.s9 sshl v0.8b, v1.8b, v2.8b
10 sshl v0.16b, v1.16b, v2.16b
11 sshl v0.4h, v1.4h, v2.4h
12 sshl v0.8h, v1.8h, v2.8h
13 sshl v0.2s, v1.2s, v2.2s
14 sshl v0.4s, v1.4s, v2.4s
15 sshl v0.2d, v1.2d, v2.2d
17 // CHECK: sshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x44,0x22,0x0e]
18 // CHECK: sshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x44,0x22,0x4e]
19 // CHECK: sshl v0
[all...]
H A Dneon-perm.s9 uzp1 v0.8b, v1.8b, v2.8b
10 uzp1 v0.16b, v1.16b, v2.16b
11 uzp1 v0.4h, v1.4h, v2.4h
12 uzp1 v0.8h, v1.8h, v2.8h
13 uzp1 v0.2s, v1.2s, v2.2s
14 uzp1 v0.4s, v1.4s, v2.4s
15 uzp1 v0.2d, v1.2d, v2.2d
17 // CHECK: uzp1 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x18,0x02,0x0e]
18 // CHECK: uzp1 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x18,0x02,0x4e]
19 // CHECK: uzp1 v0
[all...]
H A Dneon-extract.s9 ext v0.8b, v1.8b, v2.8b, #0x3
10 ext v0.16b, v1.16b, v2.16b, #0x3
12 // CHECK: ext v0.8b, v1.8b, v2.8b, #{{0x3|3}} // encoding: [0x20,0x18,0x02,0x2e]
13 // CHECK: ext v0.16b, v1.16b, v2.16b, #{{0x3|3}} // encoding: [0x20,0x18,0x02,0x6e]
H A Dneon-rounding-shift.s9 srshl v0.8b, v1.8b, v2.8b
10 srshl v0.16b, v1.16b, v2.16b
11 srshl v0.4h, v1.4h, v2.4h
12 srshl v0.8h, v1.8h, v2.8h
13 srshl v0.2s, v1.2s, v2.2s
14 srshl v0.4s, v1.4s, v2.4s
15 srshl v0.2d, v1.2d, v2.2d
17 // CHECK: srshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x54,0x22,0x0e]
18 // CHECK: srshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x54,0x22,0x4e]
19 // CHECK: srshl v0
[all...]
H A Dneon-saturating-rounding-shift.s9 sqrshl v0.8b, v1.8b, v2.8b
10 sqrshl v0.16b, v1.16b, v2.16b
11 sqrshl v0.4h, v1.4h, v2.4h
12 sqrshl v0.8h, v1.8h, v2.8h
13 sqrshl v0.2s, v1.2s, v2.2s
14 sqrshl v0.4s, v1.4s, v2.4s
15 sqrshl v0.2d, v1.2d, v2.2d
17 // CHECK: sqrshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x5c,0x22,0x0e]
18 // CHECK: sqrshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x5c,0x22,0x4e]
19 // CHECK: sqrshl v0
[all...]
H A Dneon-saturating-shift.s9 sqshl v0.8b, v1.8b, v2.8b
10 sqshl v0.16b, v1.16b, v2.16b
11 sqshl v0.4h, v1.4h, v2.4h
12 sqshl v0.8h, v1.8h, v2.8h
13 sqshl v0.2s, v1.2s, v2.2s
14 sqshl v0.4s, v1.4s, v2.4s
15 sqshl v0.2d, v1.2d, v2.2d
17 // CHECK: sqshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x4c,0x22,0x0e]
18 // CHECK: sqshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x4c,0x22,0x4e]
19 // CHECK: sqshl v0
[all...]
H A Darm64-vector-lists.s4 ST4 {v0.8B-v3.8B}, [x0]
5 ST4 {v0.4H-v3.4H}, [x0]
7 // CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c]
8 // CHECK: st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0] // encoding: [0x00,0x04,0x00,0x0c]
10 ST4 {v0.8B-v4.8B}, [x0]
11 ST4 {v0.8B-v3.8B,v4.8B}, [x0]
12 ST4 {v0.8B-v3.8H}, [x0]
13 ST4 {v0.8B-v3.16B}, [x0]
14 ST4 {v0.8B-},[x0]
/external/clang/test/Sema/
H A D2010-05-31-palignr.c16 vSInt16 v0; local
17 v0 = *vdtbl;
18 v0 = _mm_alignr_epi8(v0, v0, i); // expected-error {{argument to '__builtin_ia32_palignr128' must be a constant integer}}
/external/libmpeg2/common/armv8/
H A Dimpeg2_mem_func.s86 //// Registers Used : v0
104 dup v0.8b, w1 ////x1 is the 8-bit value to be set into
106 st1 {v0.8b}, [x0], x2 ////Store the row 1
107 st1 {v0.8b}, [x0], x2 ////Store the row 2
108 st1 {v0.8b}, [x0], x2 ////Store the row 3
109 st1 {v0.8b}, [x0], x2 ////Store the row 4
110 st1 {v0.8b}, [x0], x2 ////Store the row 5
111 st1 {v0.8b}, [x0], x2 ////Store the row 6
112 st1 {v0.8b}, [x0], x2 ////Store the row 7
113 st1 {v0
[all...]
H A Dicv_sad_av8.s78 ld1 {v0.8b}, [x0], x2
89 uabdl v0.8h, v0.8b, v4.8b
90 uabal v0.8h, v1.8b, v5.8b
91 uabal v0.8h, v2.8b, v6.8b
92 uabal v0.8h, v3.8b, v7.8b
94 addp v0.8h, v0.8h, v0.8h
95 addp v0
[all...]
/external/llvm/test/MC/AMDGPU/
H A Dvop3-errs.s4 v_add_f32_e64 v0, v1

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