Searched refs:v2 (Results 1 - 25 of 993) sorted by relevance

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/external/libcxx/test/std/numerics/numarray/template.valarray/valarray.sub/
H A Dslice_const.pass.cpp23 std::valarray<int> v2 = v1[std::slice(1, 5, 3)]; local
24 assert(v2.size() == 5);
25 assert(v2[0] == 1);
26 assert(v2[1] == 4);
27 assert(v2[2] == 7);
28 assert(v2[3] == 10);
29 assert(v2[4] == 13);
H A Dvalarray_bool_non_const.pass.cpp27 std::valarray<int> v2(5);
28 v2 = v1[vb];
29 assert(v2.size() == 5);
30 assert(v2[ 0] == 0);
31 assert(v2[ 1] == 3);
32 assert(v2[ 2] == 4);
33 assert(v2[ 3] == 7);
34 assert(v2[ 4] == 11);
H A Dvalarray_bool_const.pass.cpp27 std::valarray<int> v2(v1[vb]);
28 assert(v2.size() == 5);
29 assert(v2[ 0] == 0);
30 assert(v2[ 1] == 3);
31 assert(v2[ 2] == 4);
32 assert(v2[ 3] == 7);
33 assert(v2[ 4] == 11);
/external/llvm/test/MC/AMDGPU/
H A Dds.s9 ds_add_u32 v2, v4 offset:16
10 // SICI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
11 // VI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
17 ds_write_src2_b32 v2 offset0:4 offset1:8
18 // SICI: ds_write_src2_b32 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x34,0xda,0x02,0x00,0x00,0x00]
19 // VI: ds_write_src2_b32 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x1a,0xd9,0x02,0x00,0x00,0x00]
21 ds_write_src2_b64 v2 offset0:4 offset1:8
22 // SICI: ds_write_src2_b64 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x34,0xdb,0x02,0x00,0x00,0x00]
23 // VI: ds_write_src2_b64 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x9a,0xd9,0x02,0x00,0x00,0x00]
25 ds_write2_b32 v2, v
[all...]
H A Dvop1.s13 // GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
14 v_mov_b32_e32 v1, v2
34 // GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
35 v_mov_b32 v1, v2
37 // GCN: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
38 v_readfirstlane_b32 s1, v2
43 // GCN: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e]
44 v_cvt_f64_i32 v[1:2], v2
46 // GCN: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e]
47 v_cvt_f32_i32 v1, v2
[all...]
H A Dvopc-errs.s7 v_cmp_lt_f32_e32 s[0:1], v2, v4
H A Dvop2.s18 // SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
19 v_add_f32_e32 v1, v2, v3
42 // SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
43 v_mul_i32_i24_e32 v1, v2, v3
46 // SICI: v_mul_i32_i24_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x02,0x00]
47 v_mul_i32_i24_e64 v1, v2, v3
58 // SICI: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x01,0x00]
59 v_mul_i32_i24 v1, v2, 3
62 // SICI: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x87,0x01,0x00]
63 v_mul_i32_i24 v1, v2,
[all...]
H A Dvop2-err.s8 v_mul_i32_i24 v1, v2, 100
11 v_cndmask_b32 v1, v2, v3
19 v_mul_i32_i24_e32 v1, v2, 100
23 v_mul_i32_i24_e32 v1, v2, s3
26 v_cndmask_b32_e32 v1, v2, v3, s[0:1]
38 v_mul_i32_i24_e64 v1, v2, 100
41 v_add_i32_e32 v1, s[0:1], v2, v3
44 v_addc_u32_e32 v1, vcc, v2, v3, s[2:3]
47 v_addc_u32_e32 v1, s[0:1], v2, v3, s[2:3]
50 v_addc_u32_e32 v1, vcc, v2, v
[all...]
H A Dds-err.s6 ds_add_u32 v2, v4 offset:1000000000
10 ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
14 ds_write2_b32 v2, v4, v6 offset1:4 offset1:8
18 ds_write2_b32 v2, v4, v6 offset0:1000000000
22 ds_write2_b32 v2, v4, v6 offset1:1000000000
/external/libcxx/test/std/numerics/numarray/template.valarray/valarray.assign/
H A Dmask_array_assign.pass.cpp27 std::valarray<int> v2(5);
28 v2 = v1[vb];
29 assert(v2.size() == 5);
30 assert(v2[ 0] == 0);
31 assert(v2[ 1] == 3);
32 assert(v2[ 2] == 4);
33 assert(v2[ 3] == 7);
34 assert(v2[ 4] == 11);
/external/libcxx/test/std/numerics/numarray/template.valarray/valarray.cons/
H A Dmask_array.pass.cpp27 std::valarray<int> v2(v1[vb]);
28 assert(v2.size() == 5);
29 assert(v2[ 0] == 0);
30 assert(v2[ 1] == 3);
31 assert(v2[ 2] == 4);
32 assert(v2[ 3] == 7);
33 assert(v2[ 4] == 11);
/external/valgrind/none/tests/s390x/
H A Dspechelper-clr.c22 int wrong, ok, v1, v2; local
26 v1 = v2 = 42;
29 if (branch(0, v1, v2)) ++wrong; else ++ok;
30 if (branch(1, v1, v2)) ++wrong; else ++ok;
31 if (branch(2, v1, v2)) ++wrong; else ++ok;
32 if (branch(3, v1, v2)) ++wrong; else ++ok;
33 if (branch(4, v1, v2)) ++wrong; else ++ok;
34 if (branch(5, v1, v2)) ++wrong; else ++ok;
35 if (branch(6, v1, v2)) ++wrong; else ++ok;
36 if (branch(7, v1, v2))
55 int wrong, ok, v1, v2; local
88 int wrong, ok, v1, v2; local
[all...]
H A Dspechelper-cr.c22 int wrong, ok, v1, v2; local
26 v1 = v2 = 42;
29 if (branch(0, v1, v2)) ++wrong; else ++ok;
30 if (branch(1, v1, v2)) ++wrong; else ++ok;
31 if (branch(2, v1, v2)) ++wrong; else ++ok;
32 if (branch(3, v1, v2)) ++wrong; else ++ok;
33 if (branch(4, v1, v2)) ++wrong; else ++ok;
34 if (branch(5, v1, v2)) ++wrong; else ++ok;
35 if (branch(6, v1, v2)) ++wrong; else ++ok;
36 if (branch(7, v1, v2))
55 int wrong, ok, v1, v2; local
88 int wrong, ok, v1, v2; local
[all...]
H A Dspechelper-slgr.c28 unsigned long v1, v2; local
33 v1 = v2 = 42;
36 if (branch(0, v1, v2)) ++wrong; else ++ok;
37 if (branch(1, v1, v2)) ++wrong; else ++ok;
38 if (branch(2, v1, v2)) ++ok; else ++wrong;
39 if (branch(3, v1, v2)) ++ok; else ++wrong;
40 if (branch(4, v1, v2)) ++wrong; else ++ok;
41 if (branch(5, v1, v2)) ++wrong; else ++ok;
42 if (branch(6, v1, v2)) ++ok; else ++wrong;
43 if (branch(7, v1, v2))
62 unsigned long v1, v2; local
98 unsigned long v1, v2; local
[all...]
H A Dspechelper-slr.c26 unsigned int v1, v2; local
31 v1 = v2 = 0xffffffff;
34 if (branch(0, v1, v2)) ++wrong; else ++ok;
35 if (branch(1, v1, v2)) ++wrong; else ++ok;
36 if (branch(2, v1, v2)) ++ok; else ++wrong;
37 if (branch(3, v1, v2)) ++ok; else ++wrong;
38 if (branch(4, v1, v2)) ++wrong; else ++ok;
39 if (branch(5, v1, v2)) ++wrong; else ++ok;
40 if (branch(6, v1, v2)) ++ok; else ++wrong;
41 if (branch(7, v1, v2))
60 unsigned int v1, v2; local
96 unsigned int v1, v2; local
[all...]
H A Dspechelper-or.c22 int wrong, ok, v1, v2; local
26 v1 = v2 = 0;
28 if (branch(0, v1, v2)) ++wrong; else ++ok;
29 if (branch(1, v1, v2)) ++wrong; else ++ok;
30 if (branch(2, v1, v2)) ++wrong; else ++ok;
31 if (branch(3, v1, v2)) ++wrong; else ++ok;
32 if (branch(4, v1, v2)) ++wrong; else ++ok;
33 if (branch(5, v1, v2)) ++wrong; else ++ok;
34 if (branch(6, v1, v2)) ++wrong; else ++ok;
35 if (branch(7, v1, v2))
54 int wrong, ok, v1, v2; local
[all...]
H A Dbfp-3.c6 void maebr(float v1, float v2, float v3) argument
11 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3));
12 printf("maebr %f * %f + %f -> %f\n", v2, v3, v1, r1);
15 void madbr(double v1, double v2, double v3) argument
20 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3));
21 printf("madbr %f * %f + %f -> %f\n", v2, v3, v1, r1);
24 void msebr(float v1, float v2, float v3) argument
29 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3));
30 printf("msebr %f * %f - %f -> %f\n", v2, v3, v1, r1);
33 void msdbr(double v1, double v2, doubl argument
[all...]
H A Dspechelper-algr.c24 unsigned long v1, v2; local
29 v1 = v2 = 0;
31 if (branch(0, v1, v2)) ++wrong; else ++ok;
32 if (branch(1, v1, v2)) ++wrong; else ++ok;
33 if (branch(2, v1, v2)) ++wrong; else ++ok;
34 if (branch(3, v1, v2)) ++wrong; else ++ok;
35 if (branch(4, v1, v2)) ++wrong; else ++ok;
36 if (branch(5, v1, v2)) ++wrong; else ++ok;
37 if (branch(6, v1, v2)) ++wrong; else ++ok;
38 if (branch(7, v1, v2))
57 unsigned long v1, v2; local
91 unsigned long v1, v2; local
127 unsigned long v1, v2; local
[all...]
H A Dspechelper-alr.c24 unsigned v1, v2; local
29 v1 = v2 = 0;
31 if (branch(0, v1, v2)) ++wrong; else ++ok;
32 if (branch(1, v1, v2)) ++wrong; else ++ok;
33 if (branch(2, v1, v2)) ++wrong; else ++ok;
34 if (branch(3, v1, v2)) ++wrong; else ++ok;
35 if (branch(4, v1, v2)) ++wrong; else ++ok;
36 if (branch(5, v1, v2)) ++wrong; else ++ok;
37 if (branch(6, v1, v2)) ++wrong; else ++ok;
38 if (branch(7, v1, v2))
57 unsigned v1, v2; local
91 unsigned v1, v2; local
127 unsigned v1, v2; local
[all...]
/external/libcxx/test/std/containers/sequences/vector/vector.capacity/
H A Dswap.pass.cpp24 std::vector<int> v2(200);
26 assert(is_contiguous_container_asan_correct(v2));
27 v1.swap(v2);
31 assert(v2.size() == 100);
32 assert(v2.capacity() == 100);
33 assert(is_contiguous_container_asan_correct(v2));
38 std::vector<int, min_allocator<int>> v2(200);
40 assert(is_contiguous_container_asan_correct(v2));
41 v1.swap(v2);
45 assert(v2
[all...]
/external/llvm/test/MC/AArch64/
H A Dneon-bitwise-instructions.s8 and v0.8b, v1.8b, v2.8b
9 and v0.16b, v1.16b, v2.16b
11 // CHECK: and v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x0e]
12 // CHECK: and v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x4e]
18 orr v0.8b, v1.8b, v2.8b
19 orr v0.16b, v1.16b, v2.16b
21 // CHECK: orr v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x0e]
22 // CHECK: orr v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x4e]
28 eor v0.8b, v1.8b, v2.8b
29 eor v0.16b, v1.16b, v2
[all...]
H A Dneon-3vdiff.s17 saddl v0.8h, v1.8b, v2.8b
18 saddl v0.4s, v1.4h, v2.4h
19 saddl v0.2d, v1.2s, v2.2s
21 // CHECK: saddl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x00,0x22,0x0e]
22 // CHECK: saddl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x00,0x62,0x0e]
23 // CHECK: saddl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x00,0xa2,0x0e]
25 saddl2 v0.4s, v1.8h, v2.8h
26 saddl2 v0.8h, v1.16b, v2.16b
27 saddl2 v0.2d, v1.4s, v2.4s
29 // CHECK: saddl2 v0.4s, v1.8h, v2
[all...]
H A Dneon-mla-mls-instructions.s8 mla v0.8b, v1.8b, v2.8b
9 mla v0.16b, v1.16b, v2.16b
10 mla v0.4h, v1.4h, v2.4h
11 mla v0.8h, v1.8h, v2.8h
12 mla v0.2s, v1.2s, v2.2s
13 mla v0.4s, v1.4s, v2.4s
15 // CHECK: mla v0.8b, v1.8b, v2.8b // encoding: [0x20,0x94,0x22,0x0e]
16 // CHECK: mla v0.16b, v1.16b, v2.16b // encoding: [0x20,0x94,0x22,0x4e]
17 // CHECK: mla v0.4h, v1.4h, v2.4h // encoding: [0x20,0x94,0x62,0x0e]
18 // CHECK: mla v0.8h, v1.8h, v2
[all...]
H A Darmv8.1a-rdma.s6 sqrdmlah v0.4h, v1.4h, v2.4h
7 sqrdmlsh v0.4h, v1.4h, v2.4h
8 sqrdmlah v0.2s, v1.2s, v2.2s
9 sqrdmlsh v0.2s, v1.2s, v2.2s
10 sqrdmlah v0.4s, v1.4s, v2.4s
11 sqrdmlsh v0.4s, v1.4s, v2.4s
12 sqrdmlah v0.8h, v1.8h, v2.8h
13 sqrdmlsh v0.8h, v1.8h, v2.8h
14 // CHECK: sqrdmlah v0.4h, v1.4h, v2.4h // encoding: [0x20,0x84,0x42,0x2e]
15 // CHECK: sqrdmlsh v0.4h, v1.4h, v2
[all...]
H A Dneon-tbl.s9 tbl v0.8b, { v1.16b }, v2.8b
10 tbl v0.8b, { v1.16b, v2.16b }, v2.8b
11 tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
12 tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b
13 tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b
15 // CHECK: tbl v0.8b, { v1.16b }, v2
[all...]

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