/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_wm_pass1.c | 42 if (inst->writemask & (1<<i)) { 44 inst->writemask &= ~(1<<i); 50 return inst->writemask; 123 GLuint writemask; local 144 writemask = get_tracked_mask(c, inst); 145 if (!writemask) { 166 read0 = writemask; 180 read0 = writemask; 181 read1 = writemask; 186 read0 = writemask; [all...] |
H A D | brw_wm_debug.c | 101 if (inst->writemask != WRITEMASK_XYZW) 103 GET_BIT(inst->writemask, 0) ? "x" : "", 104 GET_BIT(inst->writemask, 1) ? "y" : "", 105 GET_BIT(inst->writemask, 2) ? "z" : "", 106 GET_BIT(inst->writemask, 3) ? "w" : "");
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H A D | brw_wm_pass0.c | 247 GLuint writemask ) 253 if (writemask & (1<<i)) { 259 out->writemask = writemask; 317 GLuint writemask = inst->DstReg.WriteMask; local 341 pass0_set_dst(c, out, inst, writemask); 353 GLuint writemask = inst->DstReg.WriteMask; local 368 if (writemask & (1 << i)) {
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H A D | brw_fs_vector_splitting.cpp | 273 unsigned int writemask; local 280 writemask = 1; 283 writemask = 1 << i; 296 NULL, writemask));
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H A D | brw_vec4.cpp | 123 if (!(reg.writemask & (1 << i))) 152 this->writemask = WRITEMASK_XYZW; 169 int writemask) 176 this->writemask = writemask; 195 this->writemask = WRITEMASK_XYZW; 735 if (!(inst->dst.writemask & (1 << i))) 783 if (scan_inst->dst.writemask & (1 << i) && 853 scan_inst->dst.writemask &= inst->dst.writemask; 168 dst_reg(register_file file, int reg, const glsl_type *type, int writemask) argument [all...] |
H A D | brw_vec4_visitor.cpp | 227 * writemask, note that uniform packing and register allocation 234 if (dst.writemask != WRITEMASK_XYZW) { 304 if (dst.writemask != WRITEMASK_XYZW) { 447 this->writemask = WRITEMASK_XYZW; 449 this->writemask = (1 << type->vector_elements) - 1; 808 dst.writemask = (1 << c->key.gl_fixed_input_size[i]) - 1; 862 reg->writemask = WRITEMASK_X; 865 reg->writemask = WRITEMASK_Y; 1048 result_dst.writemask = (1 << ir->type->vector_elements) - 1; 1432 /* System values get their swizzle from the dst_reg writemask */ 1918 int writemask = intel->gen == 4 ? WRITEMASK_W : WRITEMASK_X; local 1963 int mrf, writemask; local [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_rename_regs.c | 72 unsigned writemask; local 86 writemask = rc_variable_writemask_sum(var); 87 rc_variable_change_dst(var, new_index, writemask);
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H A D | radeon_pair_regalloc.c | 238 unsigned int writemask, 248 if (classes[i].Writemasks[j] == writemask) { 281 unsigned int writemask = rc_variable_writemask_sum(variable); local 293 writemask = RC_MASK_XYZW; 299 class_index = find_class(classes, writemask, 3); 314 writemask, c.Writemasks[i]); 321 * then the writemask will be set to RC_MASK_XYZW 379 class_index = find_class(classes, writemask, 388 variable->Dst.Index, writemask); 418 static int get_reg_id(unsigned int index, unsigned int writemask) argument 236 find_class( struct rc_class * classes, unsigned int writemask, unsigned int max_writemask_count) argument 615 unsigned int chan, class_id, writemask = 0; local 692 unsigned int writemask = reg_get_writemask(reg); local [all...] |
H A D | radeon_variable.c | 38 * Rewrite the index and writemask for the destination register of var 320 unsigned int writemask; local 334 writemask = sub_inst->WriteMask; 337 writemask = sub_inst->OutputWriteMask; 339 writemask = 0; 342 new_var = rc_variable(c, file, sub_inst->DestIndex, writemask, 392 unsigned int writemask = 0; local 394 writemask |= var->Dst.WriteMask; 397 return writemask;
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H A D | radeon_opcodes.h | 281 unsigned int writemask,
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H A D | radeon_opcodes.c | 524 unsigned int writemask, 537 if (!writemask) 542 srcmasks[src] |= writemask; 545 srcmasks[src] |= writemask; 522 rc_compute_sources_for_writemask( const struct rc_instruction *inst, unsigned int writemask, unsigned int *srcmasks) argument
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/external/mesa3d/src/gallium/auxiliary/util/ |
H A D | u_blit.h | 69 uint writemask, uint zs_writemask);
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H A D | u_simple_shaders.h | 64 unsigned writemask);
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H A D | u_blit.c | 107 ctx->dsa_write_depth.depth.writemask = 1; 115 ctx->dsa_write_stencil.stencil[0].writemask = 0xff; 202 set_fragment_shader(struct blit_state *ctx, uint writemask, argument 205 if (!ctx->fs[pipe_tex][writemask]) { 208 ctx->fs[pipe_tex][writemask] = 211 writemask); 214 cso_set_fragment_shader_handle(ctx->cso, ctx->fs[pipe_tex][writemask]); 420 * \param writemask controls which channels in the dest surface are sourced 435 uint writemask, uint zs_writemask) 476 assert((writemask 425 util_blit_pixels(struct blit_state *ctx, struct pipe_resource *src_tex, unsigned src_level, int srcX0, int srcY0, int srcX1, int srcY1, int srcZ0, struct pipe_surface *dst, int dstX0, int dstY0, int dstX1, int dstY1, float z, uint filter, uint writemask, uint zs_writemask) argument [all...] |
H A D | u_simple_shaders.c | 104 * IMM {0,0,0,1} // (if writemask != 0xf) 105 * MOV OUT[0], IMM[0] // (if writemask != 0xf) 106 * TEX OUT[0].writemask, IN[0], SAMP[0], 2D; 111 * \param writemask mask of TGSI_WRITEMASK_x 117 unsigned writemask ) 141 if (writemask != TGSI_WRITEMASK_XYZW) { 148 ureg_writemask(out, writemask),
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/external/mesa3d/src/gallium/drivers/svga/ |
H A D | svga_pipe_depthstencil.c | 89 /* SVGA3D has one ref/mask/writemask triple shared between front & 93 ds->stencil_writemask = templ->stencil[0].writemask & 0xff; 105 ds->stencil_writemask = templ->stencil[1].writemask & 0xff; 112 ds->zwriteenable = templ->depth.writemask;
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/external/mesa3d/src/mesa/state_tracker/ |
H A D | st_atom_depth.c | 107 dsa->depth.writemask = ctx->Depth.Mask; 118 dsa->stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff; 129 dsa->stencil[1].writemask = ctx->Stencil.WriteMask[back] & 0xff;
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H A D | st_glsl_to_tgsi.cpp | 148 st_dst_reg(gl_register_file file, int writemask, int type) argument 152 this->writemask = writemask; 163 this->writemask = 0; 172 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:st_dst_reg 194 this->writemask = WRITEMASK_XYZW; 596 assert(dst.writemask != 0); 708 int done_mask = ~dst.writemask; 742 inst->dst.writemask = this_mask; 798 int done_mask = ~dst.writemask; [all...] |
/external/mesa3d/src/gallium/drivers/r300/ |
H A D | r300_hyperz.c | 176 assert(!dsa->dsa.depth.writemask); 191 /* If writemask is disabled, the HiZ memory will not be changed, 193 if (dsa->dsa.depth.writemask) { 225 return s->enabled && s->writemask && 237 if (dsa->depth.enabled && dsa->depth.writemask &&
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/external/mesa3d/src/mesa/program/ |
H A D | ir_to_mesa.cpp | 105 dst_reg(gl_register_file file, int writemask) argument 109 this->writemask = writemask; 118 this->writemask = 0; 127 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:dst_reg 146 this->writemask = WRITEMASK_XYZW; 399 assert(dst.writemask != 0); 435 int done_mask = ~dst.writemask; 469 inst->dst.writemask = this_mask; 513 int done_mask = ~dst.writemask; [all...] |
/external/mesa3d/src/gallium/drivers/llvmpipe/ |
H A D | lp_bld_depth.c | 276 if (stencil[0].writemask != 0xff || 277 (stencil[1].enabled && front_facing != NULL && stencil[1].writemask != 0xff)) { 278 /* mask &= stencil[0].writemask */ 279 LLVMValueRef writemask = lp_build_const_int_vec(bld->gallivm, bld->type, local 280 stencil[0].writemask); 281 if (stencil[1].enabled && stencil[1].writemask != stencil[0].writemask && front_facing != NULL) { 283 stencil[1].writemask); 284 writemask = lp_build_select(bld, front_facing, writemask, back_writemas [all...] |
/external/mesa3d/src/gallium/include/pipe/ |
H A D | p_state.h | 219 unsigned writemask:1; /**< allow depth buffer writes? */ member in struct:pipe_depth_state 232 unsigned writemask:8; member in struct:pipe_stencil_state
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/external/mesa3d/src/glsl/ |
H A D | ir_builder.cpp | 49 assign(deref lhs, operand rhs, int writemask) argument 55 NULL, writemask);
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H A D | ir_builder.h | 84 ir_assignment *assign(deref lhs, operand rhs, int writemask);
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/external/mesa3d/src/gallium/auxiliary/tgsi/ |
H A D | tgsi_text.c | 336 uint *writemask ) 344 *writemask = TGSI_WRITEMASK_NONE; 348 *writemask |= TGSI_WRITEMASK_X; 352 *writemask |= TGSI_WRITEMASK_Y; 356 *writemask |= TGSI_WRITEMASK_Z; 360 *writemask |= TGSI_WRITEMASK_W; 363 if (*writemask == TGSI_WRITEMASK_NONE) { 371 *writemask = TGSI_WRITEMASK_XYZW; 683 uint writemask; local 696 if (!parse_opt_writemask( ctx, &writemask )) 1071 uint writemask; local [all...] |