code_generator_arm.cc revision 75afcdd3503a8a8518e5b23d21b6e73306ce39ce
1/* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "code_generator_arm.h" 18 19#include "arch/arm/instruction_set_features_arm.h" 20#include "art_method.h" 21#include "code_generator_utils.h" 22#include "compiled_method.h" 23#include "entrypoints/quick/quick_entrypoints.h" 24#include "gc/accounting/card_table.h" 25#include "intrinsics.h" 26#include "intrinsics_arm.h" 27#include "mirror/array-inl.h" 28#include "mirror/class-inl.h" 29#include "thread.h" 30#include "utils/arm/assembler_arm.h" 31#include "utils/arm/managed_register_arm.h" 32#include "utils/assembler.h" 33#include "utils/stack_checks.h" 34 35namespace art { 36 37template<class MirrorType> 38class GcRoot; 39 40namespace arm { 41 42static bool ExpectedPairLayout(Location location) { 43 // We expected this for both core and fpu register pairs. 44 return ((location.low() & 1) == 0) && (location.low() + 1 == location.high()); 45} 46 47static constexpr int kCurrentMethodStackOffset = 0; 48static constexpr Register kMethodRegisterArgument = R0; 49 50static constexpr Register kCoreAlwaysSpillRegister = R5; 51static constexpr Register kCoreCalleeSaves[] = 52 { R5, R6, R7, R8, R10, R11, LR }; 53static constexpr SRegister kFpuCalleeSaves[] = 54 { S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31 }; 55 56// D31 cannot be split into two S registers, and the register allocator only works on 57// S registers. Therefore there is no need to block it. 58static constexpr DRegister DTMP = D31; 59 60static constexpr uint32_t kPackedSwitchCompareJumpThreshold = 7; 61 62// NOLINT on __ macro to suppress wrong warning/fix (misc-macro-parentheses) from clang-tidy. 63#define __ down_cast<ArmAssembler*>(codegen->GetAssembler())-> // NOLINT 64#define QUICK_ENTRY_POINT(x) QUICK_ENTRYPOINT_OFFSET(kArmPointerSize, x).Int32Value() 65 66static constexpr int kRegListThreshold = 4; 67 68// SaveLiveRegisters and RestoreLiveRegisters from SlowPathCodeARM operate on sets of S registers, 69// for each live D registers they treat two corresponding S registers as live ones. 70// 71// Two following functions (SaveContiguousSRegisterList, RestoreContiguousSRegisterList) build 72// from a list of contiguous S registers a list of contiguous D registers (processing first/last 73// S registers corner cases) and save/restore this new list treating them as D registers. 74// - decreasing code size 75// - avoiding hazards on Cortex-A57, when a pair of S registers for an actual live D register is 76// restored and then used in regular non SlowPath code as D register. 77// 78// For the following example (v means the S register is live): 79// D names: | D0 | D1 | D2 | D4 | ... 80// S names: | S0 | S1 | S2 | S3 | S4 | S5 | S6 | S7 | ... 81// Live? | | v | v | v | v | v | v | | ... 82// 83// S1 and S6 will be saved/restored independently; D registers list (D1, D2) will be processed 84// as D registers. 85static size_t SaveContiguousSRegisterList(size_t first, 86 size_t last, 87 CodeGenerator* codegen, 88 size_t stack_offset) { 89 DCHECK_LE(first, last); 90 if ((first == last) && (first == 0)) { 91 stack_offset += codegen->SaveFloatingPointRegister(stack_offset, first); 92 return stack_offset; 93 } 94 if (first % 2 == 1) { 95 stack_offset += codegen->SaveFloatingPointRegister(stack_offset, first++); 96 } 97 98 bool save_last = false; 99 if (last % 2 == 0) { 100 save_last = true; 101 --last; 102 } 103 104 if (first < last) { 105 DRegister d_reg = static_cast<DRegister>(first / 2); 106 DCHECK_EQ((last - first + 1) % 2, 0u); 107 size_t number_of_d_regs = (last - first + 1) / 2; 108 109 if (number_of_d_regs == 1) { 110 __ StoreDToOffset(d_reg, SP, stack_offset); 111 } else if (number_of_d_regs > 1) { 112 __ add(IP, SP, ShifterOperand(stack_offset)); 113 __ vstmiad(IP, d_reg, number_of_d_regs); 114 } 115 stack_offset += number_of_d_regs * kArmWordSize * 2; 116 } 117 118 if (save_last) { 119 stack_offset += codegen->SaveFloatingPointRegister(stack_offset, last + 1); 120 } 121 122 return stack_offset; 123} 124 125static size_t RestoreContiguousSRegisterList(size_t first, 126 size_t last, 127 CodeGenerator* codegen, 128 size_t stack_offset) { 129 DCHECK_LE(first, last); 130 if ((first == last) && (first == 0)) { 131 stack_offset += codegen->RestoreFloatingPointRegister(stack_offset, first); 132 return stack_offset; 133 } 134 if (first % 2 == 1) { 135 stack_offset += codegen->RestoreFloatingPointRegister(stack_offset, first++); 136 } 137 138 bool restore_last = false; 139 if (last % 2 == 0) { 140 restore_last = true; 141 --last; 142 } 143 144 if (first < last) { 145 DRegister d_reg = static_cast<DRegister>(first / 2); 146 DCHECK_EQ((last - first + 1) % 2, 0u); 147 size_t number_of_d_regs = (last - first + 1) / 2; 148 if (number_of_d_regs == 1) { 149 __ LoadDFromOffset(d_reg, SP, stack_offset); 150 } else if (number_of_d_regs > 1) { 151 __ add(IP, SP, ShifterOperand(stack_offset)); 152 __ vldmiad(IP, d_reg, number_of_d_regs); 153 } 154 stack_offset += number_of_d_regs * kArmWordSize * 2; 155 } 156 157 if (restore_last) { 158 stack_offset += codegen->RestoreFloatingPointRegister(stack_offset, last + 1); 159 } 160 161 return stack_offset; 162} 163 164void SlowPathCodeARM::SaveLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) { 165 size_t stack_offset = codegen->GetFirstRegisterSlotInSlowPath(); 166 size_t orig_offset = stack_offset; 167 168 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); 169 for (uint32_t i : LowToHighBits(core_spills)) { 170 // If the register holds an object, update the stack mask. 171 if (locations->RegisterContainsObject(i)) { 172 locations->SetStackBit(stack_offset / kVRegSize); 173 } 174 DCHECK_LT(stack_offset, codegen->GetFrameSize() - codegen->FrameEntrySpillSize()); 175 DCHECK_LT(i, kMaximumNumberOfExpectedRegisters); 176 saved_core_stack_offsets_[i] = stack_offset; 177 stack_offset += kArmWordSize; 178 } 179 180 int reg_num = POPCOUNT(core_spills); 181 if (reg_num != 0) { 182 if (reg_num > kRegListThreshold) { 183 __ StoreList(RegList(core_spills), orig_offset); 184 } else { 185 stack_offset = orig_offset; 186 for (uint32_t i : LowToHighBits(core_spills)) { 187 stack_offset += codegen->SaveCoreRegister(stack_offset, i); 188 } 189 } 190 } 191 192 uint32_t fp_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ false); 193 orig_offset = stack_offset; 194 for (uint32_t i : LowToHighBits(fp_spills)) { 195 DCHECK_LT(i, kMaximumNumberOfExpectedRegisters); 196 saved_fpu_stack_offsets_[i] = stack_offset; 197 stack_offset += kArmWordSize; 198 } 199 200 stack_offset = orig_offset; 201 while (fp_spills != 0u) { 202 uint32_t begin = CTZ(fp_spills); 203 uint32_t tmp = fp_spills + (1u << begin); 204 fp_spills &= tmp; // Clear the contiguous range of 1s. 205 uint32_t end = (tmp == 0u) ? 32u : CTZ(tmp); // CTZ(0) is undefined. 206 stack_offset = SaveContiguousSRegisterList(begin, end - 1, codegen, stack_offset); 207 } 208 DCHECK_LE(stack_offset, codegen->GetFrameSize() - codegen->FrameEntrySpillSize()); 209} 210 211void SlowPathCodeARM::RestoreLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) { 212 size_t stack_offset = codegen->GetFirstRegisterSlotInSlowPath(); 213 size_t orig_offset = stack_offset; 214 215 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); 216 for (uint32_t i : LowToHighBits(core_spills)) { 217 DCHECK_LT(stack_offset, codegen->GetFrameSize() - codegen->FrameEntrySpillSize()); 218 DCHECK_LT(i, kMaximumNumberOfExpectedRegisters); 219 stack_offset += kArmWordSize; 220 } 221 222 int reg_num = POPCOUNT(core_spills); 223 if (reg_num != 0) { 224 if (reg_num > kRegListThreshold) { 225 __ LoadList(RegList(core_spills), orig_offset); 226 } else { 227 stack_offset = orig_offset; 228 for (uint32_t i : LowToHighBits(core_spills)) { 229 stack_offset += codegen->RestoreCoreRegister(stack_offset, i); 230 } 231 } 232 } 233 234 uint32_t fp_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ false); 235 while (fp_spills != 0u) { 236 uint32_t begin = CTZ(fp_spills); 237 uint32_t tmp = fp_spills + (1u << begin); 238 fp_spills &= tmp; // Clear the contiguous range of 1s. 239 uint32_t end = (tmp == 0u) ? 32u : CTZ(tmp); // CTZ(0) is undefined. 240 stack_offset = RestoreContiguousSRegisterList(begin, end - 1, codegen, stack_offset); 241 } 242 DCHECK_LE(stack_offset, codegen->GetFrameSize() - codegen->FrameEntrySpillSize()); 243} 244 245class NullCheckSlowPathARM : public SlowPathCodeARM { 246 public: 247 explicit NullCheckSlowPathARM(HNullCheck* instruction) : SlowPathCodeARM(instruction) {} 248 249 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 250 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 251 __ Bind(GetEntryLabel()); 252 if (instruction_->CanThrowIntoCatchBlock()) { 253 // Live registers will be restored in the catch block if caught. 254 SaveLiveRegisters(codegen, instruction_->GetLocations()); 255 } 256 arm_codegen->InvokeRuntime(kQuickThrowNullPointer, 257 instruction_, 258 instruction_->GetDexPc(), 259 this); 260 CheckEntrypointTypes<kQuickThrowNullPointer, void, void>(); 261 } 262 263 bool IsFatal() const OVERRIDE { return true; } 264 265 const char* GetDescription() const OVERRIDE { return "NullCheckSlowPathARM"; } 266 267 private: 268 DISALLOW_COPY_AND_ASSIGN(NullCheckSlowPathARM); 269}; 270 271class DivZeroCheckSlowPathARM : public SlowPathCodeARM { 272 public: 273 explicit DivZeroCheckSlowPathARM(HDivZeroCheck* instruction) : SlowPathCodeARM(instruction) {} 274 275 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 276 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 277 __ Bind(GetEntryLabel()); 278 arm_codegen->InvokeRuntime(kQuickThrowDivZero, instruction_, instruction_->GetDexPc(), this); 279 CheckEntrypointTypes<kQuickThrowDivZero, void, void>(); 280 } 281 282 bool IsFatal() const OVERRIDE { return true; } 283 284 const char* GetDescription() const OVERRIDE { return "DivZeroCheckSlowPathARM"; } 285 286 private: 287 DISALLOW_COPY_AND_ASSIGN(DivZeroCheckSlowPathARM); 288}; 289 290class SuspendCheckSlowPathARM : public SlowPathCodeARM { 291 public: 292 SuspendCheckSlowPathARM(HSuspendCheck* instruction, HBasicBlock* successor) 293 : SlowPathCodeARM(instruction), successor_(successor) {} 294 295 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 296 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 297 __ Bind(GetEntryLabel()); 298 arm_codegen->InvokeRuntime(kQuickTestSuspend, instruction_, instruction_->GetDexPc(), this); 299 CheckEntrypointTypes<kQuickTestSuspend, void, void>(); 300 if (successor_ == nullptr) { 301 __ b(GetReturnLabel()); 302 } else { 303 __ b(arm_codegen->GetLabelOf(successor_)); 304 } 305 } 306 307 Label* GetReturnLabel() { 308 DCHECK(successor_ == nullptr); 309 return &return_label_; 310 } 311 312 HBasicBlock* GetSuccessor() const { 313 return successor_; 314 } 315 316 const char* GetDescription() const OVERRIDE { return "SuspendCheckSlowPathARM"; } 317 318 private: 319 // If not null, the block to branch to after the suspend check. 320 HBasicBlock* const successor_; 321 322 // If `successor_` is null, the label to branch to after the suspend check. 323 Label return_label_; 324 325 DISALLOW_COPY_AND_ASSIGN(SuspendCheckSlowPathARM); 326}; 327 328class BoundsCheckSlowPathARM : public SlowPathCodeARM { 329 public: 330 explicit BoundsCheckSlowPathARM(HBoundsCheck* instruction) 331 : SlowPathCodeARM(instruction) {} 332 333 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 334 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 335 LocationSummary* locations = instruction_->GetLocations(); 336 337 __ Bind(GetEntryLabel()); 338 if (instruction_->CanThrowIntoCatchBlock()) { 339 // Live registers will be restored in the catch block if caught. 340 SaveLiveRegisters(codegen, instruction_->GetLocations()); 341 } 342 // We're moving two locations to locations that could overlap, so we need a parallel 343 // move resolver. 344 InvokeRuntimeCallingConvention calling_convention; 345 codegen->EmitParallelMoves( 346 locations->InAt(0), 347 Location::RegisterLocation(calling_convention.GetRegisterAt(0)), 348 Primitive::kPrimInt, 349 locations->InAt(1), 350 Location::RegisterLocation(calling_convention.GetRegisterAt(1)), 351 Primitive::kPrimInt); 352 QuickEntrypointEnum entrypoint = instruction_->AsBoundsCheck()->IsStringCharAt() 353 ? kQuickThrowStringBounds 354 : kQuickThrowArrayBounds; 355 arm_codegen->InvokeRuntime(entrypoint, instruction_, instruction_->GetDexPc(), this); 356 CheckEntrypointTypes<kQuickThrowStringBounds, void, int32_t, int32_t>(); 357 CheckEntrypointTypes<kQuickThrowArrayBounds, void, int32_t, int32_t>(); 358 } 359 360 bool IsFatal() const OVERRIDE { return true; } 361 362 const char* GetDescription() const OVERRIDE { return "BoundsCheckSlowPathARM"; } 363 364 private: 365 DISALLOW_COPY_AND_ASSIGN(BoundsCheckSlowPathARM); 366}; 367 368class LoadClassSlowPathARM : public SlowPathCodeARM { 369 public: 370 LoadClassSlowPathARM(HLoadClass* cls, 371 HInstruction* at, 372 uint32_t dex_pc, 373 bool do_clinit) 374 : SlowPathCodeARM(at), cls_(cls), at_(at), dex_pc_(dex_pc), do_clinit_(do_clinit) { 375 DCHECK(at->IsLoadClass() || at->IsClinitCheck()); 376 } 377 378 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 379 LocationSummary* locations = at_->GetLocations(); 380 381 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 382 __ Bind(GetEntryLabel()); 383 SaveLiveRegisters(codegen, locations); 384 385 InvokeRuntimeCallingConvention calling_convention; 386 __ LoadImmediate(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex()); 387 QuickEntrypointEnum entrypoint = do_clinit_ ? kQuickInitializeStaticStorage 388 : kQuickInitializeType; 389 arm_codegen->InvokeRuntime(entrypoint, at_, dex_pc_, this); 390 if (do_clinit_) { 391 CheckEntrypointTypes<kQuickInitializeStaticStorage, void*, uint32_t>(); 392 } else { 393 CheckEntrypointTypes<kQuickInitializeType, void*, uint32_t>(); 394 } 395 396 // Move the class to the desired location. 397 Location out = locations->Out(); 398 if (out.IsValid()) { 399 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg())); 400 arm_codegen->Move32(locations->Out(), Location::RegisterLocation(R0)); 401 } 402 RestoreLiveRegisters(codegen, locations); 403 __ b(GetExitLabel()); 404 } 405 406 const char* GetDescription() const OVERRIDE { return "LoadClassSlowPathARM"; } 407 408 private: 409 // The class this slow path will load. 410 HLoadClass* const cls_; 411 412 // The instruction where this slow path is happening. 413 // (Might be the load class or an initialization check). 414 HInstruction* const at_; 415 416 // The dex PC of `at_`. 417 const uint32_t dex_pc_; 418 419 // Whether to initialize the class. 420 const bool do_clinit_; 421 422 DISALLOW_COPY_AND_ASSIGN(LoadClassSlowPathARM); 423}; 424 425class LoadStringSlowPathARM : public SlowPathCodeARM { 426 public: 427 explicit LoadStringSlowPathARM(HLoadString* instruction) : SlowPathCodeARM(instruction) {} 428 429 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 430 LocationSummary* locations = instruction_->GetLocations(); 431 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); 432 HLoadString* load = instruction_->AsLoadString(); 433 const uint32_t string_index = load->GetStringIndex(); 434 Register out = locations->Out().AsRegister<Register>(); 435 Register temp = locations->GetTemp(0).AsRegister<Register>(); 436 constexpr bool call_saves_everything_except_r0 = (!kUseReadBarrier || kUseBakerReadBarrier); 437 438 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 439 __ Bind(GetEntryLabel()); 440 SaveLiveRegisters(codegen, locations); 441 442 InvokeRuntimeCallingConvention calling_convention; 443 // In the unlucky case that the `temp` is R0, we preserve the address in `out` across 444 // the kSaveEverything call (or use `out` for the address after non-kSaveEverything call). 445 bool temp_is_r0 = (temp == calling_convention.GetRegisterAt(0)); 446 Register entry_address = temp_is_r0 ? out : temp; 447 DCHECK_NE(entry_address, calling_convention.GetRegisterAt(0)); 448 if (call_saves_everything_except_r0 && temp_is_r0) { 449 __ mov(entry_address, ShifterOperand(temp)); 450 } 451 452 __ LoadImmediate(calling_convention.GetRegisterAt(0), string_index); 453 arm_codegen->InvokeRuntime(kQuickResolveString, instruction_, instruction_->GetDexPc(), this); 454 CheckEntrypointTypes<kQuickResolveString, void*, uint32_t>(); 455 456 // Store the resolved String to the .bss entry. 457 if (call_saves_everything_except_r0) { 458 // The string entry address was preserved in `entry_address` thanks to kSaveEverything. 459 __ str(R0, Address(entry_address)); 460 } else { 461 // For non-Baker read barrier, we need to re-calculate the address of the string entry. 462 CodeGeneratorARM::PcRelativePatchInfo* labels = 463 arm_codegen->NewPcRelativeStringPatch(load->GetDexFile(), string_index); 464 __ BindTrackedLabel(&labels->movw_label); 465 __ movw(entry_address, /* placeholder */ 0u); 466 __ BindTrackedLabel(&labels->movt_label); 467 __ movt(entry_address, /* placeholder */ 0u); 468 __ BindTrackedLabel(&labels->add_pc_label); 469 __ add(entry_address, entry_address, ShifterOperand(PC)); 470 __ str(R0, Address(entry_address)); 471 } 472 473 arm_codegen->Move32(locations->Out(), Location::RegisterLocation(R0)); 474 RestoreLiveRegisters(codegen, locations); 475 476 __ b(GetExitLabel()); 477 } 478 479 const char* GetDescription() const OVERRIDE { return "LoadStringSlowPathARM"; } 480 481 private: 482 DISALLOW_COPY_AND_ASSIGN(LoadStringSlowPathARM); 483}; 484 485class TypeCheckSlowPathARM : public SlowPathCodeARM { 486 public: 487 TypeCheckSlowPathARM(HInstruction* instruction, bool is_fatal) 488 : SlowPathCodeARM(instruction), is_fatal_(is_fatal) {} 489 490 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 491 LocationSummary* locations = instruction_->GetLocations(); 492 Location arg0, arg1; 493 if (instruction_->IsInstanceOf()) { 494 arg0 = locations->InAt(1); 495 arg1 = locations->Out(); 496 } else { 497 arg0 = locations->InAt(0); 498 arg1 = locations->InAt(1); 499 } 500 DCHECK(instruction_->IsCheckCast() 501 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); 502 503 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 504 __ Bind(GetEntryLabel()); 505 506 if (!is_fatal_) { 507 SaveLiveRegisters(codegen, locations); 508 } 509 510 // We're moving two locations to locations that could overlap, so we need a parallel 511 // move resolver. 512 InvokeRuntimeCallingConvention calling_convention; 513 codegen->EmitParallelMoves(arg0, 514 Location::RegisterLocation(calling_convention.GetRegisterAt(0)), 515 Primitive::kPrimNot, 516 arg1, 517 Location::RegisterLocation(calling_convention.GetRegisterAt(1)), 518 Primitive::kPrimNot); 519 if (instruction_->IsInstanceOf()) { 520 arm_codegen->InvokeRuntime(kQuickInstanceofNonTrivial, 521 instruction_, 522 instruction_->GetDexPc(), 523 this); 524 CheckEntrypointTypes<kQuickInstanceofNonTrivial, size_t, mirror::Class*, mirror::Class*>(); 525 arm_codegen->Move32(locations->Out(), Location::RegisterLocation(R0)); 526 } else { 527 DCHECK(instruction_->IsCheckCast()); 528 arm_codegen->InvokeRuntime(kQuickCheckInstanceOf, 529 instruction_, 530 instruction_->GetDexPc(), 531 this); 532 CheckEntrypointTypes<kQuickCheckInstanceOf, void, mirror::Object*, mirror::Class*>(); 533 } 534 535 if (!is_fatal_) { 536 RestoreLiveRegisters(codegen, locations); 537 __ b(GetExitLabel()); 538 } 539 } 540 541 const char* GetDescription() const OVERRIDE { return "TypeCheckSlowPathARM"; } 542 543 bool IsFatal() const OVERRIDE { return is_fatal_; } 544 545 private: 546 const bool is_fatal_; 547 548 DISALLOW_COPY_AND_ASSIGN(TypeCheckSlowPathARM); 549}; 550 551class DeoptimizationSlowPathARM : public SlowPathCodeARM { 552 public: 553 explicit DeoptimizationSlowPathARM(HDeoptimize* instruction) 554 : SlowPathCodeARM(instruction) {} 555 556 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 557 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 558 __ Bind(GetEntryLabel()); 559 arm_codegen->InvokeRuntime(kQuickDeoptimize, instruction_, instruction_->GetDexPc(), this); 560 CheckEntrypointTypes<kQuickDeoptimize, void, void>(); 561 } 562 563 const char* GetDescription() const OVERRIDE { return "DeoptimizationSlowPathARM"; } 564 565 private: 566 DISALLOW_COPY_AND_ASSIGN(DeoptimizationSlowPathARM); 567}; 568 569class ArraySetSlowPathARM : public SlowPathCodeARM { 570 public: 571 explicit ArraySetSlowPathARM(HInstruction* instruction) : SlowPathCodeARM(instruction) {} 572 573 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 574 LocationSummary* locations = instruction_->GetLocations(); 575 __ Bind(GetEntryLabel()); 576 SaveLiveRegisters(codegen, locations); 577 578 InvokeRuntimeCallingConvention calling_convention; 579 HParallelMove parallel_move(codegen->GetGraph()->GetArena()); 580 parallel_move.AddMove( 581 locations->InAt(0), 582 Location::RegisterLocation(calling_convention.GetRegisterAt(0)), 583 Primitive::kPrimNot, 584 nullptr); 585 parallel_move.AddMove( 586 locations->InAt(1), 587 Location::RegisterLocation(calling_convention.GetRegisterAt(1)), 588 Primitive::kPrimInt, 589 nullptr); 590 parallel_move.AddMove( 591 locations->InAt(2), 592 Location::RegisterLocation(calling_convention.GetRegisterAt(2)), 593 Primitive::kPrimNot, 594 nullptr); 595 codegen->GetMoveResolver()->EmitNativeCode(¶llel_move); 596 597 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 598 arm_codegen->InvokeRuntime(kQuickAputObject, instruction_, instruction_->GetDexPc(), this); 599 CheckEntrypointTypes<kQuickAputObject, void, mirror::Array*, int32_t, mirror::Object*>(); 600 RestoreLiveRegisters(codegen, locations); 601 __ b(GetExitLabel()); 602 } 603 604 const char* GetDescription() const OVERRIDE { return "ArraySetSlowPathARM"; } 605 606 private: 607 DISALLOW_COPY_AND_ASSIGN(ArraySetSlowPathARM); 608}; 609 610// Slow path marking an object reference `ref` during a read 611// barrier. The field `obj.field` in the object `obj` holding this 612// reference does not get updated by this slow path after marking (see 613// ReadBarrierMarkAndUpdateFieldSlowPathARM below for that). 614// 615// This means that after the execution of this slow path, `ref` will 616// always be up-to-date, but `obj.field` may not; i.e., after the 617// flip, `ref` will be a to-space reference, but `obj.field` will 618// probably still be a from-space reference (unless it gets updated by 619// another thread, or if another thread installed another object 620// reference (different from `ref`) in `obj.field`). 621class ReadBarrierMarkSlowPathARM : public SlowPathCodeARM { 622 public: 623 ReadBarrierMarkSlowPathARM(HInstruction* instruction, 624 Location ref, 625 Location entrypoint = Location::NoLocation()) 626 : SlowPathCodeARM(instruction), ref_(ref), entrypoint_(entrypoint) { 627 DCHECK(kEmitCompilerReadBarrier); 628 } 629 630 const char* GetDescription() const OVERRIDE { return "ReadBarrierMarkSlowPathARM"; } 631 632 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 633 LocationSummary* locations = instruction_->GetLocations(); 634 Register ref_reg = ref_.AsRegister<Register>(); 635 DCHECK(locations->CanCall()); 636 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(ref_reg)) << ref_reg; 637 DCHECK(instruction_->IsInstanceFieldGet() || 638 instruction_->IsStaticFieldGet() || 639 instruction_->IsArrayGet() || 640 instruction_->IsArraySet() || 641 instruction_->IsLoadClass() || 642 instruction_->IsLoadString() || 643 instruction_->IsInstanceOf() || 644 instruction_->IsCheckCast() || 645 (instruction_->IsInvokeVirtual() && instruction_->GetLocations()->Intrinsified()) || 646 (instruction_->IsInvokeStaticOrDirect() && instruction_->GetLocations()->Intrinsified())) 647 << "Unexpected instruction in read barrier marking slow path: " 648 << instruction_->DebugName(); 649 // The read barrier instrumentation of object ArrayGet 650 // instructions does not support the HIntermediateAddress 651 // instruction. 652 DCHECK(!(instruction_->IsArrayGet() && 653 instruction_->AsArrayGet()->GetArray()->IsIntermediateAddress())); 654 655 __ Bind(GetEntryLabel()); 656 // No need to save live registers; it's taken care of by the 657 // entrypoint. Also, there is no need to update the stack mask, 658 // as this runtime call will not trigger a garbage collection. 659 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 660 DCHECK_NE(ref_reg, SP); 661 DCHECK_NE(ref_reg, LR); 662 DCHECK_NE(ref_reg, PC); 663 // IP is used internally by the ReadBarrierMarkRegX entry point 664 // as a temporary, it cannot be the entry point's input/output. 665 DCHECK_NE(ref_reg, IP); 666 DCHECK(0 <= ref_reg && ref_reg < kNumberOfCoreRegisters) << ref_reg; 667 // "Compact" slow path, saving two moves. 668 // 669 // Instead of using the standard runtime calling convention (input 670 // and output in R0): 671 // 672 // R0 <- ref 673 // R0 <- ReadBarrierMark(R0) 674 // ref <- R0 675 // 676 // we just use rX (the register containing `ref`) as input and output 677 // of a dedicated entrypoint: 678 // 679 // rX <- ReadBarrierMarkRegX(rX) 680 // 681 if (entrypoint_.IsValid()) { 682 arm_codegen->ValidateInvokeRuntimeWithoutRecordingPcInfo(instruction_, this); 683 __ blx(entrypoint_.AsRegister<Register>()); 684 } else { 685 int32_t entry_point_offset = 686 CodeGenerator::GetReadBarrierMarkEntryPointsOffset<kArmPointerSize>(ref_reg); 687 // This runtime call does not require a stack map. 688 arm_codegen->InvokeRuntimeWithoutRecordingPcInfo(entry_point_offset, instruction_, this); 689 } 690 __ b(GetExitLabel()); 691 } 692 693 private: 694 // The location (register) of the marked object reference. 695 const Location ref_; 696 697 // The location of the entrypoint if already loaded. 698 const Location entrypoint_; 699 700 DISALLOW_COPY_AND_ASSIGN(ReadBarrierMarkSlowPathARM); 701}; 702 703// Slow path marking an object reference `ref` during a read barrier, 704// and if needed, atomically updating the field `obj.field` in the 705// object `obj` holding this reference after marking (contrary to 706// ReadBarrierMarkSlowPathARM above, which never tries to update 707// `obj.field`). 708// 709// This means that after the execution of this slow path, both `ref` 710// and `obj.field` will be up-to-date; i.e., after the flip, both will 711// hold the same to-space reference (unless another thread installed 712// another object reference (different from `ref`) in `obj.field`). 713class ReadBarrierMarkAndUpdateFieldSlowPathARM : public SlowPathCodeARM { 714 public: 715 ReadBarrierMarkAndUpdateFieldSlowPathARM(HInstruction* instruction, 716 Location ref, 717 Register obj, 718 Location field_offset, 719 Register temp1, 720 Register temp2) 721 : SlowPathCodeARM(instruction), 722 ref_(ref), 723 obj_(obj), 724 field_offset_(field_offset), 725 temp1_(temp1), 726 temp2_(temp2) { 727 DCHECK(kEmitCompilerReadBarrier); 728 } 729 730 const char* GetDescription() const OVERRIDE { return "ReadBarrierMarkAndUpdateFieldSlowPathARM"; } 731 732 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 733 LocationSummary* locations = instruction_->GetLocations(); 734 Register ref_reg = ref_.AsRegister<Register>(); 735 DCHECK(locations->CanCall()); 736 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(ref_reg)) << ref_reg; 737 // This slow path is only used by the UnsafeCASObject intrinsic. 738 DCHECK((instruction_->IsInvokeVirtual() && instruction_->GetLocations()->Intrinsified())) 739 << "Unexpected instruction in read barrier marking and field updating slow path: " 740 << instruction_->DebugName(); 741 DCHECK(instruction_->GetLocations()->Intrinsified()); 742 DCHECK_EQ(instruction_->AsInvoke()->GetIntrinsic(), Intrinsics::kUnsafeCASObject); 743 DCHECK(field_offset_.IsRegisterPair()) << field_offset_; 744 745 __ Bind(GetEntryLabel()); 746 747 // Save the old reference. 748 // Note that we cannot use IP to save the old reference, as IP is 749 // used internally by the ReadBarrierMarkRegX entry point, and we 750 // need the old reference after the call to that entry point. 751 DCHECK_NE(temp1_, IP); 752 __ Mov(temp1_, ref_reg); 753 754 // No need to save live registers; it's taken care of by the 755 // entrypoint. Also, there is no need to update the stack mask, 756 // as this runtime call will not trigger a garbage collection. 757 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 758 DCHECK_NE(ref_reg, SP); 759 DCHECK_NE(ref_reg, LR); 760 DCHECK_NE(ref_reg, PC); 761 // IP is used internally by the ReadBarrierMarkRegX entry point 762 // as a temporary, it cannot be the entry point's input/output. 763 DCHECK_NE(ref_reg, IP); 764 DCHECK(0 <= ref_reg && ref_reg < kNumberOfCoreRegisters) << ref_reg; 765 // "Compact" slow path, saving two moves. 766 // 767 // Instead of using the standard runtime calling convention (input 768 // and output in R0): 769 // 770 // R0 <- ref 771 // R0 <- ReadBarrierMark(R0) 772 // ref <- R0 773 // 774 // we just use rX (the register containing `ref`) as input and output 775 // of a dedicated entrypoint: 776 // 777 // rX <- ReadBarrierMarkRegX(rX) 778 // 779 int32_t entry_point_offset = 780 CodeGenerator::GetReadBarrierMarkEntryPointsOffset<kArmPointerSize>(ref_reg); 781 // This runtime call does not require a stack map. 782 arm_codegen->InvokeRuntimeWithoutRecordingPcInfo(entry_point_offset, instruction_, this); 783 784 // If the new reference is different from the old reference, 785 // update the field in the holder (`*(obj_ + field_offset_)`). 786 // 787 // Note that this field could also hold a different object, if 788 // another thread had concurrently changed it. In that case, the 789 // LDREX/SUBS/ITNE sequence of instructions in the compare-and-set 790 // (CAS) operation below would abort the CAS, leaving the field 791 // as-is. 792 Label done; 793 __ cmp(temp1_, ShifterOperand(ref_reg)); 794 __ b(&done, EQ); 795 796 // Update the the holder's field atomically. This may fail if 797 // mutator updates before us, but it's OK. This is achieved 798 // using a strong compare-and-set (CAS) operation with relaxed 799 // memory synchronization ordering, where the expected value is 800 // the old reference and the desired value is the new reference. 801 802 // Convenience aliases. 803 Register base = obj_; 804 // The UnsafeCASObject intrinsic uses a register pair as field 805 // offset ("long offset"), of which only the low part contains 806 // data. 807 Register offset = field_offset_.AsRegisterPairLow<Register>(); 808 Register expected = temp1_; 809 Register value = ref_reg; 810 Register tmp_ptr = IP; // Pointer to actual memory. 811 Register tmp = temp2_; // Value in memory. 812 813 __ add(tmp_ptr, base, ShifterOperand(offset)); 814 815 if (kPoisonHeapReferences) { 816 __ PoisonHeapReference(expected); 817 if (value == expected) { 818 // Do not poison `value`, as it is the same register as 819 // `expected`, which has just been poisoned. 820 } else { 821 __ PoisonHeapReference(value); 822 } 823 } 824 825 // do { 826 // tmp = [r_ptr] - expected; 827 // } while (tmp == 0 && failure([r_ptr] <- r_new_value)); 828 829 Label loop_head, exit_loop; 830 __ Bind(&loop_head); 831 832 __ ldrex(tmp, tmp_ptr); 833 834 __ subs(tmp, tmp, ShifterOperand(expected)); 835 836 __ it(NE); 837 __ clrex(NE); 838 839 __ b(&exit_loop, NE); 840 841 __ strex(tmp, value, tmp_ptr); 842 __ cmp(tmp, ShifterOperand(1)); 843 __ b(&loop_head, EQ); 844 845 __ Bind(&exit_loop); 846 847 if (kPoisonHeapReferences) { 848 __ UnpoisonHeapReference(expected); 849 if (value == expected) { 850 // Do not unpoison `value`, as it is the same register as 851 // `expected`, which has just been unpoisoned. 852 } else { 853 __ UnpoisonHeapReference(value); 854 } 855 } 856 857 __ Bind(&done); 858 __ b(GetExitLabel()); 859 } 860 861 private: 862 // The location (register) of the marked object reference. 863 const Location ref_; 864 // The register containing the object holding the marked object reference field. 865 const Register obj_; 866 // The location of the offset of the marked reference field within `obj_`. 867 Location field_offset_; 868 869 const Register temp1_; 870 const Register temp2_; 871 872 DISALLOW_COPY_AND_ASSIGN(ReadBarrierMarkAndUpdateFieldSlowPathARM); 873}; 874 875// Slow path generating a read barrier for a heap reference. 876class ReadBarrierForHeapReferenceSlowPathARM : public SlowPathCodeARM { 877 public: 878 ReadBarrierForHeapReferenceSlowPathARM(HInstruction* instruction, 879 Location out, 880 Location ref, 881 Location obj, 882 uint32_t offset, 883 Location index) 884 : SlowPathCodeARM(instruction), 885 out_(out), 886 ref_(ref), 887 obj_(obj), 888 offset_(offset), 889 index_(index) { 890 DCHECK(kEmitCompilerReadBarrier); 891 // If `obj` is equal to `out` or `ref`, it means the initial object 892 // has been overwritten by (or after) the heap object reference load 893 // to be instrumented, e.g.: 894 // 895 // __ LoadFromOffset(kLoadWord, out, out, offset); 896 // codegen_->GenerateReadBarrierSlow(instruction, out_loc, out_loc, out_loc, offset); 897 // 898 // In that case, we have lost the information about the original 899 // object, and the emitted read barrier cannot work properly. 900 DCHECK(!obj.Equals(out)) << "obj=" << obj << " out=" << out; 901 DCHECK(!obj.Equals(ref)) << "obj=" << obj << " ref=" << ref; 902 } 903 904 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 905 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 906 LocationSummary* locations = instruction_->GetLocations(); 907 Register reg_out = out_.AsRegister<Register>(); 908 DCHECK(locations->CanCall()); 909 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(reg_out)); 910 DCHECK(instruction_->IsInstanceFieldGet() || 911 instruction_->IsStaticFieldGet() || 912 instruction_->IsArrayGet() || 913 instruction_->IsInstanceOf() || 914 instruction_->IsCheckCast() || 915 (instruction_->IsInvokeVirtual()) && instruction_->GetLocations()->Intrinsified()) 916 << "Unexpected instruction in read barrier for heap reference slow path: " 917 << instruction_->DebugName(); 918 // The read barrier instrumentation of object ArrayGet 919 // instructions does not support the HIntermediateAddress 920 // instruction. 921 DCHECK(!(instruction_->IsArrayGet() && 922 instruction_->AsArrayGet()->GetArray()->IsIntermediateAddress())); 923 924 __ Bind(GetEntryLabel()); 925 SaveLiveRegisters(codegen, locations); 926 927 // We may have to change the index's value, but as `index_` is a 928 // constant member (like other "inputs" of this slow path), 929 // introduce a copy of it, `index`. 930 Location index = index_; 931 if (index_.IsValid()) { 932 // Handle `index_` for HArrayGet and UnsafeGetObject/UnsafeGetObjectVolatile intrinsics. 933 if (instruction_->IsArrayGet()) { 934 // Compute the actual memory offset and store it in `index`. 935 Register index_reg = index_.AsRegister<Register>(); 936 DCHECK(locations->GetLiveRegisters()->ContainsCoreRegister(index_reg)); 937 if (codegen->IsCoreCalleeSaveRegister(index_reg)) { 938 // We are about to change the value of `index_reg` (see the 939 // calls to art::arm::Thumb2Assembler::Lsl and 940 // art::arm::Thumb2Assembler::AddConstant below), but it has 941 // not been saved by the previous call to 942 // art::SlowPathCode::SaveLiveRegisters, as it is a 943 // callee-save register -- 944 // art::SlowPathCode::SaveLiveRegisters does not consider 945 // callee-save registers, as it has been designed with the 946 // assumption that callee-save registers are supposed to be 947 // handled by the called function. So, as a callee-save 948 // register, `index_reg` _would_ eventually be saved onto 949 // the stack, but it would be too late: we would have 950 // changed its value earlier. Therefore, we manually save 951 // it here into another freely available register, 952 // `free_reg`, chosen of course among the caller-save 953 // registers (as a callee-save `free_reg` register would 954 // exhibit the same problem). 955 // 956 // Note we could have requested a temporary register from 957 // the register allocator instead; but we prefer not to, as 958 // this is a slow path, and we know we can find a 959 // caller-save register that is available. 960 Register free_reg = FindAvailableCallerSaveRegister(codegen); 961 __ Mov(free_reg, index_reg); 962 index_reg = free_reg; 963 index = Location::RegisterLocation(index_reg); 964 } else { 965 // The initial register stored in `index_` has already been 966 // saved in the call to art::SlowPathCode::SaveLiveRegisters 967 // (as it is not a callee-save register), so we can freely 968 // use it. 969 } 970 // Shifting the index value contained in `index_reg` by the scale 971 // factor (2) cannot overflow in practice, as the runtime is 972 // unable to allocate object arrays with a size larger than 973 // 2^26 - 1 (that is, 2^28 - 4 bytes). 974 __ Lsl(index_reg, index_reg, TIMES_4); 975 static_assert( 976 sizeof(mirror::HeapReference<mirror::Object>) == sizeof(int32_t), 977 "art::mirror::HeapReference<art::mirror::Object> and int32_t have different sizes."); 978 __ AddConstant(index_reg, index_reg, offset_); 979 } else { 980 // In the case of the UnsafeGetObject/UnsafeGetObjectVolatile 981 // intrinsics, `index_` is not shifted by a scale factor of 2 982 // (as in the case of ArrayGet), as it is actually an offset 983 // to an object field within an object. 984 DCHECK(instruction_->IsInvoke()) << instruction_->DebugName(); 985 DCHECK(instruction_->GetLocations()->Intrinsified()); 986 DCHECK((instruction_->AsInvoke()->GetIntrinsic() == Intrinsics::kUnsafeGetObject) || 987 (instruction_->AsInvoke()->GetIntrinsic() == Intrinsics::kUnsafeGetObjectVolatile)) 988 << instruction_->AsInvoke()->GetIntrinsic(); 989 DCHECK_EQ(offset_, 0U); 990 DCHECK(index_.IsRegisterPair()); 991 // UnsafeGet's offset location is a register pair, the low 992 // part contains the correct offset. 993 index = index_.ToLow(); 994 } 995 } 996 997 // We're moving two or three locations to locations that could 998 // overlap, so we need a parallel move resolver. 999 InvokeRuntimeCallingConvention calling_convention; 1000 HParallelMove parallel_move(codegen->GetGraph()->GetArena()); 1001 parallel_move.AddMove(ref_, 1002 Location::RegisterLocation(calling_convention.GetRegisterAt(0)), 1003 Primitive::kPrimNot, 1004 nullptr); 1005 parallel_move.AddMove(obj_, 1006 Location::RegisterLocation(calling_convention.GetRegisterAt(1)), 1007 Primitive::kPrimNot, 1008 nullptr); 1009 if (index.IsValid()) { 1010 parallel_move.AddMove(index, 1011 Location::RegisterLocation(calling_convention.GetRegisterAt(2)), 1012 Primitive::kPrimInt, 1013 nullptr); 1014 codegen->GetMoveResolver()->EmitNativeCode(¶llel_move); 1015 } else { 1016 codegen->GetMoveResolver()->EmitNativeCode(¶llel_move); 1017 __ LoadImmediate(calling_convention.GetRegisterAt(2), offset_); 1018 } 1019 arm_codegen->InvokeRuntime(kQuickReadBarrierSlow, instruction_, instruction_->GetDexPc(), this); 1020 CheckEntrypointTypes< 1021 kQuickReadBarrierSlow, mirror::Object*, mirror::Object*, mirror::Object*, uint32_t>(); 1022 arm_codegen->Move32(out_, Location::RegisterLocation(R0)); 1023 1024 RestoreLiveRegisters(codegen, locations); 1025 __ b(GetExitLabel()); 1026 } 1027 1028 const char* GetDescription() const OVERRIDE { return "ReadBarrierForHeapReferenceSlowPathARM"; } 1029 1030 private: 1031 Register FindAvailableCallerSaveRegister(CodeGenerator* codegen) { 1032 size_t ref = static_cast<int>(ref_.AsRegister<Register>()); 1033 size_t obj = static_cast<int>(obj_.AsRegister<Register>()); 1034 for (size_t i = 0, e = codegen->GetNumberOfCoreRegisters(); i < e; ++i) { 1035 if (i != ref && i != obj && !codegen->IsCoreCalleeSaveRegister(i)) { 1036 return static_cast<Register>(i); 1037 } 1038 } 1039 // We shall never fail to find a free caller-save register, as 1040 // there are more than two core caller-save registers on ARM 1041 // (meaning it is possible to find one which is different from 1042 // `ref` and `obj`). 1043 DCHECK_GT(codegen->GetNumberOfCoreCallerSaveRegisters(), 2u); 1044 LOG(FATAL) << "Could not find a free caller-save register"; 1045 UNREACHABLE(); 1046 } 1047 1048 const Location out_; 1049 const Location ref_; 1050 const Location obj_; 1051 const uint32_t offset_; 1052 // An additional location containing an index to an array. 1053 // Only used for HArrayGet and the UnsafeGetObject & 1054 // UnsafeGetObjectVolatile intrinsics. 1055 const Location index_; 1056 1057 DISALLOW_COPY_AND_ASSIGN(ReadBarrierForHeapReferenceSlowPathARM); 1058}; 1059 1060// Slow path generating a read barrier for a GC root. 1061class ReadBarrierForRootSlowPathARM : public SlowPathCodeARM { 1062 public: 1063 ReadBarrierForRootSlowPathARM(HInstruction* instruction, Location out, Location root) 1064 : SlowPathCodeARM(instruction), out_(out), root_(root) { 1065 DCHECK(kEmitCompilerReadBarrier); 1066 } 1067 1068 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE { 1069 LocationSummary* locations = instruction_->GetLocations(); 1070 Register reg_out = out_.AsRegister<Register>(); 1071 DCHECK(locations->CanCall()); 1072 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(reg_out)); 1073 DCHECK(instruction_->IsLoadClass() || instruction_->IsLoadString()) 1074 << "Unexpected instruction in read barrier for GC root slow path: " 1075 << instruction_->DebugName(); 1076 1077 __ Bind(GetEntryLabel()); 1078 SaveLiveRegisters(codegen, locations); 1079 1080 InvokeRuntimeCallingConvention calling_convention; 1081 CodeGeneratorARM* arm_codegen = down_cast<CodeGeneratorARM*>(codegen); 1082 arm_codegen->Move32(Location::RegisterLocation(calling_convention.GetRegisterAt(0)), root_); 1083 arm_codegen->InvokeRuntime(kQuickReadBarrierForRootSlow, 1084 instruction_, 1085 instruction_->GetDexPc(), 1086 this); 1087 CheckEntrypointTypes<kQuickReadBarrierForRootSlow, mirror::Object*, GcRoot<mirror::Object>*>(); 1088 arm_codegen->Move32(out_, Location::RegisterLocation(R0)); 1089 1090 RestoreLiveRegisters(codegen, locations); 1091 __ b(GetExitLabel()); 1092 } 1093 1094 const char* GetDescription() const OVERRIDE { return "ReadBarrierForRootSlowPathARM"; } 1095 1096 private: 1097 const Location out_; 1098 const Location root_; 1099 1100 DISALLOW_COPY_AND_ASSIGN(ReadBarrierForRootSlowPathARM); 1101}; 1102 1103#undef __ 1104// NOLINT on __ macro to suppress wrong warning/fix (misc-macro-parentheses) from clang-tidy. 1105#define __ down_cast<ArmAssembler*>(GetAssembler())-> // NOLINT 1106 1107inline Condition ARMCondition(IfCondition cond) { 1108 switch (cond) { 1109 case kCondEQ: return EQ; 1110 case kCondNE: return NE; 1111 case kCondLT: return LT; 1112 case kCondLE: return LE; 1113 case kCondGT: return GT; 1114 case kCondGE: return GE; 1115 case kCondB: return LO; 1116 case kCondBE: return LS; 1117 case kCondA: return HI; 1118 case kCondAE: return HS; 1119 } 1120 LOG(FATAL) << "Unreachable"; 1121 UNREACHABLE(); 1122} 1123 1124// Maps signed condition to unsigned condition. 1125inline Condition ARMUnsignedCondition(IfCondition cond) { 1126 switch (cond) { 1127 case kCondEQ: return EQ; 1128 case kCondNE: return NE; 1129 // Signed to unsigned. 1130 case kCondLT: return LO; 1131 case kCondLE: return LS; 1132 case kCondGT: return HI; 1133 case kCondGE: return HS; 1134 // Unsigned remain unchanged. 1135 case kCondB: return LO; 1136 case kCondBE: return LS; 1137 case kCondA: return HI; 1138 case kCondAE: return HS; 1139 } 1140 LOG(FATAL) << "Unreachable"; 1141 UNREACHABLE(); 1142} 1143 1144inline Condition ARMFPCondition(IfCondition cond, bool gt_bias) { 1145 // The ARM condition codes can express all the necessary branches, see the 1146 // "Meaning (floating-point)" column in the table A8-1 of the ARMv7 reference manual. 1147 // There is no dex instruction or HIR that would need the missing conditions 1148 // "equal or unordered" or "not equal". 1149 switch (cond) { 1150 case kCondEQ: return EQ; 1151 case kCondNE: return NE /* unordered */; 1152 case kCondLT: return gt_bias ? CC : LT /* unordered */; 1153 case kCondLE: return gt_bias ? LS : LE /* unordered */; 1154 case kCondGT: return gt_bias ? HI /* unordered */ : GT; 1155 case kCondGE: return gt_bias ? CS /* unordered */ : GE; 1156 default: 1157 LOG(FATAL) << "UNREACHABLE"; 1158 UNREACHABLE(); 1159 } 1160} 1161 1162void CodeGeneratorARM::DumpCoreRegister(std::ostream& stream, int reg) const { 1163 stream << Register(reg); 1164} 1165 1166void CodeGeneratorARM::DumpFloatingPointRegister(std::ostream& stream, int reg) const { 1167 stream << SRegister(reg); 1168} 1169 1170size_t CodeGeneratorARM::SaveCoreRegister(size_t stack_index, uint32_t reg_id) { 1171 __ StoreToOffset(kStoreWord, static_cast<Register>(reg_id), SP, stack_index); 1172 return kArmWordSize; 1173} 1174 1175size_t CodeGeneratorARM::RestoreCoreRegister(size_t stack_index, uint32_t reg_id) { 1176 __ LoadFromOffset(kLoadWord, static_cast<Register>(reg_id), SP, stack_index); 1177 return kArmWordSize; 1178} 1179 1180size_t CodeGeneratorARM::SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) { 1181 __ StoreSToOffset(static_cast<SRegister>(reg_id), SP, stack_index); 1182 return kArmWordSize; 1183} 1184 1185size_t CodeGeneratorARM::RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) { 1186 __ LoadSFromOffset(static_cast<SRegister>(reg_id), SP, stack_index); 1187 return kArmWordSize; 1188} 1189 1190CodeGeneratorARM::CodeGeneratorARM(HGraph* graph, 1191 const ArmInstructionSetFeatures& isa_features, 1192 const CompilerOptions& compiler_options, 1193 OptimizingCompilerStats* stats) 1194 : CodeGenerator(graph, 1195 kNumberOfCoreRegisters, 1196 kNumberOfSRegisters, 1197 kNumberOfRegisterPairs, 1198 ComputeRegisterMask(reinterpret_cast<const int*>(kCoreCalleeSaves), 1199 arraysize(kCoreCalleeSaves)), 1200 ComputeRegisterMask(reinterpret_cast<const int*>(kFpuCalleeSaves), 1201 arraysize(kFpuCalleeSaves)), 1202 compiler_options, 1203 stats), 1204 block_labels_(nullptr), 1205 location_builder_(graph, this), 1206 instruction_visitor_(graph, this), 1207 move_resolver_(graph->GetArena(), this), 1208 assembler_(graph->GetArena()), 1209 isa_features_(isa_features), 1210 uint32_literals_(std::less<uint32_t>(), 1211 graph->GetArena()->Adapter(kArenaAllocCodeGenerator)), 1212 method_patches_(MethodReferenceComparator(), 1213 graph->GetArena()->Adapter(kArenaAllocCodeGenerator)), 1214 call_patches_(MethodReferenceComparator(), 1215 graph->GetArena()->Adapter(kArenaAllocCodeGenerator)), 1216 relative_call_patches_(graph->GetArena()->Adapter(kArenaAllocCodeGenerator)), 1217 pc_relative_dex_cache_patches_(graph->GetArena()->Adapter(kArenaAllocCodeGenerator)), 1218 boot_image_string_patches_(StringReferenceValueComparator(), 1219 graph->GetArena()->Adapter(kArenaAllocCodeGenerator)), 1220 pc_relative_string_patches_(graph->GetArena()->Adapter(kArenaAllocCodeGenerator)), 1221 boot_image_type_patches_(TypeReferenceValueComparator(), 1222 graph->GetArena()->Adapter(kArenaAllocCodeGenerator)), 1223 pc_relative_type_patches_(graph->GetArena()->Adapter(kArenaAllocCodeGenerator)), 1224 boot_image_address_patches_(std::less<uint32_t>(), 1225 graph->GetArena()->Adapter(kArenaAllocCodeGenerator)), 1226 jit_string_patches_(StringReferenceValueComparator(), 1227 graph->GetArena()->Adapter(kArenaAllocCodeGenerator)) { 1228 // Always save the LR register to mimic Quick. 1229 AddAllocatedRegister(Location::RegisterLocation(LR)); 1230} 1231 1232void CodeGeneratorARM::Finalize(CodeAllocator* allocator) { 1233 // Ensure that we fix up branches and literal loads and emit the literal pool. 1234 __ FinalizeCode(); 1235 1236 // Adjust native pc offsets in stack maps. 1237 for (size_t i = 0, num = stack_map_stream_.GetNumberOfStackMaps(); i != num; ++i) { 1238 uint32_t old_position = stack_map_stream_.GetStackMap(i).native_pc_offset; 1239 uint32_t new_position = __ GetAdjustedPosition(old_position); 1240 stack_map_stream_.SetStackMapNativePcOffset(i, new_position); 1241 } 1242 // Adjust pc offsets for the disassembly information. 1243 if (disasm_info_ != nullptr) { 1244 GeneratedCodeInterval* frame_entry_interval = disasm_info_->GetFrameEntryInterval(); 1245 frame_entry_interval->start = __ GetAdjustedPosition(frame_entry_interval->start); 1246 frame_entry_interval->end = __ GetAdjustedPosition(frame_entry_interval->end); 1247 for (auto& it : *disasm_info_->GetInstructionIntervals()) { 1248 it.second.start = __ GetAdjustedPosition(it.second.start); 1249 it.second.end = __ GetAdjustedPosition(it.second.end); 1250 } 1251 for (auto& it : *disasm_info_->GetSlowPathIntervals()) { 1252 it.code_interval.start = __ GetAdjustedPosition(it.code_interval.start); 1253 it.code_interval.end = __ GetAdjustedPosition(it.code_interval.end); 1254 } 1255 } 1256 1257 CodeGenerator::Finalize(allocator); 1258} 1259 1260void CodeGeneratorARM::SetupBlockedRegisters() const { 1261 // Stack register, LR and PC are always reserved. 1262 blocked_core_registers_[SP] = true; 1263 blocked_core_registers_[LR] = true; 1264 blocked_core_registers_[PC] = true; 1265 1266 // Reserve thread register. 1267 blocked_core_registers_[TR] = true; 1268 1269 // Reserve temp register. 1270 blocked_core_registers_[IP] = true; 1271 1272 if (GetGraph()->IsDebuggable()) { 1273 // Stubs do not save callee-save floating point registers. If the graph 1274 // is debuggable, we need to deal with these registers differently. For 1275 // now, just block them. 1276 for (size_t i = 0; i < arraysize(kFpuCalleeSaves); ++i) { 1277 blocked_fpu_registers_[kFpuCalleeSaves[i]] = true; 1278 } 1279 } 1280} 1281 1282InstructionCodeGeneratorARM::InstructionCodeGeneratorARM(HGraph* graph, CodeGeneratorARM* codegen) 1283 : InstructionCodeGenerator(graph, codegen), 1284 assembler_(codegen->GetAssembler()), 1285 codegen_(codegen) {} 1286 1287void CodeGeneratorARM::ComputeSpillMask() { 1288 core_spill_mask_ = allocated_registers_.GetCoreRegisters() & core_callee_save_mask_; 1289 DCHECK_NE(core_spill_mask_, 0u) << "At least the return address register must be saved"; 1290 // There is no easy instruction to restore just the PC on thumb2. We spill and 1291 // restore another arbitrary register. 1292 core_spill_mask_ |= (1 << kCoreAlwaysSpillRegister); 1293 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; 1294 // We use vpush and vpop for saving and restoring floating point registers, which take 1295 // a SRegister and the number of registers to save/restore after that SRegister. We 1296 // therefore update the `fpu_spill_mask_` to also contain those registers not allocated, 1297 // but in the range. 1298 if (fpu_spill_mask_ != 0) { 1299 uint32_t least_significant_bit = LeastSignificantBit(fpu_spill_mask_); 1300 uint32_t most_significant_bit = MostSignificantBit(fpu_spill_mask_); 1301 for (uint32_t i = least_significant_bit + 1 ; i < most_significant_bit; ++i) { 1302 fpu_spill_mask_ |= (1 << i); 1303 } 1304 } 1305} 1306 1307static dwarf::Reg DWARFReg(Register reg) { 1308 return dwarf::Reg::ArmCore(static_cast<int>(reg)); 1309} 1310 1311static dwarf::Reg DWARFReg(SRegister reg) { 1312 return dwarf::Reg::ArmFp(static_cast<int>(reg)); 1313} 1314 1315void CodeGeneratorARM::GenerateFrameEntry() { 1316 bool skip_overflow_check = 1317 IsLeafMethod() && !FrameNeedsStackCheck(GetFrameSize(), InstructionSet::kArm); 1318 DCHECK(GetCompilerOptions().GetImplicitStackOverflowChecks()); 1319 __ Bind(&frame_entry_label_); 1320 1321 if (HasEmptyFrame()) { 1322 return; 1323 } 1324 1325 if (!skip_overflow_check) { 1326 __ AddConstant(IP, SP, -static_cast<int32_t>(GetStackOverflowReservedBytes(kArm))); 1327 __ LoadFromOffset(kLoadWord, IP, IP, 0); 1328 RecordPcInfo(nullptr, 0); 1329 } 1330 1331 __ PushList(core_spill_mask_); 1332 __ cfi().AdjustCFAOffset(kArmWordSize * POPCOUNT(core_spill_mask_)); 1333 __ cfi().RelOffsetForMany(DWARFReg(kMethodRegisterArgument), 0, core_spill_mask_, kArmWordSize); 1334 if (fpu_spill_mask_ != 0) { 1335 SRegister start_register = SRegister(LeastSignificantBit(fpu_spill_mask_)); 1336 __ vpushs(start_register, POPCOUNT(fpu_spill_mask_)); 1337 __ cfi().AdjustCFAOffset(kArmWordSize * POPCOUNT(fpu_spill_mask_)); 1338 __ cfi().RelOffsetForMany(DWARFReg(S0), 0, fpu_spill_mask_, kArmWordSize); 1339 } 1340 int adjust = GetFrameSize() - FrameEntrySpillSize(); 1341 __ AddConstant(SP, -adjust); 1342 __ cfi().AdjustCFAOffset(adjust); 1343 1344 // Save the current method if we need it. Note that we do not 1345 // do this in HCurrentMethod, as the instruction might have been removed 1346 // in the SSA graph. 1347 if (RequiresCurrentMethod()) { 1348 __ StoreToOffset(kStoreWord, kMethodRegisterArgument, SP, 0); 1349 } 1350} 1351 1352void CodeGeneratorARM::GenerateFrameExit() { 1353 if (HasEmptyFrame()) { 1354 __ bx(LR); 1355 return; 1356 } 1357 __ cfi().RememberState(); 1358 int adjust = GetFrameSize() - FrameEntrySpillSize(); 1359 __ AddConstant(SP, adjust); 1360 __ cfi().AdjustCFAOffset(-adjust); 1361 if (fpu_spill_mask_ != 0) { 1362 SRegister start_register = SRegister(LeastSignificantBit(fpu_spill_mask_)); 1363 __ vpops(start_register, POPCOUNT(fpu_spill_mask_)); 1364 __ cfi().AdjustCFAOffset(-static_cast<int>(kArmPointerSize) * POPCOUNT(fpu_spill_mask_)); 1365 __ cfi().RestoreMany(DWARFReg(SRegister(0)), fpu_spill_mask_); 1366 } 1367 // Pop LR into PC to return. 1368 DCHECK_NE(core_spill_mask_ & (1 << LR), 0U); 1369 uint32_t pop_mask = (core_spill_mask_ & (~(1 << LR))) | 1 << PC; 1370 __ PopList(pop_mask); 1371 __ cfi().RestoreState(); 1372 __ cfi().DefCFAOffset(GetFrameSize()); 1373} 1374 1375void CodeGeneratorARM::Bind(HBasicBlock* block) { 1376 Label* label = GetLabelOf(block); 1377 __ BindTrackedLabel(label); 1378} 1379 1380Location InvokeDexCallingConventionVisitorARM::GetNextLocation(Primitive::Type type) { 1381 switch (type) { 1382 case Primitive::kPrimBoolean: 1383 case Primitive::kPrimByte: 1384 case Primitive::kPrimChar: 1385 case Primitive::kPrimShort: 1386 case Primitive::kPrimInt: 1387 case Primitive::kPrimNot: { 1388 uint32_t index = gp_index_++; 1389 uint32_t stack_index = stack_index_++; 1390 if (index < calling_convention.GetNumberOfRegisters()) { 1391 return Location::RegisterLocation(calling_convention.GetRegisterAt(index)); 1392 } else { 1393 return Location::StackSlot(calling_convention.GetStackOffsetOf(stack_index)); 1394 } 1395 } 1396 1397 case Primitive::kPrimLong: { 1398 uint32_t index = gp_index_; 1399 uint32_t stack_index = stack_index_; 1400 gp_index_ += 2; 1401 stack_index_ += 2; 1402 if (index + 1 < calling_convention.GetNumberOfRegisters()) { 1403 if (calling_convention.GetRegisterAt(index) == R1) { 1404 // Skip R1, and use R2_R3 instead. 1405 gp_index_++; 1406 index++; 1407 } 1408 } 1409 if (index + 1 < calling_convention.GetNumberOfRegisters()) { 1410 DCHECK_EQ(calling_convention.GetRegisterAt(index) + 1, 1411 calling_convention.GetRegisterAt(index + 1)); 1412 1413 return Location::RegisterPairLocation(calling_convention.GetRegisterAt(index), 1414 calling_convention.GetRegisterAt(index + 1)); 1415 } else { 1416 return Location::DoubleStackSlot(calling_convention.GetStackOffsetOf(stack_index)); 1417 } 1418 } 1419 1420 case Primitive::kPrimFloat: { 1421 uint32_t stack_index = stack_index_++; 1422 if (float_index_ % 2 == 0) { 1423 float_index_ = std::max(double_index_, float_index_); 1424 } 1425 if (float_index_ < calling_convention.GetNumberOfFpuRegisters()) { 1426 return Location::FpuRegisterLocation(calling_convention.GetFpuRegisterAt(float_index_++)); 1427 } else { 1428 return Location::StackSlot(calling_convention.GetStackOffsetOf(stack_index)); 1429 } 1430 } 1431 1432 case Primitive::kPrimDouble: { 1433 double_index_ = std::max(double_index_, RoundUp(float_index_, 2)); 1434 uint32_t stack_index = stack_index_; 1435 stack_index_ += 2; 1436 if (double_index_ + 1 < calling_convention.GetNumberOfFpuRegisters()) { 1437 uint32_t index = double_index_; 1438 double_index_ += 2; 1439 Location result = Location::FpuRegisterPairLocation( 1440 calling_convention.GetFpuRegisterAt(index), 1441 calling_convention.GetFpuRegisterAt(index + 1)); 1442 DCHECK(ExpectedPairLayout(result)); 1443 return result; 1444 } else { 1445 return Location::DoubleStackSlot(calling_convention.GetStackOffsetOf(stack_index)); 1446 } 1447 } 1448 1449 case Primitive::kPrimVoid: 1450 LOG(FATAL) << "Unexpected parameter type " << type; 1451 break; 1452 } 1453 return Location::NoLocation(); 1454} 1455 1456Location InvokeDexCallingConventionVisitorARM::GetReturnLocation(Primitive::Type type) const { 1457 switch (type) { 1458 case Primitive::kPrimBoolean: 1459 case Primitive::kPrimByte: 1460 case Primitive::kPrimChar: 1461 case Primitive::kPrimShort: 1462 case Primitive::kPrimInt: 1463 case Primitive::kPrimNot: { 1464 return Location::RegisterLocation(R0); 1465 } 1466 1467 case Primitive::kPrimFloat: { 1468 return Location::FpuRegisterLocation(S0); 1469 } 1470 1471 case Primitive::kPrimLong: { 1472 return Location::RegisterPairLocation(R0, R1); 1473 } 1474 1475 case Primitive::kPrimDouble: { 1476 return Location::FpuRegisterPairLocation(S0, S1); 1477 } 1478 1479 case Primitive::kPrimVoid: 1480 return Location::NoLocation(); 1481 } 1482 1483 UNREACHABLE(); 1484} 1485 1486Location InvokeDexCallingConventionVisitorARM::GetMethodLocation() const { 1487 return Location::RegisterLocation(kMethodRegisterArgument); 1488} 1489 1490void CodeGeneratorARM::Move32(Location destination, Location source) { 1491 if (source.Equals(destination)) { 1492 return; 1493 } 1494 if (destination.IsRegister()) { 1495 if (source.IsRegister()) { 1496 __ Mov(destination.AsRegister<Register>(), source.AsRegister<Register>()); 1497 } else if (source.IsFpuRegister()) { 1498 __ vmovrs(destination.AsRegister<Register>(), source.AsFpuRegister<SRegister>()); 1499 } else { 1500 __ LoadFromOffset(kLoadWord, destination.AsRegister<Register>(), SP, source.GetStackIndex()); 1501 } 1502 } else if (destination.IsFpuRegister()) { 1503 if (source.IsRegister()) { 1504 __ vmovsr(destination.AsFpuRegister<SRegister>(), source.AsRegister<Register>()); 1505 } else if (source.IsFpuRegister()) { 1506 __ vmovs(destination.AsFpuRegister<SRegister>(), source.AsFpuRegister<SRegister>()); 1507 } else { 1508 __ LoadSFromOffset(destination.AsFpuRegister<SRegister>(), SP, source.GetStackIndex()); 1509 } 1510 } else { 1511 DCHECK(destination.IsStackSlot()) << destination; 1512 if (source.IsRegister()) { 1513 __ StoreToOffset(kStoreWord, source.AsRegister<Register>(), SP, destination.GetStackIndex()); 1514 } else if (source.IsFpuRegister()) { 1515 __ StoreSToOffset(source.AsFpuRegister<SRegister>(), SP, destination.GetStackIndex()); 1516 } else { 1517 DCHECK(source.IsStackSlot()) << source; 1518 __ LoadFromOffset(kLoadWord, IP, SP, source.GetStackIndex()); 1519 __ StoreToOffset(kStoreWord, IP, SP, destination.GetStackIndex()); 1520 } 1521 } 1522} 1523 1524void CodeGeneratorARM::Move64(Location destination, Location source) { 1525 if (source.Equals(destination)) { 1526 return; 1527 } 1528 if (destination.IsRegisterPair()) { 1529 if (source.IsRegisterPair()) { 1530 EmitParallelMoves( 1531 Location::RegisterLocation(source.AsRegisterPairHigh<Register>()), 1532 Location::RegisterLocation(destination.AsRegisterPairHigh<Register>()), 1533 Primitive::kPrimInt, 1534 Location::RegisterLocation(source.AsRegisterPairLow<Register>()), 1535 Location::RegisterLocation(destination.AsRegisterPairLow<Register>()), 1536 Primitive::kPrimInt); 1537 } else if (source.IsFpuRegister()) { 1538 UNIMPLEMENTED(FATAL); 1539 } else if (source.IsFpuRegisterPair()) { 1540 __ vmovrrd(destination.AsRegisterPairLow<Register>(), 1541 destination.AsRegisterPairHigh<Register>(), 1542 FromLowSToD(source.AsFpuRegisterPairLow<SRegister>())); 1543 } else { 1544 DCHECK(source.IsDoubleStackSlot()); 1545 DCHECK(ExpectedPairLayout(destination)); 1546 __ LoadFromOffset(kLoadWordPair, destination.AsRegisterPairLow<Register>(), 1547 SP, source.GetStackIndex()); 1548 } 1549 } else if (destination.IsFpuRegisterPair()) { 1550 if (source.IsDoubleStackSlot()) { 1551 __ LoadDFromOffset(FromLowSToD(destination.AsFpuRegisterPairLow<SRegister>()), 1552 SP, 1553 source.GetStackIndex()); 1554 } else if (source.IsRegisterPair()) { 1555 __ vmovdrr(FromLowSToD(destination.AsFpuRegisterPairLow<SRegister>()), 1556 source.AsRegisterPairLow<Register>(), 1557 source.AsRegisterPairHigh<Register>()); 1558 } else { 1559 UNIMPLEMENTED(FATAL); 1560 } 1561 } else { 1562 DCHECK(destination.IsDoubleStackSlot()); 1563 if (source.IsRegisterPair()) { 1564 // No conflict possible, so just do the moves. 1565 if (source.AsRegisterPairLow<Register>() == R1) { 1566 DCHECK_EQ(source.AsRegisterPairHigh<Register>(), R2); 1567 __ StoreToOffset(kStoreWord, R1, SP, destination.GetStackIndex()); 1568 __ StoreToOffset(kStoreWord, R2, SP, destination.GetHighStackIndex(kArmWordSize)); 1569 } else { 1570 __ StoreToOffset(kStoreWordPair, source.AsRegisterPairLow<Register>(), 1571 SP, destination.GetStackIndex()); 1572 } 1573 } else if (source.IsFpuRegisterPair()) { 1574 __ StoreDToOffset(FromLowSToD(source.AsFpuRegisterPairLow<SRegister>()), 1575 SP, 1576 destination.GetStackIndex()); 1577 } else { 1578 DCHECK(source.IsDoubleStackSlot()); 1579 EmitParallelMoves( 1580 Location::StackSlot(source.GetStackIndex()), 1581 Location::StackSlot(destination.GetStackIndex()), 1582 Primitive::kPrimInt, 1583 Location::StackSlot(source.GetHighStackIndex(kArmWordSize)), 1584 Location::StackSlot(destination.GetHighStackIndex(kArmWordSize)), 1585 Primitive::kPrimInt); 1586 } 1587 } 1588} 1589 1590void CodeGeneratorARM::MoveConstant(Location location, int32_t value) { 1591 DCHECK(location.IsRegister()); 1592 __ LoadImmediate(location.AsRegister<Register>(), value); 1593} 1594 1595void CodeGeneratorARM::MoveLocation(Location dst, Location src, Primitive::Type dst_type) { 1596 HParallelMove move(GetGraph()->GetArena()); 1597 move.AddMove(src, dst, dst_type, nullptr); 1598 GetMoveResolver()->EmitNativeCode(&move); 1599} 1600 1601void CodeGeneratorARM::AddLocationAsTemp(Location location, LocationSummary* locations) { 1602 if (location.IsRegister()) { 1603 locations->AddTemp(location); 1604 } else if (location.IsRegisterPair()) { 1605 locations->AddTemp(Location::RegisterLocation(location.AsRegisterPairLow<Register>())); 1606 locations->AddTemp(Location::RegisterLocation(location.AsRegisterPairHigh<Register>())); 1607 } else { 1608 UNIMPLEMENTED(FATAL) << "AddLocationAsTemp not implemented for location " << location; 1609 } 1610} 1611 1612void CodeGeneratorARM::InvokeRuntime(QuickEntrypointEnum entrypoint, 1613 HInstruction* instruction, 1614 uint32_t dex_pc, 1615 SlowPathCode* slow_path) { 1616 ValidateInvokeRuntime(entrypoint, instruction, slow_path); 1617 GenerateInvokeRuntime(GetThreadOffset<kArmPointerSize>(entrypoint).Int32Value()); 1618 if (EntrypointRequiresStackMap(entrypoint)) { 1619 RecordPcInfo(instruction, dex_pc, slow_path); 1620 } 1621} 1622 1623void CodeGeneratorARM::InvokeRuntimeWithoutRecordingPcInfo(int32_t entry_point_offset, 1624 HInstruction* instruction, 1625 SlowPathCode* slow_path) { 1626 ValidateInvokeRuntimeWithoutRecordingPcInfo(instruction, slow_path); 1627 GenerateInvokeRuntime(entry_point_offset); 1628} 1629 1630void CodeGeneratorARM::GenerateInvokeRuntime(int32_t entry_point_offset) { 1631 __ LoadFromOffset(kLoadWord, LR, TR, entry_point_offset); 1632 __ blx(LR); 1633} 1634 1635void InstructionCodeGeneratorARM::HandleGoto(HInstruction* got, HBasicBlock* successor) { 1636 DCHECK(!successor->IsExitBlock()); 1637 1638 HBasicBlock* block = got->GetBlock(); 1639 HInstruction* previous = got->GetPrevious(); 1640 1641 HLoopInformation* info = block->GetLoopInformation(); 1642 if (info != nullptr && info->IsBackEdge(*block) && info->HasSuspendCheck()) { 1643 codegen_->ClearSpillSlotsFromLoopPhisInStackMap(info->GetSuspendCheck()); 1644 GenerateSuspendCheck(info->GetSuspendCheck(), successor); 1645 return; 1646 } 1647 1648 if (block->IsEntryBlock() && (previous != nullptr) && previous->IsSuspendCheck()) { 1649 GenerateSuspendCheck(previous->AsSuspendCheck(), nullptr); 1650 } 1651 if (!codegen_->GoesToNextBlock(got->GetBlock(), successor)) { 1652 __ b(codegen_->GetLabelOf(successor)); 1653 } 1654} 1655 1656void LocationsBuilderARM::VisitGoto(HGoto* got) { 1657 got->SetLocations(nullptr); 1658} 1659 1660void InstructionCodeGeneratorARM::VisitGoto(HGoto* got) { 1661 HandleGoto(got, got->GetSuccessor()); 1662} 1663 1664void LocationsBuilderARM::VisitTryBoundary(HTryBoundary* try_boundary) { 1665 try_boundary->SetLocations(nullptr); 1666} 1667 1668void InstructionCodeGeneratorARM::VisitTryBoundary(HTryBoundary* try_boundary) { 1669 HBasicBlock* successor = try_boundary->GetNormalFlowSuccessor(); 1670 if (!successor->IsExitBlock()) { 1671 HandleGoto(try_boundary, successor); 1672 } 1673} 1674 1675void LocationsBuilderARM::VisitExit(HExit* exit) { 1676 exit->SetLocations(nullptr); 1677} 1678 1679void InstructionCodeGeneratorARM::VisitExit(HExit* exit ATTRIBUTE_UNUSED) { 1680} 1681 1682void InstructionCodeGeneratorARM::GenerateVcmp(HInstruction* instruction) { 1683 Primitive::Type type = instruction->InputAt(0)->GetType(); 1684 Location lhs_loc = instruction->GetLocations()->InAt(0); 1685 Location rhs_loc = instruction->GetLocations()->InAt(1); 1686 if (rhs_loc.IsConstant()) { 1687 // 0.0 is the only immediate that can be encoded directly in 1688 // a VCMP instruction. 1689 // 1690 // Both the JLS (section 15.20.1) and the JVMS (section 6.5) 1691 // specify that in a floating-point comparison, positive zero 1692 // and negative zero are considered equal, so we can use the 1693 // literal 0.0 for both cases here. 1694 // 1695 // Note however that some methods (Float.equal, Float.compare, 1696 // Float.compareTo, Double.equal, Double.compare, 1697 // Double.compareTo, Math.max, Math.min, StrictMath.max, 1698 // StrictMath.min) consider 0.0 to be (strictly) greater than 1699 // -0.0. So if we ever translate calls to these methods into a 1700 // HCompare instruction, we must handle the -0.0 case with 1701 // care here. 1702 DCHECK(rhs_loc.GetConstant()->IsArithmeticZero()); 1703 if (type == Primitive::kPrimFloat) { 1704 __ vcmpsz(lhs_loc.AsFpuRegister<SRegister>()); 1705 } else { 1706 DCHECK_EQ(type, Primitive::kPrimDouble); 1707 __ vcmpdz(FromLowSToD(lhs_loc.AsFpuRegisterPairLow<SRegister>())); 1708 } 1709 } else { 1710 if (type == Primitive::kPrimFloat) { 1711 __ vcmps(lhs_loc.AsFpuRegister<SRegister>(), rhs_loc.AsFpuRegister<SRegister>()); 1712 } else { 1713 DCHECK_EQ(type, Primitive::kPrimDouble); 1714 __ vcmpd(FromLowSToD(lhs_loc.AsFpuRegisterPairLow<SRegister>()), 1715 FromLowSToD(rhs_loc.AsFpuRegisterPairLow<SRegister>())); 1716 } 1717 } 1718} 1719 1720void InstructionCodeGeneratorARM::GenerateFPJumps(HCondition* cond, 1721 Label* true_label, 1722 Label* false_label ATTRIBUTE_UNUSED) { 1723 __ vmstat(); // transfer FP status register to ARM APSR. 1724 __ b(true_label, ARMFPCondition(cond->GetCondition(), cond->IsGtBias())); 1725} 1726 1727void InstructionCodeGeneratorARM::GenerateLongComparesAndJumps(HCondition* cond, 1728 Label* true_label, 1729 Label* false_label) { 1730 LocationSummary* locations = cond->GetLocations(); 1731 Location left = locations->InAt(0); 1732 Location right = locations->InAt(1); 1733 IfCondition if_cond = cond->GetCondition(); 1734 1735 Register left_high = left.AsRegisterPairHigh<Register>(); 1736 Register left_low = left.AsRegisterPairLow<Register>(); 1737 IfCondition true_high_cond = if_cond; 1738 IfCondition false_high_cond = cond->GetOppositeCondition(); 1739 Condition final_condition = ARMUnsignedCondition(if_cond); // unsigned on lower part 1740 1741 // Set the conditions for the test, remembering that == needs to be 1742 // decided using the low words. 1743 // TODO: consider avoiding jumps with temporary and CMP low+SBC high 1744 switch (if_cond) { 1745 case kCondEQ: 1746 case kCondNE: 1747 // Nothing to do. 1748 break; 1749 case kCondLT: 1750 false_high_cond = kCondGT; 1751 break; 1752 case kCondLE: 1753 true_high_cond = kCondLT; 1754 break; 1755 case kCondGT: 1756 false_high_cond = kCondLT; 1757 break; 1758 case kCondGE: 1759 true_high_cond = kCondGT; 1760 break; 1761 case kCondB: 1762 false_high_cond = kCondA; 1763 break; 1764 case kCondBE: 1765 true_high_cond = kCondB; 1766 break; 1767 case kCondA: 1768 false_high_cond = kCondB; 1769 break; 1770 case kCondAE: 1771 true_high_cond = kCondA; 1772 break; 1773 } 1774 if (right.IsConstant()) { 1775 int64_t value = right.GetConstant()->AsLongConstant()->GetValue(); 1776 int32_t val_low = Low32Bits(value); 1777 int32_t val_high = High32Bits(value); 1778 1779 __ CmpConstant(left_high, val_high); 1780 if (if_cond == kCondNE) { 1781 __ b(true_label, ARMCondition(true_high_cond)); 1782 } else if (if_cond == kCondEQ) { 1783 __ b(false_label, ARMCondition(false_high_cond)); 1784 } else { 1785 __ b(true_label, ARMCondition(true_high_cond)); 1786 __ b(false_label, ARMCondition(false_high_cond)); 1787 } 1788 // Must be equal high, so compare the lows. 1789 __ CmpConstant(left_low, val_low); 1790 } else { 1791 Register right_high = right.AsRegisterPairHigh<Register>(); 1792 Register right_low = right.AsRegisterPairLow<Register>(); 1793 1794 __ cmp(left_high, ShifterOperand(right_high)); 1795 if (if_cond == kCondNE) { 1796 __ b(true_label, ARMCondition(true_high_cond)); 1797 } else if (if_cond == kCondEQ) { 1798 __ b(false_label, ARMCondition(false_high_cond)); 1799 } else { 1800 __ b(true_label, ARMCondition(true_high_cond)); 1801 __ b(false_label, ARMCondition(false_high_cond)); 1802 } 1803 // Must be equal high, so compare the lows. 1804 __ cmp(left_low, ShifterOperand(right_low)); 1805 } 1806 // The last comparison might be unsigned. 1807 // TODO: optimize cases where this is always true/false 1808 __ b(true_label, final_condition); 1809} 1810 1811void InstructionCodeGeneratorARM::GenerateCompareTestAndBranch(HCondition* condition, 1812 Label* true_target_in, 1813 Label* false_target_in) { 1814 // Generated branching requires both targets to be explicit. If either of the 1815 // targets is nullptr (fallthrough) use and bind `fallthrough_target` instead. 1816 Label fallthrough_target; 1817 Label* true_target = true_target_in == nullptr ? &fallthrough_target : true_target_in; 1818 Label* false_target = false_target_in == nullptr ? &fallthrough_target : false_target_in; 1819 1820 Primitive::Type type = condition->InputAt(0)->GetType(); 1821 switch (type) { 1822 case Primitive::kPrimLong: 1823 GenerateLongComparesAndJumps(condition, true_target, false_target); 1824 break; 1825 case Primitive::kPrimFloat: 1826 case Primitive::kPrimDouble: 1827 GenerateVcmp(condition); 1828 GenerateFPJumps(condition, true_target, false_target); 1829 break; 1830 default: 1831 LOG(FATAL) << "Unexpected compare type " << type; 1832 } 1833 1834 if (false_target != &fallthrough_target) { 1835 __ b(false_target); 1836 } 1837 1838 if (fallthrough_target.IsLinked()) { 1839 __ Bind(&fallthrough_target); 1840 } 1841} 1842 1843void InstructionCodeGeneratorARM::GenerateTestAndBranch(HInstruction* instruction, 1844 size_t condition_input_index, 1845 Label* true_target, 1846 Label* false_target) { 1847 HInstruction* cond = instruction->InputAt(condition_input_index); 1848 1849 if (true_target == nullptr && false_target == nullptr) { 1850 // Nothing to do. The code always falls through. 1851 return; 1852 } else if (cond->IsIntConstant()) { 1853 // Constant condition, statically compared against "true" (integer value 1). 1854 if (cond->AsIntConstant()->IsTrue()) { 1855 if (true_target != nullptr) { 1856 __ b(true_target); 1857 } 1858 } else { 1859 DCHECK(cond->AsIntConstant()->IsFalse()) << cond->AsIntConstant()->GetValue(); 1860 if (false_target != nullptr) { 1861 __ b(false_target); 1862 } 1863 } 1864 return; 1865 } 1866 1867 // The following code generates these patterns: 1868 // (1) true_target == nullptr && false_target != nullptr 1869 // - opposite condition true => branch to false_target 1870 // (2) true_target != nullptr && false_target == nullptr 1871 // - condition true => branch to true_target 1872 // (3) true_target != nullptr && false_target != nullptr 1873 // - condition true => branch to true_target 1874 // - branch to false_target 1875 if (IsBooleanValueOrMaterializedCondition(cond)) { 1876 // Condition has been materialized, compare the output to 0. 1877 Location cond_val = instruction->GetLocations()->InAt(condition_input_index); 1878 DCHECK(cond_val.IsRegister()); 1879 if (true_target == nullptr) { 1880 __ CompareAndBranchIfZero(cond_val.AsRegister<Register>(), false_target); 1881 } else { 1882 __ CompareAndBranchIfNonZero(cond_val.AsRegister<Register>(), true_target); 1883 } 1884 } else { 1885 // Condition has not been materialized. Use its inputs as the comparison and 1886 // its condition as the branch condition. 1887 HCondition* condition = cond->AsCondition(); 1888 1889 // If this is a long or FP comparison that has been folded into 1890 // the HCondition, generate the comparison directly. 1891 Primitive::Type type = condition->InputAt(0)->GetType(); 1892 if (type == Primitive::kPrimLong || Primitive::IsFloatingPointType(type)) { 1893 GenerateCompareTestAndBranch(condition, true_target, false_target); 1894 return; 1895 } 1896 1897 LocationSummary* locations = cond->GetLocations(); 1898 DCHECK(locations->InAt(0).IsRegister()); 1899 Register left = locations->InAt(0).AsRegister<Register>(); 1900 Location right = locations->InAt(1); 1901 if (right.IsRegister()) { 1902 __ cmp(left, ShifterOperand(right.AsRegister<Register>())); 1903 } else { 1904 DCHECK(right.IsConstant()); 1905 __ CmpConstant(left, CodeGenerator::GetInt32ValueOf(right.GetConstant())); 1906 } 1907 if (true_target == nullptr) { 1908 __ b(false_target, ARMCondition(condition->GetOppositeCondition())); 1909 } else { 1910 __ b(true_target, ARMCondition(condition->GetCondition())); 1911 } 1912 } 1913 1914 // If neither branch falls through (case 3), the conditional branch to `true_target` 1915 // was already emitted (case 2) and we need to emit a jump to `false_target`. 1916 if (true_target != nullptr && false_target != nullptr) { 1917 __ b(false_target); 1918 } 1919} 1920 1921void LocationsBuilderARM::VisitIf(HIf* if_instr) { 1922 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(if_instr); 1923 if (IsBooleanValueOrMaterializedCondition(if_instr->InputAt(0))) { 1924 locations->SetInAt(0, Location::RequiresRegister()); 1925 } 1926} 1927 1928void InstructionCodeGeneratorARM::VisitIf(HIf* if_instr) { 1929 HBasicBlock* true_successor = if_instr->IfTrueSuccessor(); 1930 HBasicBlock* false_successor = if_instr->IfFalseSuccessor(); 1931 Label* true_target = codegen_->GoesToNextBlock(if_instr->GetBlock(), true_successor) ? 1932 nullptr : codegen_->GetLabelOf(true_successor); 1933 Label* false_target = codegen_->GoesToNextBlock(if_instr->GetBlock(), false_successor) ? 1934 nullptr : codegen_->GetLabelOf(false_successor); 1935 GenerateTestAndBranch(if_instr, /* condition_input_index */ 0, true_target, false_target); 1936} 1937 1938void LocationsBuilderARM::VisitDeoptimize(HDeoptimize* deoptimize) { 1939 LocationSummary* locations = new (GetGraph()->GetArena()) 1940 LocationSummary(deoptimize, LocationSummary::kCallOnSlowPath); 1941 locations->SetCustomSlowPathCallerSaves(RegisterSet::Empty()); // No caller-save registers. 1942 if (IsBooleanValueOrMaterializedCondition(deoptimize->InputAt(0))) { 1943 locations->SetInAt(0, Location::RequiresRegister()); 1944 } 1945} 1946 1947void InstructionCodeGeneratorARM::VisitDeoptimize(HDeoptimize* deoptimize) { 1948 SlowPathCodeARM* slow_path = deopt_slow_paths_.NewSlowPath<DeoptimizationSlowPathARM>(deoptimize); 1949 GenerateTestAndBranch(deoptimize, 1950 /* condition_input_index */ 0, 1951 slow_path->GetEntryLabel(), 1952 /* false_target */ nullptr); 1953} 1954 1955void LocationsBuilderARM::VisitSelect(HSelect* select) { 1956 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(select); 1957 if (Primitive::IsFloatingPointType(select->GetType())) { 1958 locations->SetInAt(0, Location::RequiresFpuRegister()); 1959 locations->SetInAt(1, Location::RequiresFpuRegister()); 1960 } else { 1961 locations->SetInAt(0, Location::RequiresRegister()); 1962 locations->SetInAt(1, Location::RequiresRegister()); 1963 } 1964 if (IsBooleanValueOrMaterializedCondition(select->GetCondition())) { 1965 locations->SetInAt(2, Location::RequiresRegister()); 1966 } 1967 locations->SetOut(Location::SameAsFirstInput()); 1968} 1969 1970void InstructionCodeGeneratorARM::VisitSelect(HSelect* select) { 1971 LocationSummary* locations = select->GetLocations(); 1972 Label false_target; 1973 GenerateTestAndBranch(select, 1974 /* condition_input_index */ 2, 1975 /* true_target */ nullptr, 1976 &false_target); 1977 codegen_->MoveLocation(locations->Out(), locations->InAt(1), select->GetType()); 1978 __ Bind(&false_target); 1979} 1980 1981void LocationsBuilderARM::VisitNativeDebugInfo(HNativeDebugInfo* info) { 1982 new (GetGraph()->GetArena()) LocationSummary(info); 1983} 1984 1985void InstructionCodeGeneratorARM::VisitNativeDebugInfo(HNativeDebugInfo*) { 1986 // MaybeRecordNativeDebugInfo is already called implicitly in CodeGenerator::Compile. 1987} 1988 1989void CodeGeneratorARM::GenerateNop() { 1990 __ nop(); 1991} 1992 1993void LocationsBuilderARM::HandleCondition(HCondition* cond) { 1994 LocationSummary* locations = 1995 new (GetGraph()->GetArena()) LocationSummary(cond, LocationSummary::kNoCall); 1996 // Handle the long/FP comparisons made in instruction simplification. 1997 switch (cond->InputAt(0)->GetType()) { 1998 case Primitive::kPrimLong: 1999 locations->SetInAt(0, Location::RequiresRegister()); 2000 locations->SetInAt(1, Location::RegisterOrConstant(cond->InputAt(1))); 2001 if (!cond->IsEmittedAtUseSite()) { 2002 locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap); 2003 } 2004 break; 2005 2006 case Primitive::kPrimFloat: 2007 case Primitive::kPrimDouble: 2008 locations->SetInAt(0, Location::RequiresFpuRegister()); 2009 locations->SetInAt(1, ArithmeticZeroOrFpuRegister(cond->InputAt(1))); 2010 if (!cond->IsEmittedAtUseSite()) { 2011 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2012 } 2013 break; 2014 2015 default: 2016 locations->SetInAt(0, Location::RequiresRegister()); 2017 locations->SetInAt(1, Location::RegisterOrConstant(cond->InputAt(1))); 2018 if (!cond->IsEmittedAtUseSite()) { 2019 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2020 } 2021 } 2022} 2023 2024void InstructionCodeGeneratorARM::HandleCondition(HCondition* cond) { 2025 if (cond->IsEmittedAtUseSite()) { 2026 return; 2027 } 2028 2029 LocationSummary* locations = cond->GetLocations(); 2030 Location left = locations->InAt(0); 2031 Location right = locations->InAt(1); 2032 Register out = locations->Out().AsRegister<Register>(); 2033 Label true_label, false_label; 2034 2035 switch (cond->InputAt(0)->GetType()) { 2036 default: { 2037 // Integer case. 2038 if (right.IsRegister()) { 2039 __ cmp(left.AsRegister<Register>(), ShifterOperand(right.AsRegister<Register>())); 2040 } else { 2041 DCHECK(right.IsConstant()); 2042 __ CmpConstant(left.AsRegister<Register>(), 2043 CodeGenerator::GetInt32ValueOf(right.GetConstant())); 2044 } 2045 __ it(ARMCondition(cond->GetCondition()), kItElse); 2046 __ mov(locations->Out().AsRegister<Register>(), ShifterOperand(1), 2047 ARMCondition(cond->GetCondition())); 2048 __ mov(locations->Out().AsRegister<Register>(), ShifterOperand(0), 2049 ARMCondition(cond->GetOppositeCondition())); 2050 return; 2051 } 2052 case Primitive::kPrimLong: 2053 GenerateLongComparesAndJumps(cond, &true_label, &false_label); 2054 break; 2055 case Primitive::kPrimFloat: 2056 case Primitive::kPrimDouble: 2057 GenerateVcmp(cond); 2058 GenerateFPJumps(cond, &true_label, &false_label); 2059 break; 2060 } 2061 2062 // Convert the jumps into the result. 2063 Label done_label; 2064 2065 // False case: result = 0. 2066 __ Bind(&false_label); 2067 __ LoadImmediate(out, 0); 2068 __ b(&done_label); 2069 2070 // True case: result = 1. 2071 __ Bind(&true_label); 2072 __ LoadImmediate(out, 1); 2073 __ Bind(&done_label); 2074} 2075 2076void LocationsBuilderARM::VisitEqual(HEqual* comp) { 2077 HandleCondition(comp); 2078} 2079 2080void InstructionCodeGeneratorARM::VisitEqual(HEqual* comp) { 2081 HandleCondition(comp); 2082} 2083 2084void LocationsBuilderARM::VisitNotEqual(HNotEqual* comp) { 2085 HandleCondition(comp); 2086} 2087 2088void InstructionCodeGeneratorARM::VisitNotEqual(HNotEqual* comp) { 2089 HandleCondition(comp); 2090} 2091 2092void LocationsBuilderARM::VisitLessThan(HLessThan* comp) { 2093 HandleCondition(comp); 2094} 2095 2096void InstructionCodeGeneratorARM::VisitLessThan(HLessThan* comp) { 2097 HandleCondition(comp); 2098} 2099 2100void LocationsBuilderARM::VisitLessThanOrEqual(HLessThanOrEqual* comp) { 2101 HandleCondition(comp); 2102} 2103 2104void InstructionCodeGeneratorARM::VisitLessThanOrEqual(HLessThanOrEqual* comp) { 2105 HandleCondition(comp); 2106} 2107 2108void LocationsBuilderARM::VisitGreaterThan(HGreaterThan* comp) { 2109 HandleCondition(comp); 2110} 2111 2112void InstructionCodeGeneratorARM::VisitGreaterThan(HGreaterThan* comp) { 2113 HandleCondition(comp); 2114} 2115 2116void LocationsBuilderARM::VisitGreaterThanOrEqual(HGreaterThanOrEqual* comp) { 2117 HandleCondition(comp); 2118} 2119 2120void InstructionCodeGeneratorARM::VisitGreaterThanOrEqual(HGreaterThanOrEqual* comp) { 2121 HandleCondition(comp); 2122} 2123 2124void LocationsBuilderARM::VisitBelow(HBelow* comp) { 2125 HandleCondition(comp); 2126} 2127 2128void InstructionCodeGeneratorARM::VisitBelow(HBelow* comp) { 2129 HandleCondition(comp); 2130} 2131 2132void LocationsBuilderARM::VisitBelowOrEqual(HBelowOrEqual* comp) { 2133 HandleCondition(comp); 2134} 2135 2136void InstructionCodeGeneratorARM::VisitBelowOrEqual(HBelowOrEqual* comp) { 2137 HandleCondition(comp); 2138} 2139 2140void LocationsBuilderARM::VisitAbove(HAbove* comp) { 2141 HandleCondition(comp); 2142} 2143 2144void InstructionCodeGeneratorARM::VisitAbove(HAbove* comp) { 2145 HandleCondition(comp); 2146} 2147 2148void LocationsBuilderARM::VisitAboveOrEqual(HAboveOrEqual* comp) { 2149 HandleCondition(comp); 2150} 2151 2152void InstructionCodeGeneratorARM::VisitAboveOrEqual(HAboveOrEqual* comp) { 2153 HandleCondition(comp); 2154} 2155 2156void LocationsBuilderARM::VisitIntConstant(HIntConstant* constant) { 2157 LocationSummary* locations = 2158 new (GetGraph()->GetArena()) LocationSummary(constant, LocationSummary::kNoCall); 2159 locations->SetOut(Location::ConstantLocation(constant)); 2160} 2161 2162void InstructionCodeGeneratorARM::VisitIntConstant(HIntConstant* constant ATTRIBUTE_UNUSED) { 2163 // Will be generated at use site. 2164} 2165 2166void LocationsBuilderARM::VisitNullConstant(HNullConstant* constant) { 2167 LocationSummary* locations = 2168 new (GetGraph()->GetArena()) LocationSummary(constant, LocationSummary::kNoCall); 2169 locations->SetOut(Location::ConstantLocation(constant)); 2170} 2171 2172void InstructionCodeGeneratorARM::VisitNullConstant(HNullConstant* constant ATTRIBUTE_UNUSED) { 2173 // Will be generated at use site. 2174} 2175 2176void LocationsBuilderARM::VisitLongConstant(HLongConstant* constant) { 2177 LocationSummary* locations = 2178 new (GetGraph()->GetArena()) LocationSummary(constant, LocationSummary::kNoCall); 2179 locations->SetOut(Location::ConstantLocation(constant)); 2180} 2181 2182void InstructionCodeGeneratorARM::VisitLongConstant(HLongConstant* constant ATTRIBUTE_UNUSED) { 2183 // Will be generated at use site. 2184} 2185 2186void LocationsBuilderARM::VisitFloatConstant(HFloatConstant* constant) { 2187 LocationSummary* locations = 2188 new (GetGraph()->GetArena()) LocationSummary(constant, LocationSummary::kNoCall); 2189 locations->SetOut(Location::ConstantLocation(constant)); 2190} 2191 2192void InstructionCodeGeneratorARM::VisitFloatConstant(HFloatConstant* constant ATTRIBUTE_UNUSED) { 2193 // Will be generated at use site. 2194} 2195 2196void LocationsBuilderARM::VisitDoubleConstant(HDoubleConstant* constant) { 2197 LocationSummary* locations = 2198 new (GetGraph()->GetArena()) LocationSummary(constant, LocationSummary::kNoCall); 2199 locations->SetOut(Location::ConstantLocation(constant)); 2200} 2201 2202void InstructionCodeGeneratorARM::VisitDoubleConstant(HDoubleConstant* constant ATTRIBUTE_UNUSED) { 2203 // Will be generated at use site. 2204} 2205 2206void LocationsBuilderARM::VisitMemoryBarrier(HMemoryBarrier* memory_barrier) { 2207 memory_barrier->SetLocations(nullptr); 2208} 2209 2210void InstructionCodeGeneratorARM::VisitMemoryBarrier(HMemoryBarrier* memory_barrier) { 2211 codegen_->GenerateMemoryBarrier(memory_barrier->GetBarrierKind()); 2212} 2213 2214void LocationsBuilderARM::VisitReturnVoid(HReturnVoid* ret) { 2215 ret->SetLocations(nullptr); 2216} 2217 2218void InstructionCodeGeneratorARM::VisitReturnVoid(HReturnVoid* ret ATTRIBUTE_UNUSED) { 2219 codegen_->GenerateFrameExit(); 2220} 2221 2222void LocationsBuilderARM::VisitReturn(HReturn* ret) { 2223 LocationSummary* locations = 2224 new (GetGraph()->GetArena()) LocationSummary(ret, LocationSummary::kNoCall); 2225 locations->SetInAt(0, parameter_visitor_.GetReturnLocation(ret->InputAt(0)->GetType())); 2226} 2227 2228void InstructionCodeGeneratorARM::VisitReturn(HReturn* ret ATTRIBUTE_UNUSED) { 2229 codegen_->GenerateFrameExit(); 2230} 2231 2232void LocationsBuilderARM::VisitInvokeUnresolved(HInvokeUnresolved* invoke) { 2233 // The trampoline uses the same calling convention as dex calling conventions, 2234 // except instead of loading arg0/r0 with the target Method*, arg0/r0 will contain 2235 // the method_idx. 2236 HandleInvoke(invoke); 2237} 2238 2239void InstructionCodeGeneratorARM::VisitInvokeUnresolved(HInvokeUnresolved* invoke) { 2240 codegen_->GenerateInvokeUnresolvedRuntimeCall(invoke); 2241} 2242 2243void LocationsBuilderARM::VisitInvokeStaticOrDirect(HInvokeStaticOrDirect* invoke) { 2244 // Explicit clinit checks triggered by static invokes must have been pruned by 2245 // art::PrepareForRegisterAllocation. 2246 DCHECK(!invoke->IsStaticWithExplicitClinitCheck()); 2247 2248 IntrinsicLocationsBuilderARM intrinsic(codegen_); 2249 if (intrinsic.TryDispatch(invoke)) { 2250 if (invoke->GetLocations()->CanCall() && invoke->HasPcRelativeDexCache()) { 2251 invoke->GetLocations()->SetInAt(invoke->GetSpecialInputIndex(), Location::Any()); 2252 } 2253 return; 2254 } 2255 2256 HandleInvoke(invoke); 2257 2258 // For PC-relative dex cache the invoke has an extra input, the PC-relative address base. 2259 if (invoke->HasPcRelativeDexCache()) { 2260 invoke->GetLocations()->SetInAt(invoke->GetSpecialInputIndex(), Location::RequiresRegister()); 2261 } 2262} 2263 2264static bool TryGenerateIntrinsicCode(HInvoke* invoke, CodeGeneratorARM* codegen) { 2265 if (invoke->GetLocations()->Intrinsified()) { 2266 IntrinsicCodeGeneratorARM intrinsic(codegen); 2267 intrinsic.Dispatch(invoke); 2268 return true; 2269 } 2270 return false; 2271} 2272 2273void InstructionCodeGeneratorARM::VisitInvokeStaticOrDirect(HInvokeStaticOrDirect* invoke) { 2274 // Explicit clinit checks triggered by static invokes must have been pruned by 2275 // art::PrepareForRegisterAllocation. 2276 DCHECK(!invoke->IsStaticWithExplicitClinitCheck()); 2277 2278 if (TryGenerateIntrinsicCode(invoke, codegen_)) { 2279 return; 2280 } 2281 2282 LocationSummary* locations = invoke->GetLocations(); 2283 codegen_->GenerateStaticOrDirectCall( 2284 invoke, locations->HasTemps() ? locations->GetTemp(0) : Location::NoLocation()); 2285 codegen_->RecordPcInfo(invoke, invoke->GetDexPc()); 2286} 2287 2288void LocationsBuilderARM::HandleInvoke(HInvoke* invoke) { 2289 InvokeDexCallingConventionVisitorARM calling_convention_visitor; 2290 CodeGenerator::CreateCommonInvokeLocationSummary(invoke, &calling_convention_visitor); 2291} 2292 2293void LocationsBuilderARM::VisitInvokeVirtual(HInvokeVirtual* invoke) { 2294 IntrinsicLocationsBuilderARM intrinsic(codegen_); 2295 if (intrinsic.TryDispatch(invoke)) { 2296 return; 2297 } 2298 2299 HandleInvoke(invoke); 2300} 2301 2302void InstructionCodeGeneratorARM::VisitInvokeVirtual(HInvokeVirtual* invoke) { 2303 if (TryGenerateIntrinsicCode(invoke, codegen_)) { 2304 return; 2305 } 2306 2307 codegen_->GenerateVirtualCall(invoke, invoke->GetLocations()->GetTemp(0)); 2308 DCHECK(!codegen_->IsLeafMethod()); 2309 codegen_->RecordPcInfo(invoke, invoke->GetDexPc()); 2310} 2311 2312void LocationsBuilderARM::VisitInvokeInterface(HInvokeInterface* invoke) { 2313 HandleInvoke(invoke); 2314 // Add the hidden argument. 2315 invoke->GetLocations()->AddTemp(Location::RegisterLocation(R12)); 2316} 2317 2318void InstructionCodeGeneratorARM::VisitInvokeInterface(HInvokeInterface* invoke) { 2319 // TODO: b/18116999, our IMTs can miss an IncompatibleClassChangeError. 2320 LocationSummary* locations = invoke->GetLocations(); 2321 Register temp = locations->GetTemp(0).AsRegister<Register>(); 2322 Register hidden_reg = locations->GetTemp(1).AsRegister<Register>(); 2323 Location receiver = locations->InAt(0); 2324 uint32_t class_offset = mirror::Object::ClassOffset().Int32Value(); 2325 2326 // Set the hidden argument. This is safe to do this here, as R12 2327 // won't be modified thereafter, before the `blx` (call) instruction. 2328 DCHECK_EQ(R12, hidden_reg); 2329 __ LoadImmediate(hidden_reg, invoke->GetDexMethodIndex()); 2330 2331 if (receiver.IsStackSlot()) { 2332 __ LoadFromOffset(kLoadWord, temp, SP, receiver.GetStackIndex()); 2333 // /* HeapReference<Class> */ temp = temp->klass_ 2334 __ LoadFromOffset(kLoadWord, temp, temp, class_offset); 2335 } else { 2336 // /* HeapReference<Class> */ temp = receiver->klass_ 2337 __ LoadFromOffset(kLoadWord, temp, receiver.AsRegister<Register>(), class_offset); 2338 } 2339 codegen_->MaybeRecordImplicitNullCheck(invoke); 2340 // Instead of simply (possibly) unpoisoning `temp` here, we should 2341 // emit a read barrier for the previous class reference load. 2342 // However this is not required in practice, as this is an 2343 // intermediate/temporary reference and because the current 2344 // concurrent copying collector keeps the from-space memory 2345 // intact/accessible until the end of the marking phase (the 2346 // concurrent copying collector may not in the future). 2347 __ MaybeUnpoisonHeapReference(temp); 2348 __ LoadFromOffset(kLoadWord, temp, temp, 2349 mirror::Class::ImtPtrOffset(kArmPointerSize).Uint32Value()); 2350 uint32_t method_offset = static_cast<uint32_t>(ImTable::OffsetOfElement( 2351 invoke->GetImtIndex(), kArmPointerSize)); 2352 // temp = temp->GetImtEntryAt(method_offset); 2353 __ LoadFromOffset(kLoadWord, temp, temp, method_offset); 2354 uint32_t entry_point = 2355 ArtMethod::EntryPointFromQuickCompiledCodeOffset(kArmPointerSize).Int32Value(); 2356 // LR = temp->GetEntryPoint(); 2357 __ LoadFromOffset(kLoadWord, LR, temp, entry_point); 2358 // LR(); 2359 __ blx(LR); 2360 DCHECK(!codegen_->IsLeafMethod()); 2361 codegen_->RecordPcInfo(invoke, invoke->GetDexPc()); 2362} 2363 2364void LocationsBuilderARM::VisitNeg(HNeg* neg) { 2365 LocationSummary* locations = 2366 new (GetGraph()->GetArena()) LocationSummary(neg, LocationSummary::kNoCall); 2367 switch (neg->GetResultType()) { 2368 case Primitive::kPrimInt: { 2369 locations->SetInAt(0, Location::RequiresRegister()); 2370 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2371 break; 2372 } 2373 case Primitive::kPrimLong: { 2374 locations->SetInAt(0, Location::RequiresRegister()); 2375 locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap); 2376 break; 2377 } 2378 2379 case Primitive::kPrimFloat: 2380 case Primitive::kPrimDouble: 2381 locations->SetInAt(0, Location::RequiresFpuRegister()); 2382 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); 2383 break; 2384 2385 default: 2386 LOG(FATAL) << "Unexpected neg type " << neg->GetResultType(); 2387 } 2388} 2389 2390void InstructionCodeGeneratorARM::VisitNeg(HNeg* neg) { 2391 LocationSummary* locations = neg->GetLocations(); 2392 Location out = locations->Out(); 2393 Location in = locations->InAt(0); 2394 switch (neg->GetResultType()) { 2395 case Primitive::kPrimInt: 2396 DCHECK(in.IsRegister()); 2397 __ rsb(out.AsRegister<Register>(), in.AsRegister<Register>(), ShifterOperand(0)); 2398 break; 2399 2400 case Primitive::kPrimLong: 2401 DCHECK(in.IsRegisterPair()); 2402 // out.lo = 0 - in.lo (and update the carry/borrow (C) flag) 2403 __ rsbs(out.AsRegisterPairLow<Register>(), 2404 in.AsRegisterPairLow<Register>(), 2405 ShifterOperand(0)); 2406 // We cannot emit an RSC (Reverse Subtract with Carry) 2407 // instruction here, as it does not exist in the Thumb-2 2408 // instruction set. We use the following approach 2409 // using SBC and SUB instead. 2410 // 2411 // out.hi = -C 2412 __ sbc(out.AsRegisterPairHigh<Register>(), 2413 out.AsRegisterPairHigh<Register>(), 2414 ShifterOperand(out.AsRegisterPairHigh<Register>())); 2415 // out.hi = out.hi - in.hi 2416 __ sub(out.AsRegisterPairHigh<Register>(), 2417 out.AsRegisterPairHigh<Register>(), 2418 ShifterOperand(in.AsRegisterPairHigh<Register>())); 2419 break; 2420 2421 case Primitive::kPrimFloat: 2422 DCHECK(in.IsFpuRegister()); 2423 __ vnegs(out.AsFpuRegister<SRegister>(), in.AsFpuRegister<SRegister>()); 2424 break; 2425 2426 case Primitive::kPrimDouble: 2427 DCHECK(in.IsFpuRegisterPair()); 2428 __ vnegd(FromLowSToD(out.AsFpuRegisterPairLow<SRegister>()), 2429 FromLowSToD(in.AsFpuRegisterPairLow<SRegister>())); 2430 break; 2431 2432 default: 2433 LOG(FATAL) << "Unexpected neg type " << neg->GetResultType(); 2434 } 2435} 2436 2437void LocationsBuilderARM::VisitTypeConversion(HTypeConversion* conversion) { 2438 Primitive::Type result_type = conversion->GetResultType(); 2439 Primitive::Type input_type = conversion->GetInputType(); 2440 DCHECK_NE(result_type, input_type); 2441 2442 // The float-to-long, double-to-long and long-to-float type conversions 2443 // rely on a call to the runtime. 2444 LocationSummary::CallKind call_kind = 2445 (((input_type == Primitive::kPrimFloat || input_type == Primitive::kPrimDouble) 2446 && result_type == Primitive::kPrimLong) 2447 || (input_type == Primitive::kPrimLong && result_type == Primitive::kPrimFloat)) 2448 ? LocationSummary::kCallOnMainOnly 2449 : LocationSummary::kNoCall; 2450 LocationSummary* locations = 2451 new (GetGraph()->GetArena()) LocationSummary(conversion, call_kind); 2452 2453 // The Java language does not allow treating boolean as an integral type but 2454 // our bit representation makes it safe. 2455 2456 switch (result_type) { 2457 case Primitive::kPrimByte: 2458 switch (input_type) { 2459 case Primitive::kPrimLong: 2460 // Type conversion from long to byte is a result of code transformations. 2461 case Primitive::kPrimBoolean: 2462 // Boolean input is a result of code transformations. 2463 case Primitive::kPrimShort: 2464 case Primitive::kPrimInt: 2465 case Primitive::kPrimChar: 2466 // Processing a Dex `int-to-byte' instruction. 2467 locations->SetInAt(0, Location::RequiresRegister()); 2468 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2469 break; 2470 2471 default: 2472 LOG(FATAL) << "Unexpected type conversion from " << input_type 2473 << " to " << result_type; 2474 } 2475 break; 2476 2477 case Primitive::kPrimShort: 2478 switch (input_type) { 2479 case Primitive::kPrimLong: 2480 // Type conversion from long to short is a result of code transformations. 2481 case Primitive::kPrimBoolean: 2482 // Boolean input is a result of code transformations. 2483 case Primitive::kPrimByte: 2484 case Primitive::kPrimInt: 2485 case Primitive::kPrimChar: 2486 // Processing a Dex `int-to-short' instruction. 2487 locations->SetInAt(0, Location::RequiresRegister()); 2488 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2489 break; 2490 2491 default: 2492 LOG(FATAL) << "Unexpected type conversion from " << input_type 2493 << " to " << result_type; 2494 } 2495 break; 2496 2497 case Primitive::kPrimInt: 2498 switch (input_type) { 2499 case Primitive::kPrimLong: 2500 // Processing a Dex `long-to-int' instruction. 2501 locations->SetInAt(0, Location::Any()); 2502 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2503 break; 2504 2505 case Primitive::kPrimFloat: 2506 // Processing a Dex `float-to-int' instruction. 2507 locations->SetInAt(0, Location::RequiresFpuRegister()); 2508 locations->SetOut(Location::RequiresRegister()); 2509 locations->AddTemp(Location::RequiresFpuRegister()); 2510 break; 2511 2512 case Primitive::kPrimDouble: 2513 // Processing a Dex `double-to-int' instruction. 2514 locations->SetInAt(0, Location::RequiresFpuRegister()); 2515 locations->SetOut(Location::RequiresRegister()); 2516 locations->AddTemp(Location::RequiresFpuRegister()); 2517 break; 2518 2519 default: 2520 LOG(FATAL) << "Unexpected type conversion from " << input_type 2521 << " to " << result_type; 2522 } 2523 break; 2524 2525 case Primitive::kPrimLong: 2526 switch (input_type) { 2527 case Primitive::kPrimBoolean: 2528 // Boolean input is a result of code transformations. 2529 case Primitive::kPrimByte: 2530 case Primitive::kPrimShort: 2531 case Primitive::kPrimInt: 2532 case Primitive::kPrimChar: 2533 // Processing a Dex `int-to-long' instruction. 2534 locations->SetInAt(0, Location::RequiresRegister()); 2535 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2536 break; 2537 2538 case Primitive::kPrimFloat: { 2539 // Processing a Dex `float-to-long' instruction. 2540 InvokeRuntimeCallingConvention calling_convention; 2541 locations->SetInAt(0, Location::FpuRegisterLocation( 2542 calling_convention.GetFpuRegisterAt(0))); 2543 locations->SetOut(Location::RegisterPairLocation(R0, R1)); 2544 break; 2545 } 2546 2547 case Primitive::kPrimDouble: { 2548 // Processing a Dex `double-to-long' instruction. 2549 InvokeRuntimeCallingConvention calling_convention; 2550 locations->SetInAt(0, Location::FpuRegisterPairLocation( 2551 calling_convention.GetFpuRegisterAt(0), 2552 calling_convention.GetFpuRegisterAt(1))); 2553 locations->SetOut(Location::RegisterPairLocation(R0, R1)); 2554 break; 2555 } 2556 2557 default: 2558 LOG(FATAL) << "Unexpected type conversion from " << input_type 2559 << " to " << result_type; 2560 } 2561 break; 2562 2563 case Primitive::kPrimChar: 2564 switch (input_type) { 2565 case Primitive::kPrimLong: 2566 // Type conversion from long to char is a result of code transformations. 2567 case Primitive::kPrimBoolean: 2568 // Boolean input is a result of code transformations. 2569 case Primitive::kPrimByte: 2570 case Primitive::kPrimShort: 2571 case Primitive::kPrimInt: 2572 // Processing a Dex `int-to-char' instruction. 2573 locations->SetInAt(0, Location::RequiresRegister()); 2574 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2575 break; 2576 2577 default: 2578 LOG(FATAL) << "Unexpected type conversion from " << input_type 2579 << " to " << result_type; 2580 } 2581 break; 2582 2583 case Primitive::kPrimFloat: 2584 switch (input_type) { 2585 case Primitive::kPrimBoolean: 2586 // Boolean input is a result of code transformations. 2587 case Primitive::kPrimByte: 2588 case Primitive::kPrimShort: 2589 case Primitive::kPrimInt: 2590 case Primitive::kPrimChar: 2591 // Processing a Dex `int-to-float' instruction. 2592 locations->SetInAt(0, Location::RequiresRegister()); 2593 locations->SetOut(Location::RequiresFpuRegister()); 2594 break; 2595 2596 case Primitive::kPrimLong: { 2597 // Processing a Dex `long-to-float' instruction. 2598 InvokeRuntimeCallingConvention calling_convention; 2599 locations->SetInAt(0, Location::RegisterPairLocation( 2600 calling_convention.GetRegisterAt(0), calling_convention.GetRegisterAt(1))); 2601 locations->SetOut(Location::FpuRegisterLocation(calling_convention.GetFpuRegisterAt(0))); 2602 break; 2603 } 2604 2605 case Primitive::kPrimDouble: 2606 // Processing a Dex `double-to-float' instruction. 2607 locations->SetInAt(0, Location::RequiresFpuRegister()); 2608 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); 2609 break; 2610 2611 default: 2612 LOG(FATAL) << "Unexpected type conversion from " << input_type 2613 << " to " << result_type; 2614 }; 2615 break; 2616 2617 case Primitive::kPrimDouble: 2618 switch (input_type) { 2619 case Primitive::kPrimBoolean: 2620 // Boolean input is a result of code transformations. 2621 case Primitive::kPrimByte: 2622 case Primitive::kPrimShort: 2623 case Primitive::kPrimInt: 2624 case Primitive::kPrimChar: 2625 // Processing a Dex `int-to-double' instruction. 2626 locations->SetInAt(0, Location::RequiresRegister()); 2627 locations->SetOut(Location::RequiresFpuRegister()); 2628 break; 2629 2630 case Primitive::kPrimLong: 2631 // Processing a Dex `long-to-double' instruction. 2632 locations->SetInAt(0, Location::RequiresRegister()); 2633 locations->SetOut(Location::RequiresFpuRegister()); 2634 locations->AddTemp(Location::RequiresFpuRegister()); 2635 locations->AddTemp(Location::RequiresFpuRegister()); 2636 break; 2637 2638 case Primitive::kPrimFloat: 2639 // Processing a Dex `float-to-double' instruction. 2640 locations->SetInAt(0, Location::RequiresFpuRegister()); 2641 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); 2642 break; 2643 2644 default: 2645 LOG(FATAL) << "Unexpected type conversion from " << input_type 2646 << " to " << result_type; 2647 }; 2648 break; 2649 2650 default: 2651 LOG(FATAL) << "Unexpected type conversion from " << input_type 2652 << " to " << result_type; 2653 } 2654} 2655 2656void InstructionCodeGeneratorARM::VisitTypeConversion(HTypeConversion* conversion) { 2657 LocationSummary* locations = conversion->GetLocations(); 2658 Location out = locations->Out(); 2659 Location in = locations->InAt(0); 2660 Primitive::Type result_type = conversion->GetResultType(); 2661 Primitive::Type input_type = conversion->GetInputType(); 2662 DCHECK_NE(result_type, input_type); 2663 switch (result_type) { 2664 case Primitive::kPrimByte: 2665 switch (input_type) { 2666 case Primitive::kPrimLong: 2667 // Type conversion from long to byte is a result of code transformations. 2668 __ sbfx(out.AsRegister<Register>(), in.AsRegisterPairLow<Register>(), 0, 8); 2669 break; 2670 case Primitive::kPrimBoolean: 2671 // Boolean input is a result of code transformations. 2672 case Primitive::kPrimShort: 2673 case Primitive::kPrimInt: 2674 case Primitive::kPrimChar: 2675 // Processing a Dex `int-to-byte' instruction. 2676 __ sbfx(out.AsRegister<Register>(), in.AsRegister<Register>(), 0, 8); 2677 break; 2678 2679 default: 2680 LOG(FATAL) << "Unexpected type conversion from " << input_type 2681 << " to " << result_type; 2682 } 2683 break; 2684 2685 case Primitive::kPrimShort: 2686 switch (input_type) { 2687 case Primitive::kPrimLong: 2688 // Type conversion from long to short is a result of code transformations. 2689 __ sbfx(out.AsRegister<Register>(), in.AsRegisterPairLow<Register>(), 0, 16); 2690 break; 2691 case Primitive::kPrimBoolean: 2692 // Boolean input is a result of code transformations. 2693 case Primitive::kPrimByte: 2694 case Primitive::kPrimInt: 2695 case Primitive::kPrimChar: 2696 // Processing a Dex `int-to-short' instruction. 2697 __ sbfx(out.AsRegister<Register>(), in.AsRegister<Register>(), 0, 16); 2698 break; 2699 2700 default: 2701 LOG(FATAL) << "Unexpected type conversion from " << input_type 2702 << " to " << result_type; 2703 } 2704 break; 2705 2706 case Primitive::kPrimInt: 2707 switch (input_type) { 2708 case Primitive::kPrimLong: 2709 // Processing a Dex `long-to-int' instruction. 2710 DCHECK(out.IsRegister()); 2711 if (in.IsRegisterPair()) { 2712 __ Mov(out.AsRegister<Register>(), in.AsRegisterPairLow<Register>()); 2713 } else if (in.IsDoubleStackSlot()) { 2714 __ LoadFromOffset(kLoadWord, out.AsRegister<Register>(), SP, in.GetStackIndex()); 2715 } else { 2716 DCHECK(in.IsConstant()); 2717 DCHECK(in.GetConstant()->IsLongConstant()); 2718 int64_t value = in.GetConstant()->AsLongConstant()->GetValue(); 2719 __ LoadImmediate(out.AsRegister<Register>(), static_cast<int32_t>(value)); 2720 } 2721 break; 2722 2723 case Primitive::kPrimFloat: { 2724 // Processing a Dex `float-to-int' instruction. 2725 SRegister temp = locations->GetTemp(0).AsFpuRegisterPairLow<SRegister>(); 2726 __ vcvtis(temp, in.AsFpuRegister<SRegister>()); 2727 __ vmovrs(out.AsRegister<Register>(), temp); 2728 break; 2729 } 2730 2731 case Primitive::kPrimDouble: { 2732 // Processing a Dex `double-to-int' instruction. 2733 SRegister temp_s = locations->GetTemp(0).AsFpuRegisterPairLow<SRegister>(); 2734 __ vcvtid(temp_s, FromLowSToD(in.AsFpuRegisterPairLow<SRegister>())); 2735 __ vmovrs(out.AsRegister<Register>(), temp_s); 2736 break; 2737 } 2738 2739 default: 2740 LOG(FATAL) << "Unexpected type conversion from " << input_type 2741 << " to " << result_type; 2742 } 2743 break; 2744 2745 case Primitive::kPrimLong: 2746 switch (input_type) { 2747 case Primitive::kPrimBoolean: 2748 // Boolean input is a result of code transformations. 2749 case Primitive::kPrimByte: 2750 case Primitive::kPrimShort: 2751 case Primitive::kPrimInt: 2752 case Primitive::kPrimChar: 2753 // Processing a Dex `int-to-long' instruction. 2754 DCHECK(out.IsRegisterPair()); 2755 DCHECK(in.IsRegister()); 2756 __ Mov(out.AsRegisterPairLow<Register>(), in.AsRegister<Register>()); 2757 // Sign extension. 2758 __ Asr(out.AsRegisterPairHigh<Register>(), 2759 out.AsRegisterPairLow<Register>(), 2760 31); 2761 break; 2762 2763 case Primitive::kPrimFloat: 2764 // Processing a Dex `float-to-long' instruction. 2765 codegen_->InvokeRuntime(kQuickF2l, conversion, conversion->GetDexPc()); 2766 CheckEntrypointTypes<kQuickF2l, int64_t, float>(); 2767 break; 2768 2769 case Primitive::kPrimDouble: 2770 // Processing a Dex `double-to-long' instruction. 2771 codegen_->InvokeRuntime(kQuickD2l, conversion, conversion->GetDexPc()); 2772 CheckEntrypointTypes<kQuickD2l, int64_t, double>(); 2773 break; 2774 2775 default: 2776 LOG(FATAL) << "Unexpected type conversion from " << input_type 2777 << " to " << result_type; 2778 } 2779 break; 2780 2781 case Primitive::kPrimChar: 2782 switch (input_type) { 2783 case Primitive::kPrimLong: 2784 // Type conversion from long to char is a result of code transformations. 2785 __ ubfx(out.AsRegister<Register>(), in.AsRegisterPairLow<Register>(), 0, 16); 2786 break; 2787 case Primitive::kPrimBoolean: 2788 // Boolean input is a result of code transformations. 2789 case Primitive::kPrimByte: 2790 case Primitive::kPrimShort: 2791 case Primitive::kPrimInt: 2792 // Processing a Dex `int-to-char' instruction. 2793 __ ubfx(out.AsRegister<Register>(), in.AsRegister<Register>(), 0, 16); 2794 break; 2795 2796 default: 2797 LOG(FATAL) << "Unexpected type conversion from " << input_type 2798 << " to " << result_type; 2799 } 2800 break; 2801 2802 case Primitive::kPrimFloat: 2803 switch (input_type) { 2804 case Primitive::kPrimBoolean: 2805 // Boolean input is a result of code transformations. 2806 case Primitive::kPrimByte: 2807 case Primitive::kPrimShort: 2808 case Primitive::kPrimInt: 2809 case Primitive::kPrimChar: { 2810 // Processing a Dex `int-to-float' instruction. 2811 __ vmovsr(out.AsFpuRegister<SRegister>(), in.AsRegister<Register>()); 2812 __ vcvtsi(out.AsFpuRegister<SRegister>(), out.AsFpuRegister<SRegister>()); 2813 break; 2814 } 2815 2816 case Primitive::kPrimLong: 2817 // Processing a Dex `long-to-float' instruction. 2818 codegen_->InvokeRuntime(kQuickL2f, conversion, conversion->GetDexPc()); 2819 CheckEntrypointTypes<kQuickL2f, float, int64_t>(); 2820 break; 2821 2822 case Primitive::kPrimDouble: 2823 // Processing a Dex `double-to-float' instruction. 2824 __ vcvtsd(out.AsFpuRegister<SRegister>(), 2825 FromLowSToD(in.AsFpuRegisterPairLow<SRegister>())); 2826 break; 2827 2828 default: 2829 LOG(FATAL) << "Unexpected type conversion from " << input_type 2830 << " to " << result_type; 2831 }; 2832 break; 2833 2834 case Primitive::kPrimDouble: 2835 switch (input_type) { 2836 case Primitive::kPrimBoolean: 2837 // Boolean input is a result of code transformations. 2838 case Primitive::kPrimByte: 2839 case Primitive::kPrimShort: 2840 case Primitive::kPrimInt: 2841 case Primitive::kPrimChar: { 2842 // Processing a Dex `int-to-double' instruction. 2843 __ vmovsr(out.AsFpuRegisterPairLow<SRegister>(), in.AsRegister<Register>()); 2844 __ vcvtdi(FromLowSToD(out.AsFpuRegisterPairLow<SRegister>()), 2845 out.AsFpuRegisterPairLow<SRegister>()); 2846 break; 2847 } 2848 2849 case Primitive::kPrimLong: { 2850 // Processing a Dex `long-to-double' instruction. 2851 Register low = in.AsRegisterPairLow<Register>(); 2852 Register high = in.AsRegisterPairHigh<Register>(); 2853 SRegister out_s = out.AsFpuRegisterPairLow<SRegister>(); 2854 DRegister out_d = FromLowSToD(out_s); 2855 SRegister temp_s = locations->GetTemp(0).AsFpuRegisterPairLow<SRegister>(); 2856 DRegister temp_d = FromLowSToD(temp_s); 2857 SRegister constant_s = locations->GetTemp(1).AsFpuRegisterPairLow<SRegister>(); 2858 DRegister constant_d = FromLowSToD(constant_s); 2859 2860 // temp_d = int-to-double(high) 2861 __ vmovsr(temp_s, high); 2862 __ vcvtdi(temp_d, temp_s); 2863 // constant_d = k2Pow32EncodingForDouble 2864 __ LoadDImmediate(constant_d, bit_cast<double, int64_t>(k2Pow32EncodingForDouble)); 2865 // out_d = unsigned-to-double(low) 2866 __ vmovsr(out_s, low); 2867 __ vcvtdu(out_d, out_s); 2868 // out_d += temp_d * constant_d 2869 __ vmlad(out_d, temp_d, constant_d); 2870 break; 2871 } 2872 2873 case Primitive::kPrimFloat: 2874 // Processing a Dex `float-to-double' instruction. 2875 __ vcvtds(FromLowSToD(out.AsFpuRegisterPairLow<SRegister>()), 2876 in.AsFpuRegister<SRegister>()); 2877 break; 2878 2879 default: 2880 LOG(FATAL) << "Unexpected type conversion from " << input_type 2881 << " to " << result_type; 2882 }; 2883 break; 2884 2885 default: 2886 LOG(FATAL) << "Unexpected type conversion from " << input_type 2887 << " to " << result_type; 2888 } 2889} 2890 2891void LocationsBuilderARM::VisitAdd(HAdd* add) { 2892 LocationSummary* locations = 2893 new (GetGraph()->GetArena()) LocationSummary(add, LocationSummary::kNoCall); 2894 switch (add->GetResultType()) { 2895 case Primitive::kPrimInt: { 2896 locations->SetInAt(0, Location::RequiresRegister()); 2897 locations->SetInAt(1, Location::RegisterOrConstant(add->InputAt(1))); 2898 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2899 break; 2900 } 2901 2902 case Primitive::kPrimLong: { 2903 locations->SetInAt(0, Location::RequiresRegister()); 2904 locations->SetInAt(1, ArmEncodableConstantOrRegister(add->InputAt(1), ADD)); 2905 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2906 break; 2907 } 2908 2909 case Primitive::kPrimFloat: 2910 case Primitive::kPrimDouble: { 2911 locations->SetInAt(0, Location::RequiresFpuRegister()); 2912 locations->SetInAt(1, Location::RequiresFpuRegister()); 2913 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); 2914 break; 2915 } 2916 2917 default: 2918 LOG(FATAL) << "Unexpected add type " << add->GetResultType(); 2919 } 2920} 2921 2922void InstructionCodeGeneratorARM::VisitAdd(HAdd* add) { 2923 LocationSummary* locations = add->GetLocations(); 2924 Location out = locations->Out(); 2925 Location first = locations->InAt(0); 2926 Location second = locations->InAt(1); 2927 switch (add->GetResultType()) { 2928 case Primitive::kPrimInt: 2929 if (second.IsRegister()) { 2930 __ add(out.AsRegister<Register>(), 2931 first.AsRegister<Register>(), 2932 ShifterOperand(second.AsRegister<Register>())); 2933 } else { 2934 __ AddConstant(out.AsRegister<Register>(), 2935 first.AsRegister<Register>(), 2936 second.GetConstant()->AsIntConstant()->GetValue()); 2937 } 2938 break; 2939 2940 case Primitive::kPrimLong: { 2941 if (second.IsConstant()) { 2942 uint64_t value = static_cast<uint64_t>(Int64FromConstant(second.GetConstant())); 2943 GenerateAddLongConst(out, first, value); 2944 } else { 2945 DCHECK(second.IsRegisterPair()); 2946 __ adds(out.AsRegisterPairLow<Register>(), 2947 first.AsRegisterPairLow<Register>(), 2948 ShifterOperand(second.AsRegisterPairLow<Register>())); 2949 __ adc(out.AsRegisterPairHigh<Register>(), 2950 first.AsRegisterPairHigh<Register>(), 2951 ShifterOperand(second.AsRegisterPairHigh<Register>())); 2952 } 2953 break; 2954 } 2955 2956 case Primitive::kPrimFloat: 2957 __ vadds(out.AsFpuRegister<SRegister>(), 2958 first.AsFpuRegister<SRegister>(), 2959 second.AsFpuRegister<SRegister>()); 2960 break; 2961 2962 case Primitive::kPrimDouble: 2963 __ vaddd(FromLowSToD(out.AsFpuRegisterPairLow<SRegister>()), 2964 FromLowSToD(first.AsFpuRegisterPairLow<SRegister>()), 2965 FromLowSToD(second.AsFpuRegisterPairLow<SRegister>())); 2966 break; 2967 2968 default: 2969 LOG(FATAL) << "Unexpected add type " << add->GetResultType(); 2970 } 2971} 2972 2973void LocationsBuilderARM::VisitSub(HSub* sub) { 2974 LocationSummary* locations = 2975 new (GetGraph()->GetArena()) LocationSummary(sub, LocationSummary::kNoCall); 2976 switch (sub->GetResultType()) { 2977 case Primitive::kPrimInt: { 2978 locations->SetInAt(0, Location::RequiresRegister()); 2979 locations->SetInAt(1, Location::RegisterOrConstant(sub->InputAt(1))); 2980 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2981 break; 2982 } 2983 2984 case Primitive::kPrimLong: { 2985 locations->SetInAt(0, Location::RequiresRegister()); 2986 locations->SetInAt(1, ArmEncodableConstantOrRegister(sub->InputAt(1), SUB)); 2987 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 2988 break; 2989 } 2990 case Primitive::kPrimFloat: 2991 case Primitive::kPrimDouble: { 2992 locations->SetInAt(0, Location::RequiresFpuRegister()); 2993 locations->SetInAt(1, Location::RequiresFpuRegister()); 2994 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); 2995 break; 2996 } 2997 default: 2998 LOG(FATAL) << "Unexpected sub type " << sub->GetResultType(); 2999 } 3000} 3001 3002void InstructionCodeGeneratorARM::VisitSub(HSub* sub) { 3003 LocationSummary* locations = sub->GetLocations(); 3004 Location out = locations->Out(); 3005 Location first = locations->InAt(0); 3006 Location second = locations->InAt(1); 3007 switch (sub->GetResultType()) { 3008 case Primitive::kPrimInt: { 3009 if (second.IsRegister()) { 3010 __ sub(out.AsRegister<Register>(), 3011 first.AsRegister<Register>(), 3012 ShifterOperand(second.AsRegister<Register>())); 3013 } else { 3014 __ AddConstant(out.AsRegister<Register>(), 3015 first.AsRegister<Register>(), 3016 -second.GetConstant()->AsIntConstant()->GetValue()); 3017 } 3018 break; 3019 } 3020 3021 case Primitive::kPrimLong: { 3022 if (second.IsConstant()) { 3023 uint64_t value = static_cast<uint64_t>(Int64FromConstant(second.GetConstant())); 3024 GenerateAddLongConst(out, first, -value); 3025 } else { 3026 DCHECK(second.IsRegisterPair()); 3027 __ subs(out.AsRegisterPairLow<Register>(), 3028 first.AsRegisterPairLow<Register>(), 3029 ShifterOperand(second.AsRegisterPairLow<Register>())); 3030 __ sbc(out.AsRegisterPairHigh<Register>(), 3031 first.AsRegisterPairHigh<Register>(), 3032 ShifterOperand(second.AsRegisterPairHigh<Register>())); 3033 } 3034 break; 3035 } 3036 3037 case Primitive::kPrimFloat: { 3038 __ vsubs(out.AsFpuRegister<SRegister>(), 3039 first.AsFpuRegister<SRegister>(), 3040 second.AsFpuRegister<SRegister>()); 3041 break; 3042 } 3043 3044 case Primitive::kPrimDouble: { 3045 __ vsubd(FromLowSToD(out.AsFpuRegisterPairLow<SRegister>()), 3046 FromLowSToD(first.AsFpuRegisterPairLow<SRegister>()), 3047 FromLowSToD(second.AsFpuRegisterPairLow<SRegister>())); 3048 break; 3049 } 3050 3051 3052 default: 3053 LOG(FATAL) << "Unexpected sub type " << sub->GetResultType(); 3054 } 3055} 3056 3057void LocationsBuilderARM::VisitMul(HMul* mul) { 3058 LocationSummary* locations = 3059 new (GetGraph()->GetArena()) LocationSummary(mul, LocationSummary::kNoCall); 3060 switch (mul->GetResultType()) { 3061 case Primitive::kPrimInt: 3062 case Primitive::kPrimLong: { 3063 locations->SetInAt(0, Location::RequiresRegister()); 3064 locations->SetInAt(1, Location::RequiresRegister()); 3065 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 3066 break; 3067 } 3068 3069 case Primitive::kPrimFloat: 3070 case Primitive::kPrimDouble: { 3071 locations->SetInAt(0, Location::RequiresFpuRegister()); 3072 locations->SetInAt(1, Location::RequiresFpuRegister()); 3073 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); 3074 break; 3075 } 3076 3077 default: 3078 LOG(FATAL) << "Unexpected mul type " << mul->GetResultType(); 3079 } 3080} 3081 3082void InstructionCodeGeneratorARM::VisitMul(HMul* mul) { 3083 LocationSummary* locations = mul->GetLocations(); 3084 Location out = locations->Out(); 3085 Location first = locations->InAt(0); 3086 Location second = locations->InAt(1); 3087 switch (mul->GetResultType()) { 3088 case Primitive::kPrimInt: { 3089 __ mul(out.AsRegister<Register>(), 3090 first.AsRegister<Register>(), 3091 second.AsRegister<Register>()); 3092 break; 3093 } 3094 case Primitive::kPrimLong: { 3095 Register out_hi = out.AsRegisterPairHigh<Register>(); 3096 Register out_lo = out.AsRegisterPairLow<Register>(); 3097 Register in1_hi = first.AsRegisterPairHigh<Register>(); 3098 Register in1_lo = first.AsRegisterPairLow<Register>(); 3099 Register in2_hi = second.AsRegisterPairHigh<Register>(); 3100 Register in2_lo = second.AsRegisterPairLow<Register>(); 3101 3102 // Extra checks to protect caused by the existence of R1_R2. 3103 // The algorithm is wrong if out.hi is either in1.lo or in2.lo: 3104 // (e.g. in1=r0_r1, in2=r2_r3 and out=r1_r2); 3105 DCHECK_NE(out_hi, in1_lo); 3106 DCHECK_NE(out_hi, in2_lo); 3107 3108 // input: in1 - 64 bits, in2 - 64 bits 3109 // output: out 3110 // formula: out.hi : out.lo = (in1.lo * in2.hi + in1.hi * in2.lo)* 2^32 + in1.lo * in2.lo 3111 // parts: out.hi = in1.lo * in2.hi + in1.hi * in2.lo + (in1.lo * in2.lo)[63:32] 3112 // parts: out.lo = (in1.lo * in2.lo)[31:0] 3113 3114 // IP <- in1.lo * in2.hi 3115 __ mul(IP, in1_lo, in2_hi); 3116 // out.hi <- in1.lo * in2.hi + in1.hi * in2.lo 3117 __ mla(out_hi, in1_hi, in2_lo, IP); 3118 // out.lo <- (in1.lo * in2.lo)[31:0]; 3119 __ umull(out_lo, IP, in1_lo, in2_lo); 3120 // out.hi <- in2.hi * in1.lo + in2.lo * in1.hi + (in1.lo * in2.lo)[63:32] 3121 __ add(out_hi, out_hi, ShifterOperand(IP)); 3122 break; 3123 } 3124 3125 case Primitive::kPrimFloat: { 3126 __ vmuls(out.AsFpuRegister<SRegister>(), 3127 first.AsFpuRegister<SRegister>(), 3128 second.AsFpuRegister<SRegister>()); 3129 break; 3130 } 3131 3132 case Primitive::kPrimDouble: { 3133 __ vmuld(FromLowSToD(out.AsFpuRegisterPairLow<SRegister>()), 3134 FromLowSToD(first.AsFpuRegisterPairLow<SRegister>()), 3135 FromLowSToD(second.AsFpuRegisterPairLow<SRegister>())); 3136 break; 3137 } 3138 3139 default: 3140 LOG(FATAL) << "Unexpected mul type " << mul->GetResultType(); 3141 } 3142} 3143 3144void InstructionCodeGeneratorARM::DivRemOneOrMinusOne(HBinaryOperation* instruction) { 3145 DCHECK(instruction->IsDiv() || instruction->IsRem()); 3146 DCHECK(instruction->GetResultType() == Primitive::kPrimInt); 3147 3148 LocationSummary* locations = instruction->GetLocations(); 3149 Location second = locations->InAt(1); 3150 DCHECK(second.IsConstant()); 3151 3152 Register out = locations->Out().AsRegister<Register>(); 3153 Register dividend = locations->InAt(0).AsRegister<Register>(); 3154 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); 3155 DCHECK(imm == 1 || imm == -1); 3156 3157 if (instruction->IsRem()) { 3158 __ LoadImmediate(out, 0); 3159 } else { 3160 if (imm == 1) { 3161 __ Mov(out, dividend); 3162 } else { 3163 __ rsb(out, dividend, ShifterOperand(0)); 3164 } 3165 } 3166} 3167 3168void InstructionCodeGeneratorARM::DivRemByPowerOfTwo(HBinaryOperation* instruction) { 3169 DCHECK(instruction->IsDiv() || instruction->IsRem()); 3170 DCHECK(instruction->GetResultType() == Primitive::kPrimInt); 3171 3172 LocationSummary* locations = instruction->GetLocations(); 3173 Location second = locations->InAt(1); 3174 DCHECK(second.IsConstant()); 3175 3176 Register out = locations->Out().AsRegister<Register>(); 3177 Register dividend = locations->InAt(0).AsRegister<Register>(); 3178 Register temp = locations->GetTemp(0).AsRegister<Register>(); 3179 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); 3180 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm)); 3181 int ctz_imm = CTZ(abs_imm); 3182 3183 if (ctz_imm == 1) { 3184 __ Lsr(temp, dividend, 32 - ctz_imm); 3185 } else { 3186 __ Asr(temp, dividend, 31); 3187 __ Lsr(temp, temp, 32 - ctz_imm); 3188 } 3189 __ add(out, temp, ShifterOperand(dividend)); 3190 3191 if (instruction->IsDiv()) { 3192 __ Asr(out, out, ctz_imm); 3193 if (imm < 0) { 3194 __ rsb(out, out, ShifterOperand(0)); 3195 } 3196 } else { 3197 __ ubfx(out, out, 0, ctz_imm); 3198 __ sub(out, out, ShifterOperand(temp)); 3199 } 3200} 3201 3202void InstructionCodeGeneratorARM::GenerateDivRemWithAnyConstant(HBinaryOperation* instruction) { 3203 DCHECK(instruction->IsDiv() || instruction->IsRem()); 3204 DCHECK(instruction->GetResultType() == Primitive::kPrimInt); 3205 3206 LocationSummary* locations = instruction->GetLocations(); 3207 Location second = locations->InAt(1); 3208 DCHECK(second.IsConstant()); 3209 3210 Register out = locations->Out().AsRegister<Register>(); 3211 Register dividend = locations->InAt(0).AsRegister<Register>(); 3212 Register temp1 = locations->GetTemp(0).AsRegister<Register>(); 3213 Register temp2 = locations->GetTemp(1).AsRegister<Register>(); 3214 int64_t imm = second.GetConstant()->AsIntConstant()->GetValue(); 3215 3216 int64_t magic; 3217 int shift; 3218 CalculateMagicAndShiftForDivRem(imm, false /* is_long */, &magic, &shift); 3219 3220 __ LoadImmediate(temp1, magic); 3221 __ smull(temp2, temp1, dividend, temp1); 3222 3223 if (imm > 0 && magic < 0) { 3224 __ add(temp1, temp1, ShifterOperand(dividend)); 3225 } else if (imm < 0 && magic > 0) { 3226 __ sub(temp1, temp1, ShifterOperand(dividend)); 3227 } 3228 3229 if (shift != 0) { 3230 __ Asr(temp1, temp1, shift); 3231 } 3232 3233 if (instruction->IsDiv()) { 3234 __ sub(out, temp1, ShifterOperand(temp1, ASR, 31)); 3235 } else { 3236 __ sub(temp1, temp1, ShifterOperand(temp1, ASR, 31)); 3237 // TODO: Strength reduction for mls. 3238 __ LoadImmediate(temp2, imm); 3239 __ mls(out, temp1, temp2, dividend); 3240 } 3241} 3242 3243void InstructionCodeGeneratorARM::GenerateDivRemConstantIntegral(HBinaryOperation* instruction) { 3244 DCHECK(instruction->IsDiv() || instruction->IsRem()); 3245 DCHECK(instruction->GetResultType() == Primitive::kPrimInt); 3246 3247 LocationSummary* locations = instruction->GetLocations(); 3248 Location second = locations->InAt(1); 3249 DCHECK(second.IsConstant()); 3250 3251 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); 3252 if (imm == 0) { 3253 // Do not generate anything. DivZeroCheck would prevent any code to be executed. 3254 } else if (imm == 1 || imm == -1) { 3255 DivRemOneOrMinusOne(instruction); 3256 } else if (IsPowerOfTwo(AbsOrMin(imm))) { 3257 DivRemByPowerOfTwo(instruction); 3258 } else { 3259 DCHECK(imm <= -2 || imm >= 2); 3260 GenerateDivRemWithAnyConstant(instruction); 3261 } 3262} 3263 3264void LocationsBuilderARM::VisitDiv(HDiv* div) { 3265 LocationSummary::CallKind call_kind = LocationSummary::kNoCall; 3266 if (div->GetResultType() == Primitive::kPrimLong) { 3267 // pLdiv runtime call. 3268 call_kind = LocationSummary::kCallOnMainOnly; 3269 } else if (div->GetResultType() == Primitive::kPrimInt && div->InputAt(1)->IsConstant()) { 3270 // sdiv will be replaced by other instruction sequence. 3271 } else if (div->GetResultType() == Primitive::kPrimInt && 3272 !codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { 3273 // pIdivmod runtime call. 3274 call_kind = LocationSummary::kCallOnMainOnly; 3275 } 3276 3277 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(div, call_kind); 3278 3279 switch (div->GetResultType()) { 3280 case Primitive::kPrimInt: { 3281 if (div->InputAt(1)->IsConstant()) { 3282 locations->SetInAt(0, Location::RequiresRegister()); 3283 locations->SetInAt(1, Location::ConstantLocation(div->InputAt(1)->AsConstant())); 3284 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 3285 int32_t value = div->InputAt(1)->AsIntConstant()->GetValue(); 3286 if (value == 1 || value == 0 || value == -1) { 3287 // No temp register required. 3288 } else { 3289 locations->AddTemp(Location::RequiresRegister()); 3290 if (!IsPowerOfTwo(AbsOrMin(value))) { 3291 locations->AddTemp(Location::RequiresRegister()); 3292 } 3293 } 3294 } else if (codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { 3295 locations->SetInAt(0, Location::RequiresRegister()); 3296 locations->SetInAt(1, Location::RequiresRegister()); 3297 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 3298 } else { 3299 InvokeRuntimeCallingConvention calling_convention; 3300 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(0))); 3301 locations->SetInAt(1, Location::RegisterLocation(calling_convention.GetRegisterAt(1))); 3302 // Note: divrem will compute both the quotient and the remainder as the pair R0 and R1, but 3303 // we only need the former. 3304 locations->SetOut(Location::RegisterLocation(R0)); 3305 } 3306 break; 3307 } 3308 case Primitive::kPrimLong: { 3309 InvokeRuntimeCallingConvention calling_convention; 3310 locations->SetInAt(0, Location::RegisterPairLocation( 3311 calling_convention.GetRegisterAt(0), calling_convention.GetRegisterAt(1))); 3312 locations->SetInAt(1, Location::RegisterPairLocation( 3313 calling_convention.GetRegisterAt(2), calling_convention.GetRegisterAt(3))); 3314 locations->SetOut(Location::RegisterPairLocation(R0, R1)); 3315 break; 3316 } 3317 case Primitive::kPrimFloat: 3318 case Primitive::kPrimDouble: { 3319 locations->SetInAt(0, Location::RequiresFpuRegister()); 3320 locations->SetInAt(1, Location::RequiresFpuRegister()); 3321 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); 3322 break; 3323 } 3324 3325 default: 3326 LOG(FATAL) << "Unexpected div type " << div->GetResultType(); 3327 } 3328} 3329 3330void InstructionCodeGeneratorARM::VisitDiv(HDiv* div) { 3331 LocationSummary* locations = div->GetLocations(); 3332 Location out = locations->Out(); 3333 Location first = locations->InAt(0); 3334 Location second = locations->InAt(1); 3335 3336 switch (div->GetResultType()) { 3337 case Primitive::kPrimInt: { 3338 if (second.IsConstant()) { 3339 GenerateDivRemConstantIntegral(div); 3340 } else if (codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { 3341 __ sdiv(out.AsRegister<Register>(), 3342 first.AsRegister<Register>(), 3343 second.AsRegister<Register>()); 3344 } else { 3345 InvokeRuntimeCallingConvention calling_convention; 3346 DCHECK_EQ(calling_convention.GetRegisterAt(0), first.AsRegister<Register>()); 3347 DCHECK_EQ(calling_convention.GetRegisterAt(1), second.AsRegister<Register>()); 3348 DCHECK_EQ(R0, out.AsRegister<Register>()); 3349 3350 codegen_->InvokeRuntime(kQuickIdivmod, div, div->GetDexPc()); 3351 CheckEntrypointTypes<kQuickIdivmod, int32_t, int32_t, int32_t>(); 3352 } 3353 break; 3354 } 3355 3356 case Primitive::kPrimLong: { 3357 InvokeRuntimeCallingConvention calling_convention; 3358 DCHECK_EQ(calling_convention.GetRegisterAt(0), first.AsRegisterPairLow<Register>()); 3359 DCHECK_EQ(calling_convention.GetRegisterAt(1), first.AsRegisterPairHigh<Register>()); 3360 DCHECK_EQ(calling_convention.GetRegisterAt(2), second.AsRegisterPairLow<Register>()); 3361 DCHECK_EQ(calling_convention.GetRegisterAt(3), second.AsRegisterPairHigh<Register>()); 3362 DCHECK_EQ(R0, out.AsRegisterPairLow<Register>()); 3363 DCHECK_EQ(R1, out.AsRegisterPairHigh<Register>()); 3364 3365 codegen_->InvokeRuntime(kQuickLdiv, div, div->GetDexPc()); 3366 CheckEntrypointTypes<kQuickLdiv, int64_t, int64_t, int64_t>(); 3367 break; 3368 } 3369 3370 case Primitive::kPrimFloat: { 3371 __ vdivs(out.AsFpuRegister<SRegister>(), 3372 first.AsFpuRegister<SRegister>(), 3373 second.AsFpuRegister<SRegister>()); 3374 break; 3375 } 3376 3377 case Primitive::kPrimDouble: { 3378 __ vdivd(FromLowSToD(out.AsFpuRegisterPairLow<SRegister>()), 3379 FromLowSToD(first.AsFpuRegisterPairLow<SRegister>()), 3380 FromLowSToD(second.AsFpuRegisterPairLow<SRegister>())); 3381 break; 3382 } 3383 3384 default: 3385 LOG(FATAL) << "Unexpected div type " << div->GetResultType(); 3386 } 3387} 3388 3389void LocationsBuilderARM::VisitRem(HRem* rem) { 3390 Primitive::Type type = rem->GetResultType(); 3391 3392 // Most remainders are implemented in the runtime. 3393 LocationSummary::CallKind call_kind = LocationSummary::kCallOnMainOnly; 3394 if (rem->GetResultType() == Primitive::kPrimInt && rem->InputAt(1)->IsConstant()) { 3395 // sdiv will be replaced by other instruction sequence. 3396 call_kind = LocationSummary::kNoCall; 3397 } else if ((rem->GetResultType() == Primitive::kPrimInt) 3398 && codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { 3399 // Have hardware divide instruction for int, do it with three instructions. 3400 call_kind = LocationSummary::kNoCall; 3401 } 3402 3403 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(rem, call_kind); 3404 3405 switch (type) { 3406 case Primitive::kPrimInt: { 3407 if (rem->InputAt(1)->IsConstant()) { 3408 locations->SetInAt(0, Location::RequiresRegister()); 3409 locations->SetInAt(1, Location::ConstantLocation(rem->InputAt(1)->AsConstant())); 3410 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 3411 int32_t value = rem->InputAt(1)->AsIntConstant()->GetValue(); 3412 if (value == 1 || value == 0 || value == -1) { 3413 // No temp register required. 3414 } else { 3415 locations->AddTemp(Location::RequiresRegister()); 3416 if (!IsPowerOfTwo(AbsOrMin(value))) { 3417 locations->AddTemp(Location::RequiresRegister()); 3418 } 3419 } 3420 } else if (codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { 3421 locations->SetInAt(0, Location::RequiresRegister()); 3422 locations->SetInAt(1, Location::RequiresRegister()); 3423 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 3424 locations->AddTemp(Location::RequiresRegister()); 3425 } else { 3426 InvokeRuntimeCallingConvention calling_convention; 3427 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(0))); 3428 locations->SetInAt(1, Location::RegisterLocation(calling_convention.GetRegisterAt(1))); 3429 // Note: divrem will compute both the quotient and the remainder as the pair R0 and R1, but 3430 // we only need the latter. 3431 locations->SetOut(Location::RegisterLocation(R1)); 3432 } 3433 break; 3434 } 3435 case Primitive::kPrimLong: { 3436 InvokeRuntimeCallingConvention calling_convention; 3437 locations->SetInAt(0, Location::RegisterPairLocation( 3438 calling_convention.GetRegisterAt(0), calling_convention.GetRegisterAt(1))); 3439 locations->SetInAt(1, Location::RegisterPairLocation( 3440 calling_convention.GetRegisterAt(2), calling_convention.GetRegisterAt(3))); 3441 // The runtime helper puts the output in R2,R3. 3442 locations->SetOut(Location::RegisterPairLocation(R2, R3)); 3443 break; 3444 } 3445 case Primitive::kPrimFloat: { 3446 InvokeRuntimeCallingConvention calling_convention; 3447 locations->SetInAt(0, Location::FpuRegisterLocation(calling_convention.GetFpuRegisterAt(0))); 3448 locations->SetInAt(1, Location::FpuRegisterLocation(calling_convention.GetFpuRegisterAt(1))); 3449 locations->SetOut(Location::FpuRegisterLocation(S0)); 3450 break; 3451 } 3452 3453 case Primitive::kPrimDouble: { 3454 InvokeRuntimeCallingConvention calling_convention; 3455 locations->SetInAt(0, Location::FpuRegisterPairLocation( 3456 calling_convention.GetFpuRegisterAt(0), calling_convention.GetFpuRegisterAt(1))); 3457 locations->SetInAt(1, Location::FpuRegisterPairLocation( 3458 calling_convention.GetFpuRegisterAt(2), calling_convention.GetFpuRegisterAt(3))); 3459 locations->SetOut(Location::Location::FpuRegisterPairLocation(S0, S1)); 3460 break; 3461 } 3462 3463 default: 3464 LOG(FATAL) << "Unexpected rem type " << type; 3465 } 3466} 3467 3468void InstructionCodeGeneratorARM::VisitRem(HRem* rem) { 3469 LocationSummary* locations = rem->GetLocations(); 3470 Location out = locations->Out(); 3471 Location first = locations->InAt(0); 3472 Location second = locations->InAt(1); 3473 3474 Primitive::Type type = rem->GetResultType(); 3475 switch (type) { 3476 case Primitive::kPrimInt: { 3477 if (second.IsConstant()) { 3478 GenerateDivRemConstantIntegral(rem); 3479 } else if (codegen_->GetInstructionSetFeatures().HasDivideInstruction()) { 3480 Register reg1 = first.AsRegister<Register>(); 3481 Register reg2 = second.AsRegister<Register>(); 3482 Register temp = locations->GetTemp(0).AsRegister<Register>(); 3483 3484 // temp = reg1 / reg2 (integer division) 3485 // dest = reg1 - temp * reg2 3486 __ sdiv(temp, reg1, reg2); 3487 __ mls(out.AsRegister<Register>(), temp, reg2, reg1); 3488 } else { 3489 InvokeRuntimeCallingConvention calling_convention; 3490 DCHECK_EQ(calling_convention.GetRegisterAt(0), first.AsRegister<Register>()); 3491 DCHECK_EQ(calling_convention.GetRegisterAt(1), second.AsRegister<Register>()); 3492 DCHECK_EQ(R1, out.AsRegister<Register>()); 3493 3494 codegen_->InvokeRuntime(kQuickIdivmod, rem, rem->GetDexPc()); 3495 CheckEntrypointTypes<kQuickIdivmod, int32_t, int32_t, int32_t>(); 3496 } 3497 break; 3498 } 3499 3500 case Primitive::kPrimLong: { 3501 codegen_->InvokeRuntime(kQuickLmod, rem, rem->GetDexPc()); 3502 CheckEntrypointTypes<kQuickLmod, int64_t, int64_t, int64_t>(); 3503 break; 3504 } 3505 3506 case Primitive::kPrimFloat: { 3507 codegen_->InvokeRuntime(kQuickFmodf, rem, rem->GetDexPc()); 3508 CheckEntrypointTypes<kQuickFmodf, float, float, float>(); 3509 break; 3510 } 3511 3512 case Primitive::kPrimDouble: { 3513 codegen_->InvokeRuntime(kQuickFmod, rem, rem->GetDexPc()); 3514 CheckEntrypointTypes<kQuickFmod, double, double, double>(); 3515 break; 3516 } 3517 3518 default: 3519 LOG(FATAL) << "Unexpected rem type " << type; 3520 } 3521} 3522 3523void LocationsBuilderARM::VisitDivZeroCheck(HDivZeroCheck* instruction) { 3524 LocationSummary* locations = codegen_->CreateThrowingSlowPathLocations(instruction); 3525 locations->SetInAt(0, Location::RegisterOrConstant(instruction->InputAt(0))); 3526} 3527 3528void InstructionCodeGeneratorARM::VisitDivZeroCheck(HDivZeroCheck* instruction) { 3529 SlowPathCodeARM* slow_path = new (GetGraph()->GetArena()) DivZeroCheckSlowPathARM(instruction); 3530 codegen_->AddSlowPath(slow_path); 3531 3532 LocationSummary* locations = instruction->GetLocations(); 3533 Location value = locations->InAt(0); 3534 3535 switch (instruction->GetType()) { 3536 case Primitive::kPrimBoolean: 3537 case Primitive::kPrimByte: 3538 case Primitive::kPrimChar: 3539 case Primitive::kPrimShort: 3540 case Primitive::kPrimInt: { 3541 if (value.IsRegister()) { 3542 __ CompareAndBranchIfZero(value.AsRegister<Register>(), slow_path->GetEntryLabel()); 3543 } else { 3544 DCHECK(value.IsConstant()) << value; 3545 if (value.GetConstant()->AsIntConstant()->GetValue() == 0) { 3546 __ b(slow_path->GetEntryLabel()); 3547 } 3548 } 3549 break; 3550 } 3551 case Primitive::kPrimLong: { 3552 if (value.IsRegisterPair()) { 3553 __ orrs(IP, 3554 value.AsRegisterPairLow<Register>(), 3555 ShifterOperand(value.AsRegisterPairHigh<Register>())); 3556 __ b(slow_path->GetEntryLabel(), EQ); 3557 } else { 3558 DCHECK(value.IsConstant()) << value; 3559 if (value.GetConstant()->AsLongConstant()->GetValue() == 0) { 3560 __ b(slow_path->GetEntryLabel()); 3561 } 3562 } 3563 break; 3564 default: 3565 LOG(FATAL) << "Unexpected type for HDivZeroCheck " << instruction->GetType(); 3566 } 3567 } 3568} 3569 3570void InstructionCodeGeneratorARM::HandleIntegerRotate(LocationSummary* locations) { 3571 Register in = locations->InAt(0).AsRegister<Register>(); 3572 Location rhs = locations->InAt(1); 3573 Register out = locations->Out().AsRegister<Register>(); 3574 3575 if (rhs.IsConstant()) { 3576 // Arm32 and Thumb2 assemblers require a rotation on the interval [1,31], 3577 // so map all rotations to a +ve. equivalent in that range. 3578 // (e.g. left *or* right by -2 bits == 30 bits in the same direction.) 3579 uint32_t rot = CodeGenerator::GetInt32ValueOf(rhs.GetConstant()) & 0x1F; 3580 if (rot) { 3581 // Rotate, mapping left rotations to right equivalents if necessary. 3582 // (e.g. left by 2 bits == right by 30.) 3583 __ Ror(out, in, rot); 3584 } else if (out != in) { 3585 __ Mov(out, in); 3586 } 3587 } else { 3588 __ Ror(out, in, rhs.AsRegister<Register>()); 3589 } 3590} 3591 3592// Gain some speed by mapping all Long rotates onto equivalent pairs of Integer 3593// rotates by swapping input regs (effectively rotating by the first 32-bits of 3594// a larger rotation) or flipping direction (thus treating larger right/left 3595// rotations as sub-word sized rotations in the other direction) as appropriate. 3596void InstructionCodeGeneratorARM::HandleLongRotate(LocationSummary* locations) { 3597 Register in_reg_lo = locations->InAt(0).AsRegisterPairLow<Register>(); 3598 Register in_reg_hi = locations->InAt(0).AsRegisterPairHigh<Register>(); 3599 Location rhs = locations->InAt(1); 3600 Register out_reg_lo = locations->Out().AsRegisterPairLow<Register>(); 3601 Register out_reg_hi = locations->Out().AsRegisterPairHigh<Register>(); 3602 3603 if (rhs.IsConstant()) { 3604 uint64_t rot = CodeGenerator::GetInt64ValueOf(rhs.GetConstant()); 3605 // Map all rotations to +ve. equivalents on the interval [0,63]. 3606 rot &= kMaxLongShiftDistance; 3607 // For rotates over a word in size, 'pre-rotate' by 32-bits to keep rotate 3608 // logic below to a simple pair of binary orr. 3609 // (e.g. 34 bits == in_reg swap + 2 bits right.) 3610 if (rot >= kArmBitsPerWord) { 3611 rot -= kArmBitsPerWord; 3612 std::swap(in_reg_hi, in_reg_lo); 3613 } 3614 // Rotate, or mov to out for zero or word size rotations. 3615 if (rot != 0u) { 3616 __ Lsr(out_reg_hi, in_reg_hi, rot); 3617 __ orr(out_reg_hi, out_reg_hi, ShifterOperand(in_reg_lo, arm::LSL, kArmBitsPerWord - rot)); 3618 __ Lsr(out_reg_lo, in_reg_lo, rot); 3619 __ orr(out_reg_lo, out_reg_lo, ShifterOperand(in_reg_hi, arm::LSL, kArmBitsPerWord - rot)); 3620 } else { 3621 __ Mov(out_reg_lo, in_reg_lo); 3622 __ Mov(out_reg_hi, in_reg_hi); 3623 } 3624 } else { 3625 Register shift_right = locations->GetTemp(0).AsRegister<Register>(); 3626 Register shift_left = locations->GetTemp(1).AsRegister<Register>(); 3627 Label end; 3628 Label shift_by_32_plus_shift_right; 3629 3630 __ and_(shift_right, rhs.AsRegister<Register>(), ShifterOperand(0x1F)); 3631 __ Lsrs(shift_left, rhs.AsRegister<Register>(), 6); 3632 __ rsb(shift_left, shift_right, ShifterOperand(kArmBitsPerWord), AL, kCcKeep); 3633 __ b(&shift_by_32_plus_shift_right, CC); 3634 3635 // out_reg_hi = (reg_hi << shift_left) | (reg_lo >> shift_right). 3636 // out_reg_lo = (reg_lo << shift_left) | (reg_hi >> shift_right). 3637 __ Lsl(out_reg_hi, in_reg_hi, shift_left); 3638 __ Lsr(out_reg_lo, in_reg_lo, shift_right); 3639 __ add(out_reg_hi, out_reg_hi, ShifterOperand(out_reg_lo)); 3640 __ Lsl(out_reg_lo, in_reg_lo, shift_left); 3641 __ Lsr(shift_left, in_reg_hi, shift_right); 3642 __ add(out_reg_lo, out_reg_lo, ShifterOperand(shift_left)); 3643 __ b(&end); 3644 3645 __ Bind(&shift_by_32_plus_shift_right); // Shift by 32+shift_right. 3646 // out_reg_hi = (reg_hi >> shift_right) | (reg_lo << shift_left). 3647 // out_reg_lo = (reg_lo >> shift_right) | (reg_hi << shift_left). 3648 __ Lsr(out_reg_hi, in_reg_hi, shift_right); 3649 __ Lsl(out_reg_lo, in_reg_lo, shift_left); 3650 __ add(out_reg_hi, out_reg_hi, ShifterOperand(out_reg_lo)); 3651 __ Lsr(out_reg_lo, in_reg_lo, shift_right); 3652 __ Lsl(shift_right, in_reg_hi, shift_left); 3653 __ add(out_reg_lo, out_reg_lo, ShifterOperand(shift_right)); 3654 3655 __ Bind(&end); 3656 } 3657} 3658 3659void LocationsBuilderARM::VisitRor(HRor* ror) { 3660 LocationSummary* locations = 3661 new (GetGraph()->GetArena()) LocationSummary(ror, LocationSummary::kNoCall); 3662 switch (ror->GetResultType()) { 3663 case Primitive::kPrimInt: { 3664 locations->SetInAt(0, Location::RequiresRegister()); 3665 locations->SetInAt(1, Location::RegisterOrConstant(ror->InputAt(1))); 3666 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 3667 break; 3668 } 3669 case Primitive::kPrimLong: { 3670 locations->SetInAt(0, Location::RequiresRegister()); 3671 if (ror->InputAt(1)->IsConstant()) { 3672 locations->SetInAt(1, Location::ConstantLocation(ror->InputAt(1)->AsConstant())); 3673 } else { 3674 locations->SetInAt(1, Location::RequiresRegister()); 3675 locations->AddTemp(Location::RequiresRegister()); 3676 locations->AddTemp(Location::RequiresRegister()); 3677 } 3678 locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap); 3679 break; 3680 } 3681 default: 3682 LOG(FATAL) << "Unexpected operation type " << ror->GetResultType(); 3683 } 3684} 3685 3686void InstructionCodeGeneratorARM::VisitRor(HRor* ror) { 3687 LocationSummary* locations = ror->GetLocations(); 3688 Primitive::Type type = ror->GetResultType(); 3689 switch (type) { 3690 case Primitive::kPrimInt: { 3691 HandleIntegerRotate(locations); 3692 break; 3693 } 3694 case Primitive::kPrimLong: { 3695 HandleLongRotate(locations); 3696 break; 3697 } 3698 default: 3699 LOG(FATAL) << "Unexpected operation type " << type; 3700 UNREACHABLE(); 3701 } 3702} 3703 3704void LocationsBuilderARM::HandleShift(HBinaryOperation* op) { 3705 DCHECK(op->IsShl() || op->IsShr() || op->IsUShr()); 3706 3707 LocationSummary* locations = 3708 new (GetGraph()->GetArena()) LocationSummary(op, LocationSummary::kNoCall); 3709 3710 switch (op->GetResultType()) { 3711 case Primitive::kPrimInt: { 3712 locations->SetInAt(0, Location::RequiresRegister()); 3713 if (op->InputAt(1)->IsConstant()) { 3714 locations->SetInAt(1, Location::ConstantLocation(op->InputAt(1)->AsConstant())); 3715 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 3716 } else { 3717 locations->SetInAt(1, Location::RequiresRegister()); 3718 // Make the output overlap, as it will be used to hold the masked 3719 // second input. 3720 locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap); 3721 } 3722 break; 3723 } 3724 case Primitive::kPrimLong: { 3725 locations->SetInAt(0, Location::RequiresRegister()); 3726 if (op->InputAt(1)->IsConstant()) { 3727 locations->SetInAt(1, Location::ConstantLocation(op->InputAt(1)->AsConstant())); 3728 // For simplicity, use kOutputOverlap even though we only require that low registers 3729 // don't clash with high registers which the register allocator currently guarantees. 3730 locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap); 3731 } else { 3732 locations->SetInAt(1, Location::RequiresRegister()); 3733 locations->AddTemp(Location::RequiresRegister()); 3734 locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap); 3735 } 3736 break; 3737 } 3738 default: 3739 LOG(FATAL) << "Unexpected operation type " << op->GetResultType(); 3740 } 3741} 3742 3743void InstructionCodeGeneratorARM::HandleShift(HBinaryOperation* op) { 3744 DCHECK(op->IsShl() || op->IsShr() || op->IsUShr()); 3745 3746 LocationSummary* locations = op->GetLocations(); 3747 Location out = locations->Out(); 3748 Location first = locations->InAt(0); 3749 Location second = locations->InAt(1); 3750 3751 Primitive::Type type = op->GetResultType(); 3752 switch (type) { 3753 case Primitive::kPrimInt: { 3754 Register out_reg = out.AsRegister<Register>(); 3755 Register first_reg = first.AsRegister<Register>(); 3756 if (second.IsRegister()) { 3757 Register second_reg = second.AsRegister<Register>(); 3758 // ARM doesn't mask the shift count so we need to do it ourselves. 3759 __ and_(out_reg, second_reg, ShifterOperand(kMaxIntShiftDistance)); 3760 if (op->IsShl()) { 3761 __ Lsl(out_reg, first_reg, out_reg); 3762 } else if (op->IsShr()) { 3763 __ Asr(out_reg, first_reg, out_reg); 3764 } else { 3765 __ Lsr(out_reg, first_reg, out_reg); 3766 } 3767 } else { 3768 int32_t cst = second.GetConstant()->AsIntConstant()->GetValue(); 3769 uint32_t shift_value = cst & kMaxIntShiftDistance; 3770 if (shift_value == 0) { // ARM does not support shifting with 0 immediate. 3771 __ Mov(out_reg, first_reg); 3772 } else if (op->IsShl()) { 3773 __ Lsl(out_reg, first_reg, shift_value); 3774 } else if (op->IsShr()) { 3775 __ Asr(out_reg, first_reg, shift_value); 3776 } else { 3777 __ Lsr(out_reg, first_reg, shift_value); 3778 } 3779 } 3780 break; 3781 } 3782 case Primitive::kPrimLong: { 3783 Register o_h = out.AsRegisterPairHigh<Register>(); 3784 Register o_l = out.AsRegisterPairLow<Register>(); 3785 3786 Register high = first.AsRegisterPairHigh<Register>(); 3787 Register low = first.AsRegisterPairLow<Register>(); 3788 3789 if (second.IsRegister()) { 3790 Register temp = locations->GetTemp(0).AsRegister<Register>(); 3791 3792 Register second_reg = second.AsRegister<Register>(); 3793 3794 if (op->IsShl()) { 3795 __ and_(o_l, second_reg, ShifterOperand(kMaxLongShiftDistance)); 3796 // Shift the high part 3797 __ Lsl(o_h, high, o_l); 3798 // Shift the low part and `or` what overflew on the high part 3799 __ rsb(temp, o_l, ShifterOperand(kArmBitsPerWord)); 3800 __ Lsr(temp, low, temp); 3801 __ orr(o_h, o_h, ShifterOperand(temp)); 3802 // If the shift is > 32 bits, override the high part 3803 __ subs(temp, o_l, ShifterOperand(kArmBitsPerWord)); 3804 __ it(PL); 3805 __ Lsl(o_h, low, temp, PL); 3806 // Shift the low part 3807 __ Lsl(o_l, low, o_l); 3808 } else if (op->IsShr()) { 3809 __ and_(o_h, second_reg, ShifterOperand(kMaxLongShiftDistance)); 3810 // Shift the low part 3811 __ Lsr(o_l, low, o_h); 3812 // Shift the high part and `or` what underflew on the low part 3813 __ rsb(temp, o_h, ShifterOperand(kArmBitsPerWord)); 3814 __ Lsl(temp, high, temp); 3815 __ orr(o_l, o_l, ShifterOperand(temp)); 3816 // If the shift is > 32 bits, override the low part 3817 __ subs(temp, o_h, ShifterOperand(kArmBitsPerWord)); 3818 __ it(PL); 3819 __ Asr(o_l, high, temp, PL); 3820 // Shift the high part 3821 __ Asr(o_h, high, o_h); 3822 } else { 3823 __ and_(o_h, second_reg, ShifterOperand(kMaxLongShiftDistance)); 3824 // same as Shr except we use `Lsr`s and not `Asr`s 3825 __ Lsr(o_l, low, o_h); 3826 __ rsb(temp, o_h, ShifterOperand(kArmBitsPerWord)); 3827 __ Lsl(temp, high, temp); 3828 __ orr(o_l, o_l, ShifterOperand(temp)); 3829 __ subs(temp, o_h, ShifterOperand(kArmBitsPerWord)); 3830 __ it(PL); 3831 __ Lsr(o_l, high, temp, PL); 3832 __ Lsr(o_h, high, o_h); 3833 } 3834 } else { 3835 // Register allocator doesn't create partial overlap. 3836 DCHECK_NE(o_l, high); 3837 DCHECK_NE(o_h, low); 3838 int32_t cst = second.GetConstant()->AsIntConstant()->GetValue(); 3839 uint32_t shift_value = cst & kMaxLongShiftDistance; 3840 if (shift_value > 32) { 3841 if (op->IsShl()) { 3842 __ Lsl(o_h, low, shift_value - 32); 3843 __ LoadImmediate(o_l, 0); 3844 } else if (op->IsShr()) { 3845 __ Asr(o_l, high, shift_value - 32); 3846 __ Asr(o_h, high, 31); 3847 } else { 3848 __ Lsr(o_l, high, shift_value - 32); 3849 __ LoadImmediate(o_h, 0); 3850 } 3851 } else if (shift_value == 32) { 3852 if (op->IsShl()) { 3853 __ mov(o_h, ShifterOperand(low)); 3854 __ LoadImmediate(o_l, 0); 3855 } else if (op->IsShr()) { 3856 __ mov(o_l, ShifterOperand(high)); 3857 __ Asr(o_h, high, 31); 3858 } else { 3859 __ mov(o_l, ShifterOperand(high)); 3860 __ LoadImmediate(o_h, 0); 3861 } 3862 } else if (shift_value == 1) { 3863 if (op->IsShl()) { 3864 __ Lsls(o_l, low, 1); 3865 __ adc(o_h, high, ShifterOperand(high)); 3866 } else if (op->IsShr()) { 3867 __ Asrs(o_h, high, 1); 3868 __ Rrx(o_l, low); 3869 } else { 3870 __ Lsrs(o_h, high, 1); 3871 __ Rrx(o_l, low); 3872 } 3873 } else { 3874 DCHECK(2 <= shift_value && shift_value < 32) << shift_value; 3875 if (op->IsShl()) { 3876 __ Lsl(o_h, high, shift_value); 3877 __ orr(o_h, o_h, ShifterOperand(low, LSR, 32 - shift_value)); 3878 __ Lsl(o_l, low, shift_value); 3879 } else if (op->IsShr()) { 3880 __ Lsr(o_l, low, shift_value); 3881 __ orr(o_l, o_l, ShifterOperand(high, LSL, 32 - shift_value)); 3882 __ Asr(o_h, high, shift_value); 3883 } else { 3884 __ Lsr(o_l, low, shift_value); 3885 __ orr(o_l, o_l, ShifterOperand(high, LSL, 32 - shift_value)); 3886 __ Lsr(o_h, high, shift_value); 3887 } 3888 } 3889 } 3890 break; 3891 } 3892 default: 3893 LOG(FATAL) << "Unexpected operation type " << type; 3894 UNREACHABLE(); 3895 } 3896} 3897 3898void LocationsBuilderARM::VisitShl(HShl* shl) { 3899 HandleShift(shl); 3900} 3901 3902void InstructionCodeGeneratorARM::VisitShl(HShl* shl) { 3903 HandleShift(shl); 3904} 3905 3906void LocationsBuilderARM::VisitShr(HShr* shr) { 3907 HandleShift(shr); 3908} 3909 3910void InstructionCodeGeneratorARM::VisitShr(HShr* shr) { 3911 HandleShift(shr); 3912} 3913 3914void LocationsBuilderARM::VisitUShr(HUShr* ushr) { 3915 HandleShift(ushr); 3916} 3917 3918void InstructionCodeGeneratorARM::VisitUShr(HUShr* ushr) { 3919 HandleShift(ushr); 3920} 3921 3922void LocationsBuilderARM::VisitNewInstance(HNewInstance* instruction) { 3923 LocationSummary* locations = 3924 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kCallOnMainOnly); 3925 if (instruction->IsStringAlloc()) { 3926 locations->AddTemp(Location::RegisterLocation(kMethodRegisterArgument)); 3927 } else { 3928 InvokeRuntimeCallingConvention calling_convention; 3929 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(0))); 3930 locations->SetInAt(1, Location::RegisterLocation(calling_convention.GetRegisterAt(1))); 3931 } 3932 locations->SetOut(Location::RegisterLocation(R0)); 3933} 3934 3935void InstructionCodeGeneratorARM::VisitNewInstance(HNewInstance* instruction) { 3936 // Note: if heap poisoning is enabled, the entry point takes cares 3937 // of poisoning the reference. 3938 if (instruction->IsStringAlloc()) { 3939 // String is allocated through StringFactory. Call NewEmptyString entry point. 3940 Register temp = instruction->GetLocations()->GetTemp(0).AsRegister<Register>(); 3941 MemberOffset code_offset = ArtMethod::EntryPointFromQuickCompiledCodeOffset(kArmPointerSize); 3942 __ LoadFromOffset(kLoadWord, temp, TR, QUICK_ENTRY_POINT(pNewEmptyString)); 3943 __ LoadFromOffset(kLoadWord, LR, temp, code_offset.Int32Value()); 3944 __ blx(LR); 3945 codegen_->RecordPcInfo(instruction, instruction->GetDexPc()); 3946 } else { 3947 codegen_->InvokeRuntime(instruction->GetEntrypoint(), instruction, instruction->GetDexPc()); 3948 CheckEntrypointTypes<kQuickAllocObjectWithAccessCheck, void*, uint32_t, ArtMethod*>(); 3949 } 3950} 3951 3952void LocationsBuilderARM::VisitNewArray(HNewArray* instruction) { 3953 LocationSummary* locations = 3954 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kCallOnMainOnly); 3955 InvokeRuntimeCallingConvention calling_convention; 3956 locations->AddTemp(Location::RegisterLocation(calling_convention.GetRegisterAt(0))); 3957 locations->SetOut(Location::RegisterLocation(R0)); 3958 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(1))); 3959 locations->SetInAt(1, Location::RegisterLocation(calling_convention.GetRegisterAt(2))); 3960} 3961 3962void InstructionCodeGeneratorARM::VisitNewArray(HNewArray* instruction) { 3963 InvokeRuntimeCallingConvention calling_convention; 3964 __ LoadImmediate(calling_convention.GetRegisterAt(0), instruction->GetTypeIndex()); 3965 // Note: if heap poisoning is enabled, the entry point takes cares 3966 // of poisoning the reference. 3967 codegen_->InvokeRuntime(instruction->GetEntrypoint(), instruction, instruction->GetDexPc()); 3968 CheckEntrypointTypes<kQuickAllocArrayWithAccessCheck, void*, uint32_t, int32_t, ArtMethod*>(); 3969} 3970 3971void LocationsBuilderARM::VisitParameterValue(HParameterValue* instruction) { 3972 LocationSummary* locations = 3973 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall); 3974 Location location = parameter_visitor_.GetNextLocation(instruction->GetType()); 3975 if (location.IsStackSlot()) { 3976 location = Location::StackSlot(location.GetStackIndex() + codegen_->GetFrameSize()); 3977 } else if (location.IsDoubleStackSlot()) { 3978 location = Location::DoubleStackSlot(location.GetStackIndex() + codegen_->GetFrameSize()); 3979 } 3980 locations->SetOut(location); 3981} 3982 3983void InstructionCodeGeneratorARM::VisitParameterValue( 3984 HParameterValue* instruction ATTRIBUTE_UNUSED) { 3985 // Nothing to do, the parameter is already at its location. 3986} 3987 3988void LocationsBuilderARM::VisitCurrentMethod(HCurrentMethod* instruction) { 3989 LocationSummary* locations = 3990 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall); 3991 locations->SetOut(Location::RegisterLocation(kMethodRegisterArgument)); 3992} 3993 3994void InstructionCodeGeneratorARM::VisitCurrentMethod(HCurrentMethod* instruction ATTRIBUTE_UNUSED) { 3995 // Nothing to do, the method is already at its location. 3996} 3997 3998void LocationsBuilderARM::VisitNot(HNot* not_) { 3999 LocationSummary* locations = 4000 new (GetGraph()->GetArena()) LocationSummary(not_, LocationSummary::kNoCall); 4001 locations->SetInAt(0, Location::RequiresRegister()); 4002 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 4003} 4004 4005void InstructionCodeGeneratorARM::VisitNot(HNot* not_) { 4006 LocationSummary* locations = not_->GetLocations(); 4007 Location out = locations->Out(); 4008 Location in = locations->InAt(0); 4009 switch (not_->GetResultType()) { 4010 case Primitive::kPrimInt: 4011 __ mvn(out.AsRegister<Register>(), ShifterOperand(in.AsRegister<Register>())); 4012 break; 4013 4014 case Primitive::kPrimLong: 4015 __ mvn(out.AsRegisterPairLow<Register>(), 4016 ShifterOperand(in.AsRegisterPairLow<Register>())); 4017 __ mvn(out.AsRegisterPairHigh<Register>(), 4018 ShifterOperand(in.AsRegisterPairHigh<Register>())); 4019 break; 4020 4021 default: 4022 LOG(FATAL) << "Unimplemented type for not operation " << not_->GetResultType(); 4023 } 4024} 4025 4026void LocationsBuilderARM::VisitBooleanNot(HBooleanNot* bool_not) { 4027 LocationSummary* locations = 4028 new (GetGraph()->GetArena()) LocationSummary(bool_not, LocationSummary::kNoCall); 4029 locations->SetInAt(0, Location::RequiresRegister()); 4030 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 4031} 4032 4033void InstructionCodeGeneratorARM::VisitBooleanNot(HBooleanNot* bool_not) { 4034 LocationSummary* locations = bool_not->GetLocations(); 4035 Location out = locations->Out(); 4036 Location in = locations->InAt(0); 4037 __ eor(out.AsRegister<Register>(), in.AsRegister<Register>(), ShifterOperand(1)); 4038} 4039 4040void LocationsBuilderARM::VisitCompare(HCompare* compare) { 4041 LocationSummary* locations = 4042 new (GetGraph()->GetArena()) LocationSummary(compare, LocationSummary::kNoCall); 4043 switch (compare->InputAt(0)->GetType()) { 4044 case Primitive::kPrimBoolean: 4045 case Primitive::kPrimByte: 4046 case Primitive::kPrimShort: 4047 case Primitive::kPrimChar: 4048 case Primitive::kPrimInt: 4049 case Primitive::kPrimLong: { 4050 locations->SetInAt(0, Location::RequiresRegister()); 4051 locations->SetInAt(1, Location::RequiresRegister()); 4052 // Output overlaps because it is written before doing the low comparison. 4053 locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap); 4054 break; 4055 } 4056 case Primitive::kPrimFloat: 4057 case Primitive::kPrimDouble: { 4058 locations->SetInAt(0, Location::RequiresFpuRegister()); 4059 locations->SetInAt(1, ArithmeticZeroOrFpuRegister(compare->InputAt(1))); 4060 locations->SetOut(Location::RequiresRegister()); 4061 break; 4062 } 4063 default: 4064 LOG(FATAL) << "Unexpected type for compare operation " << compare->InputAt(0)->GetType(); 4065 } 4066} 4067 4068void InstructionCodeGeneratorARM::VisitCompare(HCompare* compare) { 4069 LocationSummary* locations = compare->GetLocations(); 4070 Register out = locations->Out().AsRegister<Register>(); 4071 Location left = locations->InAt(0); 4072 Location right = locations->InAt(1); 4073 4074 Label less, greater, done; 4075 Primitive::Type type = compare->InputAt(0)->GetType(); 4076 Condition less_cond; 4077 switch (type) { 4078 case Primitive::kPrimBoolean: 4079 case Primitive::kPrimByte: 4080 case Primitive::kPrimShort: 4081 case Primitive::kPrimChar: 4082 case Primitive::kPrimInt: { 4083 __ LoadImmediate(out, 0); 4084 __ cmp(left.AsRegister<Register>(), 4085 ShifterOperand(right.AsRegister<Register>())); // Signed compare. 4086 less_cond = LT; 4087 break; 4088 } 4089 case Primitive::kPrimLong: { 4090 __ cmp(left.AsRegisterPairHigh<Register>(), 4091 ShifterOperand(right.AsRegisterPairHigh<Register>())); // Signed compare. 4092 __ b(&less, LT); 4093 __ b(&greater, GT); 4094 // Do LoadImmediate before the last `cmp`, as LoadImmediate might affect the status flags. 4095 __ LoadImmediate(out, 0); 4096 __ cmp(left.AsRegisterPairLow<Register>(), 4097 ShifterOperand(right.AsRegisterPairLow<Register>())); // Unsigned compare. 4098 less_cond = LO; 4099 break; 4100 } 4101 case Primitive::kPrimFloat: 4102 case Primitive::kPrimDouble: { 4103 __ LoadImmediate(out, 0); 4104 GenerateVcmp(compare); 4105 __ vmstat(); // transfer FP status register to ARM APSR. 4106 less_cond = ARMFPCondition(kCondLT, compare->IsGtBias()); 4107 break; 4108 } 4109 default: 4110 LOG(FATAL) << "Unexpected compare type " << type; 4111 UNREACHABLE(); 4112 } 4113 4114 __ b(&done, EQ); 4115 __ b(&less, less_cond); 4116 4117 __ Bind(&greater); 4118 __ LoadImmediate(out, 1); 4119 __ b(&done); 4120 4121 __ Bind(&less); 4122 __ LoadImmediate(out, -1); 4123 4124 __ Bind(&done); 4125} 4126 4127void LocationsBuilderARM::VisitPhi(HPhi* instruction) { 4128 LocationSummary* locations = 4129 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall); 4130 for (size_t i = 0, e = locations->GetInputCount(); i < e; ++i) { 4131 locations->SetInAt(i, Location::Any()); 4132 } 4133 locations->SetOut(Location::Any()); 4134} 4135 4136void InstructionCodeGeneratorARM::VisitPhi(HPhi* instruction ATTRIBUTE_UNUSED) { 4137 LOG(FATAL) << "Unreachable"; 4138} 4139 4140void CodeGeneratorARM::GenerateMemoryBarrier(MemBarrierKind kind) { 4141 // TODO (ported from quick): revisit ARM barrier kinds. 4142 DmbOptions flavor = DmbOptions::ISH; // Quiet C++ warnings. 4143 switch (kind) { 4144 case MemBarrierKind::kAnyStore: 4145 case MemBarrierKind::kLoadAny: 4146 case MemBarrierKind::kAnyAny: { 4147 flavor = DmbOptions::ISH; 4148 break; 4149 } 4150 case MemBarrierKind::kStoreStore: { 4151 flavor = DmbOptions::ISHST; 4152 break; 4153 } 4154 default: 4155 LOG(FATAL) << "Unexpected memory barrier " << kind; 4156 } 4157 __ dmb(flavor); 4158} 4159 4160void InstructionCodeGeneratorARM::GenerateWideAtomicLoad(Register addr, 4161 uint32_t offset, 4162 Register out_lo, 4163 Register out_hi) { 4164 if (offset != 0) { 4165 // Ensure `out_lo` is different from `addr`, so that loading 4166 // `offset` into `out_lo` does not clutter `addr`. 4167 DCHECK_NE(out_lo, addr); 4168 __ LoadImmediate(out_lo, offset); 4169 __ add(IP, addr, ShifterOperand(out_lo)); 4170 addr = IP; 4171 } 4172 __ ldrexd(out_lo, out_hi, addr); 4173} 4174 4175void InstructionCodeGeneratorARM::GenerateWideAtomicStore(Register addr, 4176 uint32_t offset, 4177 Register value_lo, 4178 Register value_hi, 4179 Register temp1, 4180 Register temp2, 4181 HInstruction* instruction) { 4182 Label fail; 4183 if (offset != 0) { 4184 __ LoadImmediate(temp1, offset); 4185 __ add(IP, addr, ShifterOperand(temp1)); 4186 addr = IP; 4187 } 4188 __ Bind(&fail); 4189 // We need a load followed by store. (The address used in a STREX instruction must 4190 // be the same as the address in the most recently executed LDREX instruction.) 4191 __ ldrexd(temp1, temp2, addr); 4192 codegen_->MaybeRecordImplicitNullCheck(instruction); 4193 __ strexd(temp1, value_lo, value_hi, addr); 4194 __ CompareAndBranchIfNonZero(temp1, &fail); 4195} 4196 4197void LocationsBuilderARM::HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info) { 4198 DCHECK(instruction->IsInstanceFieldSet() || instruction->IsStaticFieldSet()); 4199 4200 LocationSummary* locations = 4201 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall); 4202 locations->SetInAt(0, Location::RequiresRegister()); 4203 4204 Primitive::Type field_type = field_info.GetFieldType(); 4205 if (Primitive::IsFloatingPointType(field_type)) { 4206 locations->SetInAt(1, Location::RequiresFpuRegister()); 4207 } else { 4208 locations->SetInAt(1, Location::RequiresRegister()); 4209 } 4210 4211 bool is_wide = field_type == Primitive::kPrimLong || field_type == Primitive::kPrimDouble; 4212 bool generate_volatile = field_info.IsVolatile() 4213 && is_wide 4214 && !codegen_->GetInstructionSetFeatures().HasAtomicLdrdAndStrd(); 4215 bool needs_write_barrier = 4216 CodeGenerator::StoreNeedsWriteBarrier(field_type, instruction->InputAt(1)); 4217 // Temporary registers for the write barrier. 4218 // TODO: consider renaming StoreNeedsWriteBarrier to StoreNeedsGCMark. 4219 if (needs_write_barrier) { 4220 locations->AddTemp(Location::RequiresRegister()); // Possibly used for reference poisoning too. 4221 locations->AddTemp(Location::RequiresRegister()); 4222 } else if (generate_volatile) { 4223 // ARM encoding have some additional constraints for ldrexd/strexd: 4224 // - registers need to be consecutive 4225 // - the first register should be even but not R14. 4226 // We don't test for ARM yet, and the assertion makes sure that we 4227 // revisit this if we ever enable ARM encoding. 4228 DCHECK_EQ(InstructionSet::kThumb2, codegen_->GetInstructionSet()); 4229 4230 locations->AddTemp(Location::RequiresRegister()); 4231 locations->AddTemp(Location::RequiresRegister()); 4232 if (field_type == Primitive::kPrimDouble) { 4233 // For doubles we need two more registers to copy the value. 4234 locations->AddTemp(Location::RegisterLocation(R2)); 4235 locations->AddTemp(Location::RegisterLocation(R3)); 4236 } 4237 } 4238} 4239 4240void InstructionCodeGeneratorARM::HandleFieldSet(HInstruction* instruction, 4241 const FieldInfo& field_info, 4242 bool value_can_be_null) { 4243 DCHECK(instruction->IsInstanceFieldSet() || instruction->IsStaticFieldSet()); 4244 4245 LocationSummary* locations = instruction->GetLocations(); 4246 Register base = locations->InAt(0).AsRegister<Register>(); 4247 Location value = locations->InAt(1); 4248 4249 bool is_volatile = field_info.IsVolatile(); 4250 bool atomic_ldrd_strd = codegen_->GetInstructionSetFeatures().HasAtomicLdrdAndStrd(); 4251 Primitive::Type field_type = field_info.GetFieldType(); 4252 uint32_t offset = field_info.GetFieldOffset().Uint32Value(); 4253 bool needs_write_barrier = 4254 CodeGenerator::StoreNeedsWriteBarrier(field_type, instruction->InputAt(1)); 4255 4256 if (is_volatile) { 4257 codegen_->GenerateMemoryBarrier(MemBarrierKind::kAnyStore); 4258 } 4259 4260 switch (field_type) { 4261 case Primitive::kPrimBoolean: 4262 case Primitive::kPrimByte: { 4263 __ StoreToOffset(kStoreByte, value.AsRegister<Register>(), base, offset); 4264 break; 4265 } 4266 4267 case Primitive::kPrimShort: 4268 case Primitive::kPrimChar: { 4269 __ StoreToOffset(kStoreHalfword, value.AsRegister<Register>(), base, offset); 4270 break; 4271 } 4272 4273 case Primitive::kPrimInt: 4274 case Primitive::kPrimNot: { 4275 if (kPoisonHeapReferences && needs_write_barrier) { 4276 // Note that in the case where `value` is a null reference, 4277 // we do not enter this block, as a null reference does not 4278 // need poisoning. 4279 DCHECK_EQ(field_type, Primitive::kPrimNot); 4280 Register temp = locations->GetTemp(0).AsRegister<Register>(); 4281 __ Mov(temp, value.AsRegister<Register>()); 4282 __ PoisonHeapReference(temp); 4283 __ StoreToOffset(kStoreWord, temp, base, offset); 4284 } else { 4285 __ StoreToOffset(kStoreWord, value.AsRegister<Register>(), base, offset); 4286 } 4287 break; 4288 } 4289 4290 case Primitive::kPrimLong: { 4291 if (is_volatile && !atomic_ldrd_strd) { 4292 GenerateWideAtomicStore(base, offset, 4293 value.AsRegisterPairLow<Register>(), 4294 value.AsRegisterPairHigh<Register>(), 4295 locations->GetTemp(0).AsRegister<Register>(), 4296 locations->GetTemp(1).AsRegister<Register>(), 4297 instruction); 4298 } else { 4299 __ StoreToOffset(kStoreWordPair, value.AsRegisterPairLow<Register>(), base, offset); 4300 codegen_->MaybeRecordImplicitNullCheck(instruction); 4301 } 4302 break; 4303 } 4304 4305 case Primitive::kPrimFloat: { 4306 __ StoreSToOffset(value.AsFpuRegister<SRegister>(), base, offset); 4307 break; 4308 } 4309 4310 case Primitive::kPrimDouble: { 4311 DRegister value_reg = FromLowSToD(value.AsFpuRegisterPairLow<SRegister>()); 4312 if (is_volatile && !atomic_ldrd_strd) { 4313 Register value_reg_lo = locations->GetTemp(0).AsRegister<Register>(); 4314 Register value_reg_hi = locations->GetTemp(1).AsRegister<Register>(); 4315 4316 __ vmovrrd(value_reg_lo, value_reg_hi, value_reg); 4317 4318 GenerateWideAtomicStore(base, offset, 4319 value_reg_lo, 4320 value_reg_hi, 4321 locations->GetTemp(2).AsRegister<Register>(), 4322 locations->GetTemp(3).AsRegister<Register>(), 4323 instruction); 4324 } else { 4325 __ StoreDToOffset(value_reg, base, offset); 4326 codegen_->MaybeRecordImplicitNullCheck(instruction); 4327 } 4328 break; 4329 } 4330 4331 case Primitive::kPrimVoid: 4332 LOG(FATAL) << "Unreachable type " << field_type; 4333 UNREACHABLE(); 4334 } 4335 4336 // Longs and doubles are handled in the switch. 4337 if (field_type != Primitive::kPrimLong && field_type != Primitive::kPrimDouble) { 4338 codegen_->MaybeRecordImplicitNullCheck(instruction); 4339 } 4340 4341 if (CodeGenerator::StoreNeedsWriteBarrier(field_type, instruction->InputAt(1))) { 4342 Register temp = locations->GetTemp(0).AsRegister<Register>(); 4343 Register card = locations->GetTemp(1).AsRegister<Register>(); 4344 codegen_->MarkGCCard( 4345 temp, card, base, value.AsRegister<Register>(), value_can_be_null); 4346 } 4347 4348 if (is_volatile) { 4349 codegen_->GenerateMemoryBarrier(MemBarrierKind::kAnyAny); 4350 } 4351} 4352 4353void LocationsBuilderARM::HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info) { 4354 DCHECK(instruction->IsInstanceFieldGet() || instruction->IsStaticFieldGet()); 4355 4356 bool object_field_get_with_read_barrier = 4357 kEmitCompilerReadBarrier && (field_info.GetFieldType() == Primitive::kPrimNot); 4358 LocationSummary* locations = 4359 new (GetGraph()->GetArena()) LocationSummary(instruction, 4360 object_field_get_with_read_barrier ? 4361 LocationSummary::kCallOnSlowPath : 4362 LocationSummary::kNoCall); 4363 if (object_field_get_with_read_barrier && kUseBakerReadBarrier) { 4364 locations->SetCustomSlowPathCallerSaves(RegisterSet::Empty()); // No caller-save registers. 4365 } 4366 locations->SetInAt(0, Location::RequiresRegister()); 4367 4368 bool volatile_for_double = field_info.IsVolatile() 4369 && (field_info.GetFieldType() == Primitive::kPrimDouble) 4370 && !codegen_->GetInstructionSetFeatures().HasAtomicLdrdAndStrd(); 4371 // The output overlaps in case of volatile long: we don't want the 4372 // code generated by GenerateWideAtomicLoad to overwrite the 4373 // object's location. Likewise, in the case of an object field get 4374 // with read barriers enabled, we do not want the load to overwrite 4375 // the object's location, as we need it to emit the read barrier. 4376 bool overlap = (field_info.IsVolatile() && (field_info.GetFieldType() == Primitive::kPrimLong)) || 4377 object_field_get_with_read_barrier; 4378 4379 if (Primitive::IsFloatingPointType(instruction->GetType())) { 4380 locations->SetOut(Location::RequiresFpuRegister()); 4381 } else { 4382 locations->SetOut(Location::RequiresRegister(), 4383 (overlap ? Location::kOutputOverlap : Location::kNoOutputOverlap)); 4384 } 4385 if (volatile_for_double) { 4386 // ARM encoding have some additional constraints for ldrexd/strexd: 4387 // - registers need to be consecutive 4388 // - the first register should be even but not R14. 4389 // We don't test for ARM yet, and the assertion makes sure that we 4390 // revisit this if we ever enable ARM encoding. 4391 DCHECK_EQ(InstructionSet::kThumb2, codegen_->GetInstructionSet()); 4392 locations->AddTemp(Location::RequiresRegister()); 4393 locations->AddTemp(Location::RequiresRegister()); 4394 } else if (object_field_get_with_read_barrier && kUseBakerReadBarrier) { 4395 // We need a temporary register for the read barrier marking slow 4396 // path in CodeGeneratorARM::GenerateFieldLoadWithBakerReadBarrier. 4397 locations->AddTemp(Location::RequiresRegister()); 4398 } 4399} 4400 4401Location LocationsBuilderARM::ArithmeticZeroOrFpuRegister(HInstruction* input) { 4402 DCHECK(input->GetType() == Primitive::kPrimDouble || input->GetType() == Primitive::kPrimFloat) 4403 << input->GetType(); 4404 if ((input->IsFloatConstant() && (input->AsFloatConstant()->IsArithmeticZero())) || 4405 (input->IsDoubleConstant() && (input->AsDoubleConstant()->IsArithmeticZero()))) { 4406 return Location::ConstantLocation(input->AsConstant()); 4407 } else { 4408 return Location::RequiresFpuRegister(); 4409 } 4410} 4411 4412Location LocationsBuilderARM::ArmEncodableConstantOrRegister(HInstruction* constant, 4413 Opcode opcode) { 4414 DCHECK(!Primitive::IsFloatingPointType(constant->GetType())); 4415 if (constant->IsConstant() && 4416 CanEncodeConstantAsImmediate(constant->AsConstant(), opcode)) { 4417 return Location::ConstantLocation(constant->AsConstant()); 4418 } 4419 return Location::RequiresRegister(); 4420} 4421 4422bool LocationsBuilderARM::CanEncodeConstantAsImmediate(HConstant* input_cst, 4423 Opcode opcode) { 4424 uint64_t value = static_cast<uint64_t>(Int64FromConstant(input_cst)); 4425 if (Primitive::Is64BitType(input_cst->GetType())) { 4426 Opcode high_opcode = opcode; 4427 SetCc low_set_cc = kCcDontCare; 4428 switch (opcode) { 4429 case SUB: 4430 // Flip the operation to an ADD. 4431 value = -value; 4432 opcode = ADD; 4433 FALLTHROUGH_INTENDED; 4434 case ADD: 4435 if (Low32Bits(value) == 0u) { 4436 return CanEncodeConstantAsImmediate(High32Bits(value), opcode, kCcDontCare); 4437 } 4438 high_opcode = ADC; 4439 low_set_cc = kCcSet; 4440 break; 4441 default: 4442 break; 4443 } 4444 return CanEncodeConstantAsImmediate(Low32Bits(value), opcode, low_set_cc) && 4445 CanEncodeConstantAsImmediate(High32Bits(value), high_opcode, kCcDontCare); 4446 } else { 4447 return CanEncodeConstantAsImmediate(Low32Bits(value), opcode); 4448 } 4449} 4450 4451bool LocationsBuilderARM::CanEncodeConstantAsImmediate(uint32_t value, 4452 Opcode opcode, 4453 SetCc set_cc) { 4454 ShifterOperand so; 4455 ArmAssembler* assembler = codegen_->GetAssembler(); 4456 if (assembler->ShifterOperandCanHold(kNoRegister, kNoRegister, opcode, value, set_cc, &so)) { 4457 return true; 4458 } 4459 Opcode neg_opcode = kNoOperand; 4460 switch (opcode) { 4461 case AND: neg_opcode = BIC; value = ~value; break; 4462 case ORR: neg_opcode = ORN; value = ~value; break; 4463 case ADD: neg_opcode = SUB; value = -value; break; 4464 case ADC: neg_opcode = SBC; value = ~value; break; 4465 case SUB: neg_opcode = ADD; value = -value; break; 4466 case SBC: neg_opcode = ADC; value = ~value; break; 4467 default: 4468 return false; 4469 } 4470 return assembler->ShifterOperandCanHold(kNoRegister, kNoRegister, neg_opcode, value, set_cc, &so); 4471} 4472 4473void InstructionCodeGeneratorARM::HandleFieldGet(HInstruction* instruction, 4474 const FieldInfo& field_info) { 4475 DCHECK(instruction->IsInstanceFieldGet() || instruction->IsStaticFieldGet()); 4476 4477 LocationSummary* locations = instruction->GetLocations(); 4478 Location base_loc = locations->InAt(0); 4479 Register base = base_loc.AsRegister<Register>(); 4480 Location out = locations->Out(); 4481 bool is_volatile = field_info.IsVolatile(); 4482 bool atomic_ldrd_strd = codegen_->GetInstructionSetFeatures().HasAtomicLdrdAndStrd(); 4483 Primitive::Type field_type = field_info.GetFieldType(); 4484 uint32_t offset = field_info.GetFieldOffset().Uint32Value(); 4485 4486 switch (field_type) { 4487 case Primitive::kPrimBoolean: 4488 __ LoadFromOffset(kLoadUnsignedByte, out.AsRegister<Register>(), base, offset); 4489 break; 4490 4491 case Primitive::kPrimByte: 4492 __ LoadFromOffset(kLoadSignedByte, out.AsRegister<Register>(), base, offset); 4493 break; 4494 4495 case Primitive::kPrimShort: 4496 __ LoadFromOffset(kLoadSignedHalfword, out.AsRegister<Register>(), base, offset); 4497 break; 4498 4499 case Primitive::kPrimChar: 4500 __ LoadFromOffset(kLoadUnsignedHalfword, out.AsRegister<Register>(), base, offset); 4501 break; 4502 4503 case Primitive::kPrimInt: 4504 __ LoadFromOffset(kLoadWord, out.AsRegister<Register>(), base, offset); 4505 break; 4506 4507 case Primitive::kPrimNot: { 4508 // /* HeapReference<Object> */ out = *(base + offset) 4509 if (kEmitCompilerReadBarrier && kUseBakerReadBarrier) { 4510 Location temp_loc = locations->GetTemp(0); 4511 // Note that a potential implicit null check is handled in this 4512 // CodeGeneratorARM::GenerateFieldLoadWithBakerReadBarrier call. 4513 codegen_->GenerateFieldLoadWithBakerReadBarrier( 4514 instruction, out, base, offset, temp_loc, /* needs_null_check */ true); 4515 if (is_volatile) { 4516 codegen_->GenerateMemoryBarrier(MemBarrierKind::kLoadAny); 4517 } 4518 } else { 4519 __ LoadFromOffset(kLoadWord, out.AsRegister<Register>(), base, offset); 4520 codegen_->MaybeRecordImplicitNullCheck(instruction); 4521 if (is_volatile) { 4522 codegen_->GenerateMemoryBarrier(MemBarrierKind::kLoadAny); 4523 } 4524 // If read barriers are enabled, emit read barriers other than 4525 // Baker's using a slow path (and also unpoison the loaded 4526 // reference, if heap poisoning is enabled). 4527 codegen_->MaybeGenerateReadBarrierSlow(instruction, out, out, base_loc, offset); 4528 } 4529 break; 4530 } 4531 4532 case Primitive::kPrimLong: 4533 if (is_volatile && !atomic_ldrd_strd) { 4534 GenerateWideAtomicLoad(base, offset, 4535 out.AsRegisterPairLow<Register>(), 4536 out.AsRegisterPairHigh<Register>()); 4537 } else { 4538 __ LoadFromOffset(kLoadWordPair, out.AsRegisterPairLow<Register>(), base, offset); 4539 } 4540 break; 4541 4542 case Primitive::kPrimFloat: 4543 __ LoadSFromOffset(out.AsFpuRegister<SRegister>(), base, offset); 4544 break; 4545 4546 case Primitive::kPrimDouble: { 4547 DRegister out_reg = FromLowSToD(out.AsFpuRegisterPairLow<SRegister>()); 4548 if (is_volatile && !atomic_ldrd_strd) { 4549 Register lo = locations->GetTemp(0).AsRegister<Register>(); 4550 Register hi = locations->GetTemp(1).AsRegister<Register>(); 4551 GenerateWideAtomicLoad(base, offset, lo, hi); 4552 codegen_->MaybeRecordImplicitNullCheck(instruction); 4553 __ vmovdrr(out_reg, lo, hi); 4554 } else { 4555 __ LoadDFromOffset(out_reg, base, offset); 4556 codegen_->MaybeRecordImplicitNullCheck(instruction); 4557 } 4558 break; 4559 } 4560 4561 case Primitive::kPrimVoid: 4562 LOG(FATAL) << "Unreachable type " << field_type; 4563 UNREACHABLE(); 4564 } 4565 4566 if (field_type == Primitive::kPrimNot || field_type == Primitive::kPrimDouble) { 4567 // Potential implicit null checks, in the case of reference or 4568 // double fields, are handled in the previous switch statement. 4569 } else { 4570 codegen_->MaybeRecordImplicitNullCheck(instruction); 4571 } 4572 4573 if (is_volatile) { 4574 if (field_type == Primitive::kPrimNot) { 4575 // Memory barriers, in the case of references, are also handled 4576 // in the previous switch statement. 4577 } else { 4578 codegen_->GenerateMemoryBarrier(MemBarrierKind::kLoadAny); 4579 } 4580 } 4581} 4582 4583void LocationsBuilderARM::VisitInstanceFieldSet(HInstanceFieldSet* instruction) { 4584 HandleFieldSet(instruction, instruction->GetFieldInfo()); 4585} 4586 4587void InstructionCodeGeneratorARM::VisitInstanceFieldSet(HInstanceFieldSet* instruction) { 4588 HandleFieldSet(instruction, instruction->GetFieldInfo(), instruction->GetValueCanBeNull()); 4589} 4590 4591void LocationsBuilderARM::VisitInstanceFieldGet(HInstanceFieldGet* instruction) { 4592 HandleFieldGet(instruction, instruction->GetFieldInfo()); 4593} 4594 4595void InstructionCodeGeneratorARM::VisitInstanceFieldGet(HInstanceFieldGet* instruction) { 4596 HandleFieldGet(instruction, instruction->GetFieldInfo()); 4597} 4598 4599void LocationsBuilderARM::VisitStaticFieldGet(HStaticFieldGet* instruction) { 4600 HandleFieldGet(instruction, instruction->GetFieldInfo()); 4601} 4602 4603void InstructionCodeGeneratorARM::VisitStaticFieldGet(HStaticFieldGet* instruction) { 4604 HandleFieldGet(instruction, instruction->GetFieldInfo()); 4605} 4606 4607void LocationsBuilderARM::VisitStaticFieldSet(HStaticFieldSet* instruction) { 4608 HandleFieldSet(instruction, instruction->GetFieldInfo()); 4609} 4610 4611void InstructionCodeGeneratorARM::VisitStaticFieldSet(HStaticFieldSet* instruction) { 4612 HandleFieldSet(instruction, instruction->GetFieldInfo(), instruction->GetValueCanBeNull()); 4613} 4614 4615void LocationsBuilderARM::VisitUnresolvedInstanceFieldGet( 4616 HUnresolvedInstanceFieldGet* instruction) { 4617 FieldAccessCallingConventionARM calling_convention; 4618 codegen_->CreateUnresolvedFieldLocationSummary( 4619 instruction, instruction->GetFieldType(), calling_convention); 4620} 4621 4622void InstructionCodeGeneratorARM::VisitUnresolvedInstanceFieldGet( 4623 HUnresolvedInstanceFieldGet* instruction) { 4624 FieldAccessCallingConventionARM calling_convention; 4625 codegen_->GenerateUnresolvedFieldAccess(instruction, 4626 instruction->GetFieldType(), 4627 instruction->GetFieldIndex(), 4628 instruction->GetDexPc(), 4629 calling_convention); 4630} 4631 4632void LocationsBuilderARM::VisitUnresolvedInstanceFieldSet( 4633 HUnresolvedInstanceFieldSet* instruction) { 4634 FieldAccessCallingConventionARM calling_convention; 4635 codegen_->CreateUnresolvedFieldLocationSummary( 4636 instruction, instruction->GetFieldType(), calling_convention); 4637} 4638 4639void InstructionCodeGeneratorARM::VisitUnresolvedInstanceFieldSet( 4640 HUnresolvedInstanceFieldSet* instruction) { 4641 FieldAccessCallingConventionARM calling_convention; 4642 codegen_->GenerateUnresolvedFieldAccess(instruction, 4643 instruction->GetFieldType(), 4644 instruction->GetFieldIndex(), 4645 instruction->GetDexPc(), 4646 calling_convention); 4647} 4648 4649void LocationsBuilderARM::VisitUnresolvedStaticFieldGet( 4650 HUnresolvedStaticFieldGet* instruction) { 4651 FieldAccessCallingConventionARM calling_convention; 4652 codegen_->CreateUnresolvedFieldLocationSummary( 4653 instruction, instruction->GetFieldType(), calling_convention); 4654} 4655 4656void InstructionCodeGeneratorARM::VisitUnresolvedStaticFieldGet( 4657 HUnresolvedStaticFieldGet* instruction) { 4658 FieldAccessCallingConventionARM calling_convention; 4659 codegen_->GenerateUnresolvedFieldAccess(instruction, 4660 instruction->GetFieldType(), 4661 instruction->GetFieldIndex(), 4662 instruction->GetDexPc(), 4663 calling_convention); 4664} 4665 4666void LocationsBuilderARM::VisitUnresolvedStaticFieldSet( 4667 HUnresolvedStaticFieldSet* instruction) { 4668 FieldAccessCallingConventionARM calling_convention; 4669 codegen_->CreateUnresolvedFieldLocationSummary( 4670 instruction, instruction->GetFieldType(), calling_convention); 4671} 4672 4673void InstructionCodeGeneratorARM::VisitUnresolvedStaticFieldSet( 4674 HUnresolvedStaticFieldSet* instruction) { 4675 FieldAccessCallingConventionARM calling_convention; 4676 codegen_->GenerateUnresolvedFieldAccess(instruction, 4677 instruction->GetFieldType(), 4678 instruction->GetFieldIndex(), 4679 instruction->GetDexPc(), 4680 calling_convention); 4681} 4682 4683void LocationsBuilderARM::VisitNullCheck(HNullCheck* instruction) { 4684 LocationSummary* locations = codegen_->CreateThrowingSlowPathLocations(instruction); 4685 locations->SetInAt(0, Location::RequiresRegister()); 4686} 4687 4688void CodeGeneratorARM::GenerateImplicitNullCheck(HNullCheck* instruction) { 4689 if (CanMoveNullCheckToUser(instruction)) { 4690 return; 4691 } 4692 Location obj = instruction->GetLocations()->InAt(0); 4693 4694 __ LoadFromOffset(kLoadWord, IP, obj.AsRegister<Register>(), 0); 4695 RecordPcInfo(instruction, instruction->GetDexPc()); 4696} 4697 4698void CodeGeneratorARM::GenerateExplicitNullCheck(HNullCheck* instruction) { 4699 SlowPathCodeARM* slow_path = new (GetGraph()->GetArena()) NullCheckSlowPathARM(instruction); 4700 AddSlowPath(slow_path); 4701 4702 LocationSummary* locations = instruction->GetLocations(); 4703 Location obj = locations->InAt(0); 4704 4705 __ CompareAndBranchIfZero(obj.AsRegister<Register>(), slow_path->GetEntryLabel()); 4706} 4707 4708void InstructionCodeGeneratorARM::VisitNullCheck(HNullCheck* instruction) { 4709 codegen_->GenerateNullCheck(instruction); 4710} 4711 4712static LoadOperandType GetLoadOperandType(Primitive::Type type) { 4713 switch (type) { 4714 case Primitive::kPrimNot: 4715 return kLoadWord; 4716 case Primitive::kPrimBoolean: 4717 return kLoadUnsignedByte; 4718 case Primitive::kPrimByte: 4719 return kLoadSignedByte; 4720 case Primitive::kPrimChar: 4721 return kLoadUnsignedHalfword; 4722 case Primitive::kPrimShort: 4723 return kLoadSignedHalfword; 4724 case Primitive::kPrimInt: 4725 return kLoadWord; 4726 case Primitive::kPrimLong: 4727 return kLoadWordPair; 4728 case Primitive::kPrimFloat: 4729 return kLoadSWord; 4730 case Primitive::kPrimDouble: 4731 return kLoadDWord; 4732 default: 4733 LOG(FATAL) << "Unreachable type " << type; 4734 UNREACHABLE(); 4735 } 4736} 4737 4738static StoreOperandType GetStoreOperandType(Primitive::Type type) { 4739 switch (type) { 4740 case Primitive::kPrimNot: 4741 return kStoreWord; 4742 case Primitive::kPrimBoolean: 4743 case Primitive::kPrimByte: 4744 return kStoreByte; 4745 case Primitive::kPrimChar: 4746 case Primitive::kPrimShort: 4747 return kStoreHalfword; 4748 case Primitive::kPrimInt: 4749 return kStoreWord; 4750 case Primitive::kPrimLong: 4751 return kStoreWordPair; 4752 case Primitive::kPrimFloat: 4753 return kStoreSWord; 4754 case Primitive::kPrimDouble: 4755 return kStoreDWord; 4756 default: 4757 LOG(FATAL) << "Unreachable type " << type; 4758 UNREACHABLE(); 4759 } 4760} 4761 4762void CodeGeneratorARM::LoadFromShiftedRegOffset(Primitive::Type type, 4763 Location out_loc, 4764 Register base, 4765 Register reg_offset, 4766 Condition cond) { 4767 uint32_t shift_count = Primitive::ComponentSizeShift(type); 4768 Address mem_address(base, reg_offset, Shift::LSL, shift_count); 4769 4770 switch (type) { 4771 case Primitive::kPrimByte: 4772 __ ldrsb(out_loc.AsRegister<Register>(), mem_address, cond); 4773 break; 4774 case Primitive::kPrimBoolean: 4775 __ ldrb(out_loc.AsRegister<Register>(), mem_address, cond); 4776 break; 4777 case Primitive::kPrimShort: 4778 __ ldrsh(out_loc.AsRegister<Register>(), mem_address, cond); 4779 break; 4780 case Primitive::kPrimChar: 4781 __ ldrh(out_loc.AsRegister<Register>(), mem_address, cond); 4782 break; 4783 case Primitive::kPrimNot: 4784 case Primitive::kPrimInt: 4785 __ ldr(out_loc.AsRegister<Register>(), mem_address, cond); 4786 break; 4787 // T32 doesn't support LoadFromShiftedRegOffset mem address mode for these types. 4788 case Primitive::kPrimLong: 4789 case Primitive::kPrimFloat: 4790 case Primitive::kPrimDouble: 4791 default: 4792 LOG(FATAL) << "Unreachable type " << type; 4793 UNREACHABLE(); 4794 } 4795} 4796 4797void CodeGeneratorARM::StoreToShiftedRegOffset(Primitive::Type type, 4798 Location loc, 4799 Register base, 4800 Register reg_offset, 4801 Condition cond) { 4802 uint32_t shift_count = Primitive::ComponentSizeShift(type); 4803 Address mem_address(base, reg_offset, Shift::LSL, shift_count); 4804 4805 switch (type) { 4806 case Primitive::kPrimByte: 4807 case Primitive::kPrimBoolean: 4808 __ strb(loc.AsRegister<Register>(), mem_address, cond); 4809 break; 4810 case Primitive::kPrimShort: 4811 case Primitive::kPrimChar: 4812 __ strh(loc.AsRegister<Register>(), mem_address, cond); 4813 break; 4814 case Primitive::kPrimNot: 4815 case Primitive::kPrimInt: 4816 __ str(loc.AsRegister<Register>(), mem_address, cond); 4817 break; 4818 // T32 doesn't support StoreToShiftedRegOffset mem address mode for these types. 4819 case Primitive::kPrimLong: 4820 case Primitive::kPrimFloat: 4821 case Primitive::kPrimDouble: 4822 default: 4823 LOG(FATAL) << "Unreachable type " << type; 4824 UNREACHABLE(); 4825 } 4826} 4827 4828void LocationsBuilderARM::VisitArrayGet(HArrayGet* instruction) { 4829 bool object_array_get_with_read_barrier = 4830 kEmitCompilerReadBarrier && (instruction->GetType() == Primitive::kPrimNot); 4831 LocationSummary* locations = 4832 new (GetGraph()->GetArena()) LocationSummary(instruction, 4833 object_array_get_with_read_barrier ? 4834 LocationSummary::kCallOnSlowPath : 4835 LocationSummary::kNoCall); 4836 if (object_array_get_with_read_barrier && kUseBakerReadBarrier) { 4837 locations->SetCustomSlowPathCallerSaves(RegisterSet::Empty()); // No caller-save registers. 4838 } 4839 locations->SetInAt(0, Location::RequiresRegister()); 4840 locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1))); 4841 if (Primitive::IsFloatingPointType(instruction->GetType())) { 4842 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); 4843 } else { 4844 // The output overlaps in the case of an object array get with 4845 // read barriers enabled: we do not want the move to overwrite the 4846 // array's location, as we need it to emit the read barrier. 4847 locations->SetOut( 4848 Location::RequiresRegister(), 4849 object_array_get_with_read_barrier ? Location::kOutputOverlap : Location::kNoOutputOverlap); 4850 } 4851 // We need a temporary register for the read barrier marking slow 4852 // path in CodeGeneratorARM::GenerateArrayLoadWithBakerReadBarrier. 4853 // Also need for String compression feature. 4854 if ((object_array_get_with_read_barrier && kUseBakerReadBarrier) 4855 || (mirror::kUseStringCompression && instruction->IsStringCharAt())) { 4856 locations->AddTemp(Location::RequiresRegister()); 4857 } 4858} 4859 4860void InstructionCodeGeneratorARM::VisitArrayGet(HArrayGet* instruction) { 4861 LocationSummary* locations = instruction->GetLocations(); 4862 Location obj_loc = locations->InAt(0); 4863 Register obj = obj_loc.AsRegister<Register>(); 4864 Location index = locations->InAt(1); 4865 Location out_loc = locations->Out(); 4866 uint32_t data_offset = CodeGenerator::GetArrayDataOffset(instruction); 4867 Primitive::Type type = instruction->GetType(); 4868 const bool maybe_compressed_char_at = mirror::kUseStringCompression && 4869 instruction->IsStringCharAt(); 4870 HInstruction* array_instr = instruction->GetArray(); 4871 bool has_intermediate_address = array_instr->IsIntermediateAddress(); 4872 4873 switch (type) { 4874 case Primitive::kPrimBoolean: 4875 case Primitive::kPrimByte: 4876 case Primitive::kPrimShort: 4877 case Primitive::kPrimChar: 4878 case Primitive::kPrimInt: { 4879 Register length; 4880 if (maybe_compressed_char_at) { 4881 length = locations->GetTemp(0).AsRegister<Register>(); 4882 uint32_t count_offset = mirror::String::CountOffset().Uint32Value(); 4883 __ LoadFromOffset(kLoadWord, length, obj, count_offset); 4884 codegen_->MaybeRecordImplicitNullCheck(instruction); 4885 } 4886 if (index.IsConstant()) { 4887 int32_t const_index = index.GetConstant()->AsIntConstant()->GetValue(); 4888 if (maybe_compressed_char_at) { 4889 Label uncompressed_load, done; 4890 __ Lsrs(length, length, 1u); // LSRS has a 16-bit encoding, TST (immediate) does not. 4891 static_assert(static_cast<uint32_t>(mirror::StringCompressionFlag::kCompressed) == 0u, 4892 "Expecting 0=compressed, 1=uncompressed"); 4893 __ b(&uncompressed_load, CS); 4894 __ LoadFromOffset(kLoadUnsignedByte, 4895 out_loc.AsRegister<Register>(), 4896 obj, 4897 data_offset + const_index); 4898 __ b(&done); 4899 __ Bind(&uncompressed_load); 4900 __ LoadFromOffset(GetLoadOperandType(Primitive::kPrimChar), 4901 out_loc.AsRegister<Register>(), 4902 obj, 4903 data_offset + (const_index << 1)); 4904 __ Bind(&done); 4905 } else { 4906 uint32_t full_offset = data_offset + (const_index << Primitive::ComponentSizeShift(type)); 4907 4908 LoadOperandType load_type = GetLoadOperandType(type); 4909 __ LoadFromOffset(load_type, out_loc.AsRegister<Register>(), obj, full_offset); 4910 } 4911 } else { 4912 Register temp = IP; 4913 4914 if (has_intermediate_address) { 4915 // We do not need to compute the intermediate address from the array: the 4916 // input instruction has done it already. See the comment in 4917 // `TryExtractArrayAccessAddress()`. 4918 if (kIsDebugBuild) { 4919 HIntermediateAddress* tmp = array_instr->AsIntermediateAddress(); 4920 DCHECK_EQ(tmp->GetOffset()->AsIntConstant()->GetValueAsUint64(), data_offset); 4921 } 4922 temp = obj; 4923 } else { 4924 __ add(temp, obj, ShifterOperand(data_offset)); 4925 } 4926 if (maybe_compressed_char_at) { 4927 Label uncompressed_load, done; 4928 __ Lsrs(length, length, 1u); // LSRS has a 16-bit encoding, TST (immediate) does not. 4929 static_assert(static_cast<uint32_t>(mirror::StringCompressionFlag::kCompressed) == 0u, 4930 "Expecting 0=compressed, 1=uncompressed"); 4931 __ b(&uncompressed_load, CS); 4932 __ ldrb(out_loc.AsRegister<Register>(), 4933 Address(temp, index.AsRegister<Register>(), Shift::LSL, 0)); 4934 __ b(&done); 4935 __ Bind(&uncompressed_load); 4936 __ ldrh(out_loc.AsRegister<Register>(), 4937 Address(temp, index.AsRegister<Register>(), Shift::LSL, 1)); 4938 __ Bind(&done); 4939 } else { 4940 codegen_->LoadFromShiftedRegOffset(type, out_loc, temp, index.AsRegister<Register>()); 4941 } 4942 } 4943 break; 4944 } 4945 4946 case Primitive::kPrimNot: { 4947 // The read barrier instrumentation of object ArrayGet 4948 // instructions does not support the HIntermediateAddress 4949 // instruction. 4950 DCHECK(!(has_intermediate_address && kEmitCompilerReadBarrier)); 4951 4952 static_assert( 4953 sizeof(mirror::HeapReference<mirror::Object>) == sizeof(int32_t), 4954 "art::mirror::HeapReference<art::mirror::Object> and int32_t have different sizes."); 4955 // /* HeapReference<Object> */ out = 4956 // *(obj + data_offset + index * sizeof(HeapReference<Object>)) 4957 if (kEmitCompilerReadBarrier && kUseBakerReadBarrier) { 4958 Location temp = locations->GetTemp(0); 4959 // Note that a potential implicit null check is handled in this 4960 // CodeGeneratorARM::GenerateArrayLoadWithBakerReadBarrier call. 4961 codegen_->GenerateArrayLoadWithBakerReadBarrier( 4962 instruction, out_loc, obj, data_offset, index, temp, /* needs_null_check */ true); 4963 } else { 4964 Register out = out_loc.AsRegister<Register>(); 4965 if (index.IsConstant()) { 4966 size_t offset = 4967 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset; 4968 __ LoadFromOffset(kLoadWord, out, obj, offset); 4969 codegen_->MaybeRecordImplicitNullCheck(instruction); 4970 // If read barriers are enabled, emit read barriers other than 4971 // Baker's using a slow path (and also unpoison the loaded 4972 // reference, if heap poisoning is enabled). 4973 codegen_->MaybeGenerateReadBarrierSlow(instruction, out_loc, out_loc, obj_loc, offset); 4974 } else { 4975 Register temp = IP; 4976 4977 if (has_intermediate_address) { 4978 // We do not need to compute the intermediate address from the array: the 4979 // input instruction has done it already. See the comment in 4980 // `TryExtractArrayAccessAddress()`. 4981 if (kIsDebugBuild) { 4982 HIntermediateAddress* tmp = array_instr->AsIntermediateAddress(); 4983 DCHECK_EQ(tmp->GetOffset()->AsIntConstant()->GetValueAsUint64(), data_offset); 4984 } 4985 temp = obj; 4986 } else { 4987 __ add(temp, obj, ShifterOperand(data_offset)); 4988 } 4989 codegen_->LoadFromShiftedRegOffset(type, out_loc, temp, index.AsRegister<Register>()); 4990 4991 codegen_->MaybeRecordImplicitNullCheck(instruction); 4992 // If read barriers are enabled, emit read barriers other than 4993 // Baker's using a slow path (and also unpoison the loaded 4994 // reference, if heap poisoning is enabled). 4995 codegen_->MaybeGenerateReadBarrierSlow( 4996 instruction, out_loc, out_loc, obj_loc, data_offset, index); 4997 } 4998 } 4999 break; 5000 } 5001 5002 case Primitive::kPrimLong: { 5003 if (index.IsConstant()) { 5004 size_t offset = 5005 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset; 5006 __ LoadFromOffset(kLoadWordPair, out_loc.AsRegisterPairLow<Register>(), obj, offset); 5007 } else { 5008 __ add(IP, obj, ShifterOperand(index.AsRegister<Register>(), LSL, TIMES_8)); 5009 __ LoadFromOffset(kLoadWordPair, out_loc.AsRegisterPairLow<Register>(), IP, data_offset); 5010 } 5011 break; 5012 } 5013 5014 case Primitive::kPrimFloat: { 5015 SRegister out = out_loc.AsFpuRegister<SRegister>(); 5016 if (index.IsConstant()) { 5017 size_t offset = (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset; 5018 __ LoadSFromOffset(out, obj, offset); 5019 } else { 5020 __ add(IP, obj, ShifterOperand(index.AsRegister<Register>(), LSL, TIMES_4)); 5021 __ LoadSFromOffset(out, IP, data_offset); 5022 } 5023 break; 5024 } 5025 5026 case Primitive::kPrimDouble: { 5027 SRegister out = out_loc.AsFpuRegisterPairLow<SRegister>(); 5028 if (index.IsConstant()) { 5029 size_t offset = (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset; 5030 __ LoadDFromOffset(FromLowSToD(out), obj, offset); 5031 } else { 5032 __ add(IP, obj, ShifterOperand(index.AsRegister<Register>(), LSL, TIMES_8)); 5033 __ LoadDFromOffset(FromLowSToD(out), IP, data_offset); 5034 } 5035 break; 5036 } 5037 5038 case Primitive::kPrimVoid: 5039 LOG(FATAL) << "Unreachable type " << type; 5040 UNREACHABLE(); 5041 } 5042 5043 if (type == Primitive::kPrimNot) { 5044 // Potential implicit null checks, in the case of reference 5045 // arrays, are handled in the previous switch statement. 5046 } else if (!maybe_compressed_char_at) { 5047 codegen_->MaybeRecordImplicitNullCheck(instruction); 5048 } 5049} 5050 5051void LocationsBuilderARM::VisitArraySet(HArraySet* instruction) { 5052 Primitive::Type value_type = instruction->GetComponentType(); 5053 5054 bool needs_write_barrier = 5055 CodeGenerator::StoreNeedsWriteBarrier(value_type, instruction->GetValue()); 5056 bool may_need_runtime_call_for_type_check = instruction->NeedsTypeCheck(); 5057 5058 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary( 5059 instruction, 5060 may_need_runtime_call_for_type_check ? 5061 LocationSummary::kCallOnSlowPath : 5062 LocationSummary::kNoCall); 5063 5064 locations->SetInAt(0, Location::RequiresRegister()); 5065 locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1))); 5066 if (Primitive::IsFloatingPointType(value_type)) { 5067 locations->SetInAt(2, Location::RequiresFpuRegister()); 5068 } else { 5069 locations->SetInAt(2, Location::RequiresRegister()); 5070 } 5071 if (needs_write_barrier) { 5072 // Temporary registers for the write barrier. 5073 locations->AddTemp(Location::RequiresRegister()); // Possibly used for ref. poisoning too. 5074 locations->AddTemp(Location::RequiresRegister()); 5075 } 5076} 5077 5078void InstructionCodeGeneratorARM::VisitArraySet(HArraySet* instruction) { 5079 LocationSummary* locations = instruction->GetLocations(); 5080 Location array_loc = locations->InAt(0); 5081 Register array = array_loc.AsRegister<Register>(); 5082 Location index = locations->InAt(1); 5083 Primitive::Type value_type = instruction->GetComponentType(); 5084 bool may_need_runtime_call_for_type_check = instruction->NeedsTypeCheck(); 5085 bool needs_write_barrier = 5086 CodeGenerator::StoreNeedsWriteBarrier(value_type, instruction->GetValue()); 5087 uint32_t data_offset = 5088 mirror::Array::DataOffset(Primitive::ComponentSize(value_type)).Uint32Value(); 5089 Location value_loc = locations->InAt(2); 5090 HInstruction* array_instr = instruction->GetArray(); 5091 bool has_intermediate_address = array_instr->IsIntermediateAddress(); 5092 5093 switch (value_type) { 5094 case Primitive::kPrimBoolean: 5095 case Primitive::kPrimByte: 5096 case Primitive::kPrimShort: 5097 case Primitive::kPrimChar: 5098 case Primitive::kPrimInt: { 5099 if (index.IsConstant()) { 5100 int32_t const_index = index.GetConstant()->AsIntConstant()->GetValue(); 5101 uint32_t full_offset = 5102 data_offset + (const_index << Primitive::ComponentSizeShift(value_type)); 5103 StoreOperandType store_type = GetStoreOperandType(value_type); 5104 __ StoreToOffset(store_type, value_loc.AsRegister<Register>(), array, full_offset); 5105 } else { 5106 Register temp = IP; 5107 5108 if (has_intermediate_address) { 5109 // We do not need to compute the intermediate address from the array: the 5110 // input instruction has done it already. See the comment in 5111 // `TryExtractArrayAccessAddress()`. 5112 if (kIsDebugBuild) { 5113 HIntermediateAddress* tmp = array_instr->AsIntermediateAddress(); 5114 DCHECK(tmp->GetOffset()->AsIntConstant()->GetValueAsUint64() == data_offset); 5115 } 5116 temp = array; 5117 } else { 5118 __ add(temp, array, ShifterOperand(data_offset)); 5119 } 5120 codegen_->StoreToShiftedRegOffset(value_type, 5121 value_loc, 5122 temp, 5123 index.AsRegister<Register>()); 5124 } 5125 break; 5126 } 5127 5128 case Primitive::kPrimNot: { 5129 Register value = value_loc.AsRegister<Register>(); 5130 // TryExtractArrayAccessAddress optimization is never applied for non-primitive ArraySet. 5131 // See the comment in instruction_simplifier_shared.cc. 5132 DCHECK(!has_intermediate_address); 5133 5134 if (instruction->InputAt(2)->IsNullConstant()) { 5135 // Just setting null. 5136 if (index.IsConstant()) { 5137 size_t offset = 5138 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset; 5139 __ StoreToOffset(kStoreWord, value, array, offset); 5140 } else { 5141 DCHECK(index.IsRegister()) << index; 5142 __ add(IP, array, ShifterOperand(data_offset)); 5143 codegen_->StoreToShiftedRegOffset(value_type, 5144 value_loc, 5145 IP, 5146 index.AsRegister<Register>()); 5147 } 5148 codegen_->MaybeRecordImplicitNullCheck(instruction); 5149 DCHECK(!needs_write_barrier); 5150 DCHECK(!may_need_runtime_call_for_type_check); 5151 break; 5152 } 5153 5154 DCHECK(needs_write_barrier); 5155 Location temp1_loc = locations->GetTemp(0); 5156 Register temp1 = temp1_loc.AsRegister<Register>(); 5157 Location temp2_loc = locations->GetTemp(1); 5158 Register temp2 = temp2_loc.AsRegister<Register>(); 5159 uint32_t class_offset = mirror::Object::ClassOffset().Int32Value(); 5160 uint32_t super_offset = mirror::Class::SuperClassOffset().Int32Value(); 5161 uint32_t component_offset = mirror::Class::ComponentTypeOffset().Int32Value(); 5162 Label done; 5163 SlowPathCodeARM* slow_path = nullptr; 5164 5165 if (may_need_runtime_call_for_type_check) { 5166 slow_path = new (GetGraph()->GetArena()) ArraySetSlowPathARM(instruction); 5167 codegen_->AddSlowPath(slow_path); 5168 if (instruction->GetValueCanBeNull()) { 5169 Label non_zero; 5170 __ CompareAndBranchIfNonZero(value, &non_zero); 5171 if (index.IsConstant()) { 5172 size_t offset = 5173 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset; 5174 __ StoreToOffset(kStoreWord, value, array, offset); 5175 } else { 5176 DCHECK(index.IsRegister()) << index; 5177 __ add(IP, array, ShifterOperand(data_offset)); 5178 codegen_->StoreToShiftedRegOffset(value_type, 5179 value_loc, 5180 IP, 5181 index.AsRegister<Register>()); 5182 } 5183 codegen_->MaybeRecordImplicitNullCheck(instruction); 5184 __ b(&done); 5185 __ Bind(&non_zero); 5186 } 5187 5188 // Note that when read barriers are enabled, the type checks 5189 // are performed without read barriers. This is fine, even in 5190 // the case where a class object is in the from-space after 5191 // the flip, as a comparison involving such a type would not 5192 // produce a false positive; it may of course produce a false 5193 // negative, in which case we would take the ArraySet slow 5194 // path. 5195 5196 // /* HeapReference<Class> */ temp1 = array->klass_ 5197 __ LoadFromOffset(kLoadWord, temp1, array, class_offset); 5198 codegen_->MaybeRecordImplicitNullCheck(instruction); 5199 __ MaybeUnpoisonHeapReference(temp1); 5200 5201 // /* HeapReference<Class> */ temp1 = temp1->component_type_ 5202 __ LoadFromOffset(kLoadWord, temp1, temp1, component_offset); 5203 // /* HeapReference<Class> */ temp2 = value->klass_ 5204 __ LoadFromOffset(kLoadWord, temp2, value, class_offset); 5205 // If heap poisoning is enabled, no need to unpoison `temp1` 5206 // nor `temp2`, as we are comparing two poisoned references. 5207 __ cmp(temp1, ShifterOperand(temp2)); 5208 5209 if (instruction->StaticTypeOfArrayIsObjectArray()) { 5210 Label do_put; 5211 __ b(&do_put, EQ); 5212 // If heap poisoning is enabled, the `temp1` reference has 5213 // not been unpoisoned yet; unpoison it now. 5214 __ MaybeUnpoisonHeapReference(temp1); 5215 5216 // /* HeapReference<Class> */ temp1 = temp1->super_class_ 5217 __ LoadFromOffset(kLoadWord, temp1, temp1, super_offset); 5218 // If heap poisoning is enabled, no need to unpoison 5219 // `temp1`, as we are comparing against null below. 5220 __ CompareAndBranchIfNonZero(temp1, slow_path->GetEntryLabel()); 5221 __ Bind(&do_put); 5222 } else { 5223 __ b(slow_path->GetEntryLabel(), NE); 5224 } 5225 } 5226 5227 Register source = value; 5228 if (kPoisonHeapReferences) { 5229 // Note that in the case where `value` is a null reference, 5230 // we do not enter this block, as a null reference does not 5231 // need poisoning. 5232 DCHECK_EQ(value_type, Primitive::kPrimNot); 5233 __ Mov(temp1, value); 5234 __ PoisonHeapReference(temp1); 5235 source = temp1; 5236 } 5237 5238 if (index.IsConstant()) { 5239 size_t offset = 5240 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset; 5241 __ StoreToOffset(kStoreWord, source, array, offset); 5242 } else { 5243 DCHECK(index.IsRegister()) << index; 5244 5245 __ add(IP, array, ShifterOperand(data_offset)); 5246 codegen_->StoreToShiftedRegOffset(value_type, 5247 Location::RegisterLocation(source), 5248 IP, 5249 index.AsRegister<Register>()); 5250 } 5251 5252 if (!may_need_runtime_call_for_type_check) { 5253 codegen_->MaybeRecordImplicitNullCheck(instruction); 5254 } 5255 5256 codegen_->MarkGCCard(temp1, temp2, array, value, instruction->GetValueCanBeNull()); 5257 5258 if (done.IsLinked()) { 5259 __ Bind(&done); 5260 } 5261 5262 if (slow_path != nullptr) { 5263 __ Bind(slow_path->GetExitLabel()); 5264 } 5265 5266 break; 5267 } 5268 5269 case Primitive::kPrimLong: { 5270 Location value = locations->InAt(2); 5271 if (index.IsConstant()) { 5272 size_t offset = 5273 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset; 5274 __ StoreToOffset(kStoreWordPair, value.AsRegisterPairLow<Register>(), array, offset); 5275 } else { 5276 __ add(IP, array, ShifterOperand(index.AsRegister<Register>(), LSL, TIMES_8)); 5277 __ StoreToOffset(kStoreWordPair, value.AsRegisterPairLow<Register>(), IP, data_offset); 5278 } 5279 break; 5280 } 5281 5282 case Primitive::kPrimFloat: { 5283 Location value = locations->InAt(2); 5284 DCHECK(value.IsFpuRegister()); 5285 if (index.IsConstant()) { 5286 size_t offset = (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset; 5287 __ StoreSToOffset(value.AsFpuRegister<SRegister>(), array, offset); 5288 } else { 5289 __ add(IP, array, ShifterOperand(index.AsRegister<Register>(), LSL, TIMES_4)); 5290 __ StoreSToOffset(value.AsFpuRegister<SRegister>(), IP, data_offset); 5291 } 5292 break; 5293 } 5294 5295 case Primitive::kPrimDouble: { 5296 Location value = locations->InAt(2); 5297 DCHECK(value.IsFpuRegisterPair()); 5298 if (index.IsConstant()) { 5299 size_t offset = (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset; 5300 __ StoreDToOffset(FromLowSToD(value.AsFpuRegisterPairLow<SRegister>()), array, offset); 5301 } else { 5302 __ add(IP, array, ShifterOperand(index.AsRegister<Register>(), LSL, TIMES_8)); 5303 __ StoreDToOffset(FromLowSToD(value.AsFpuRegisterPairLow<SRegister>()), IP, data_offset); 5304 } 5305 5306 break; 5307 } 5308 5309 case Primitive::kPrimVoid: 5310 LOG(FATAL) << "Unreachable type " << value_type; 5311 UNREACHABLE(); 5312 } 5313 5314 // Objects are handled in the switch. 5315 if (value_type != Primitive::kPrimNot) { 5316 codegen_->MaybeRecordImplicitNullCheck(instruction); 5317 } 5318} 5319 5320void LocationsBuilderARM::VisitArrayLength(HArrayLength* instruction) { 5321 LocationSummary* locations = 5322 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall); 5323 locations->SetInAt(0, Location::RequiresRegister()); 5324 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 5325} 5326 5327void InstructionCodeGeneratorARM::VisitArrayLength(HArrayLength* instruction) { 5328 LocationSummary* locations = instruction->GetLocations(); 5329 uint32_t offset = CodeGenerator::GetArrayLengthOffset(instruction); 5330 Register obj = locations->InAt(0).AsRegister<Register>(); 5331 Register out = locations->Out().AsRegister<Register>(); 5332 __ LoadFromOffset(kLoadWord, out, obj, offset); 5333 codegen_->MaybeRecordImplicitNullCheck(instruction); 5334 // Mask out compression flag from String's array length. 5335 if (mirror::kUseStringCompression && instruction->IsStringLength()) { 5336 __ Lsr(out, out, 1u); 5337 } 5338} 5339 5340void LocationsBuilderARM::VisitIntermediateAddress(HIntermediateAddress* instruction) { 5341 LocationSummary* locations = 5342 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall); 5343 5344 locations->SetInAt(0, Location::RequiresRegister()); 5345 locations->SetInAt(1, Location::RegisterOrConstant(instruction->GetOffset())); 5346 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 5347} 5348 5349void InstructionCodeGeneratorARM::VisitIntermediateAddress(HIntermediateAddress* instruction) { 5350 LocationSummary* locations = instruction->GetLocations(); 5351 Location out = locations->Out(); 5352 Location first = locations->InAt(0); 5353 Location second = locations->InAt(1); 5354 5355 if (second.IsRegister()) { 5356 __ add(out.AsRegister<Register>(), 5357 first.AsRegister<Register>(), 5358 ShifterOperand(second.AsRegister<Register>())); 5359 } else { 5360 __ AddConstant(out.AsRegister<Register>(), 5361 first.AsRegister<Register>(), 5362 second.GetConstant()->AsIntConstant()->GetValue()); 5363 } 5364} 5365 5366void LocationsBuilderARM::VisitBoundsCheck(HBoundsCheck* instruction) { 5367 RegisterSet caller_saves = RegisterSet::Empty(); 5368 InvokeRuntimeCallingConvention calling_convention; 5369 caller_saves.Add(Location::RegisterLocation(calling_convention.GetRegisterAt(0))); 5370 caller_saves.Add(Location::RegisterLocation(calling_convention.GetRegisterAt(1))); 5371 LocationSummary* locations = codegen_->CreateThrowingSlowPathLocations(instruction, caller_saves); 5372 locations->SetInAt(0, Location::RequiresRegister()); 5373 locations->SetInAt(1, Location::RequiresRegister()); 5374} 5375 5376void InstructionCodeGeneratorARM::VisitBoundsCheck(HBoundsCheck* instruction) { 5377 LocationSummary* locations = instruction->GetLocations(); 5378 SlowPathCodeARM* slow_path = 5379 new (GetGraph()->GetArena()) BoundsCheckSlowPathARM(instruction); 5380 codegen_->AddSlowPath(slow_path); 5381 5382 Register index = locations->InAt(0).AsRegister<Register>(); 5383 Register length = locations->InAt(1).AsRegister<Register>(); 5384 5385 __ cmp(index, ShifterOperand(length)); 5386 __ b(slow_path->GetEntryLabel(), HS); 5387} 5388 5389void CodeGeneratorARM::MarkGCCard(Register temp, 5390 Register card, 5391 Register object, 5392 Register value, 5393 bool can_be_null) { 5394 Label is_null; 5395 if (can_be_null) { 5396 __ CompareAndBranchIfZero(value, &is_null); 5397 } 5398 __ LoadFromOffset(kLoadWord, card, TR, Thread::CardTableOffset<kArmPointerSize>().Int32Value()); 5399 __ Lsr(temp, object, gc::accounting::CardTable::kCardShift); 5400 __ strb(card, Address(card, temp)); 5401 if (can_be_null) { 5402 __ Bind(&is_null); 5403 } 5404} 5405 5406void LocationsBuilderARM::VisitParallelMove(HParallelMove* instruction ATTRIBUTE_UNUSED) { 5407 LOG(FATAL) << "Unreachable"; 5408} 5409 5410void InstructionCodeGeneratorARM::VisitParallelMove(HParallelMove* instruction) { 5411 codegen_->GetMoveResolver()->EmitNativeCode(instruction); 5412} 5413 5414void LocationsBuilderARM::VisitSuspendCheck(HSuspendCheck* instruction) { 5415 LocationSummary* locations = 5416 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kCallOnSlowPath); 5417 locations->SetCustomSlowPathCallerSaves(RegisterSet::Empty()); // No caller-save registers. 5418} 5419 5420void InstructionCodeGeneratorARM::VisitSuspendCheck(HSuspendCheck* instruction) { 5421 HBasicBlock* block = instruction->GetBlock(); 5422 if (block->GetLoopInformation() != nullptr) { 5423 DCHECK(block->GetLoopInformation()->GetSuspendCheck() == instruction); 5424 // The back edge will generate the suspend check. 5425 return; 5426 } 5427 if (block->IsEntryBlock() && instruction->GetNext()->IsGoto()) { 5428 // The goto will generate the suspend check. 5429 return; 5430 } 5431 GenerateSuspendCheck(instruction, nullptr); 5432} 5433 5434void InstructionCodeGeneratorARM::GenerateSuspendCheck(HSuspendCheck* instruction, 5435 HBasicBlock* successor) { 5436 SuspendCheckSlowPathARM* slow_path = 5437 down_cast<SuspendCheckSlowPathARM*>(instruction->GetSlowPath()); 5438 if (slow_path == nullptr) { 5439 slow_path = new (GetGraph()->GetArena()) SuspendCheckSlowPathARM(instruction, successor); 5440 instruction->SetSlowPath(slow_path); 5441 codegen_->AddSlowPath(slow_path); 5442 if (successor != nullptr) { 5443 DCHECK(successor->IsLoopHeader()); 5444 codegen_->ClearSpillSlotsFromLoopPhisInStackMap(instruction); 5445 } 5446 } else { 5447 DCHECK_EQ(slow_path->GetSuccessor(), successor); 5448 } 5449 5450 __ LoadFromOffset( 5451 kLoadUnsignedHalfword, IP, TR, Thread::ThreadFlagsOffset<kArmPointerSize>().Int32Value()); 5452 if (successor == nullptr) { 5453 __ CompareAndBranchIfNonZero(IP, slow_path->GetEntryLabel()); 5454 __ Bind(slow_path->GetReturnLabel()); 5455 } else { 5456 __ CompareAndBranchIfZero(IP, codegen_->GetLabelOf(successor)); 5457 __ b(slow_path->GetEntryLabel()); 5458 } 5459} 5460 5461ArmAssembler* ParallelMoveResolverARM::GetAssembler() const { 5462 return codegen_->GetAssembler(); 5463} 5464 5465void ParallelMoveResolverARM::EmitMove(size_t index) { 5466 MoveOperands* move = moves_[index]; 5467 Location source = move->GetSource(); 5468 Location destination = move->GetDestination(); 5469 5470 if (source.IsRegister()) { 5471 if (destination.IsRegister()) { 5472 __ Mov(destination.AsRegister<Register>(), source.AsRegister<Register>()); 5473 } else if (destination.IsFpuRegister()) { 5474 __ vmovsr(destination.AsFpuRegister<SRegister>(), source.AsRegister<Register>()); 5475 } else { 5476 DCHECK(destination.IsStackSlot()); 5477 __ StoreToOffset(kStoreWord, source.AsRegister<Register>(), 5478 SP, destination.GetStackIndex()); 5479 } 5480 } else if (source.IsStackSlot()) { 5481 if (destination.IsRegister()) { 5482 __ LoadFromOffset(kLoadWord, destination.AsRegister<Register>(), 5483 SP, source.GetStackIndex()); 5484 } else if (destination.IsFpuRegister()) { 5485 __ LoadSFromOffset(destination.AsFpuRegister<SRegister>(), SP, source.GetStackIndex()); 5486 } else { 5487 DCHECK(destination.IsStackSlot()); 5488 __ LoadFromOffset(kLoadWord, IP, SP, source.GetStackIndex()); 5489 __ StoreToOffset(kStoreWord, IP, SP, destination.GetStackIndex()); 5490 } 5491 } else if (source.IsFpuRegister()) { 5492 if (destination.IsRegister()) { 5493 __ vmovrs(destination.AsRegister<Register>(), source.AsFpuRegister<SRegister>()); 5494 } else if (destination.IsFpuRegister()) { 5495 __ vmovs(destination.AsFpuRegister<SRegister>(), source.AsFpuRegister<SRegister>()); 5496 } else { 5497 DCHECK(destination.IsStackSlot()); 5498 __ StoreSToOffset(source.AsFpuRegister<SRegister>(), SP, destination.GetStackIndex()); 5499 } 5500 } else if (source.IsDoubleStackSlot()) { 5501 if (destination.IsDoubleStackSlot()) { 5502 __ LoadDFromOffset(DTMP, SP, source.GetStackIndex()); 5503 __ StoreDToOffset(DTMP, SP, destination.GetStackIndex()); 5504 } else if (destination.IsRegisterPair()) { 5505 DCHECK(ExpectedPairLayout(destination)); 5506 __ LoadFromOffset( 5507 kLoadWordPair, destination.AsRegisterPairLow<Register>(), SP, source.GetStackIndex()); 5508 } else { 5509 DCHECK(destination.IsFpuRegisterPair()) << destination; 5510 __ LoadDFromOffset(FromLowSToD(destination.AsFpuRegisterPairLow<SRegister>()), 5511 SP, 5512 source.GetStackIndex()); 5513 } 5514 } else if (source.IsRegisterPair()) { 5515 if (destination.IsRegisterPair()) { 5516 __ Mov(destination.AsRegisterPairLow<Register>(), source.AsRegisterPairLow<Register>()); 5517 __ Mov(destination.AsRegisterPairHigh<Register>(), source.AsRegisterPairHigh<Register>()); 5518 } else if (destination.IsFpuRegisterPair()) { 5519 __ vmovdrr(FromLowSToD(destination.AsFpuRegisterPairLow<SRegister>()), 5520 source.AsRegisterPairLow<Register>(), 5521 source.AsRegisterPairHigh<Register>()); 5522 } else { 5523 DCHECK(destination.IsDoubleStackSlot()) << destination; 5524 DCHECK(ExpectedPairLayout(source)); 5525 __ StoreToOffset( 5526 kStoreWordPair, source.AsRegisterPairLow<Register>(), SP, destination.GetStackIndex()); 5527 } 5528 } else if (source.IsFpuRegisterPair()) { 5529 if (destination.IsRegisterPair()) { 5530 __ vmovrrd(destination.AsRegisterPairLow<Register>(), 5531 destination.AsRegisterPairHigh<Register>(), 5532 FromLowSToD(source.AsFpuRegisterPairLow<SRegister>())); 5533 } else if (destination.IsFpuRegisterPair()) { 5534 __ vmovd(FromLowSToD(destination.AsFpuRegisterPairLow<SRegister>()), 5535 FromLowSToD(source.AsFpuRegisterPairLow<SRegister>())); 5536 } else { 5537 DCHECK(destination.IsDoubleStackSlot()) << destination; 5538 __ StoreDToOffset(FromLowSToD(source.AsFpuRegisterPairLow<SRegister>()), 5539 SP, 5540 destination.GetStackIndex()); 5541 } 5542 } else { 5543 DCHECK(source.IsConstant()) << source; 5544 HConstant* constant = source.GetConstant(); 5545 if (constant->IsIntConstant() || constant->IsNullConstant()) { 5546 int32_t value = CodeGenerator::GetInt32ValueOf(constant); 5547 if (destination.IsRegister()) { 5548 __ LoadImmediate(destination.AsRegister<Register>(), value); 5549 } else { 5550 DCHECK(destination.IsStackSlot()); 5551 __ LoadImmediate(IP, value); 5552 __ StoreToOffset(kStoreWord, IP, SP, destination.GetStackIndex()); 5553 } 5554 } else if (constant->IsLongConstant()) { 5555 int64_t value = constant->AsLongConstant()->GetValue(); 5556 if (destination.IsRegisterPair()) { 5557 __ LoadImmediate(destination.AsRegisterPairLow<Register>(), Low32Bits(value)); 5558 __ LoadImmediate(destination.AsRegisterPairHigh<Register>(), High32Bits(value)); 5559 } else { 5560 DCHECK(destination.IsDoubleStackSlot()) << destination; 5561 __ LoadImmediate(IP, Low32Bits(value)); 5562 __ StoreToOffset(kStoreWord, IP, SP, destination.GetStackIndex()); 5563 __ LoadImmediate(IP, High32Bits(value)); 5564 __ StoreToOffset(kStoreWord, IP, SP, destination.GetHighStackIndex(kArmWordSize)); 5565 } 5566 } else if (constant->IsDoubleConstant()) { 5567 double value = constant->AsDoubleConstant()->GetValue(); 5568 if (destination.IsFpuRegisterPair()) { 5569 __ LoadDImmediate(FromLowSToD(destination.AsFpuRegisterPairLow<SRegister>()), value); 5570 } else { 5571 DCHECK(destination.IsDoubleStackSlot()) << destination; 5572 uint64_t int_value = bit_cast<uint64_t, double>(value); 5573 __ LoadImmediate(IP, Low32Bits(int_value)); 5574 __ StoreToOffset(kStoreWord, IP, SP, destination.GetStackIndex()); 5575 __ LoadImmediate(IP, High32Bits(int_value)); 5576 __ StoreToOffset(kStoreWord, IP, SP, destination.GetHighStackIndex(kArmWordSize)); 5577 } 5578 } else { 5579 DCHECK(constant->IsFloatConstant()) << constant->DebugName(); 5580 float value = constant->AsFloatConstant()->GetValue(); 5581 if (destination.IsFpuRegister()) { 5582 __ LoadSImmediate(destination.AsFpuRegister<SRegister>(), value); 5583 } else { 5584 DCHECK(destination.IsStackSlot()); 5585 __ LoadImmediate(IP, bit_cast<int32_t, float>(value)); 5586 __ StoreToOffset(kStoreWord, IP, SP, destination.GetStackIndex()); 5587 } 5588 } 5589 } 5590} 5591 5592void ParallelMoveResolverARM::Exchange(Register reg, int mem) { 5593 __ Mov(IP, reg); 5594 __ LoadFromOffset(kLoadWord, reg, SP, mem); 5595 __ StoreToOffset(kStoreWord, IP, SP, mem); 5596} 5597 5598void ParallelMoveResolverARM::Exchange(int mem1, int mem2) { 5599 ScratchRegisterScope ensure_scratch(this, IP, R0, codegen_->GetNumberOfCoreRegisters()); 5600 int stack_offset = ensure_scratch.IsSpilled() ? kArmWordSize : 0; 5601 __ LoadFromOffset(kLoadWord, static_cast<Register>(ensure_scratch.GetRegister()), 5602 SP, mem1 + stack_offset); 5603 __ LoadFromOffset(kLoadWord, IP, SP, mem2 + stack_offset); 5604 __ StoreToOffset(kStoreWord, static_cast<Register>(ensure_scratch.GetRegister()), 5605 SP, mem2 + stack_offset); 5606 __ StoreToOffset(kStoreWord, IP, SP, mem1 + stack_offset); 5607} 5608 5609void ParallelMoveResolverARM::EmitSwap(size_t index) { 5610 MoveOperands* move = moves_[index]; 5611 Location source = move->GetSource(); 5612 Location destination = move->GetDestination(); 5613 5614 if (source.IsRegister() && destination.IsRegister()) { 5615 DCHECK_NE(source.AsRegister<Register>(), IP); 5616 DCHECK_NE(destination.AsRegister<Register>(), IP); 5617 __ Mov(IP, source.AsRegister<Register>()); 5618 __ Mov(source.AsRegister<Register>(), destination.AsRegister<Register>()); 5619 __ Mov(destination.AsRegister<Register>(), IP); 5620 } else if (source.IsRegister() && destination.IsStackSlot()) { 5621 Exchange(source.AsRegister<Register>(), destination.GetStackIndex()); 5622 } else if (source.IsStackSlot() && destination.IsRegister()) { 5623 Exchange(destination.AsRegister<Register>(), source.GetStackIndex()); 5624 } else if (source.IsStackSlot() && destination.IsStackSlot()) { 5625 Exchange(source.GetStackIndex(), destination.GetStackIndex()); 5626 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { 5627 __ vmovrs(IP, source.AsFpuRegister<SRegister>()); 5628 __ vmovs(source.AsFpuRegister<SRegister>(), destination.AsFpuRegister<SRegister>()); 5629 __ vmovsr(destination.AsFpuRegister<SRegister>(), IP); 5630 } else if (source.IsRegisterPair() && destination.IsRegisterPair()) { 5631 __ vmovdrr(DTMP, source.AsRegisterPairLow<Register>(), source.AsRegisterPairHigh<Register>()); 5632 __ Mov(source.AsRegisterPairLow<Register>(), destination.AsRegisterPairLow<Register>()); 5633 __ Mov(source.AsRegisterPairHigh<Register>(), destination.AsRegisterPairHigh<Register>()); 5634 __ vmovrrd(destination.AsRegisterPairLow<Register>(), 5635 destination.AsRegisterPairHigh<Register>(), 5636 DTMP); 5637 } else if (source.IsRegisterPair() || destination.IsRegisterPair()) { 5638 Register low_reg = source.IsRegisterPair() 5639 ? source.AsRegisterPairLow<Register>() 5640 : destination.AsRegisterPairLow<Register>(); 5641 int mem = source.IsRegisterPair() 5642 ? destination.GetStackIndex() 5643 : source.GetStackIndex(); 5644 DCHECK(ExpectedPairLayout(source.IsRegisterPair() ? source : destination)); 5645 __ vmovdrr(DTMP, low_reg, static_cast<Register>(low_reg + 1)); 5646 __ LoadFromOffset(kLoadWordPair, low_reg, SP, mem); 5647 __ StoreDToOffset(DTMP, SP, mem); 5648 } else if (source.IsFpuRegisterPair() && destination.IsFpuRegisterPair()) { 5649 DRegister first = FromLowSToD(source.AsFpuRegisterPairLow<SRegister>()); 5650 DRegister second = FromLowSToD(destination.AsFpuRegisterPairLow<SRegister>()); 5651 __ vmovd(DTMP, first); 5652 __ vmovd(first, second); 5653 __ vmovd(second, DTMP); 5654 } else if (source.IsFpuRegisterPair() || destination.IsFpuRegisterPair()) { 5655 DRegister reg = source.IsFpuRegisterPair() 5656 ? FromLowSToD(source.AsFpuRegisterPairLow<SRegister>()) 5657 : FromLowSToD(destination.AsFpuRegisterPairLow<SRegister>()); 5658 int mem = source.IsFpuRegisterPair() 5659 ? destination.GetStackIndex() 5660 : source.GetStackIndex(); 5661 __ vmovd(DTMP, reg); 5662 __ LoadDFromOffset(reg, SP, mem); 5663 __ StoreDToOffset(DTMP, SP, mem); 5664 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { 5665 SRegister reg = source.IsFpuRegister() ? source.AsFpuRegister<SRegister>() 5666 : destination.AsFpuRegister<SRegister>(); 5667 int mem = source.IsFpuRegister() 5668 ? destination.GetStackIndex() 5669 : source.GetStackIndex(); 5670 5671 __ vmovrs(IP, reg); 5672 __ LoadSFromOffset(reg, SP, mem); 5673 __ StoreToOffset(kStoreWord, IP, SP, mem); 5674 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) { 5675 Exchange(source.GetStackIndex(), destination.GetStackIndex()); 5676 Exchange(source.GetHighStackIndex(kArmWordSize), destination.GetHighStackIndex(kArmWordSize)); 5677 } else { 5678 LOG(FATAL) << "Unimplemented" << source << " <-> " << destination; 5679 } 5680} 5681 5682void ParallelMoveResolverARM::SpillScratch(int reg) { 5683 __ Push(static_cast<Register>(reg)); 5684} 5685 5686void ParallelMoveResolverARM::RestoreScratch(int reg) { 5687 __ Pop(static_cast<Register>(reg)); 5688} 5689 5690HLoadClass::LoadKind CodeGeneratorARM::GetSupportedLoadClassKind( 5691 HLoadClass::LoadKind desired_class_load_kind) { 5692 switch (desired_class_load_kind) { 5693 case HLoadClass::LoadKind::kReferrersClass: 5694 break; 5695 case HLoadClass::LoadKind::kBootImageLinkTimeAddress: 5696 DCHECK(!GetCompilerOptions().GetCompilePic()); 5697 break; 5698 case HLoadClass::LoadKind::kBootImageLinkTimePcRelative: 5699 DCHECK(GetCompilerOptions().GetCompilePic()); 5700 break; 5701 case HLoadClass::LoadKind::kBootImageAddress: 5702 break; 5703 case HLoadClass::LoadKind::kDexCacheAddress: 5704 DCHECK(Runtime::Current()->UseJitCompilation()); 5705 break; 5706 case HLoadClass::LoadKind::kDexCachePcRelative: 5707 DCHECK(!Runtime::Current()->UseJitCompilation()); 5708 // We disable pc-relative load when there is an irreducible loop, as the optimization 5709 // is incompatible with it. 5710 // TODO: Create as many ArmDexCacheArraysBase instructions as needed for methods 5711 // with irreducible loops. 5712 if (GetGraph()->HasIrreducibleLoops()) { 5713 return HLoadClass::LoadKind::kDexCacheViaMethod; 5714 } 5715 break; 5716 case HLoadClass::LoadKind::kDexCacheViaMethod: 5717 break; 5718 } 5719 return desired_class_load_kind; 5720} 5721 5722void LocationsBuilderARM::VisitLoadClass(HLoadClass* cls) { 5723 if (cls->NeedsAccessCheck()) { 5724 InvokeRuntimeCallingConvention calling_convention; 5725 CodeGenerator::CreateLoadClassLocationSummary( 5726 cls, 5727 Location::RegisterLocation(calling_convention.GetRegisterAt(0)), 5728 Location::RegisterLocation(R0), 5729 /* code_generator_supports_read_barrier */ true); 5730 return; 5731 } 5732 5733 const bool requires_read_barrier = kEmitCompilerReadBarrier && !cls->IsInBootImage(); 5734 LocationSummary::CallKind call_kind = (cls->NeedsEnvironment() || requires_read_barrier) 5735 ? LocationSummary::kCallOnSlowPath 5736 : LocationSummary::kNoCall; 5737 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(cls, call_kind); 5738 if (kUseBakerReadBarrier && requires_read_barrier && !cls->NeedsEnvironment()) { 5739 locations->SetCustomSlowPathCallerSaves(RegisterSet::Empty()); // No caller-save registers. 5740 } 5741 5742 HLoadClass::LoadKind load_kind = cls->GetLoadKind(); 5743 if (load_kind == HLoadClass::LoadKind::kReferrersClass || 5744 load_kind == HLoadClass::LoadKind::kDexCacheViaMethod || 5745 load_kind == HLoadClass::LoadKind::kDexCachePcRelative) { 5746 locations->SetInAt(0, Location::RequiresRegister()); 5747 } 5748 locations->SetOut(Location::RequiresRegister()); 5749} 5750 5751void InstructionCodeGeneratorARM::VisitLoadClass(HLoadClass* cls) { 5752 LocationSummary* locations = cls->GetLocations(); 5753 if (cls->NeedsAccessCheck()) { 5754 codegen_->MoveConstant(locations->GetTemp(0), cls->GetTypeIndex()); 5755 codegen_->InvokeRuntime(kQuickInitializeTypeAndVerifyAccess, cls, cls->GetDexPc()); 5756 CheckEntrypointTypes<kQuickInitializeTypeAndVerifyAccess, void*, uint32_t>(); 5757 return; 5758 } 5759 5760 Location out_loc = locations->Out(); 5761 Register out = out_loc.AsRegister<Register>(); 5762 5763 const ReadBarrierOption read_barrier_option = cls->IsInBootImage() 5764 ? kWithoutReadBarrier 5765 : kCompilerReadBarrierOption; 5766 bool generate_null_check = false; 5767 switch (cls->GetLoadKind()) { 5768 case HLoadClass::LoadKind::kReferrersClass: { 5769 DCHECK(!cls->CanCallRuntime()); 5770 DCHECK(!cls->MustGenerateClinitCheck()); 5771 // /* GcRoot<mirror::Class> */ out = current_method->declaring_class_ 5772 Register current_method = locations->InAt(0).AsRegister<Register>(); 5773 GenerateGcRootFieldLoad(cls, 5774 out_loc, 5775 current_method, 5776 ArtMethod::DeclaringClassOffset().Int32Value(), 5777 read_barrier_option); 5778 break; 5779 } 5780 case HLoadClass::LoadKind::kBootImageLinkTimeAddress: { 5781 DCHECK_EQ(read_barrier_option, kWithoutReadBarrier); 5782 __ LoadLiteral(out, codegen_->DeduplicateBootImageTypeLiteral(cls->GetDexFile(), 5783 cls->GetTypeIndex())); 5784 break; 5785 } 5786 case HLoadClass::LoadKind::kBootImageLinkTimePcRelative: { 5787 DCHECK_EQ(read_barrier_option, kWithoutReadBarrier); 5788 CodeGeneratorARM::PcRelativePatchInfo* labels = 5789 codegen_->NewPcRelativeTypePatch(cls->GetDexFile(), cls->GetTypeIndex()); 5790 __ BindTrackedLabel(&labels->movw_label); 5791 __ movw(out, /* placeholder */ 0u); 5792 __ BindTrackedLabel(&labels->movt_label); 5793 __ movt(out, /* placeholder */ 0u); 5794 __ BindTrackedLabel(&labels->add_pc_label); 5795 __ add(out, out, ShifterOperand(PC)); 5796 break; 5797 } 5798 case HLoadClass::LoadKind::kBootImageAddress: { 5799 DCHECK_EQ(read_barrier_option, kWithoutReadBarrier); 5800 DCHECK_NE(cls->GetAddress(), 0u); 5801 uint32_t address = dchecked_integral_cast<uint32_t>(cls->GetAddress()); 5802 __ LoadLiteral(out, codegen_->DeduplicateBootImageAddressLiteral(address)); 5803 break; 5804 } 5805 case HLoadClass::LoadKind::kDexCacheAddress: { 5806 DCHECK_NE(cls->GetAddress(), 0u); 5807 uint32_t address = dchecked_integral_cast<uint32_t>(cls->GetAddress()); 5808 // 16-bit LDR immediate has a 5-bit offset multiplied by the size and that gives 5809 // a 128B range. To try and reduce the number of literals if we load multiple types, 5810 // simply split the dex cache address to a 128B aligned base loaded from a literal 5811 // and the remaining offset embedded in the load. 5812 static_assert(sizeof(GcRoot<mirror::Class>) == 4u, "Expected GC root to be 4 bytes."); 5813 DCHECK_ALIGNED(cls->GetAddress(), 4u); 5814 constexpr size_t offset_bits = /* encoded bits */ 5 + /* scale */ 2; 5815 uint32_t base_address = address & ~MaxInt<uint32_t>(offset_bits); 5816 uint32_t offset = address & MaxInt<uint32_t>(offset_bits); 5817 __ LoadLiteral(out, codegen_->DeduplicateDexCacheAddressLiteral(base_address)); 5818 // /* GcRoot<mirror::Class> */ out = *(base_address + offset) 5819 GenerateGcRootFieldLoad(cls, out_loc, out, offset, read_barrier_option); 5820 generate_null_check = !cls->IsInDexCache(); 5821 break; 5822 } 5823 case HLoadClass::LoadKind::kDexCachePcRelative: { 5824 Register base_reg = locations->InAt(0).AsRegister<Register>(); 5825 HArmDexCacheArraysBase* base = cls->InputAt(0)->AsArmDexCacheArraysBase(); 5826 int32_t offset = cls->GetDexCacheElementOffset() - base->GetElementOffset(); 5827 // /* GcRoot<mirror::Class> */ out = *(dex_cache_arrays_base + offset) 5828 GenerateGcRootFieldLoad(cls, out_loc, base_reg, offset, read_barrier_option); 5829 generate_null_check = !cls->IsInDexCache(); 5830 break; 5831 } 5832 case HLoadClass::LoadKind::kDexCacheViaMethod: { 5833 // /* GcRoot<mirror::Class>[] */ out = 5834 // current_method.ptr_sized_fields_->dex_cache_resolved_types_ 5835 Register current_method = locations->InAt(0).AsRegister<Register>(); 5836 __ LoadFromOffset(kLoadWord, 5837 out, 5838 current_method, 5839 ArtMethod::DexCacheResolvedTypesOffset(kArmPointerSize).Int32Value()); 5840 // /* GcRoot<mirror::Class> */ out = out[type_index] 5841 size_t offset = CodeGenerator::GetCacheOffset(cls->GetTypeIndex()); 5842 GenerateGcRootFieldLoad(cls, out_loc, out, offset, read_barrier_option); 5843 generate_null_check = !cls->IsInDexCache(); 5844 } 5845 } 5846 5847 if (generate_null_check || cls->MustGenerateClinitCheck()) { 5848 DCHECK(cls->CanCallRuntime()); 5849 SlowPathCodeARM* slow_path = new (GetGraph()->GetArena()) LoadClassSlowPathARM( 5850 cls, cls, cls->GetDexPc(), cls->MustGenerateClinitCheck()); 5851 codegen_->AddSlowPath(slow_path); 5852 if (generate_null_check) { 5853 __ CompareAndBranchIfZero(out, slow_path->GetEntryLabel()); 5854 } 5855 if (cls->MustGenerateClinitCheck()) { 5856 GenerateClassInitializationCheck(slow_path, out); 5857 } else { 5858 __ Bind(slow_path->GetExitLabel()); 5859 } 5860 } 5861} 5862 5863void LocationsBuilderARM::VisitClinitCheck(HClinitCheck* check) { 5864 LocationSummary* locations = 5865 new (GetGraph()->GetArena()) LocationSummary(check, LocationSummary::kCallOnSlowPath); 5866 locations->SetInAt(0, Location::RequiresRegister()); 5867 if (check->HasUses()) { 5868 locations->SetOut(Location::SameAsFirstInput()); 5869 } 5870} 5871 5872void InstructionCodeGeneratorARM::VisitClinitCheck(HClinitCheck* check) { 5873 // We assume the class is not null. 5874 SlowPathCodeARM* slow_path = new (GetGraph()->GetArena()) LoadClassSlowPathARM( 5875 check->GetLoadClass(), check, check->GetDexPc(), true); 5876 codegen_->AddSlowPath(slow_path); 5877 GenerateClassInitializationCheck(slow_path, 5878 check->GetLocations()->InAt(0).AsRegister<Register>()); 5879} 5880 5881void InstructionCodeGeneratorARM::GenerateClassInitializationCheck( 5882 SlowPathCodeARM* slow_path, Register class_reg) { 5883 __ LoadFromOffset(kLoadWord, IP, class_reg, mirror::Class::StatusOffset().Int32Value()); 5884 __ cmp(IP, ShifterOperand(mirror::Class::kStatusInitialized)); 5885 __ b(slow_path->GetEntryLabel(), LT); 5886 // Even if the initialized flag is set, we may be in a situation where caches are not synced 5887 // properly. Therefore, we do a memory fence. 5888 __ dmb(ISH); 5889 __ Bind(slow_path->GetExitLabel()); 5890} 5891 5892HLoadString::LoadKind CodeGeneratorARM::GetSupportedLoadStringKind( 5893 HLoadString::LoadKind desired_string_load_kind) { 5894 switch (desired_string_load_kind) { 5895 case HLoadString::LoadKind::kBootImageLinkTimeAddress: 5896 DCHECK(!GetCompilerOptions().GetCompilePic()); 5897 break; 5898 case HLoadString::LoadKind::kBootImageLinkTimePcRelative: 5899 DCHECK(GetCompilerOptions().GetCompilePic()); 5900 break; 5901 case HLoadString::LoadKind::kBootImageAddress: 5902 break; 5903 case HLoadString::LoadKind::kBssEntry: 5904 DCHECK(!Runtime::Current()->UseJitCompilation()); 5905 break; 5906 case HLoadString::LoadKind::kJitTableAddress: 5907 DCHECK(Runtime::Current()->UseJitCompilation()); 5908 break; 5909 case HLoadString::LoadKind::kDexCacheViaMethod: 5910 break; 5911 } 5912 return desired_string_load_kind; 5913} 5914 5915void LocationsBuilderARM::VisitLoadString(HLoadString* load) { 5916 LocationSummary::CallKind call_kind = CodeGenerator::GetLoadStringCallKind(load); 5917 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(load, call_kind); 5918 HLoadString::LoadKind load_kind = load->GetLoadKind(); 5919 if (load_kind == HLoadString::LoadKind::kDexCacheViaMethod) { 5920 locations->SetOut(Location::RegisterLocation(R0)); 5921 } else { 5922 locations->SetOut(Location::RequiresRegister()); 5923 if (load_kind == HLoadString::LoadKind::kBssEntry) { 5924 if (!kUseReadBarrier || kUseBakerReadBarrier) { 5925 // Rely on the pResolveString and/or marking to save everything, including temps. 5926 // Note that IP may theoretically be clobbered by saving/restoring the live register 5927 // (only one thanks to the custom calling convention), so we request a different temp. 5928 locations->AddTemp(Location::RequiresRegister()); 5929 RegisterSet caller_saves = RegisterSet::Empty(); 5930 InvokeRuntimeCallingConvention calling_convention; 5931 caller_saves.Add(Location::RegisterLocation(calling_convention.GetRegisterAt(0))); 5932 // TODO: Add GetReturnLocation() to the calling convention so that we can DCHECK() 5933 // that the the kPrimNot result register is the same as the first argument register. 5934 locations->SetCustomSlowPathCallerSaves(caller_saves); 5935 } else { 5936 // For non-Baker read barrier we have a temp-clobbering call. 5937 } 5938 } 5939 } 5940} 5941 5942void InstructionCodeGeneratorARM::VisitLoadString(HLoadString* load) { 5943 LocationSummary* locations = load->GetLocations(); 5944 Location out_loc = locations->Out(); 5945 Register out = out_loc.AsRegister<Register>(); 5946 HLoadString::LoadKind load_kind = load->GetLoadKind(); 5947 5948 switch (load_kind) { 5949 case HLoadString::LoadKind::kBootImageLinkTimeAddress: { 5950 __ LoadLiteral(out, codegen_->DeduplicateBootImageStringLiteral(load->GetDexFile(), 5951 load->GetStringIndex())); 5952 return; // No dex cache slow path. 5953 } 5954 case HLoadString::LoadKind::kBootImageLinkTimePcRelative: { 5955 DCHECK(codegen_->GetCompilerOptions().IsBootImage()); 5956 CodeGeneratorARM::PcRelativePatchInfo* labels = 5957 codegen_->NewPcRelativeStringPatch(load->GetDexFile(), load->GetStringIndex()); 5958 __ BindTrackedLabel(&labels->movw_label); 5959 __ movw(out, /* placeholder */ 0u); 5960 __ BindTrackedLabel(&labels->movt_label); 5961 __ movt(out, /* placeholder */ 0u); 5962 __ BindTrackedLabel(&labels->add_pc_label); 5963 __ add(out, out, ShifterOperand(PC)); 5964 return; // No dex cache slow path. 5965 } 5966 case HLoadString::LoadKind::kBootImageAddress: { 5967 DCHECK_NE(load->GetAddress(), 0u); 5968 uint32_t address = dchecked_integral_cast<uint32_t>(load->GetAddress()); 5969 __ LoadLiteral(out, codegen_->DeduplicateBootImageAddressLiteral(address)); 5970 return; // No dex cache slow path. 5971 } 5972 case HLoadString::LoadKind::kBssEntry: { 5973 DCHECK(!codegen_->GetCompilerOptions().IsBootImage()); 5974 Register temp = locations->GetTemp(0).AsRegister<Register>(); 5975 CodeGeneratorARM::PcRelativePatchInfo* labels = 5976 codegen_->NewPcRelativeStringPatch(load->GetDexFile(), load->GetStringIndex()); 5977 __ BindTrackedLabel(&labels->movw_label); 5978 __ movw(temp, /* placeholder */ 0u); 5979 __ BindTrackedLabel(&labels->movt_label); 5980 __ movt(temp, /* placeholder */ 0u); 5981 __ BindTrackedLabel(&labels->add_pc_label); 5982 __ add(temp, temp, ShifterOperand(PC)); 5983 GenerateGcRootFieldLoad(load, out_loc, temp, /* offset */ 0, kCompilerReadBarrierOption); 5984 SlowPathCode* slow_path = new (GetGraph()->GetArena()) LoadStringSlowPathARM(load); 5985 codegen_->AddSlowPath(slow_path); 5986 __ CompareAndBranchIfZero(out, slow_path->GetEntryLabel()); 5987 __ Bind(slow_path->GetExitLabel()); 5988 return; 5989 } 5990 case HLoadString::LoadKind::kJitTableAddress: { 5991 __ LoadLiteral(out, codegen_->DeduplicateJitStringLiteral(load->GetDexFile(), 5992 load->GetStringIndex())); 5993 // /* GcRoot<mirror::String> */ out = *out 5994 GenerateGcRootFieldLoad(load, out_loc, out, /* offset */ 0, kCompilerReadBarrierOption); 5995 return; 5996 } 5997 default: 5998 break; 5999 } 6000 6001 // TODO: Consider re-adding the compiler code to do string dex cache lookup again. 6002 DCHECK(load_kind == HLoadString::LoadKind::kDexCacheViaMethod); 6003 InvokeRuntimeCallingConvention calling_convention; 6004 DCHECK_EQ(calling_convention.GetRegisterAt(0), out); 6005 __ LoadImmediate(calling_convention.GetRegisterAt(0), load->GetStringIndex()); 6006 codegen_->InvokeRuntime(kQuickResolveString, load, load->GetDexPc()); 6007 CheckEntrypointTypes<kQuickResolveString, void*, uint32_t>(); 6008} 6009 6010static int32_t GetExceptionTlsOffset() { 6011 return Thread::ExceptionOffset<kArmPointerSize>().Int32Value(); 6012} 6013 6014void LocationsBuilderARM::VisitLoadException(HLoadException* load) { 6015 LocationSummary* locations = 6016 new (GetGraph()->GetArena()) LocationSummary(load, LocationSummary::kNoCall); 6017 locations->SetOut(Location::RequiresRegister()); 6018} 6019 6020void InstructionCodeGeneratorARM::VisitLoadException(HLoadException* load) { 6021 Register out = load->GetLocations()->Out().AsRegister<Register>(); 6022 __ LoadFromOffset(kLoadWord, out, TR, GetExceptionTlsOffset()); 6023} 6024 6025void LocationsBuilderARM::VisitClearException(HClearException* clear) { 6026 new (GetGraph()->GetArena()) LocationSummary(clear, LocationSummary::kNoCall); 6027} 6028 6029void InstructionCodeGeneratorARM::VisitClearException(HClearException* clear ATTRIBUTE_UNUSED) { 6030 __ LoadImmediate(IP, 0); 6031 __ StoreToOffset(kStoreWord, IP, TR, GetExceptionTlsOffset()); 6032} 6033 6034void LocationsBuilderARM::VisitThrow(HThrow* instruction) { 6035 LocationSummary* locations = 6036 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kCallOnMainOnly); 6037 InvokeRuntimeCallingConvention calling_convention; 6038 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(0))); 6039} 6040 6041void InstructionCodeGeneratorARM::VisitThrow(HThrow* instruction) { 6042 codegen_->InvokeRuntime(kQuickDeliverException, instruction, instruction->GetDexPc()); 6043 CheckEntrypointTypes<kQuickDeliverException, void, mirror::Object*>(); 6044} 6045 6046// Temp is used for read barrier. 6047static size_t NumberOfInstanceOfTemps(TypeCheckKind type_check_kind) { 6048 if (kEmitCompilerReadBarrier && 6049 (kUseBakerReadBarrier || 6050 type_check_kind == TypeCheckKind::kAbstractClassCheck || 6051 type_check_kind == TypeCheckKind::kClassHierarchyCheck || 6052 type_check_kind == TypeCheckKind::kArrayObjectCheck)) { 6053 return 1; 6054 } 6055 return 0; 6056} 6057 6058// Interface case has 3 temps, one for holding the number of interfaces, one for the current 6059// interface pointer, one for loading the current interface. 6060// The other checks have one temp for loading the object's class. 6061static size_t NumberOfCheckCastTemps(TypeCheckKind type_check_kind) { 6062 if (type_check_kind == TypeCheckKind::kInterfaceCheck) { 6063 return 3; 6064 } 6065 return 1 + NumberOfInstanceOfTemps(type_check_kind); 6066} 6067 6068void LocationsBuilderARM::VisitInstanceOf(HInstanceOf* instruction) { 6069 LocationSummary::CallKind call_kind = LocationSummary::kNoCall; 6070 TypeCheckKind type_check_kind = instruction->GetTypeCheckKind(); 6071 bool baker_read_barrier_slow_path = false; 6072 switch (type_check_kind) { 6073 case TypeCheckKind::kExactCheck: 6074 case TypeCheckKind::kAbstractClassCheck: 6075 case TypeCheckKind::kClassHierarchyCheck: 6076 case TypeCheckKind::kArrayObjectCheck: 6077 call_kind = 6078 kEmitCompilerReadBarrier ? LocationSummary::kCallOnSlowPath : LocationSummary::kNoCall; 6079 baker_read_barrier_slow_path = kUseBakerReadBarrier; 6080 break; 6081 case TypeCheckKind::kArrayCheck: 6082 case TypeCheckKind::kUnresolvedCheck: 6083 case TypeCheckKind::kInterfaceCheck: 6084 call_kind = LocationSummary::kCallOnSlowPath; 6085 break; 6086 } 6087 6088 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction, call_kind); 6089 if (baker_read_barrier_slow_path) { 6090 locations->SetCustomSlowPathCallerSaves(RegisterSet::Empty()); // No caller-save registers. 6091 } 6092 locations->SetInAt(0, Location::RequiresRegister()); 6093 locations->SetInAt(1, Location::RequiresRegister()); 6094 // The "out" register is used as a temporary, so it overlaps with the inputs. 6095 // Note that TypeCheckSlowPathARM uses this register too. 6096 locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap); 6097 locations->AddRegisterTemps(NumberOfInstanceOfTemps(type_check_kind)); 6098} 6099 6100void InstructionCodeGeneratorARM::VisitInstanceOf(HInstanceOf* instruction) { 6101 TypeCheckKind type_check_kind = instruction->GetTypeCheckKind(); 6102 LocationSummary* locations = instruction->GetLocations(); 6103 Location obj_loc = locations->InAt(0); 6104 Register obj = obj_loc.AsRegister<Register>(); 6105 Register cls = locations->InAt(1).AsRegister<Register>(); 6106 Location out_loc = locations->Out(); 6107 Register out = out_loc.AsRegister<Register>(); 6108 const size_t num_temps = NumberOfInstanceOfTemps(type_check_kind); 6109 DCHECK_LE(num_temps, 1u); 6110 Location maybe_temp_loc = (num_temps >= 1) ? locations->GetTemp(0) : Location::NoLocation(); 6111 uint32_t class_offset = mirror::Object::ClassOffset().Int32Value(); 6112 uint32_t super_offset = mirror::Class::SuperClassOffset().Int32Value(); 6113 uint32_t component_offset = mirror::Class::ComponentTypeOffset().Int32Value(); 6114 uint32_t primitive_offset = mirror::Class::PrimitiveTypeOffset().Int32Value(); 6115 Label done, zero; 6116 SlowPathCodeARM* slow_path = nullptr; 6117 6118 // Return 0 if `obj` is null. 6119 // avoid null check if we know obj is not null. 6120 if (instruction->MustDoNullCheck()) { 6121 __ CompareAndBranchIfZero(obj, &zero); 6122 } 6123 6124 // /* HeapReference<Class> */ out = obj->klass_ 6125 GenerateReferenceLoadTwoRegisters(instruction, 6126 out_loc, 6127 obj_loc, 6128 class_offset, 6129 maybe_temp_loc, 6130 kCompilerReadBarrierOption); 6131 6132 switch (type_check_kind) { 6133 case TypeCheckKind::kExactCheck: { 6134 __ cmp(out, ShifterOperand(cls)); 6135 // Classes must be equal for the instanceof to succeed. 6136 __ b(&zero, NE); 6137 __ LoadImmediate(out, 1); 6138 __ b(&done); 6139 break; 6140 } 6141 6142 case TypeCheckKind::kAbstractClassCheck: { 6143 // If the class is abstract, we eagerly fetch the super class of the 6144 // object to avoid doing a comparison we know will fail. 6145 Label loop; 6146 __ Bind(&loop); 6147 // /* HeapReference<Class> */ out = out->super_class_ 6148 GenerateReferenceLoadOneRegister(instruction, 6149 out_loc, 6150 super_offset, 6151 maybe_temp_loc, 6152 kCompilerReadBarrierOption); 6153 // If `out` is null, we use it for the result, and jump to `done`. 6154 __ CompareAndBranchIfZero(out, &done); 6155 __ cmp(out, ShifterOperand(cls)); 6156 __ b(&loop, NE); 6157 __ LoadImmediate(out, 1); 6158 if (zero.IsLinked()) { 6159 __ b(&done); 6160 } 6161 break; 6162 } 6163 6164 case TypeCheckKind::kClassHierarchyCheck: { 6165 // Walk over the class hierarchy to find a match. 6166 Label loop, success; 6167 __ Bind(&loop); 6168 __ cmp(out, ShifterOperand(cls)); 6169 __ b(&success, EQ); 6170 // /* HeapReference<Class> */ out = out->super_class_ 6171 GenerateReferenceLoadOneRegister(instruction, 6172 out_loc, 6173 super_offset, 6174 maybe_temp_loc, 6175 kCompilerReadBarrierOption); 6176 __ CompareAndBranchIfNonZero(out, &loop); 6177 // If `out` is null, we use it for the result, and jump to `done`. 6178 __ b(&done); 6179 __ Bind(&success); 6180 __ LoadImmediate(out, 1); 6181 if (zero.IsLinked()) { 6182 __ b(&done); 6183 } 6184 break; 6185 } 6186 6187 case TypeCheckKind::kArrayObjectCheck: { 6188 // Do an exact check. 6189 Label exact_check; 6190 __ cmp(out, ShifterOperand(cls)); 6191 __ b(&exact_check, EQ); 6192 // Otherwise, we need to check that the object's class is a non-primitive array. 6193 // /* HeapReference<Class> */ out = out->component_type_ 6194 GenerateReferenceLoadOneRegister(instruction, 6195 out_loc, 6196 component_offset, 6197 maybe_temp_loc, 6198 kCompilerReadBarrierOption); 6199 // If `out` is null, we use it for the result, and jump to `done`. 6200 __ CompareAndBranchIfZero(out, &done); 6201 __ LoadFromOffset(kLoadUnsignedHalfword, out, out, primitive_offset); 6202 static_assert(Primitive::kPrimNot == 0, "Expected 0 for kPrimNot"); 6203 __ CompareAndBranchIfNonZero(out, &zero); 6204 __ Bind(&exact_check); 6205 __ LoadImmediate(out, 1); 6206 __ b(&done); 6207 break; 6208 } 6209 6210 case TypeCheckKind::kArrayCheck: { 6211 __ cmp(out, ShifterOperand(cls)); 6212 DCHECK(locations->OnlyCallsOnSlowPath()); 6213 slow_path = new (GetGraph()->GetArena()) TypeCheckSlowPathARM(instruction, 6214 /* is_fatal */ false); 6215 codegen_->AddSlowPath(slow_path); 6216 __ b(slow_path->GetEntryLabel(), NE); 6217 __ LoadImmediate(out, 1); 6218 if (zero.IsLinked()) { 6219 __ b(&done); 6220 } 6221 break; 6222 } 6223 6224 case TypeCheckKind::kUnresolvedCheck: 6225 case TypeCheckKind::kInterfaceCheck: { 6226 // Note that we indeed only call on slow path, but we always go 6227 // into the slow path for the unresolved and interface check 6228 // cases. 6229 // 6230 // We cannot directly call the InstanceofNonTrivial runtime 6231 // entry point without resorting to a type checking slow path 6232 // here (i.e. by calling InvokeRuntime directly), as it would 6233 // require to assign fixed registers for the inputs of this 6234 // HInstanceOf instruction (following the runtime calling 6235 // convention), which might be cluttered by the potential first 6236 // read barrier emission at the beginning of this method. 6237 // 6238 // TODO: Introduce a new runtime entry point taking the object 6239 // to test (instead of its class) as argument, and let it deal 6240 // with the read barrier issues. This will let us refactor this 6241 // case of the `switch` code as it was previously (with a direct 6242 // call to the runtime not using a type checking slow path). 6243 // This should also be beneficial for the other cases above. 6244 DCHECK(locations->OnlyCallsOnSlowPath()); 6245 slow_path = new (GetGraph()->GetArena()) TypeCheckSlowPathARM(instruction, 6246 /* is_fatal */ false); 6247 codegen_->AddSlowPath(slow_path); 6248 __ b(slow_path->GetEntryLabel()); 6249 if (zero.IsLinked()) { 6250 __ b(&done); 6251 } 6252 break; 6253 } 6254 } 6255 6256 if (zero.IsLinked()) { 6257 __ Bind(&zero); 6258 __ LoadImmediate(out, 0); 6259 } 6260 6261 if (done.IsLinked()) { 6262 __ Bind(&done); 6263 } 6264 6265 if (slow_path != nullptr) { 6266 __ Bind(slow_path->GetExitLabel()); 6267 } 6268} 6269 6270void LocationsBuilderARM::VisitCheckCast(HCheckCast* instruction) { 6271 LocationSummary::CallKind call_kind = LocationSummary::kNoCall; 6272 bool throws_into_catch = instruction->CanThrowIntoCatchBlock(); 6273 6274 TypeCheckKind type_check_kind = instruction->GetTypeCheckKind(); 6275 switch (type_check_kind) { 6276 case TypeCheckKind::kExactCheck: 6277 case TypeCheckKind::kAbstractClassCheck: 6278 case TypeCheckKind::kClassHierarchyCheck: 6279 case TypeCheckKind::kArrayObjectCheck: 6280 call_kind = (throws_into_catch || kEmitCompilerReadBarrier) ? 6281 LocationSummary::kCallOnSlowPath : 6282 LocationSummary::kNoCall; // In fact, call on a fatal (non-returning) slow path. 6283 break; 6284 case TypeCheckKind::kArrayCheck: 6285 case TypeCheckKind::kUnresolvedCheck: 6286 case TypeCheckKind::kInterfaceCheck: 6287 call_kind = LocationSummary::kCallOnSlowPath; 6288 break; 6289 } 6290 6291 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction, call_kind); 6292 locations->SetInAt(0, Location::RequiresRegister()); 6293 locations->SetInAt(1, Location::RequiresRegister()); 6294 locations->AddRegisterTemps(NumberOfCheckCastTemps(type_check_kind)); 6295} 6296 6297void InstructionCodeGeneratorARM::VisitCheckCast(HCheckCast* instruction) { 6298 TypeCheckKind type_check_kind = instruction->GetTypeCheckKind(); 6299 LocationSummary* locations = instruction->GetLocations(); 6300 Location obj_loc = locations->InAt(0); 6301 Register obj = obj_loc.AsRegister<Register>(); 6302 Register cls = locations->InAt(1).AsRegister<Register>(); 6303 Location temp_loc = locations->GetTemp(0); 6304 Register temp = temp_loc.AsRegister<Register>(); 6305 const size_t num_temps = NumberOfCheckCastTemps(type_check_kind); 6306 DCHECK_LE(num_temps, 3u); 6307 Location maybe_temp2_loc = (num_temps >= 2) ? locations->GetTemp(1) : Location::NoLocation(); 6308 Location maybe_temp3_loc = (num_temps >= 3) ? locations->GetTemp(2) : Location::NoLocation(); 6309 const uint32_t class_offset = mirror::Object::ClassOffset().Int32Value(); 6310 const uint32_t super_offset = mirror::Class::SuperClassOffset().Int32Value(); 6311 const uint32_t component_offset = mirror::Class::ComponentTypeOffset().Int32Value(); 6312 const uint32_t primitive_offset = mirror::Class::PrimitiveTypeOffset().Int32Value(); 6313 const uint32_t iftable_offset = mirror::Class::IfTableOffset().Uint32Value(); 6314 const uint32_t array_length_offset = mirror::Array::LengthOffset().Uint32Value(); 6315 const uint32_t object_array_data_offset = 6316 mirror::Array::DataOffset(kHeapReferenceSize).Uint32Value(); 6317 6318 // Always false for read barriers since we may need to go to the entrypoint for non-fatal cases 6319 // from false negatives. The false negatives may come from avoiding read barriers below. Avoiding 6320 // read barriers is done for performance and code size reasons. 6321 bool is_type_check_slow_path_fatal = false; 6322 if (!kEmitCompilerReadBarrier) { 6323 is_type_check_slow_path_fatal = 6324 (type_check_kind == TypeCheckKind::kExactCheck || 6325 type_check_kind == TypeCheckKind::kAbstractClassCheck || 6326 type_check_kind == TypeCheckKind::kClassHierarchyCheck || 6327 type_check_kind == TypeCheckKind::kArrayObjectCheck) && 6328 !instruction->CanThrowIntoCatchBlock(); 6329 } 6330 SlowPathCodeARM* type_check_slow_path = 6331 new (GetGraph()->GetArena()) TypeCheckSlowPathARM(instruction, 6332 is_type_check_slow_path_fatal); 6333 codegen_->AddSlowPath(type_check_slow_path); 6334 6335 Label done; 6336 // Avoid null check if we know obj is not null. 6337 if (instruction->MustDoNullCheck()) { 6338 __ CompareAndBranchIfZero(obj, &done); 6339 } 6340 6341 switch (type_check_kind) { 6342 case TypeCheckKind::kExactCheck: 6343 case TypeCheckKind::kArrayCheck: { 6344 // /* HeapReference<Class> */ temp = obj->klass_ 6345 GenerateReferenceLoadTwoRegisters(instruction, 6346 temp_loc, 6347 obj_loc, 6348 class_offset, 6349 maybe_temp2_loc, 6350 kWithoutReadBarrier); 6351 6352 __ cmp(temp, ShifterOperand(cls)); 6353 // Jump to slow path for throwing the exception or doing a 6354 // more involved array check. 6355 __ b(type_check_slow_path->GetEntryLabel(), NE); 6356 break; 6357 } 6358 6359 case TypeCheckKind::kAbstractClassCheck: { 6360 // /* HeapReference<Class> */ temp = obj->klass_ 6361 GenerateReferenceLoadTwoRegisters(instruction, 6362 temp_loc, 6363 obj_loc, 6364 class_offset, 6365 maybe_temp2_loc, 6366 kWithoutReadBarrier); 6367 6368 // If the class is abstract, we eagerly fetch the super class of the 6369 // object to avoid doing a comparison we know will fail. 6370 Label loop; 6371 __ Bind(&loop); 6372 // /* HeapReference<Class> */ temp = temp->super_class_ 6373 GenerateReferenceLoadOneRegister(instruction, 6374 temp_loc, 6375 super_offset, 6376 maybe_temp2_loc, 6377 kWithoutReadBarrier); 6378 6379 // If the class reference currently in `temp` is null, jump to the slow path to throw the 6380 // exception. 6381 __ CompareAndBranchIfZero(temp, type_check_slow_path->GetEntryLabel()); 6382 6383 // Otherwise, compare the classes. 6384 __ cmp(temp, ShifterOperand(cls)); 6385 __ b(&loop, NE); 6386 break; 6387 } 6388 6389 case TypeCheckKind::kClassHierarchyCheck: { 6390 // /* HeapReference<Class> */ temp = obj->klass_ 6391 GenerateReferenceLoadTwoRegisters(instruction, 6392 temp_loc, 6393 obj_loc, 6394 class_offset, 6395 maybe_temp2_loc, 6396 kWithoutReadBarrier); 6397 6398 // Walk over the class hierarchy to find a match. 6399 Label loop; 6400 __ Bind(&loop); 6401 __ cmp(temp, ShifterOperand(cls)); 6402 __ b(&done, EQ); 6403 6404 // /* HeapReference<Class> */ temp = temp->super_class_ 6405 GenerateReferenceLoadOneRegister(instruction, 6406 temp_loc, 6407 super_offset, 6408 maybe_temp2_loc, 6409 kWithoutReadBarrier); 6410 6411 // If the class reference currently in `temp` is null, jump to the slow path to throw the 6412 // exception. 6413 __ CompareAndBranchIfZero(temp, type_check_slow_path->GetEntryLabel()); 6414 // Otherwise, jump to the beginning of the loop. 6415 __ b(&loop); 6416 break; 6417 } 6418 6419 case TypeCheckKind::kArrayObjectCheck: { 6420 // /* HeapReference<Class> */ temp = obj->klass_ 6421 GenerateReferenceLoadTwoRegisters(instruction, 6422 temp_loc, 6423 obj_loc, 6424 class_offset, 6425 maybe_temp2_loc, 6426 kWithoutReadBarrier); 6427 6428 // Do an exact check. 6429 __ cmp(temp, ShifterOperand(cls)); 6430 __ b(&done, EQ); 6431 6432 // Otherwise, we need to check that the object's class is a non-primitive array. 6433 // /* HeapReference<Class> */ temp = temp->component_type_ 6434 GenerateReferenceLoadOneRegister(instruction, 6435 temp_loc, 6436 component_offset, 6437 maybe_temp2_loc, 6438 kWithoutReadBarrier); 6439 // If the component type is null, jump to the slow path to throw the exception. 6440 __ CompareAndBranchIfZero(temp, type_check_slow_path->GetEntryLabel()); 6441 // Otherwise,the object is indeed an array, jump to label `check_non_primitive_component_type` 6442 // to further check that this component type is not a primitive type. 6443 __ LoadFromOffset(kLoadUnsignedHalfword, temp, temp, primitive_offset); 6444 static_assert(Primitive::kPrimNot == 0, "Expected 0 for art::Primitive::kPrimNot"); 6445 __ CompareAndBranchIfNonZero(temp, type_check_slow_path->GetEntryLabel()); 6446 break; 6447 } 6448 6449 case TypeCheckKind::kUnresolvedCheck: 6450 // We always go into the type check slow path for the unresolved check case. 6451 // We cannot directly call the CheckCast runtime entry point 6452 // without resorting to a type checking slow path here (i.e. by 6453 // calling InvokeRuntime directly), as it would require to 6454 // assign fixed registers for the inputs of this HInstanceOf 6455 // instruction (following the runtime calling convention), which 6456 // might be cluttered by the potential first read barrier 6457 // emission at the beginning of this method. 6458 6459 __ b(type_check_slow_path->GetEntryLabel()); 6460 break; 6461 6462 case TypeCheckKind::kInterfaceCheck: { 6463 // Avoid read barriers to improve performance of the fast path. We can not get false 6464 // positives by doing this. 6465 // /* HeapReference<Class> */ temp = obj->klass_ 6466 GenerateReferenceLoadTwoRegisters(instruction, 6467 temp_loc, 6468 obj_loc, 6469 class_offset, 6470 maybe_temp2_loc, 6471 kWithoutReadBarrier); 6472 6473 // /* HeapReference<Class> */ temp = temp->iftable_ 6474 GenerateReferenceLoadTwoRegisters(instruction, 6475 temp_loc, 6476 temp_loc, 6477 iftable_offset, 6478 maybe_temp2_loc, 6479 kWithoutReadBarrier); 6480 Label is_null; 6481 // Null iftable means it is empty and will always fail the check. 6482 // Not cbz since the temp may not be a low register. 6483 __ CompareAndBranchIfZero(temp, &is_null); 6484 6485 // Loop through the iftable and check if any class matches. 6486 __ ldr(maybe_temp2_loc.AsRegister<Register>(), Address(temp, array_length_offset)); 6487 6488 Label start_loop; 6489 __ Bind(&start_loop); 6490 __ ldr(maybe_temp3_loc.AsRegister<Register>(), Address(temp, object_array_data_offset)); 6491 __ MaybeUnpoisonHeapReference(maybe_temp3_loc.AsRegister<Register>()); 6492 __ cmp(cls, ShifterOperand(maybe_temp3_loc.AsRegister<Register>())); 6493 __ b(&done, EQ); // Return if same class. 6494 // Go to next interface. 6495 __ add(temp, temp, ShifterOperand(2 * kHeapReferenceSize)); 6496 __ sub(maybe_temp2_loc.AsRegister<Register>(), 6497 maybe_temp2_loc.AsRegister<Register>(), 6498 ShifterOperand(2)); 6499 // Not cbnz since the temp may not be a low register. 6500 __ CompareAndBranchIfNonZero(maybe_temp2_loc.AsRegister<Register>(), &start_loop); 6501 __ Bind(&is_null); 6502 6503 __ b(type_check_slow_path->GetEntryLabel()); 6504 break; 6505 } 6506 } 6507 __ Bind(&done); 6508 6509 __ Bind(type_check_slow_path->GetExitLabel()); 6510} 6511 6512void LocationsBuilderARM::VisitMonitorOperation(HMonitorOperation* instruction) { 6513 LocationSummary* locations = 6514 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kCallOnMainOnly); 6515 InvokeRuntimeCallingConvention calling_convention; 6516 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(0))); 6517} 6518 6519void InstructionCodeGeneratorARM::VisitMonitorOperation(HMonitorOperation* instruction) { 6520 codegen_->InvokeRuntime(instruction->IsEnter() ? kQuickLockObject : kQuickUnlockObject, 6521 instruction, 6522 instruction->GetDexPc()); 6523 if (instruction->IsEnter()) { 6524 CheckEntrypointTypes<kQuickLockObject, void, mirror::Object*>(); 6525 } else { 6526 CheckEntrypointTypes<kQuickUnlockObject, void, mirror::Object*>(); 6527 } 6528} 6529 6530void LocationsBuilderARM::VisitAnd(HAnd* instruction) { HandleBitwiseOperation(instruction, AND); } 6531void LocationsBuilderARM::VisitOr(HOr* instruction) { HandleBitwiseOperation(instruction, ORR); } 6532void LocationsBuilderARM::VisitXor(HXor* instruction) { HandleBitwiseOperation(instruction, EOR); } 6533 6534void LocationsBuilderARM::HandleBitwiseOperation(HBinaryOperation* instruction, Opcode opcode) { 6535 LocationSummary* locations = 6536 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall); 6537 DCHECK(instruction->GetResultType() == Primitive::kPrimInt 6538 || instruction->GetResultType() == Primitive::kPrimLong); 6539 // Note: GVN reorders commutative operations to have the constant on the right hand side. 6540 locations->SetInAt(0, Location::RequiresRegister()); 6541 locations->SetInAt(1, ArmEncodableConstantOrRegister(instruction->InputAt(1), opcode)); 6542 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 6543} 6544 6545void InstructionCodeGeneratorARM::VisitAnd(HAnd* instruction) { 6546 HandleBitwiseOperation(instruction); 6547} 6548 6549void InstructionCodeGeneratorARM::VisitOr(HOr* instruction) { 6550 HandleBitwiseOperation(instruction); 6551} 6552 6553void InstructionCodeGeneratorARM::VisitXor(HXor* instruction) { 6554 HandleBitwiseOperation(instruction); 6555} 6556 6557 6558void LocationsBuilderARM::VisitBitwiseNegatedRight(HBitwiseNegatedRight* instruction) { 6559 LocationSummary* locations = 6560 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall); 6561 DCHECK(instruction->GetResultType() == Primitive::kPrimInt 6562 || instruction->GetResultType() == Primitive::kPrimLong); 6563 6564 locations->SetInAt(0, Location::RequiresRegister()); 6565 locations->SetInAt(1, Location::RequiresRegister()); 6566 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 6567} 6568 6569void InstructionCodeGeneratorARM::VisitBitwiseNegatedRight(HBitwiseNegatedRight* instruction) { 6570 LocationSummary* locations = instruction->GetLocations(); 6571 Location first = locations->InAt(0); 6572 Location second = locations->InAt(1); 6573 Location out = locations->Out(); 6574 6575 if (instruction->GetResultType() == Primitive::kPrimInt) { 6576 Register first_reg = first.AsRegister<Register>(); 6577 ShifterOperand second_reg(second.AsRegister<Register>()); 6578 Register out_reg = out.AsRegister<Register>(); 6579 6580 switch (instruction->GetOpKind()) { 6581 case HInstruction::kAnd: 6582 __ bic(out_reg, first_reg, second_reg); 6583 break; 6584 case HInstruction::kOr: 6585 __ orn(out_reg, first_reg, second_reg); 6586 break; 6587 // There is no EON on arm. 6588 case HInstruction::kXor: 6589 default: 6590 LOG(FATAL) << "Unexpected instruction " << instruction->DebugName(); 6591 UNREACHABLE(); 6592 } 6593 return; 6594 6595 } else { 6596 DCHECK_EQ(instruction->GetResultType(), Primitive::kPrimLong); 6597 Register first_low = first.AsRegisterPairLow<Register>(); 6598 Register first_high = first.AsRegisterPairHigh<Register>(); 6599 ShifterOperand second_low(second.AsRegisterPairLow<Register>()); 6600 ShifterOperand second_high(second.AsRegisterPairHigh<Register>()); 6601 Register out_low = out.AsRegisterPairLow<Register>(); 6602 Register out_high = out.AsRegisterPairHigh<Register>(); 6603 6604 switch (instruction->GetOpKind()) { 6605 case HInstruction::kAnd: 6606 __ bic(out_low, first_low, second_low); 6607 __ bic(out_high, first_high, second_high); 6608 break; 6609 case HInstruction::kOr: 6610 __ orn(out_low, first_low, second_low); 6611 __ orn(out_high, first_high, second_high); 6612 break; 6613 // There is no EON on arm. 6614 case HInstruction::kXor: 6615 default: 6616 LOG(FATAL) << "Unexpected instruction " << instruction->DebugName(); 6617 UNREACHABLE(); 6618 } 6619 } 6620} 6621 6622void InstructionCodeGeneratorARM::GenerateAndConst(Register out, Register first, uint32_t value) { 6623 // Optimize special cases for individual halfs of `and-long` (`and` is simplified earlier). 6624 if (value == 0xffffffffu) { 6625 if (out != first) { 6626 __ mov(out, ShifterOperand(first)); 6627 } 6628 return; 6629 } 6630 if (value == 0u) { 6631 __ mov(out, ShifterOperand(0)); 6632 return; 6633 } 6634 ShifterOperand so; 6635 if (__ ShifterOperandCanHold(kNoRegister, kNoRegister, AND, value, &so)) { 6636 __ and_(out, first, so); 6637 } else { 6638 DCHECK(__ ShifterOperandCanHold(kNoRegister, kNoRegister, BIC, ~value, &so)); 6639 __ bic(out, first, ShifterOperand(~value)); 6640 } 6641} 6642 6643void InstructionCodeGeneratorARM::GenerateOrrConst(Register out, Register first, uint32_t value) { 6644 // Optimize special cases for individual halfs of `or-long` (`or` is simplified earlier). 6645 if (value == 0u) { 6646 if (out != first) { 6647 __ mov(out, ShifterOperand(first)); 6648 } 6649 return; 6650 } 6651 if (value == 0xffffffffu) { 6652 __ mvn(out, ShifterOperand(0)); 6653 return; 6654 } 6655 ShifterOperand so; 6656 if (__ ShifterOperandCanHold(kNoRegister, kNoRegister, ORR, value, &so)) { 6657 __ orr(out, first, so); 6658 } else { 6659 DCHECK(__ ShifterOperandCanHold(kNoRegister, kNoRegister, ORN, ~value, &so)); 6660 __ orn(out, first, ShifterOperand(~value)); 6661 } 6662} 6663 6664void InstructionCodeGeneratorARM::GenerateEorConst(Register out, Register first, uint32_t value) { 6665 // Optimize special case for individual halfs of `xor-long` (`xor` is simplified earlier). 6666 if (value == 0u) { 6667 if (out != first) { 6668 __ mov(out, ShifterOperand(first)); 6669 } 6670 return; 6671 } 6672 __ eor(out, first, ShifterOperand(value)); 6673} 6674 6675void InstructionCodeGeneratorARM::GenerateAddLongConst(Location out, 6676 Location first, 6677 uint64_t value) { 6678 Register out_low = out.AsRegisterPairLow<Register>(); 6679 Register out_high = out.AsRegisterPairHigh<Register>(); 6680 Register first_low = first.AsRegisterPairLow<Register>(); 6681 Register first_high = first.AsRegisterPairHigh<Register>(); 6682 uint32_t value_low = Low32Bits(value); 6683 uint32_t value_high = High32Bits(value); 6684 if (value_low == 0u) { 6685 if (out_low != first_low) { 6686 __ mov(out_low, ShifterOperand(first_low)); 6687 } 6688 __ AddConstant(out_high, first_high, value_high); 6689 return; 6690 } 6691 __ AddConstantSetFlags(out_low, first_low, value_low); 6692 ShifterOperand so; 6693 if (__ ShifterOperandCanHold(out_high, first_high, ADC, value_high, kCcDontCare, &so)) { 6694 __ adc(out_high, first_high, so); 6695 } else if (__ ShifterOperandCanHold(out_low, first_low, SBC, ~value_high, kCcDontCare, &so)) { 6696 __ sbc(out_high, first_high, so); 6697 } else { 6698 LOG(FATAL) << "Unexpected constant " << value_high; 6699 UNREACHABLE(); 6700 } 6701} 6702 6703void InstructionCodeGeneratorARM::HandleBitwiseOperation(HBinaryOperation* instruction) { 6704 LocationSummary* locations = instruction->GetLocations(); 6705 Location first = locations->InAt(0); 6706 Location second = locations->InAt(1); 6707 Location out = locations->Out(); 6708 6709 if (second.IsConstant()) { 6710 uint64_t value = static_cast<uint64_t>(Int64FromConstant(second.GetConstant())); 6711 uint32_t value_low = Low32Bits(value); 6712 if (instruction->GetResultType() == Primitive::kPrimInt) { 6713 Register first_reg = first.AsRegister<Register>(); 6714 Register out_reg = out.AsRegister<Register>(); 6715 if (instruction->IsAnd()) { 6716 GenerateAndConst(out_reg, first_reg, value_low); 6717 } else if (instruction->IsOr()) { 6718 GenerateOrrConst(out_reg, first_reg, value_low); 6719 } else { 6720 DCHECK(instruction->IsXor()); 6721 GenerateEorConst(out_reg, first_reg, value_low); 6722 } 6723 } else { 6724 DCHECK_EQ(instruction->GetResultType(), Primitive::kPrimLong); 6725 uint32_t value_high = High32Bits(value); 6726 Register first_low = first.AsRegisterPairLow<Register>(); 6727 Register first_high = first.AsRegisterPairHigh<Register>(); 6728 Register out_low = out.AsRegisterPairLow<Register>(); 6729 Register out_high = out.AsRegisterPairHigh<Register>(); 6730 if (instruction->IsAnd()) { 6731 GenerateAndConst(out_low, first_low, value_low); 6732 GenerateAndConst(out_high, first_high, value_high); 6733 } else if (instruction->IsOr()) { 6734 GenerateOrrConst(out_low, first_low, value_low); 6735 GenerateOrrConst(out_high, first_high, value_high); 6736 } else { 6737 DCHECK(instruction->IsXor()); 6738 GenerateEorConst(out_low, first_low, value_low); 6739 GenerateEorConst(out_high, first_high, value_high); 6740 } 6741 } 6742 return; 6743 } 6744 6745 if (instruction->GetResultType() == Primitive::kPrimInt) { 6746 Register first_reg = first.AsRegister<Register>(); 6747 ShifterOperand second_reg(second.AsRegister<Register>()); 6748 Register out_reg = out.AsRegister<Register>(); 6749 if (instruction->IsAnd()) { 6750 __ and_(out_reg, first_reg, second_reg); 6751 } else if (instruction->IsOr()) { 6752 __ orr(out_reg, first_reg, second_reg); 6753 } else { 6754 DCHECK(instruction->IsXor()); 6755 __ eor(out_reg, first_reg, second_reg); 6756 } 6757 } else { 6758 DCHECK_EQ(instruction->GetResultType(), Primitive::kPrimLong); 6759 Register first_low = first.AsRegisterPairLow<Register>(); 6760 Register first_high = first.AsRegisterPairHigh<Register>(); 6761 ShifterOperand second_low(second.AsRegisterPairLow<Register>()); 6762 ShifterOperand second_high(second.AsRegisterPairHigh<Register>()); 6763 Register out_low = out.AsRegisterPairLow<Register>(); 6764 Register out_high = out.AsRegisterPairHigh<Register>(); 6765 if (instruction->IsAnd()) { 6766 __ and_(out_low, first_low, second_low); 6767 __ and_(out_high, first_high, second_high); 6768 } else if (instruction->IsOr()) { 6769 __ orr(out_low, first_low, second_low); 6770 __ orr(out_high, first_high, second_high); 6771 } else { 6772 DCHECK(instruction->IsXor()); 6773 __ eor(out_low, first_low, second_low); 6774 __ eor(out_high, first_high, second_high); 6775 } 6776 } 6777} 6778 6779void InstructionCodeGeneratorARM::GenerateReferenceLoadOneRegister( 6780 HInstruction* instruction, 6781 Location out, 6782 uint32_t offset, 6783 Location maybe_temp, 6784 ReadBarrierOption read_barrier_option) { 6785 Register out_reg = out.AsRegister<Register>(); 6786 if (read_barrier_option == kWithReadBarrier) { 6787 CHECK(kEmitCompilerReadBarrier); 6788 DCHECK(maybe_temp.IsRegister()) << maybe_temp; 6789 if (kUseBakerReadBarrier) { 6790 // Load with fast path based Baker's read barrier. 6791 // /* HeapReference<Object> */ out = *(out + offset) 6792 codegen_->GenerateFieldLoadWithBakerReadBarrier( 6793 instruction, out, out_reg, offset, maybe_temp, /* needs_null_check */ false); 6794 } else { 6795 // Load with slow path based read barrier. 6796 // Save the value of `out` into `maybe_temp` before overwriting it 6797 // in the following move operation, as we will need it for the 6798 // read barrier below. 6799 __ Mov(maybe_temp.AsRegister<Register>(), out_reg); 6800 // /* HeapReference<Object> */ out = *(out + offset) 6801 __ LoadFromOffset(kLoadWord, out_reg, out_reg, offset); 6802 codegen_->GenerateReadBarrierSlow(instruction, out, out, maybe_temp, offset); 6803 } 6804 } else { 6805 // Plain load with no read barrier. 6806 // /* HeapReference<Object> */ out = *(out + offset) 6807 __ LoadFromOffset(kLoadWord, out_reg, out_reg, offset); 6808 __ MaybeUnpoisonHeapReference(out_reg); 6809 } 6810} 6811 6812void InstructionCodeGeneratorARM::GenerateReferenceLoadTwoRegisters( 6813 HInstruction* instruction, 6814 Location out, 6815 Location obj, 6816 uint32_t offset, 6817 Location maybe_temp, 6818 ReadBarrierOption read_barrier_option) { 6819 Register out_reg = out.AsRegister<Register>(); 6820 Register obj_reg = obj.AsRegister<Register>(); 6821 if (read_barrier_option == kWithReadBarrier) { 6822 CHECK(kEmitCompilerReadBarrier); 6823 if (kUseBakerReadBarrier) { 6824 DCHECK(maybe_temp.IsRegister()) << maybe_temp; 6825 // Load with fast path based Baker's read barrier. 6826 // /* HeapReference<Object> */ out = *(obj + offset) 6827 codegen_->GenerateFieldLoadWithBakerReadBarrier( 6828 instruction, out, obj_reg, offset, maybe_temp, /* needs_null_check */ false); 6829 } else { 6830 // Load with slow path based read barrier. 6831 // /* HeapReference<Object> */ out = *(obj + offset) 6832 __ LoadFromOffset(kLoadWord, out_reg, obj_reg, offset); 6833 codegen_->GenerateReadBarrierSlow(instruction, out, out, obj, offset); 6834 } 6835 } else { 6836 // Plain load with no read barrier. 6837 // /* HeapReference<Object> */ out = *(obj + offset) 6838 __ LoadFromOffset(kLoadWord, out_reg, obj_reg, offset); 6839 __ MaybeUnpoisonHeapReference(out_reg); 6840 } 6841} 6842 6843void InstructionCodeGeneratorARM::GenerateGcRootFieldLoad(HInstruction* instruction, 6844 Location root, 6845 Register obj, 6846 uint32_t offset, 6847 ReadBarrierOption read_barrier_option) { 6848 Register root_reg = root.AsRegister<Register>(); 6849 if (read_barrier_option == kWithReadBarrier) { 6850 DCHECK(kEmitCompilerReadBarrier); 6851 if (kUseBakerReadBarrier) { 6852 // Fast path implementation of art::ReadBarrier::BarrierForRoot when 6853 // Baker's read barrier are used: 6854 // 6855 // root = obj.field; 6856 // temp = Thread::Current()->pReadBarrierMarkReg ## root.reg() 6857 // if (temp != null) { 6858 // root = temp(root) 6859 // } 6860 6861 // /* GcRoot<mirror::Object> */ root = *(obj + offset) 6862 __ LoadFromOffset(kLoadWord, root_reg, obj, offset); 6863 static_assert( 6864 sizeof(mirror::CompressedReference<mirror::Object>) == sizeof(GcRoot<mirror::Object>), 6865 "art::mirror::CompressedReference<mirror::Object> and art::GcRoot<mirror::Object> " 6866 "have different sizes."); 6867 static_assert(sizeof(mirror::CompressedReference<mirror::Object>) == sizeof(int32_t), 6868 "art::mirror::CompressedReference<mirror::Object> and int32_t " 6869 "have different sizes."); 6870 6871 // Slow path marking the GC root `root`. 6872 Location temp = Location::RegisterLocation(LR); 6873 SlowPathCodeARM* slow_path = 6874 new (GetGraph()->GetArena()) ReadBarrierMarkSlowPathARM( 6875 instruction, 6876 root, 6877 /*entrypoint*/ temp); 6878 codegen_->AddSlowPath(slow_path); 6879 6880 // temp = Thread::Current()->pReadBarrierMarkReg ## root.reg() 6881 const int32_t entry_point_offset = 6882 CodeGenerator::GetReadBarrierMarkEntryPointsOffset<kArmPointerSize>(root.reg()); 6883 // Loading the entrypoint does not require a load acquire since it is only changed when 6884 // threads are suspended or running a checkpoint. 6885 __ LoadFromOffset(kLoadWord, temp.AsRegister<Register>(), TR, entry_point_offset); 6886 // The entrypoint is null when the GC is not marking, this prevents one load compared to 6887 // checking GetIsGcMarking. 6888 __ CompareAndBranchIfNonZero(temp.AsRegister<Register>(), slow_path->GetEntryLabel()); 6889 __ Bind(slow_path->GetExitLabel()); 6890 } else { 6891 // GC root loaded through a slow path for read barriers other 6892 // than Baker's. 6893 // /* GcRoot<mirror::Object>* */ root = obj + offset 6894 __ AddConstant(root_reg, obj, offset); 6895 // /* mirror::Object* */ root = root->Read() 6896 codegen_->GenerateReadBarrierForRootSlow(instruction, root, root); 6897 } 6898 } else { 6899 // Plain GC root load with no read barrier. 6900 // /* GcRoot<mirror::Object> */ root = *(obj + offset) 6901 __ LoadFromOffset(kLoadWord, root_reg, obj, offset); 6902 // Note that GC roots are not affected by heap poisoning, thus we 6903 // do not have to unpoison `root_reg` here. 6904 } 6905} 6906 6907void CodeGeneratorARM::GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction, 6908 Location ref, 6909 Register obj, 6910 uint32_t offset, 6911 Location temp, 6912 bool needs_null_check) { 6913 DCHECK(kEmitCompilerReadBarrier); 6914 DCHECK(kUseBakerReadBarrier); 6915 6916 // /* HeapReference<Object> */ ref = *(obj + offset) 6917 Location no_index = Location::NoLocation(); 6918 ScaleFactor no_scale_factor = TIMES_1; 6919 GenerateReferenceLoadWithBakerReadBarrier( 6920 instruction, ref, obj, offset, no_index, no_scale_factor, temp, needs_null_check); 6921} 6922 6923void CodeGeneratorARM::GenerateArrayLoadWithBakerReadBarrier(HInstruction* instruction, 6924 Location ref, 6925 Register obj, 6926 uint32_t data_offset, 6927 Location index, 6928 Location temp, 6929 bool needs_null_check) { 6930 DCHECK(kEmitCompilerReadBarrier); 6931 DCHECK(kUseBakerReadBarrier); 6932 6933 static_assert( 6934 sizeof(mirror::HeapReference<mirror::Object>) == sizeof(int32_t), 6935 "art::mirror::HeapReference<art::mirror::Object> and int32_t have different sizes."); 6936 // /* HeapReference<Object> */ ref = 6937 // *(obj + data_offset + index * sizeof(HeapReference<Object>)) 6938 ScaleFactor scale_factor = TIMES_4; 6939 GenerateReferenceLoadWithBakerReadBarrier( 6940 instruction, ref, obj, data_offset, index, scale_factor, temp, needs_null_check); 6941} 6942 6943void CodeGeneratorARM::GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction, 6944 Location ref, 6945 Register obj, 6946 uint32_t offset, 6947 Location index, 6948 ScaleFactor scale_factor, 6949 Location temp, 6950 bool needs_null_check, 6951 bool always_update_field, 6952 Register* temp2) { 6953 DCHECK(kEmitCompilerReadBarrier); 6954 DCHECK(kUseBakerReadBarrier); 6955 6956 // In slow path based read barriers, the read barrier call is 6957 // inserted after the original load. However, in fast path based 6958 // Baker's read barriers, we need to perform the load of 6959 // mirror::Object::monitor_ *before* the original reference load. 6960 // This load-load ordering is required by the read barrier. 6961 // The fast path/slow path (for Baker's algorithm) should look like: 6962 // 6963 // uint32_t rb_state = Lockword(obj->monitor_).ReadBarrierState(); 6964 // lfence; // Load fence or artificial data dependency to prevent load-load reordering 6965 // HeapReference<Object> ref = *src; // Original reference load. 6966 // bool is_gray = (rb_state == ReadBarrier::GrayState()); 6967 // if (is_gray) { 6968 // ref = ReadBarrier::Mark(ref); // Performed by runtime entrypoint slow path. 6969 // } 6970 // 6971 // Note: the original implementation in ReadBarrier::Barrier is 6972 // slightly more complex as it performs additional checks that we do 6973 // not do here for performance reasons. 6974 6975 Register ref_reg = ref.AsRegister<Register>(); 6976 Register temp_reg = temp.AsRegister<Register>(); 6977 uint32_t monitor_offset = mirror::Object::MonitorOffset().Int32Value(); 6978 6979 // /* int32_t */ monitor = obj->monitor_ 6980 __ LoadFromOffset(kLoadWord, temp_reg, obj, monitor_offset); 6981 if (needs_null_check) { 6982 MaybeRecordImplicitNullCheck(instruction); 6983 } 6984 // /* LockWord */ lock_word = LockWord(monitor) 6985 static_assert(sizeof(LockWord) == sizeof(int32_t), 6986 "art::LockWord and int32_t have different sizes."); 6987 6988 // Introduce a dependency on the lock_word including the rb_state, 6989 // which shall prevent load-load reordering without using 6990 // a memory barrier (which would be more expensive). 6991 // `obj` is unchanged by this operation, but its value now depends 6992 // on `temp_reg`. 6993 __ add(obj, obj, ShifterOperand(temp_reg, LSR, 32)); 6994 6995 // The actual reference load. 6996 if (index.IsValid()) { 6997 // Load types involving an "index": ArrayGet, 6998 // UnsafeGetObject/UnsafeGetObjectVolatile and UnsafeCASObject 6999 // intrinsics. 7000 // /* HeapReference<Object> */ ref = *(obj + offset + (index << scale_factor)) 7001 if (index.IsConstant()) { 7002 size_t computed_offset = 7003 (index.GetConstant()->AsIntConstant()->GetValue() << scale_factor) + offset; 7004 __ LoadFromOffset(kLoadWord, ref_reg, obj, computed_offset); 7005 } else { 7006 // Handle the special case of the 7007 // UnsafeGetObject/UnsafeGetObjectVolatile and UnsafeCASObject 7008 // intrinsics, which use a register pair as index ("long 7009 // offset"), of which only the low part contains data. 7010 Register index_reg = index.IsRegisterPair() 7011 ? index.AsRegisterPairLow<Register>() 7012 : index.AsRegister<Register>(); 7013 __ add(IP, obj, ShifterOperand(index_reg, LSL, scale_factor)); 7014 __ LoadFromOffset(kLoadWord, ref_reg, IP, offset); 7015 } 7016 } else { 7017 // /* HeapReference<Object> */ ref = *(obj + offset) 7018 __ LoadFromOffset(kLoadWord, ref_reg, obj, offset); 7019 } 7020 7021 // Object* ref = ref_addr->AsMirrorPtr() 7022 __ MaybeUnpoisonHeapReference(ref_reg); 7023 7024 // Slow path marking the object `ref` when it is gray. 7025 SlowPathCodeARM* slow_path; 7026 if (always_update_field) { 7027 DCHECK(temp2 != nullptr); 7028 // ReadBarrierMarkAndUpdateFieldSlowPathARM only supports address 7029 // of the form `obj + field_offset`, where `obj` is a register and 7030 // `field_offset` is a register pair (of which only the lower half 7031 // is used). Thus `offset` and `scale_factor` above are expected 7032 // to be null in this code path. 7033 DCHECK_EQ(offset, 0u); 7034 DCHECK_EQ(scale_factor, ScaleFactor::TIMES_1); 7035 slow_path = new (GetGraph()->GetArena()) ReadBarrierMarkAndUpdateFieldSlowPathARM( 7036 instruction, ref, obj, /* field_offset */ index, temp_reg, *temp2); 7037 } else { 7038 slow_path = new (GetGraph()->GetArena()) ReadBarrierMarkSlowPathARM(instruction, ref); 7039 } 7040 AddSlowPath(slow_path); 7041 7042 // if (rb_state == ReadBarrier::GrayState()) 7043 // ref = ReadBarrier::Mark(ref); 7044 // Given the numeric representation, it's enough to check the low bit of the 7045 // rb_state. We do that by shifting the bit out of the lock word with LSRS 7046 // which can be a 16-bit instruction unlike the TST immediate. 7047 static_assert(ReadBarrier::WhiteState() == 0, "Expecting white to have value 0"); 7048 static_assert(ReadBarrier::GrayState() == 1, "Expecting gray to have value 1"); 7049 __ Lsrs(temp_reg, temp_reg, LockWord::kReadBarrierStateShift + 1); 7050 __ b(slow_path->GetEntryLabel(), CS); // Carry flag is the last bit shifted out by LSRS. 7051 __ Bind(slow_path->GetExitLabel()); 7052} 7053 7054void CodeGeneratorARM::GenerateReadBarrierSlow(HInstruction* instruction, 7055 Location out, 7056 Location ref, 7057 Location obj, 7058 uint32_t offset, 7059 Location index) { 7060 DCHECK(kEmitCompilerReadBarrier); 7061 7062 // Insert a slow path based read barrier *after* the reference load. 7063 // 7064 // If heap poisoning is enabled, the unpoisoning of the loaded 7065 // reference will be carried out by the runtime within the slow 7066 // path. 7067 // 7068 // Note that `ref` currently does not get unpoisoned (when heap 7069 // poisoning is enabled), which is alright as the `ref` argument is 7070 // not used by the artReadBarrierSlow entry point. 7071 // 7072 // TODO: Unpoison `ref` when it is used by artReadBarrierSlow. 7073 SlowPathCodeARM* slow_path = new (GetGraph()->GetArena()) 7074 ReadBarrierForHeapReferenceSlowPathARM(instruction, out, ref, obj, offset, index); 7075 AddSlowPath(slow_path); 7076 7077 __ b(slow_path->GetEntryLabel()); 7078 __ Bind(slow_path->GetExitLabel()); 7079} 7080 7081void CodeGeneratorARM::MaybeGenerateReadBarrierSlow(HInstruction* instruction, 7082 Location out, 7083 Location ref, 7084 Location obj, 7085 uint32_t offset, 7086 Location index) { 7087 if (kEmitCompilerReadBarrier) { 7088 // Baker's read barriers shall be handled by the fast path 7089 // (CodeGeneratorARM::GenerateReferenceLoadWithBakerReadBarrier). 7090 DCHECK(!kUseBakerReadBarrier); 7091 // If heap poisoning is enabled, unpoisoning will be taken care of 7092 // by the runtime within the slow path. 7093 GenerateReadBarrierSlow(instruction, out, ref, obj, offset, index); 7094 } else if (kPoisonHeapReferences) { 7095 __ UnpoisonHeapReference(out.AsRegister<Register>()); 7096 } 7097} 7098 7099void CodeGeneratorARM::GenerateReadBarrierForRootSlow(HInstruction* instruction, 7100 Location out, 7101 Location root) { 7102 DCHECK(kEmitCompilerReadBarrier); 7103 7104 // Insert a slow path based read barrier *after* the GC root load. 7105 // 7106 // Note that GC roots are not affected by heap poisoning, so we do 7107 // not need to do anything special for this here. 7108 SlowPathCodeARM* slow_path = 7109 new (GetGraph()->GetArena()) ReadBarrierForRootSlowPathARM(instruction, out, root); 7110 AddSlowPath(slow_path); 7111 7112 __ b(slow_path->GetEntryLabel()); 7113 __ Bind(slow_path->GetExitLabel()); 7114} 7115 7116HInvokeStaticOrDirect::DispatchInfo CodeGeneratorARM::GetSupportedInvokeStaticOrDirectDispatch( 7117 const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info, 7118 HInvokeStaticOrDirect* invoke) { 7119 HInvokeStaticOrDirect::DispatchInfo dispatch_info = desired_dispatch_info; 7120 // We disable pc-relative load when there is an irreducible loop, as the optimization 7121 // is incompatible with it. 7122 // TODO: Create as many ArmDexCacheArraysBase instructions as needed for methods 7123 // with irreducible loops. 7124 if (GetGraph()->HasIrreducibleLoops() && 7125 (dispatch_info.method_load_kind == 7126 HInvokeStaticOrDirect::MethodLoadKind::kDexCachePcRelative)) { 7127 dispatch_info.method_load_kind = HInvokeStaticOrDirect::MethodLoadKind::kDexCacheViaMethod; 7128 } 7129 7130 if (dispatch_info.code_ptr_location == HInvokeStaticOrDirect::CodePtrLocation::kCallPCRelative) { 7131 const DexFile& outer_dex_file = GetGraph()->GetDexFile(); 7132 if (&outer_dex_file != invoke->GetTargetMethod().dex_file) { 7133 // Calls across dex files are more likely to exceed the available BL range, 7134 // so use absolute patch with fixup if available and kCallArtMethod otherwise. 7135 HInvokeStaticOrDirect::CodePtrLocation code_ptr_location = 7136 (desired_dispatch_info.method_load_kind == 7137 HInvokeStaticOrDirect::MethodLoadKind::kDirectAddressWithFixup) 7138 ? HInvokeStaticOrDirect::CodePtrLocation::kCallDirectWithFixup 7139 : HInvokeStaticOrDirect::CodePtrLocation::kCallArtMethod; 7140 return HInvokeStaticOrDirect::DispatchInfo { 7141 dispatch_info.method_load_kind, 7142 code_ptr_location, 7143 dispatch_info.method_load_data, 7144 0u 7145 }; 7146 } 7147 } 7148 return dispatch_info; 7149} 7150 7151Register CodeGeneratorARM::GetInvokeStaticOrDirectExtraParameter(HInvokeStaticOrDirect* invoke, 7152 Register temp) { 7153 DCHECK_EQ(invoke->InputCount(), invoke->GetNumberOfArguments() + 1u); 7154 Location location = invoke->GetLocations()->InAt(invoke->GetSpecialInputIndex()); 7155 if (!invoke->GetLocations()->Intrinsified()) { 7156 return location.AsRegister<Register>(); 7157 } 7158 // For intrinsics we allow any location, so it may be on the stack. 7159 if (!location.IsRegister()) { 7160 __ LoadFromOffset(kLoadWord, temp, SP, location.GetStackIndex()); 7161 return temp; 7162 } 7163 // For register locations, check if the register was saved. If so, get it from the stack. 7164 // Note: There is a chance that the register was saved but not overwritten, so we could 7165 // save one load. However, since this is just an intrinsic slow path we prefer this 7166 // simple and more robust approach rather that trying to determine if that's the case. 7167 SlowPathCode* slow_path = GetCurrentSlowPath(); 7168 DCHECK(slow_path != nullptr); // For intrinsified invokes the call is emitted on the slow path. 7169 if (slow_path->IsCoreRegisterSaved(location.AsRegister<Register>())) { 7170 int stack_offset = slow_path->GetStackOffsetOfCoreRegister(location.AsRegister<Register>()); 7171 __ LoadFromOffset(kLoadWord, temp, SP, stack_offset); 7172 return temp; 7173 } 7174 return location.AsRegister<Register>(); 7175} 7176 7177void CodeGeneratorARM::GenerateStaticOrDirectCall(HInvokeStaticOrDirect* invoke, Location temp) { 7178 // For better instruction scheduling we load the direct code pointer before the method pointer. 7179 switch (invoke->GetCodePtrLocation()) { 7180 case HInvokeStaticOrDirect::CodePtrLocation::kCallDirectWithFixup: 7181 // LR = code address from literal pool with link-time patch. 7182 __ LoadLiteral(LR, DeduplicateMethodCodeLiteral(invoke->GetTargetMethod())); 7183 break; 7184 case HInvokeStaticOrDirect::CodePtrLocation::kCallDirect: 7185 // LR = invoke->GetDirectCodePtr(); 7186 __ LoadImmediate(LR, invoke->GetDirectCodePtr()); 7187 break; 7188 default: 7189 break; 7190 } 7191 7192 Location callee_method = temp; // For all kinds except kRecursive, callee will be in temp. 7193 switch (invoke->GetMethodLoadKind()) { 7194 case HInvokeStaticOrDirect::MethodLoadKind::kStringInit: { 7195 uint32_t offset = 7196 GetThreadOffset<kArmPointerSize>(invoke->GetStringInitEntryPoint()).Int32Value(); 7197 // temp = thread->string_init_entrypoint 7198 __ LoadFromOffset(kLoadWord, temp.AsRegister<Register>(), TR, offset); 7199 break; 7200 } 7201 case HInvokeStaticOrDirect::MethodLoadKind::kRecursive: 7202 callee_method = invoke->GetLocations()->InAt(invoke->GetSpecialInputIndex()); 7203 break; 7204 case HInvokeStaticOrDirect::MethodLoadKind::kDirectAddress: 7205 __ LoadImmediate(temp.AsRegister<Register>(), invoke->GetMethodAddress()); 7206 break; 7207 case HInvokeStaticOrDirect::MethodLoadKind::kDirectAddressWithFixup: 7208 __ LoadLiteral(temp.AsRegister<Register>(), 7209 DeduplicateMethodAddressLiteral(invoke->GetTargetMethod())); 7210 break; 7211 case HInvokeStaticOrDirect::MethodLoadKind::kDexCachePcRelative: { 7212 HArmDexCacheArraysBase* base = 7213 invoke->InputAt(invoke->GetSpecialInputIndex())->AsArmDexCacheArraysBase(); 7214 Register base_reg = GetInvokeStaticOrDirectExtraParameter(invoke, 7215 temp.AsRegister<Register>()); 7216 int32_t offset = invoke->GetDexCacheArrayOffset() - base->GetElementOffset(); 7217 __ LoadFromOffset(kLoadWord, temp.AsRegister<Register>(), base_reg, offset); 7218 break; 7219 } 7220 case HInvokeStaticOrDirect::MethodLoadKind::kDexCacheViaMethod: { 7221 Location current_method = invoke->GetLocations()->InAt(invoke->GetSpecialInputIndex()); 7222 Register method_reg; 7223 Register reg = temp.AsRegister<Register>(); 7224 if (current_method.IsRegister()) { 7225 method_reg = current_method.AsRegister<Register>(); 7226 } else { 7227 DCHECK(invoke->GetLocations()->Intrinsified()); 7228 DCHECK(!current_method.IsValid()); 7229 method_reg = reg; 7230 __ LoadFromOffset(kLoadWord, reg, SP, kCurrentMethodStackOffset); 7231 } 7232 // /* ArtMethod*[] */ temp = temp.ptr_sized_fields_->dex_cache_resolved_methods_; 7233 __ LoadFromOffset(kLoadWord, 7234 reg, 7235 method_reg, 7236 ArtMethod::DexCacheResolvedMethodsOffset(kArmPointerSize).Int32Value()); 7237 // temp = temp[index_in_cache]; 7238 // Note: Don't use invoke->GetTargetMethod() as it may point to a different dex file. 7239 uint32_t index_in_cache = invoke->GetDexMethodIndex(); 7240 __ LoadFromOffset(kLoadWord, reg, reg, CodeGenerator::GetCachePointerOffset(index_in_cache)); 7241 break; 7242 } 7243 } 7244 7245 switch (invoke->GetCodePtrLocation()) { 7246 case HInvokeStaticOrDirect::CodePtrLocation::kCallSelf: 7247 __ bl(GetFrameEntryLabel()); 7248 break; 7249 case HInvokeStaticOrDirect::CodePtrLocation::kCallPCRelative: 7250 relative_call_patches_.emplace_back(*invoke->GetTargetMethod().dex_file, 7251 invoke->GetTargetMethod().dex_method_index); 7252 __ BindTrackedLabel(&relative_call_patches_.back().label); 7253 // Arbitrarily branch to the BL itself, override at link time. 7254 __ bl(&relative_call_patches_.back().label); 7255 break; 7256 case HInvokeStaticOrDirect::CodePtrLocation::kCallDirectWithFixup: 7257 case HInvokeStaticOrDirect::CodePtrLocation::kCallDirect: 7258 // LR prepared above for better instruction scheduling. 7259 // LR() 7260 __ blx(LR); 7261 break; 7262 case HInvokeStaticOrDirect::CodePtrLocation::kCallArtMethod: 7263 // LR = callee_method->entry_point_from_quick_compiled_code_ 7264 __ LoadFromOffset( 7265 kLoadWord, LR, callee_method.AsRegister<Register>(), 7266 ArtMethod::EntryPointFromQuickCompiledCodeOffset(kArmPointerSize).Int32Value()); 7267 // LR() 7268 __ blx(LR); 7269 break; 7270 } 7271 7272 DCHECK(!IsLeafMethod()); 7273} 7274 7275void CodeGeneratorARM::GenerateVirtualCall(HInvokeVirtual* invoke, Location temp_location) { 7276 Register temp = temp_location.AsRegister<Register>(); 7277 uint32_t method_offset = mirror::Class::EmbeddedVTableEntryOffset( 7278 invoke->GetVTableIndex(), kArmPointerSize).Uint32Value(); 7279 7280 // Use the calling convention instead of the location of the receiver, as 7281 // intrinsics may have put the receiver in a different register. In the intrinsics 7282 // slow path, the arguments have been moved to the right place, so here we are 7283 // guaranteed that the receiver is the first register of the calling convention. 7284 InvokeDexCallingConvention calling_convention; 7285 Register receiver = calling_convention.GetRegisterAt(0); 7286 uint32_t class_offset = mirror::Object::ClassOffset().Int32Value(); 7287 // /* HeapReference<Class> */ temp = receiver->klass_ 7288 __ LoadFromOffset(kLoadWord, temp, receiver, class_offset); 7289 MaybeRecordImplicitNullCheck(invoke); 7290 // Instead of simply (possibly) unpoisoning `temp` here, we should 7291 // emit a read barrier for the previous class reference load. 7292 // However this is not required in practice, as this is an 7293 // intermediate/temporary reference and because the current 7294 // concurrent copying collector keeps the from-space memory 7295 // intact/accessible until the end of the marking phase (the 7296 // concurrent copying collector may not in the future). 7297 __ MaybeUnpoisonHeapReference(temp); 7298 // temp = temp->GetMethodAt(method_offset); 7299 uint32_t entry_point = ArtMethod::EntryPointFromQuickCompiledCodeOffset( 7300 kArmPointerSize).Int32Value(); 7301 __ LoadFromOffset(kLoadWord, temp, temp, method_offset); 7302 // LR = temp->GetEntryPoint(); 7303 __ LoadFromOffset(kLoadWord, LR, temp, entry_point); 7304 // LR(); 7305 __ blx(LR); 7306} 7307 7308CodeGeneratorARM::PcRelativePatchInfo* CodeGeneratorARM::NewPcRelativeStringPatch( 7309 const DexFile& dex_file, uint32_t string_index) { 7310 return NewPcRelativePatch(dex_file, string_index, &pc_relative_string_patches_); 7311} 7312 7313CodeGeneratorARM::PcRelativePatchInfo* CodeGeneratorARM::NewPcRelativeTypePatch( 7314 const DexFile& dex_file, uint32_t type_index) { 7315 return NewPcRelativePatch(dex_file, type_index, &pc_relative_type_patches_); 7316} 7317 7318CodeGeneratorARM::PcRelativePatchInfo* CodeGeneratorARM::NewPcRelativeDexCacheArrayPatch( 7319 const DexFile& dex_file, uint32_t element_offset) { 7320 return NewPcRelativePatch(dex_file, element_offset, &pc_relative_dex_cache_patches_); 7321} 7322 7323CodeGeneratorARM::PcRelativePatchInfo* CodeGeneratorARM::NewPcRelativePatch( 7324 const DexFile& dex_file, uint32_t offset_or_index, ArenaDeque<PcRelativePatchInfo>* patches) { 7325 patches->emplace_back(dex_file, offset_or_index); 7326 return &patches->back(); 7327} 7328 7329Literal* CodeGeneratorARM::DeduplicateBootImageStringLiteral(const DexFile& dex_file, 7330 uint32_t string_index) { 7331 return boot_image_string_patches_.GetOrCreate( 7332 StringReference(&dex_file, string_index), 7333 [this]() { return __ NewLiteral<uint32_t>(/* placeholder */ 0u); }); 7334} 7335 7336Literal* CodeGeneratorARM::DeduplicateBootImageTypeLiteral(const DexFile& dex_file, 7337 uint32_t type_index) { 7338 return boot_image_type_patches_.GetOrCreate( 7339 TypeReference(&dex_file, type_index), 7340 [this]() { return __ NewLiteral<uint32_t>(/* placeholder */ 0u); }); 7341} 7342 7343Literal* CodeGeneratorARM::DeduplicateBootImageAddressLiteral(uint32_t address) { 7344 bool needs_patch = GetCompilerOptions().GetIncludePatchInformation(); 7345 Uint32ToLiteralMap* map = needs_patch ? &boot_image_address_patches_ : &uint32_literals_; 7346 return DeduplicateUint32Literal(dchecked_integral_cast<uint32_t>(address), map); 7347} 7348 7349Literal* CodeGeneratorARM::DeduplicateDexCacheAddressLiteral(uint32_t address) { 7350 return DeduplicateUint32Literal(address, &uint32_literals_); 7351} 7352 7353Literal* CodeGeneratorARM::DeduplicateJitStringLiteral(const DexFile& dex_file, 7354 uint32_t string_index) { 7355 jit_string_roots_.Overwrite(StringReference(&dex_file, string_index), /* placeholder */ 0u); 7356 return jit_string_patches_.GetOrCreate( 7357 StringReference(&dex_file, string_index), 7358 [this]() { return __ NewLiteral<uint32_t>(/* placeholder */ 0u); }); 7359} 7360 7361template <LinkerPatch (*Factory)(size_t, const DexFile*, uint32_t, uint32_t)> 7362inline void CodeGeneratorARM::EmitPcRelativeLinkerPatches( 7363 const ArenaDeque<PcRelativePatchInfo>& infos, 7364 ArenaVector<LinkerPatch>* linker_patches) { 7365 for (const PcRelativePatchInfo& info : infos) { 7366 const DexFile& dex_file = info.target_dex_file; 7367 size_t offset_or_index = info.offset_or_index; 7368 DCHECK(info.add_pc_label.IsBound()); 7369 uint32_t add_pc_offset = dchecked_integral_cast<uint32_t>(info.add_pc_label.Position()); 7370 // Add MOVW patch. 7371 DCHECK(info.movw_label.IsBound()); 7372 uint32_t movw_offset = dchecked_integral_cast<uint32_t>(info.movw_label.Position()); 7373 linker_patches->push_back(Factory(movw_offset, &dex_file, add_pc_offset, offset_or_index)); 7374 // Add MOVT patch. 7375 DCHECK(info.movt_label.IsBound()); 7376 uint32_t movt_offset = dchecked_integral_cast<uint32_t>(info.movt_label.Position()); 7377 linker_patches->push_back(Factory(movt_offset, &dex_file, add_pc_offset, offset_or_index)); 7378 } 7379} 7380 7381void CodeGeneratorARM::EmitLinkerPatches(ArenaVector<LinkerPatch>* linker_patches) { 7382 DCHECK(linker_patches->empty()); 7383 size_t size = 7384 method_patches_.size() + 7385 call_patches_.size() + 7386 relative_call_patches_.size() + 7387 /* MOVW+MOVT for each entry */ 2u * pc_relative_dex_cache_patches_.size() + 7388 boot_image_string_patches_.size() + 7389 /* MOVW+MOVT for each entry */ 2u * pc_relative_string_patches_.size() + 7390 boot_image_type_patches_.size() + 7391 /* MOVW+MOVT for each entry */ 2u * pc_relative_type_patches_.size() + 7392 boot_image_address_patches_.size(); 7393 linker_patches->reserve(size); 7394 for (const auto& entry : method_patches_) { 7395 const MethodReference& target_method = entry.first; 7396 Literal* literal = entry.second; 7397 DCHECK(literal->GetLabel()->IsBound()); 7398 uint32_t literal_offset = literal->GetLabel()->Position(); 7399 linker_patches->push_back(LinkerPatch::MethodPatch(literal_offset, 7400 target_method.dex_file, 7401 target_method.dex_method_index)); 7402 } 7403 for (const auto& entry : call_patches_) { 7404 const MethodReference& target_method = entry.first; 7405 Literal* literal = entry.second; 7406 DCHECK(literal->GetLabel()->IsBound()); 7407 uint32_t literal_offset = literal->GetLabel()->Position(); 7408 linker_patches->push_back(LinkerPatch::CodePatch(literal_offset, 7409 target_method.dex_file, 7410 target_method.dex_method_index)); 7411 } 7412 for (const PatchInfo<Label>& info : relative_call_patches_) { 7413 uint32_t literal_offset = info.label.Position(); 7414 linker_patches->push_back( 7415 LinkerPatch::RelativeCodePatch(literal_offset, &info.dex_file, info.index)); 7416 } 7417 EmitPcRelativeLinkerPatches<LinkerPatch::DexCacheArrayPatch>(pc_relative_dex_cache_patches_, 7418 linker_patches); 7419 for (const auto& entry : boot_image_string_patches_) { 7420 const StringReference& target_string = entry.first; 7421 Literal* literal = entry.second; 7422 DCHECK(literal->GetLabel()->IsBound()); 7423 uint32_t literal_offset = literal->GetLabel()->Position(); 7424 linker_patches->push_back(LinkerPatch::StringPatch(literal_offset, 7425 target_string.dex_file, 7426 target_string.string_index)); 7427 } 7428 if (!GetCompilerOptions().IsBootImage()) { 7429 EmitPcRelativeLinkerPatches<LinkerPatch::StringBssEntryPatch>(pc_relative_string_patches_, 7430 linker_patches); 7431 } else { 7432 EmitPcRelativeLinkerPatches<LinkerPatch::RelativeStringPatch>(pc_relative_string_patches_, 7433 linker_patches); 7434 } 7435 for (const auto& entry : boot_image_type_patches_) { 7436 const TypeReference& target_type = entry.first; 7437 Literal* literal = entry.second; 7438 DCHECK(literal->GetLabel()->IsBound()); 7439 uint32_t literal_offset = literal->GetLabel()->Position(); 7440 linker_patches->push_back(LinkerPatch::TypePatch(literal_offset, 7441 target_type.dex_file, 7442 target_type.type_index)); 7443 } 7444 EmitPcRelativeLinkerPatches<LinkerPatch::RelativeTypePatch>(pc_relative_type_patches_, 7445 linker_patches); 7446 for (const auto& entry : boot_image_address_patches_) { 7447 DCHECK(GetCompilerOptions().GetIncludePatchInformation()); 7448 Literal* literal = entry.second; 7449 DCHECK(literal->GetLabel()->IsBound()); 7450 uint32_t literal_offset = literal->GetLabel()->Position(); 7451 linker_patches->push_back(LinkerPatch::RecordPosition(literal_offset)); 7452 } 7453} 7454 7455Literal* CodeGeneratorARM::DeduplicateUint32Literal(uint32_t value, Uint32ToLiteralMap* map) { 7456 return map->GetOrCreate( 7457 value, 7458 [this, value]() { return __ NewLiteral<uint32_t>(value); }); 7459} 7460 7461Literal* CodeGeneratorARM::DeduplicateMethodLiteral(MethodReference target_method, 7462 MethodToLiteralMap* map) { 7463 return map->GetOrCreate( 7464 target_method, 7465 [this]() { return __ NewLiteral<uint32_t>(/* placeholder */ 0u); }); 7466} 7467 7468Literal* CodeGeneratorARM::DeduplicateMethodAddressLiteral(MethodReference target_method) { 7469 return DeduplicateMethodLiteral(target_method, &method_patches_); 7470} 7471 7472Literal* CodeGeneratorARM::DeduplicateMethodCodeLiteral(MethodReference target_method) { 7473 return DeduplicateMethodLiteral(target_method, &call_patches_); 7474} 7475 7476void LocationsBuilderARM::VisitMultiplyAccumulate(HMultiplyAccumulate* instr) { 7477 LocationSummary* locations = 7478 new (GetGraph()->GetArena()) LocationSummary(instr, LocationSummary::kNoCall); 7479 locations->SetInAt(HMultiplyAccumulate::kInputAccumulatorIndex, 7480 Location::RequiresRegister()); 7481 locations->SetInAt(HMultiplyAccumulate::kInputMulLeftIndex, Location::RequiresRegister()); 7482 locations->SetInAt(HMultiplyAccumulate::kInputMulRightIndex, Location::RequiresRegister()); 7483 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap); 7484} 7485 7486void InstructionCodeGeneratorARM::VisitMultiplyAccumulate(HMultiplyAccumulate* instr) { 7487 LocationSummary* locations = instr->GetLocations(); 7488 Register res = locations->Out().AsRegister<Register>(); 7489 Register accumulator = 7490 locations->InAt(HMultiplyAccumulate::kInputAccumulatorIndex).AsRegister<Register>(); 7491 Register mul_left = 7492 locations->InAt(HMultiplyAccumulate::kInputMulLeftIndex).AsRegister<Register>(); 7493 Register mul_right = 7494 locations->InAt(HMultiplyAccumulate::kInputMulRightIndex).AsRegister<Register>(); 7495 7496 if (instr->GetOpKind() == HInstruction::kAdd) { 7497 __ mla(res, mul_left, mul_right, accumulator); 7498 } else { 7499 __ mls(res, mul_left, mul_right, accumulator); 7500 } 7501} 7502 7503void LocationsBuilderARM::VisitBoundType(HBoundType* instruction ATTRIBUTE_UNUSED) { 7504 // Nothing to do, this should be removed during prepare for register allocator. 7505 LOG(FATAL) << "Unreachable"; 7506} 7507 7508void InstructionCodeGeneratorARM::VisitBoundType(HBoundType* instruction ATTRIBUTE_UNUSED) { 7509 // Nothing to do, this should be removed during prepare for register allocator. 7510 LOG(FATAL) << "Unreachable"; 7511} 7512 7513// Simple implementation of packed switch - generate cascaded compare/jumps. 7514void LocationsBuilderARM::VisitPackedSwitch(HPackedSwitch* switch_instr) { 7515 LocationSummary* locations = 7516 new (GetGraph()->GetArena()) LocationSummary(switch_instr, LocationSummary::kNoCall); 7517 locations->SetInAt(0, Location::RequiresRegister()); 7518 if (switch_instr->GetNumEntries() > kPackedSwitchCompareJumpThreshold && 7519 codegen_->GetAssembler()->IsThumb()) { 7520 locations->AddTemp(Location::RequiresRegister()); // We need a temp for the table base. 7521 if (switch_instr->GetStartValue() != 0) { 7522 locations->AddTemp(Location::RequiresRegister()); // We need a temp for the bias. 7523 } 7524 } 7525} 7526 7527void InstructionCodeGeneratorARM::VisitPackedSwitch(HPackedSwitch* switch_instr) { 7528 int32_t lower_bound = switch_instr->GetStartValue(); 7529 uint32_t num_entries = switch_instr->GetNumEntries(); 7530 LocationSummary* locations = switch_instr->GetLocations(); 7531 Register value_reg = locations->InAt(0).AsRegister<Register>(); 7532 HBasicBlock* default_block = switch_instr->GetDefaultBlock(); 7533 7534 if (num_entries <= kPackedSwitchCompareJumpThreshold || !codegen_->GetAssembler()->IsThumb()) { 7535 // Create a series of compare/jumps. 7536 Register temp_reg = IP; 7537 // Note: It is fine for the below AddConstantSetFlags() using IP register to temporarily store 7538 // the immediate, because IP is used as the destination register. For the other 7539 // AddConstantSetFlags() and GenerateCompareWithImmediate(), the immediate values are constant, 7540 // and they can be encoded in the instruction without making use of IP register. 7541 __ AddConstantSetFlags(temp_reg, value_reg, -lower_bound); 7542 7543 const ArenaVector<HBasicBlock*>& successors = switch_instr->GetBlock()->GetSuccessors(); 7544 // Jump to successors[0] if value == lower_bound. 7545 __ b(codegen_->GetLabelOf(successors[0]), EQ); 7546 int32_t last_index = 0; 7547 for (; num_entries - last_index > 2; last_index += 2) { 7548 __ AddConstantSetFlags(temp_reg, temp_reg, -2); 7549 // Jump to successors[last_index + 1] if value < case_value[last_index + 2]. 7550 __ b(codegen_->GetLabelOf(successors[last_index + 1]), LO); 7551 // Jump to successors[last_index + 2] if value == case_value[last_index + 2]. 7552 __ b(codegen_->GetLabelOf(successors[last_index + 2]), EQ); 7553 } 7554 if (num_entries - last_index == 2) { 7555 // The last missing case_value. 7556 __ CmpConstant(temp_reg, 1); 7557 __ b(codegen_->GetLabelOf(successors[last_index + 1]), EQ); 7558 } 7559 7560 // And the default for any other value. 7561 if (!codegen_->GoesToNextBlock(switch_instr->GetBlock(), default_block)) { 7562 __ b(codegen_->GetLabelOf(default_block)); 7563 } 7564 } else { 7565 // Create a table lookup. 7566 Register temp_reg = locations->GetTemp(0).AsRegister<Register>(); 7567 7568 // Materialize a pointer to the switch table 7569 std::vector<Label*> labels(num_entries); 7570 const ArenaVector<HBasicBlock*>& successors = switch_instr->GetBlock()->GetSuccessors(); 7571 for (uint32_t i = 0; i < num_entries; i++) { 7572 labels[i] = codegen_->GetLabelOf(successors[i]); 7573 } 7574 JumpTable* table = __ CreateJumpTable(std::move(labels), temp_reg); 7575 7576 // Remove the bias. 7577 Register key_reg; 7578 if (lower_bound != 0) { 7579 key_reg = locations->GetTemp(1).AsRegister<Register>(); 7580 __ AddConstant(key_reg, value_reg, -lower_bound); 7581 } else { 7582 key_reg = value_reg; 7583 } 7584 7585 // Check whether the value is in the table, jump to default block if not. 7586 __ CmpConstant(key_reg, num_entries - 1); 7587 __ b(codegen_->GetLabelOf(default_block), Condition::HI); 7588 7589 // Load the displacement from the table. 7590 __ ldr(temp_reg, Address(temp_reg, key_reg, Shift::LSL, 2)); 7591 7592 // Dispatch is a direct add to the PC (for Thumb2). 7593 __ EmitJumpTableDispatch(table, temp_reg); 7594 } 7595} 7596 7597void LocationsBuilderARM::VisitArmDexCacheArraysBase(HArmDexCacheArraysBase* base) { 7598 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(base); 7599 locations->SetOut(Location::RequiresRegister()); 7600} 7601 7602void InstructionCodeGeneratorARM::VisitArmDexCacheArraysBase(HArmDexCacheArraysBase* base) { 7603 Register base_reg = base->GetLocations()->Out().AsRegister<Register>(); 7604 CodeGeneratorARM::PcRelativePatchInfo* labels = 7605 codegen_->NewPcRelativeDexCacheArrayPatch(base->GetDexFile(), base->GetElementOffset()); 7606 __ BindTrackedLabel(&labels->movw_label); 7607 __ movw(base_reg, /* placeholder */ 0u); 7608 __ BindTrackedLabel(&labels->movt_label); 7609 __ movt(base_reg, /* placeholder */ 0u); 7610 __ BindTrackedLabel(&labels->add_pc_label); 7611 __ add(base_reg, base_reg, ShifterOperand(PC)); 7612} 7613 7614void CodeGeneratorARM::MoveFromReturnRegister(Location trg, Primitive::Type type) { 7615 if (!trg.IsValid()) { 7616 DCHECK_EQ(type, Primitive::kPrimVoid); 7617 return; 7618 } 7619 7620 DCHECK_NE(type, Primitive::kPrimVoid); 7621 7622 Location return_loc = InvokeDexCallingConventionVisitorARM().GetReturnLocation(type); 7623 if (return_loc.Equals(trg)) { 7624 return; 7625 } 7626 7627 // TODO: Consider pairs in the parallel move resolver, then this could be nicely merged 7628 // with the last branch. 7629 if (type == Primitive::kPrimLong) { 7630 HParallelMove parallel_move(GetGraph()->GetArena()); 7631 parallel_move.AddMove(return_loc.ToLow(), trg.ToLow(), Primitive::kPrimInt, nullptr); 7632 parallel_move.AddMove(return_loc.ToHigh(), trg.ToHigh(), Primitive::kPrimInt, nullptr); 7633 GetMoveResolver()->EmitNativeCode(¶llel_move); 7634 } else if (type == Primitive::kPrimDouble) { 7635 HParallelMove parallel_move(GetGraph()->GetArena()); 7636 parallel_move.AddMove(return_loc.ToLow(), trg.ToLow(), Primitive::kPrimFloat, nullptr); 7637 parallel_move.AddMove(return_loc.ToHigh(), trg.ToHigh(), Primitive::kPrimFloat, nullptr); 7638 GetMoveResolver()->EmitNativeCode(¶llel_move); 7639 } else { 7640 // Let the parallel move resolver take care of all of this. 7641 HParallelMove parallel_move(GetGraph()->GetArena()); 7642 parallel_move.AddMove(return_loc, trg, type, nullptr); 7643 GetMoveResolver()->EmitNativeCode(¶llel_move); 7644 } 7645} 7646 7647void LocationsBuilderARM::VisitClassTableGet(HClassTableGet* instruction) { 7648 LocationSummary* locations = 7649 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall); 7650 locations->SetInAt(0, Location::RequiresRegister()); 7651 locations->SetOut(Location::RequiresRegister()); 7652} 7653 7654void InstructionCodeGeneratorARM::VisitClassTableGet(HClassTableGet* instruction) { 7655 LocationSummary* locations = instruction->GetLocations(); 7656 if (instruction->GetTableKind() == HClassTableGet::TableKind::kVTable) { 7657 uint32_t method_offset = mirror::Class::EmbeddedVTableEntryOffset( 7658 instruction->GetIndex(), kArmPointerSize).SizeValue(); 7659 __ LoadFromOffset(kLoadWord, 7660 locations->Out().AsRegister<Register>(), 7661 locations->InAt(0).AsRegister<Register>(), 7662 method_offset); 7663 } else { 7664 uint32_t method_offset = static_cast<uint32_t>(ImTable::OffsetOfElement( 7665 instruction->GetIndex(), kArmPointerSize)); 7666 __ LoadFromOffset(kLoadWord, 7667 locations->Out().AsRegister<Register>(), 7668 locations->InAt(0).AsRegister<Register>(), 7669 mirror::Class::ImtPtrOffset(kArmPointerSize).Uint32Value()); 7670 __ LoadFromOffset(kLoadWord, 7671 locations->Out().AsRegister<Register>(), 7672 locations->Out().AsRegister<Register>(), 7673 method_offset); 7674 } 7675} 7676 7677void CodeGeneratorARM::EmitJitRootPatches(uint8_t* code, const uint8_t* roots_data) { 7678 for (const auto& entry : jit_string_patches_) { 7679 const auto& it = jit_string_roots_.find(entry.first); 7680 DCHECK(it != jit_string_roots_.end()); 7681 size_t index_in_table = it->second; 7682 Literal* literal = entry.second; 7683 DCHECK(literal->GetLabel()->IsBound()); 7684 uint32_t literal_offset = literal->GetLabel()->Position(); 7685 uintptr_t address = 7686 reinterpret_cast<uintptr_t>(roots_data) + index_in_table * sizeof(GcRoot<mirror::Object>); 7687 uint8_t* data = code + literal_offset; 7688 reinterpret_cast<uint32_t*>(data)[0] = dchecked_integral_cast<uint32_t>(address); 7689 } 7690} 7691 7692#undef __ 7693#undef QUICK_ENTRY_POINT 7694 7695} // namespace arm 7696} // namespace art 7697