1/** @file 2* SMSC LAN91x series Network Controller Driver. 3* 4* Copyright (c) 2013 Linaro.org 5* 6* This program and the accompanying materials are licensed and 7* made available under the terms and conditions of the BSD License 8* which accompanies this distribution. The full text of the license 9* may be found at: http://opensource.org/licenses/bsd-license.php 10* 11* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13* 14**/ 15 16#ifndef __LAN91XDXEHW_H__ 17#define __LAN91XDXEHW_H__ 18 19#include <Base.h> 20 21#define MakeRegister(Bank, Offset) (((Bank) << 8) | (Offset)) 22#define RegisterToBank(Register) (((Register) >> 8) & 0x07) 23#define RegisterToOffset(Register) ((Register) & 0x0f) 24 25/*--------------------------------------------------------------------------------------------------------------------- 26 27 SMSC LAN91x Registers 28 29---------------------------------------------------------------------------------------------------------------------*/ 30#define LAN91X_BANK_OFFSET 0xe // Bank Select Register (all banks) 31 32#define LAN91X_TCR MakeRegister (0, 0x0) // Transmit Control Register 33#define LAN91X_EPHSR MakeRegister (0, 0x2) // EPH Status Register 34#define LAN91X_RCR MakeRegister (0, 0x4) // Receive Control Register 35#define LAN91X_ECR MakeRegister (0, 0x6) // Counter Register 36#define LAN91X_MIR MakeRegister (0, 0x8) // Memory Information Register 37#define LAN91X_RPCR MakeRegister (0, 0xa) // Receive/Phy Control Register 38 39#define LAN91X_CR MakeRegister (1, 0x0) // Configuration Register 40#define LAN91X_BAR MakeRegister (1, 0x2) // Base Address Register 41#define LAN91X_IAR0 MakeRegister (1, 0x4) // Individual Address Register 0 42#define LAN91X_IAR1 MakeRegister (1, 0x5) // Individual Address Register 1 43#define LAN91X_IAR2 MakeRegister (1, 0x6) // Individual Address Register 2 44#define LAN91X_IAR3 MakeRegister (1, 0x7) // Individual Address Register 3 45#define LAN91X_IAR4 MakeRegister (1, 0x8) // Individual Address Register 4 46#define LAN91X_IAR5 MakeRegister (1, 0x9) // Individual Address Register 5 47#define LAN91X_GPR MakeRegister (1, 0xa) // General Purpose Register 48#define LAN91X_CTR MakeRegister (1, 0xc) // Control Register 49 50#define LAN91X_MMUCR MakeRegister (2, 0x0) // MMU Command Register 51#define LAN91X_PNR MakeRegister (2, 0x2) // Packet Number Register 52#define LAN91X_ARR MakeRegister (2, 0x3) // Allocation Result Register 53#define LAN91X_FIFO MakeRegister (2, 0x4) // FIFO Ports Register 54#define LAN91X_PTR MakeRegister (2, 0x6) // Pointer Register 55#define LAN91X_DATA0 MakeRegister (2, 0x8) // Data Register 0 56#define LAN91X_DATA1 MakeRegister (2, 0x9) // Data Register 1 57#define LAN91X_DATA2 MakeRegister (2, 0xa) // Data Register 2 58#define LAN91X_DATA3 MakeRegister (2, 0xb) // Data Register 3 59#define LAN91X_IST MakeRegister (2, 0xc) // Interrupt Status Register 60#define LAN91X_MSK MakeRegister (2, 0xd) // Interrupt Mask Register 61 62#define LAN91X_MT0 MakeRegister (3, 0x0) // Multicast Table Register 0 63#define LAN91X_MT1 MakeRegister (3, 0x1) // Multicast Table Register 1 64#define LAN91X_MT2 MakeRegister (3, 0x2) // Multicast Table Register 2 65#define LAN91X_MT3 MakeRegister (3, 0x3) // Multicast Table Register 3 66#define LAN91X_MT4 MakeRegister (3, 0x4) // Multicast Table Register 4 67#define LAN91X_MT5 MakeRegister (3, 0x5) // Multicast Table Register 5 68#define LAN91X_MT6 MakeRegister (3, 0x6) // Multicast Table Register 6 69#define LAN91X_MT7 MakeRegister (3, 0x7) // Multicast Table Register 7 70#define LAN91X_MGMT MakeRegister (3, 0x8) // Management Interface Register 71#define LAN91X_REV MakeRegister (3, 0xa) // Revision Register 72#define LAN91X_RCV MakeRegister (3, 0xc) // RCV Register 73 74// Transmit Control Register Bits 75#define TCR_TXENA BIT0 76#define TCR_LOOP BIT1 77#define TCR_FORCOL BIT2 78#define TCR_PAD_EN BIT7 79#define TCR_NOCRC BIT8 80#define TCR_MON_CSN BIT10 81#define TCR_FDUPLX BIT11 82#define TCR_STP_SQET BIT12 83#define TCR_EPH_LOOP BIT13 84#define TCR_SWFDUP BIT15 85 86#define TCR_DEFAULT (TCR_TXENA | TCR_PAD_EN) 87#define TCR_CLEAR 0x0 88 89// EPH Status Register Bits 90#define EPHSR_TX_SUC BIT0 91#define EPHSR_SNGLCOL BIT1 92#define EPHSR_MULCOL BIT2 93#define EPHSR_LTX_MULT BIT3 94#define EPHSR_16COL BIT4 95#define EPHSR_SQET BIT5 96#define EPHSR_LTX_BRD BIT6 97#define EPHSR_TX_DEFR BIT7 98#define EPHSR_LATCOL BIT9 99#define EPHSR_LOST_CARR BIT10 100#define EPHSR_EXC_DEF BIT11 101#define EPHSR_CTR_ROL BIT12 102#define EPHSR_LINK_OK BIT14 103 104// Receive Control Register Bits 105#define RCR_RX_ABORT BIT0 106#define RCR_PRMS BIT1 107#define RCR_ALMUL BIT2 108#define RCR_RXEN BIT8 109#define RCR_STRIP_CRC BIT9 110#define RCR_ABORT_ENB BIT13 111#define RCR_FILT_CAR BIT14 112#define RCR_SOFT_RST BIT15 113 114#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) 115#define RCR_CLEAR 0x0 116 117// Receive/Phy Control Register Bits 118#define RPCR_LS0B BIT2 119#define RPCR_LS1B BIT3 120#define RPCR_LS2B BIT4 121#define RPCR_LS0A BIT5 122#define RPCR_LS1A BIT6 123#define RPCR_LS2A BIT7 124#define RPCR_ANEG BIT11 125#define RPCR_DPLX BIT12 126#define RPCR_SPEED BIT13 127 128// Configuration Register Bits 129#define CR_EXT_PHY BIT9 130#define CR_GPCNTRL BIT10 131#define CR_NO_WAIT BIT12 132#define CR_EPH_POWER_EN BIT15 133 134#define CR_DEFAULT (CR_EPH_POWER_EN | CR_NO_WAIT) 135 136// Control Register Bits 137#define CTR_STORE BIT0 138#define CTR_RELOAD BIT1 139#define CTR_EEPROM_SEL BIT2 140#define CTR_TE_ENABLE BIT5 141#define CTR_CR_ENABLE BIT6 142#define CTR_LE_ENABLE BIT7 143#define CTR_AUTO_REL BIT11 144#define CTR_RCV_BAD BIT14 145 146#define CTR_RESERVED (BIT12 | BIT9 | BIT4) 147#define CTR_DEFAULT (CTR_RESERVED | CTR_AUTO_REL) 148 149// MMU Command Register Bits 150#define MMUCR_BUSY BIT0 151 152// MMU Command Register Operaction Codes 153#define MMUCR_OP_NOOP (0 << 5) // No operation 154#define MMUCR_OP_TX_ALLOC (1 << 5) // Allocate memory for TX 155#define MMUCR_OP_RESET_MMU (2 << 5) // Reset MMU to initial state 156#define MMUCR_OP_RX_POP (3 << 5) // Remove frame from top of RX FIFO 157#define MMUCR_OP_RX_POP_REL (4 << 5) // Remove and release frame from top of RX FIFO 158#define MMUCR_OP_RX_REL (5 << 5) // Release specific RX frame 159#define MMUCR_OP_TX_PUSH (6 << 5) // Enqueue packet number into TX FIFO 160#define MMUCR_OP_TX_RESET (7 << 5) // Reset TX FIFOs 161 162// Packet Number Register Bits 163#define PNR_PACKET (0x3f) 164 165// Allocation Result Register Bits 166#define ARR_PACKET (0x3f) 167#define ARR_FAILED BIT7 168 169// FIFO Ports Register Bits 170#define FIFO_TX_PACKET (0x003f) 171#define FIFO_TEMPTY BIT7 172#define FIFO_RX_PACKET (0x3f00) 173#define FIFO_REMPTY BIT15 174 175// Pointer Register Bits 176#define PTR_POINTER (0x07ff) 177#define PTR_NOT_EMPTY BIT11 178#define PTR_READ BIT13 179#define PTR_AUTO_INCR BIT14 180#define PTR_RCV BIT15 181 182// Interupt Status and Mask Register Bits 183#define IST_RCV BIT0 184#define IST_TX BIT1 185#define IST_TX_EMPTY BIT2 186#define IST_ALLOC BIT3 187#define IST_RX_OVRN BIT4 188#define IST_EPH BIT5 189#define IST_MD BIT7 190 191// Management Interface 192#define MGMT_MDO BIT0 193#define MGMT_MDI BIT1 194#define MGMT_MCLK BIT2 195#define MGMT_MDOE BIT3 196#define MGMT_MSK_CRS100 BIT14 197 198// RCV Register 199#define RCV_MBO (0x1f) 200#define RCV_RCV_DISCRD BIT7 201 202// Packet RX Status word bits 203#define RX_MULTICAST BIT0 204#define RX_HASH (0x7e) 205#define RX_TOO_SHORT BIT10 206#define RX_TOO_LONG BIT11 207#define RX_ODD_FRAME BIT12 208#define RX_BAD_CRC BIT13 209#define RX_BROADCAST BIT14 210#define RX_ALGN_ERR BIT15 211 212// Packet Byte Count word bits 213#define BCW_COUNT (0x7fe) 214 215// Packet Control Word bits 216#define PCW_ODD_BYTE (0x00ff) 217#define PCW_CRC BIT12 218#define PCW_ODD BIT13 219 220/*--------------------------------------------------------------------------------------------------------------------- 221 222 SMSC PHY Registers 223 224 Most of these should be common, as there is 225 documented STANDARD for PHY registers! 226 227---------------------------------------------------------------------------------------------------------------------*/ 228// 229// PHY Register Numbers 230// 231#define PHY_INDEX_BASIC_CTRL 0 232#define PHY_INDEX_BASIC_STATUS 1 233#define PHY_INDEX_ID1 2 234#define PHY_INDEX_ID2 3 235#define PHY_INDEX_AUTO_NEG_ADVERT 4 236#define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5 237 238#define PHY_INDEX_CONFIG1 16 239#define PHY_INDEX_CONFIG2 17 240#define PHY_INDEX_STATUS_OUTPUT 18 241#define PHY_INDEX_MASK 19 242 243 244// PHY control register bits 245#define PHYCR_COLL_TEST BIT7 // Collision test enable 246#define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 247#define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities 248#define PHYCR_PD BIT11 // Power-Down switch 249#define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable 250#define PHYCR_SPEED_SEL BIT13 // Link Speed Selection 251#define PHYCR_LOOPBK BIT14 // Set loopback mode 252#define PHYCR_RESET BIT15 // Do a PHY reset 253 254// PHY status register bits 255#define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability 256#define PHYSTS_JABBER BIT1 // Jabber condition detected 257#define PHYSTS_LINK_STS BIT2 // Link Status 258#define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability 259#define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected 260#define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed 261#define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability 262#define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability 263#define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability 264#define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability 265#define PHYSTS_100BASE_T4 BIT15 // Base T4 ability 266 267// PHY Auto-Negotiation advertisement 268#define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector 269#define PHYANA_CSMA BIT0 // Advertise CSMA capability 270#define PHYANA_10BASET BIT5 // Advertise 10BASET capability 271#define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability 272#define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability 273#define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability 274#define PHYANA_100BASET4 BIT9 // Advertise 100 BASETX Full duplex capability 275#define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability 276#define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected 277 278#endif /* __LAN91XDXEHW_H__ */ 279