1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch_helpers.h> 32#include <arm_gic.h> 33#include <assert.h> 34#include <bl_common.h> 35#include <debug.h> 36#include <mmio.h> 37#include <platform.h> 38#include <platform_def.h> 39#include <xlat_tables.h> 40#include "../juno_def.h" 41 42#define MAP_MHU_SECURE MAP_REGION_FLAT(MHU_SECURE_BASE, \ 43 MHU_SECURE_SIZE, \ 44 (MHU_PAYLOAD_CACHED ? \ 45 MT_MEMORY : MT_DEVICE) \ 46 | MT_RW | MT_SECURE) 47 48#define MAP_FLASH MAP_REGION_FLAT(FLASH_BASE, \ 49 FLASH_SIZE, \ 50 MT_MEMORY | MT_RO | MT_SECURE) 51 52#define MAP_IOFPGA MAP_REGION_FLAT(IOFPGA_BASE, \ 53 IOFPGA_SIZE, \ 54 MT_DEVICE | MT_RW | MT_SECURE) 55 56#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 57 DEVICE0_SIZE, \ 58 MT_DEVICE | MT_RW | MT_SECURE) 59 60#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 61 DEVICE1_SIZE, \ 62 MT_DEVICE | MT_RW | MT_SECURE) 63 64#define MAP_NS_DRAM MAP_REGION_FLAT(DRAM_NS_BASE, \ 65 DRAM_NS_SIZE, \ 66 MT_MEMORY | MT_RW | MT_NS) 67 68#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \ 69 TSP_SEC_MEM_SIZE, \ 70 MT_MEMORY | MT_RW | MT_SECURE) 71 72/* 73 * Table of regions for different BL stages to map using the MMU. 74 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to 75 * configure_mmu_elx() will give the available subset of that, 76 */ 77#if IMAGE_BL1 78static const mmap_region_t juno_mmap[] = { 79 MAP_MHU_SECURE, 80 MAP_FLASH, 81 MAP_IOFPGA, 82 MAP_DEVICE0, 83 MAP_DEVICE1, 84 {0} 85}; 86#endif 87#if IMAGE_BL2 88static const mmap_region_t juno_mmap[] = { 89 MAP_MHU_SECURE, 90 MAP_FLASH, 91 MAP_IOFPGA, 92 MAP_DEVICE0, 93 MAP_DEVICE1, 94 MAP_NS_DRAM, 95 MAP_TSP_MEM, 96 {0} 97}; 98#endif 99#if IMAGE_BL31 100static const mmap_region_t juno_mmap[] = { 101 MAP_MHU_SECURE, 102 MAP_IOFPGA, 103 MAP_DEVICE0, 104 MAP_DEVICE1, 105 MAP_TSP_MEM, 106 {0} 107}; 108#endif 109#if IMAGE_BL32 110static const mmap_region_t juno_mmap[] = { 111 MAP_IOFPGA, 112 MAP_DEVICE0, 113 MAP_DEVICE1, 114 {0} 115}; 116#endif 117 118/* Array of secure interrupts to be configured by the gic driver */ 119const unsigned int irq_sec_array[] = { 120 IRQ_MHU, 121 IRQ_GPU_SMMU_0, 122 IRQ_GPU_SMMU_1, 123 IRQ_ETR_SMMU, 124 IRQ_TZC400, 125 IRQ_TZ_WDOG, 126 IRQ_SEC_PHY_TIMER, 127 IRQ_SEC_SGI_0, 128 IRQ_SEC_SGI_1, 129 IRQ_SEC_SGI_2, 130 IRQ_SEC_SGI_3, 131 IRQ_SEC_SGI_4, 132 IRQ_SEC_SGI_5, 133 IRQ_SEC_SGI_6, 134 IRQ_SEC_SGI_7 135}; 136 137const unsigned int num_sec_irqs = sizeof(irq_sec_array) / 138 sizeof(irq_sec_array[0]); 139 140/******************************************************************************* 141 * Macro generating the code for the function setting up the pagetables as per 142 * the platform memory map & initialize the mmu, for the given exception level 143 ******************************************************************************/ 144#if USE_COHERENT_MEM 145#define DEFINE_CONFIGURE_MMU_EL(_el) \ 146 void configure_mmu_el##_el(unsigned long total_base, \ 147 unsigned long total_size, \ 148 unsigned long ro_start, \ 149 unsigned long ro_limit, \ 150 unsigned long coh_start, \ 151 unsigned long coh_limit) \ 152 { \ 153 mmap_add_region(total_base, total_base, \ 154 total_size, \ 155 MT_MEMORY | MT_RW | MT_SECURE); \ 156 mmap_add_region(ro_start, ro_start, \ 157 ro_limit - ro_start, \ 158 MT_MEMORY | MT_RO | MT_SECURE); \ 159 mmap_add_region(coh_start, coh_start, \ 160 coh_limit - coh_start, \ 161 MT_DEVICE | MT_RW | MT_SECURE); \ 162 mmap_add(juno_mmap); \ 163 init_xlat_tables(); \ 164 \ 165 enable_mmu_el##_el(0); \ 166 } 167#else 168#define DEFINE_CONFIGURE_MMU_EL(_el) \ 169 void configure_mmu_el##_el(unsigned long total_base, \ 170 unsigned long total_size, \ 171 unsigned long ro_start, \ 172 unsigned long ro_limit) \ 173 { \ 174 mmap_add_region(total_base, total_base, \ 175 total_size, \ 176 MT_MEMORY | MT_RW | MT_SECURE); \ 177 mmap_add_region(ro_start, ro_start, \ 178 ro_limit - ro_start, \ 179 MT_MEMORY | MT_RO | MT_SECURE); \ 180 mmap_add(juno_mmap); \ 181 init_xlat_tables(); \ 182 \ 183 enable_mmu_el##_el(0); \ 184 } 185#endif 186/* Define EL1 and EL3 variants of the function initialising the MMU */ 187DEFINE_CONFIGURE_MMU_EL(1) 188DEFINE_CONFIGURE_MMU_EL(3) 189 190 191unsigned long plat_get_ns_image_entrypoint(void) 192{ 193 return NS_IMAGE_OFFSET; 194} 195 196uint64_t plat_get_syscnt_freq(void) 197{ 198 uint64_t counter_base_frequency; 199 200 /* Read the frequency from Frequency modes table */ 201 counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); 202 203 /* The first entry of the frequency modes table must not be 0 */ 204 if (counter_base_frequency == 0) 205 panic(); 206 207 return counter_base_frequency; 208} 209 210void plat_gic_init(void) 211{ 212 arm_gic_init(GICC_BASE, GICD_BASE, 0, irq_sec_array, num_sec_irqs); 213} 214