ArmV7.h revision 168d724568ff1525517b1d0b00361419ca564310 
1/** @file
2
3  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4  Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
5
6  This program and the accompanying materials
7  are licensed and made available under the terms and conditions of the BSD License
8  which accompanies this distribution.  The full text of the license may be found at
9  http://opensource.org/licenses/bsd-license.php
10
11  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14**/
15
16#ifndef __ARM_V7_H__
17#define __ARM_V7_H__
18
19#include <Chipset/ArmV7Mmu.h>
20#include <Chipset/ArmArchTimer.h>
21
22// ARM Interrupt ID in Exception Table
23#define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_ARM_IRQ
24
25// Domain Access Control Register
26#define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))
27#define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))
28#define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))
29#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
30#define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))
31
32// CPSR - Coprocessor Status Register definitions
33#define CPSR_MODE_USER       0x10
34#define CPSR_MODE_FIQ        0x11
35#define CPSR_MODE_IRQ        0x12
36#define CPSR_MODE_SVC        0x13
37#define CPSR_MODE_ABORT      0x17
38#define CPSR_MODE_HYP        0x1A
39#define CPSR_MODE_UNDEFINED  0x1B
40#define CPSR_MODE_SYSTEM     0x1F
41#define CPSR_MODE_MASK       0x1F
42#define CPSR_ASYNC_ABORT     (1 << 8)
43#define CPSR_IRQ             (1 << 7)
44#define CPSR_FIQ             (1 << 6)
45
46
47// CPACR - Coprocessor Access Control Register definitions
48#define CPACR_CP_DENIED(cp)     0x00
49#define CPACR_CP_PRIV(cp)       ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
50#define CPACR_CP_FULL(cp)       ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
51#define CPACR_ASEDIS            (1 << 31)
52#define CPACR_D32DIS            (1 << 30)
53#define CPACR_CP_FULL_ACCESS    0x0FFFFFFF
54
55// NSACR - Non-Secure Access Control Register definitions
56#define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)
57#define NSACR_NSD32DIS          (1 << 14)
58#define NSACR_NSASEDIS          (1 << 15)
59#define NSACR_PLE               (1 << 16)
60#define NSACR_TL                (1 << 17)
61#define NSACR_NS_SMP            (1 << 18)
62#define NSACR_RFR               (1 << 19)
63
64// SCR - Secure Configuration Register definitions
65#define SCR_NS                  (1 << 0)
66#define SCR_IRQ                 (1 << 1)
67#define SCR_FIQ                 (1 << 2)
68#define SCR_EA                  (1 << 3)
69#define SCR_FW                  (1 << 4)
70#define SCR_AW                  (1 << 5)
71
72// MIDR - Main ID Register definitions
73#define ARM_CPU_TYPE_MASK       0xFFF
74#define ARM_CPU_TYPE_A15        0xC0F
75#define ARM_CPU_TYPE_A9         0xC09
76#define ARM_CPU_TYPE_A5         0xC05
77
78#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
79
80VOID
81EFIAPI
82ArmEnableSWPInstruction (
83  VOID
84  );
85
86UINTN
87EFIAPI
88ArmReadCbar (
89  VOID
90  );
91
92UINTN
93EFIAPI
94ArmReadTpidrurw (
95  VOID
96  );
97
98VOID
99EFIAPI
100ArmWriteTpidrurw (
101  UINTN Value
102  );
103
104UINT32
105EFIAPI
106ArmReadNsacr (
107  VOID
108  );
109
110VOID
111EFIAPI
112ArmWriteNsacr (
113  IN  UINT32   Nsacr
114  );
115
116#endif // __ARM_V7_H__
117