1/*++ 2 3Copyright (c) 2005 - 2006, Intel Corporation. All rights reserved.<BR> 4This program and the accompanying materials 5are licensed and made available under the terms and conditions of the BSD License 6which accompanies this distribution. The full text of the license may be found at 7http://opensource.org/licenses/bsd-license.php 8 9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 12Module Name: 13 PcatPciRootBridge.h 14 15Abstract: 16 17 The driver for the host to pci bridge (root bridge). 18 19--*/ 20 21#ifndef _PCAT_PCI_ROOT_BRIDGE_H_ 22#define _PCAT_PCI_ROOT_BRIDGE_H_ 23 24#include <PiDxe.h> 25#include <Protocol/PciRootBridgeIo.h> 26#include <Protocol/DeviceIo.h> 27#include <Protocol/CpuIo2.h> 28 29#include <Library/UefiLib.h> 30#include <Library/BaseLib.h> 31#include <Library/MemoryAllocationLib.h> 32#include <Library/UefiBootServicesTableLib.h> 33#include <Library/DebugLib.h> 34#include <Library/BaseMemoryLib.h> 35#include <Library/DevicePathLib.h> 36#include <Library/HobLib.h> 37 38#include <Guid/PciOptionRomTable.h> 39#include <Guid/HobList.h> 40#include <Guid/PciExpressBaseAddress.h> 41 42#include <IndustryStandard/Acpi.h> 43#include <IndustryStandard/Pci.h> 44 45#define PCI_MAX_SEGMENT 0 46// 47// Driver Instance Data Prototypes 48// 49#define PCAT_PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('p', 'c', 'r', 'b') 50 51typedef struct { 52 UINT32 Signature; 53 EFI_HANDLE Handle; 54 55 EFI_DEVICE_PATH_PROTOCOL *DevicePath; 56 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; 57 EFI_CPU_IO2_PROTOCOL *CpuIo; 58 59 UINT32 RootBridgeNumber; 60 UINT32 PrimaryBus; 61 UINT32 SubordinateBus; 62 63 UINT64 MemBase; // Offsets host to bus memory addr. 64 UINT64 MemLimit; // Max allowable memory access 65 66 UINT64 IoBase; // Offsets host to bus io addr. 67 UINT64 IoLimit; // Max allowable io access 68 69 UINT64 PciAddress; 70 UINT64 PciData; 71 72 UINT64 PhysicalMemoryBase; 73 UINT64 PhysicalIoBase; 74 75 EFI_LOCK PciLock; 76 77 UINT64 Attributes; 78 79 UINT64 Mem32Base; 80 UINT64 Mem32Limit; 81 UINT64 Pmem32Base; 82 UINT64 Pmem32Limit; 83 UINT64 Mem64Base; 84 UINT64 Mem64Limit; 85 UINT64 Pmem64Base; 86 UINT64 Pmem64Limit; 87 88 UINT64 PciExpressBaseAddress; 89 90 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration; 91 92 LIST_ENTRY MapInfo; 93} PCAT_PCI_ROOT_BRIDGE_INSTANCE; 94 95// 96// Driver Instance Data Macros 97// 98#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \ 99 CR(a, PCAT_PCI_ROOT_BRIDGE_INSTANCE, Io, PCAT_PCI_ROOT_BRIDGE_SIGNATURE) 100 101// 102// Private data types 103// 104typedef union { 105 UINT8 volatile *buf; 106 UINT8 volatile *ui8; 107 UINT16 volatile *ui16; 108 UINT32 volatile *ui32; 109 UINT64 volatile *ui64; 110 UINTN volatile ui; 111} PTR; 112 113typedef struct { 114 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation; 115 UINTN NumberOfBytes; 116 UINTN NumberOfPages; 117 EFI_PHYSICAL_ADDRESS HostAddress; 118 EFI_PHYSICAL_ADDRESS MappedHostAddress; 119} MAP_INFO; 120 121typedef struct { 122 LIST_ENTRY Link; 123 MAP_INFO * Map; 124} MAP_INFO_INSTANCE; 125 126typedef 127VOID 128(*EFI_PCI_BUS_SCAN_CALLBACK) ( 129 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev, 130 UINT16 MinBus, 131 UINT16 MaxBus, 132 UINT16 MinDevice, 133 UINT16 MaxDevice, 134 UINT16 MinFunc, 135 UINT16 MaxFunc, 136 UINT16 Bus, 137 UINT16 Device, 138 UINT16 Func, 139 IN VOID *Context 140 ); 141 142typedef struct { 143 UINT16 *CommandRegisterBuffer; 144 UINT32 PpbMemoryWindow; 145} PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT; 146 147typedef struct { 148 UINT8 Register; 149 UINT8 Function; 150 UINT8 Device; 151 UINT8 Bus; 152 UINT8 Reserved[4]; 153} DEFIO_PCI_ADDR; 154 155// 156// Driver Protocol Constructor Prototypes 157// 158EFI_STATUS 159ConstructConfiguration( 160 IN OUT PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData 161 ); 162 163EFI_STATUS 164PcatPciRootBridgeParseBars ( 165 IN PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData, 166 IN UINT16 Command, 167 IN UINTN Bus, 168 IN UINTN Device, 169 IN UINTN Function 170 ); 171 172EFI_STATUS 173ScanPciRootBridgeForRoms( 174 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev 175 ); 176 177EFI_STATUS 178PcatRootBridgeDevicePathConstructor ( 179 IN EFI_DEVICE_PATH_PROTOCOL **Protocol, 180 IN UINTN RootBridgeNumber, 181 IN BOOLEAN IsPciExpress 182 ); 183 184EFI_STATUS 185PcatRootBridgeIoConstructor ( 186 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, 187 IN UINTN SegmentNumber 188 ); 189 190EFI_STATUS 191PcatRootBridgeIoGetIoPortMapping ( 192 OUT EFI_PHYSICAL_ADDRESS *IoPortMapping, 193 OUT EFI_PHYSICAL_ADDRESS *MemoryPortMapping 194 ); 195 196EFI_STATUS 197PcatRootBridgeIoPciRW ( 198 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 199 IN BOOLEAN Write, 200 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 201 IN UINT64 UserAddress, 202 IN UINTN Count, 203 IN OUT VOID *UserBuffer 204 ); 205 206UINT64 207GetPciExpressBaseAddressForRootBridge ( 208 IN UINTN HostBridgeNumber, 209 IN UINTN RootBridgeNumber 210 ); 211 212EFI_STATUS 213EFIAPI 214PcatRootBridgeIoIoRead ( 215 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 216 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 217 IN UINT64 UserAddress, 218 IN UINTN Count, 219 IN OUT VOID *UserBuffer 220 ); 221 222EFI_STATUS 223EFIAPI 224PcatRootBridgeIoIoWrite ( 225 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 226 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, 227 IN UINT64 UserAddress, 228 IN UINTN Count, 229 IN OUT VOID *UserBuffer 230 ); 231 232// 233// Driver entry point prototype 234// 235EFI_STATUS 236EFIAPI 237InitializePcatPciRootBridge ( 238 IN EFI_HANDLE ImageHandle, 239 IN EFI_SYSTEM_TABLE *SystemTable 240 ); 241 242extern EFI_CPU_IO2_PROTOCOL *gCpuIo; 243 244#endif 245