CGBuiltin.cpp revision af521dae8ee15ebf4ecceae3d25f66a475104a07 
1//===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This contains code to emit Builtin calls as LLVM code.
11//
12//===----------------------------------------------------------------------===//
13
14#include "TargetInfo.h"
15#include "CodeGenFunction.h"
16#include "CodeGenModule.h"
17#include "CGObjCRuntime.h"
18#include "clang/Basic/TargetInfo.h"
19#include "clang/AST/ASTContext.h"
20#include "clang/AST/Decl.h"
21#include "clang/Basic/TargetBuiltins.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/Target/TargetData.h"
24
25using namespace clang;
26using namespace CodeGen;
27using namespace llvm;
28
29/// getBuiltinLibFunction - Given a builtin id for a function like
30/// "__builtin_fabsf", return a Function* for "fabsf".
31llvm::Value *CodeGenModule::getBuiltinLibFunction(const FunctionDecl *FD,
32                                                  unsigned BuiltinID) {
33  assert(Context.BuiltinInfo.isLibFunction(BuiltinID));
34
35  // Get the name, skip over the __builtin_ prefix (if necessary).
36  StringRef Name;
37  GlobalDecl D(FD);
38
39  // If the builtin has been declared explicitly with an assembler label,
40  // use the mangled name. This differs from the plain label on platforms
41  // that prefix labels.
42  if (FD->hasAttr<AsmLabelAttr>())
43    Name = getMangledName(D);
44  else
45    Name = Context.BuiltinInfo.GetName(BuiltinID) + 10;
46
47  llvm::FunctionType *Ty =
48    cast<llvm::FunctionType>(getTypes().ConvertType(FD->getType()));
49
50  return GetOrCreateLLVMFunction(Name, Ty, D, /*ForVTable=*/false);
51}
52
53/// Emit the conversions required to turn the given value into an
54/// integer of the given size.
55static Value *EmitToInt(CodeGenFunction &CGF, llvm::Value *V,
56                        QualType T, llvm::IntegerType *IntType) {
57  V = CGF.EmitToMemory(V, T);
58
59  if (V->getType()->isPointerTy())
60    return CGF.Builder.CreatePtrToInt(V, IntType);
61
62  assert(V->getType() == IntType);
63  return V;
64}
65
66static Value *EmitFromInt(CodeGenFunction &CGF, llvm::Value *V,
67                          QualType T, llvm::Type *ResultType) {
68  V = CGF.EmitFromMemory(V, T);
69
70  if (ResultType->isPointerTy())
71    return CGF.Builder.CreateIntToPtr(V, ResultType);
72
73  assert(V->getType() == ResultType);
74  return V;
75}
76
77/// Utility to insert an atomic instruction based on Instrinsic::ID
78/// and the expression node.
79static RValue EmitBinaryAtomic(CodeGenFunction &CGF,
80                               llvm::AtomicRMWInst::BinOp Kind,
81                               const CallExpr *E) {
82  QualType T = E->getType();
83  assert(E->getArg(0)->getType()->isPointerType());
84  assert(CGF.getContext().hasSameUnqualifiedType(T,
85                                  E->getArg(0)->getType()->getPointeeType()));
86  assert(CGF.getContext().hasSameUnqualifiedType(T, E->getArg(1)->getType()));
87
88  llvm::Value *DestPtr = CGF.EmitScalarExpr(E->getArg(0));
89  unsigned AddrSpace =
90    cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace();
91
92  llvm::IntegerType *IntType =
93    llvm::IntegerType::get(CGF.getLLVMContext(),
94                           CGF.getContext().getTypeSize(T));
95  llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace);
96
97  llvm::Value *Args[2];
98  Args[0] = CGF.Builder.CreateBitCast(DestPtr, IntPtrType);
99  Args[1] = CGF.EmitScalarExpr(E->getArg(1));
100  llvm::Type *ValueType = Args[1]->getType();
101  Args[1] = EmitToInt(CGF, Args[1], T, IntType);
102
103  llvm::Value *Result =
104      CGF.Builder.CreateAtomicRMW(Kind, Args[0], Args[1],
105                                  llvm::SequentiallyConsistent);
106  Result = EmitFromInt(CGF, Result, T, ValueType);
107  return RValue::get(Result);
108}
109
110/// Utility to insert an atomic instruction based Instrinsic::ID and
111/// the expression node, where the return value is the result of the
112/// operation.
113static RValue EmitBinaryAtomicPost(CodeGenFunction &CGF,
114                                   llvm::AtomicRMWInst::BinOp Kind,
115                                   const CallExpr *E,
116                                   Instruction::BinaryOps Op) {
117  QualType T = E->getType();
118  assert(E->getArg(0)->getType()->isPointerType());
119  assert(CGF.getContext().hasSameUnqualifiedType(T,
120                                  E->getArg(0)->getType()->getPointeeType()));
121  assert(CGF.getContext().hasSameUnqualifiedType(T, E->getArg(1)->getType()));
122
123  llvm::Value *DestPtr = CGF.EmitScalarExpr(E->getArg(0));
124  unsigned AddrSpace =
125    cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace();
126
127  llvm::IntegerType *IntType =
128    llvm::IntegerType::get(CGF.getLLVMContext(),
129                           CGF.getContext().getTypeSize(T));
130  llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace);
131
132  llvm::Value *Args[2];
133  Args[1] = CGF.EmitScalarExpr(E->getArg(1));
134  llvm::Type *ValueType = Args[1]->getType();
135  Args[1] = EmitToInt(CGF, Args[1], T, IntType);
136  Args[0] = CGF.Builder.CreateBitCast(DestPtr, IntPtrType);
137
138  llvm::Value *Result =
139      CGF.Builder.CreateAtomicRMW(Kind, Args[0], Args[1],
140                                  llvm::SequentiallyConsistent);
141  Result = CGF.Builder.CreateBinOp(Op, Result, Args[1]);
142  Result = EmitFromInt(CGF, Result, T, ValueType);
143  return RValue::get(Result);
144}
145
146/// EmitFAbs - Emit a call to fabs/fabsf/fabsl, depending on the type of ValTy,
147/// which must be a scalar floating point type.
148static Value *EmitFAbs(CodeGenFunction &CGF, Value *V, QualType ValTy) {
149  const BuiltinType *ValTyP = ValTy->getAs<BuiltinType>();
150  assert(ValTyP && "isn't scalar fp type!");
151
152  StringRef FnName;
153  switch (ValTyP->getKind()) {
154  default: llvm_unreachable("Isn't a scalar fp type!");
155  case BuiltinType::Float:      FnName = "fabsf"; break;
156  case BuiltinType::Double:     FnName = "fabs"; break;
157  case BuiltinType::LongDouble: FnName = "fabsl"; break;
158  }
159
160  // The prototype is something that takes and returns whatever V's type is.
161  llvm::FunctionType *FT = llvm::FunctionType::get(V->getType(), V->getType(),
162                                                   false);
163  llvm::Value *Fn = CGF.CGM.CreateRuntimeFunction(FT, FnName);
164
165  return CGF.Builder.CreateCall(Fn, V, "abs");
166}
167
168static RValue emitLibraryCall(CodeGenFunction &CGF, const FunctionDecl *Fn,
169                              const CallExpr *E, llvm::Value *calleeValue) {
170  return CGF.EmitCall(E->getCallee()->getType(), calleeValue,
171                      ReturnValueSlot(), E->arg_begin(), E->arg_end(), Fn);
172}
173
174RValue CodeGenFunction::EmitBuiltinExpr(const FunctionDecl *FD,
175                                        unsigned BuiltinID, const CallExpr *E) {
176  // See if we can constant fold this builtin.  If so, don't emit it at all.
177  Expr::EvalResult Result;
178  if (E->EvaluateAsRValue(Result, CGM.getContext()) &&
179      !Result.hasSideEffects()) {
180    if (Result.Val.isInt())
181      return RValue::get(llvm::ConstantInt::get(getLLVMContext(),
182                                                Result.Val.getInt()));
183    if (Result.Val.isFloat())
184      return RValue::get(llvm::ConstantFP::get(getLLVMContext(),
185                                               Result.Val.getFloat()));
186  }
187
188  switch (BuiltinID) {
189  default: break;  // Handle intrinsics and libm functions below.
190  case Builtin::BI__builtin___CFStringMakeConstantString:
191  case Builtin::BI__builtin___NSStringMakeConstantString:
192    return RValue::get(CGM.EmitConstantExpr(E, E->getType(), 0));
193  case Builtin::BI__builtin_stdarg_start:
194  case Builtin::BI__builtin_va_start:
195  case Builtin::BI__builtin_va_end: {
196    Value *ArgValue = EmitVAListRef(E->getArg(0));
197    llvm::Type *DestType = Int8PtrTy;
198    if (ArgValue->getType() != DestType)
199      ArgValue = Builder.CreateBitCast(ArgValue, DestType,
200                                       ArgValue->getName().data());
201
202    Intrinsic::ID inst = (BuiltinID == Builtin::BI__builtin_va_end) ?
203      Intrinsic::vaend : Intrinsic::vastart;
204    return RValue::get(Builder.CreateCall(CGM.getIntrinsic(inst), ArgValue));
205  }
206  case Builtin::BI__builtin_va_copy: {
207    Value *DstPtr = EmitVAListRef(E->getArg(0));
208    Value *SrcPtr = EmitVAListRef(E->getArg(1));
209
210    llvm::Type *Type = Int8PtrTy;
211
212    DstPtr = Builder.CreateBitCast(DstPtr, Type);
213    SrcPtr = Builder.CreateBitCast(SrcPtr, Type);
214    return RValue::get(Builder.CreateCall2(CGM.getIntrinsic(Intrinsic::vacopy),
215                                           DstPtr, SrcPtr));
216  }
217  case Builtin::BI__builtin_abs:
218  case Builtin::BI__builtin_labs:
219  case Builtin::BI__builtin_llabs: {
220    Value *ArgValue = EmitScalarExpr(E->getArg(0));
221
222    Value *NegOp = Builder.CreateNeg(ArgValue, "neg");
223    Value *CmpResult =
224    Builder.CreateICmpSGE(ArgValue,
225                          llvm::Constant::getNullValue(ArgValue->getType()),
226                                                            "abscond");
227    Value *Result =
228      Builder.CreateSelect(CmpResult, ArgValue, NegOp, "abs");
229
230    return RValue::get(Result);
231  }
232  case Builtin::BI__builtin_ctz:
233  case Builtin::BI__builtin_ctzl:
234  case Builtin::BI__builtin_ctzll: {
235    Value *ArgValue = EmitScalarExpr(E->getArg(0));
236
237    llvm::Type *ArgType = ArgValue->getType();
238    Value *F = CGM.getIntrinsic(Intrinsic::cttz, ArgType);
239
240    llvm::Type *ResultType = ConvertType(E->getType());
241    Value *Result = Builder.CreateCall2(F, ArgValue, Builder.getTrue());
242    if (Result->getType() != ResultType)
243      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
244                                     "cast");
245    return RValue::get(Result);
246  }
247  case Builtin::BI__builtin_clz:
248  case Builtin::BI__builtin_clzl:
249  case Builtin::BI__builtin_clzll: {
250    Value *ArgValue = EmitScalarExpr(E->getArg(0));
251
252    llvm::Type *ArgType = ArgValue->getType();
253    Value *F = CGM.getIntrinsic(Intrinsic::ctlz, ArgType);
254
255    llvm::Type *ResultType = ConvertType(E->getType());
256    Value *Result = Builder.CreateCall2(F, ArgValue, Builder.getTrue());
257    if (Result->getType() != ResultType)
258      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
259                                     "cast");
260    return RValue::get(Result);
261  }
262  case Builtin::BI__builtin_ffs:
263  case Builtin::BI__builtin_ffsl:
264  case Builtin::BI__builtin_ffsll: {
265    // ffs(x) -> x ? cttz(x) + 1 : 0
266    Value *ArgValue = EmitScalarExpr(E->getArg(0));
267
268    llvm::Type *ArgType = ArgValue->getType();
269    Value *F = CGM.getIntrinsic(Intrinsic::cttz, ArgType);
270
271    llvm::Type *ResultType = ConvertType(E->getType());
272    Value *Tmp = Builder.CreateAdd(Builder.CreateCall2(F, ArgValue,
273                                                       Builder.getTrue()),
274                                   llvm::ConstantInt::get(ArgType, 1));
275    Value *Zero = llvm::Constant::getNullValue(ArgType);
276    Value *IsZero = Builder.CreateICmpEQ(ArgValue, Zero, "iszero");
277    Value *Result = Builder.CreateSelect(IsZero, Zero, Tmp, "ffs");
278    if (Result->getType() != ResultType)
279      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
280                                     "cast");
281    return RValue::get(Result);
282  }
283  case Builtin::BI__builtin_parity:
284  case Builtin::BI__builtin_parityl:
285  case Builtin::BI__builtin_parityll: {
286    // parity(x) -> ctpop(x) & 1
287    Value *ArgValue = EmitScalarExpr(E->getArg(0));
288
289    llvm::Type *ArgType = ArgValue->getType();
290    Value *F = CGM.getIntrinsic(Intrinsic::ctpop, ArgType);
291
292    llvm::Type *ResultType = ConvertType(E->getType());
293    Value *Tmp = Builder.CreateCall(F, ArgValue);
294    Value *Result = Builder.CreateAnd(Tmp, llvm::ConstantInt::get(ArgType, 1));
295    if (Result->getType() != ResultType)
296      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
297                                     "cast");
298    return RValue::get(Result);
299  }
300  case Builtin::BI__builtin_popcount:
301  case Builtin::BI__builtin_popcountl:
302  case Builtin::BI__builtin_popcountll: {
303    Value *ArgValue = EmitScalarExpr(E->getArg(0));
304
305    llvm::Type *ArgType = ArgValue->getType();
306    Value *F = CGM.getIntrinsic(Intrinsic::ctpop, ArgType);
307
308    llvm::Type *ResultType = ConvertType(E->getType());
309    Value *Result = Builder.CreateCall(F, ArgValue);
310    if (Result->getType() != ResultType)
311      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
312                                     "cast");
313    return RValue::get(Result);
314  }
315  case Builtin::BI__builtin_expect: {
316    Value *ArgValue = EmitScalarExpr(E->getArg(0));
317    llvm::Type *ArgType = ArgValue->getType();
318
319    Value *FnExpect = CGM.getIntrinsic(Intrinsic::expect, ArgType);
320    Value *ExpectedValue = EmitScalarExpr(E->getArg(1));
321
322    Value *Result = Builder.CreateCall2(FnExpect, ArgValue, ExpectedValue,
323                                        "expval");
324    return RValue::get(Result);
325  }
326  case Builtin::BI__builtin_bswap32:
327  case Builtin::BI__builtin_bswap64: {
328    Value *ArgValue = EmitScalarExpr(E->getArg(0));
329    llvm::Type *ArgType = ArgValue->getType();
330    Value *F = CGM.getIntrinsic(Intrinsic::bswap, ArgType);
331    return RValue::get(Builder.CreateCall(F, ArgValue));
332  }
333  case Builtin::BI__builtin_object_size: {
334    // We pass this builtin onto the optimizer so that it can
335    // figure out the object size in more complex cases.
336    llvm::Type *ResType = ConvertType(E->getType());
337
338    // LLVM only supports 0 and 2, make sure that we pass along that
339    // as a boolean.
340    Value *Ty = EmitScalarExpr(E->getArg(1));
341    ConstantInt *CI = dyn_cast<ConstantInt>(Ty);
342    assert(CI);
343    uint64_t val = CI->getZExtValue();
344    CI = ConstantInt::get(Builder.getInt1Ty(), (val & 0x2) >> 1);
345
346    Value *F = CGM.getIntrinsic(Intrinsic::objectsize, ResType);
347    return RValue::get(Builder.CreateCall2(F,
348                                           EmitScalarExpr(E->getArg(0)),
349                                           CI));
350  }
351  case Builtin::BI__builtin_prefetch: {
352    Value *Locality, *RW, *Address = EmitScalarExpr(E->getArg(0));
353    // FIXME: Technically these constants should of type 'int', yes?
354    RW = (E->getNumArgs() > 1) ? EmitScalarExpr(E->getArg(1)) :
355      llvm::ConstantInt::get(Int32Ty, 0);
356    Locality = (E->getNumArgs() > 2) ? EmitScalarExpr(E->getArg(2)) :
357      llvm::ConstantInt::get(Int32Ty, 3);
358    Value *Data = llvm::ConstantInt::get(Int32Ty, 1);
359    Value *F = CGM.getIntrinsic(Intrinsic::prefetch);
360    return RValue::get(Builder.CreateCall4(F, Address, RW, Locality, Data));
361  }
362  case Builtin::BI__builtin_trap: {
363    Value *F = CGM.getIntrinsic(Intrinsic::trap);
364    return RValue::get(Builder.CreateCall(F));
365  }
366  case Builtin::BI__builtin_unreachable: {
367    if (CatchUndefined)
368      EmitBranch(getTrapBB());
369    else
370      Builder.CreateUnreachable();
371
372    // We do need to preserve an insertion point.
373    EmitBlock(createBasicBlock("unreachable.cont"));
374
375    return RValue::get(0);
376  }
377
378  case Builtin::BI__builtin_powi:
379  case Builtin::BI__builtin_powif:
380  case Builtin::BI__builtin_powil: {
381    Value *Base = EmitScalarExpr(E->getArg(0));
382    Value *Exponent = EmitScalarExpr(E->getArg(1));
383    llvm::Type *ArgType = Base->getType();
384    Value *F = CGM.getIntrinsic(Intrinsic::powi, ArgType);
385    return RValue::get(Builder.CreateCall2(F, Base, Exponent));
386  }
387
388  case Builtin::BI__builtin_isgreater:
389  case Builtin::BI__builtin_isgreaterequal:
390  case Builtin::BI__builtin_isless:
391  case Builtin::BI__builtin_islessequal:
392  case Builtin::BI__builtin_islessgreater:
393  case Builtin::BI__builtin_isunordered: {
394    // Ordered comparisons: we know the arguments to these are matching scalar
395    // floating point values.
396    Value *LHS = EmitScalarExpr(E->getArg(0));
397    Value *RHS = EmitScalarExpr(E->getArg(1));
398
399    switch (BuiltinID) {
400    default: llvm_unreachable("Unknown ordered comparison");
401    case Builtin::BI__builtin_isgreater:
402      LHS = Builder.CreateFCmpOGT(LHS, RHS, "cmp");
403      break;
404    case Builtin::BI__builtin_isgreaterequal:
405      LHS = Builder.CreateFCmpOGE(LHS, RHS, "cmp");
406      break;
407    case Builtin::BI__builtin_isless:
408      LHS = Builder.CreateFCmpOLT(LHS, RHS, "cmp");
409      break;
410    case Builtin::BI__builtin_islessequal:
411      LHS = Builder.CreateFCmpOLE(LHS, RHS, "cmp");
412      break;
413    case Builtin::BI__builtin_islessgreater:
414      LHS = Builder.CreateFCmpONE(LHS, RHS, "cmp");
415      break;
416    case Builtin::BI__builtin_isunordered:
417      LHS = Builder.CreateFCmpUNO(LHS, RHS, "cmp");
418      break;
419    }
420    // ZExt bool to int type.
421    return RValue::get(Builder.CreateZExt(LHS, ConvertType(E->getType())));
422  }
423  case Builtin::BI__builtin_isnan: {
424    Value *V = EmitScalarExpr(E->getArg(0));
425    V = Builder.CreateFCmpUNO(V, V, "cmp");
426    return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType())));
427  }
428
429  case Builtin::BI__builtin_isinf: {
430    // isinf(x) --> fabs(x) == infinity
431    Value *V = EmitScalarExpr(E->getArg(0));
432    V = EmitFAbs(*this, V, E->getArg(0)->getType());
433
434    V = Builder.CreateFCmpOEQ(V, ConstantFP::getInfinity(V->getType()),"isinf");
435    return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType())));
436  }
437
438  // TODO: BI__builtin_isinf_sign
439  //   isinf_sign(x) -> isinf(x) ? (signbit(x) ? -1 : 1) : 0
440
441  case Builtin::BI__builtin_isnormal: {
442    // isnormal(x) --> x == x && fabsf(x) < infinity && fabsf(x) >= float_min
443    Value *V = EmitScalarExpr(E->getArg(0));
444    Value *Eq = Builder.CreateFCmpOEQ(V, V, "iseq");
445
446    Value *Abs = EmitFAbs(*this, V, E->getArg(0)->getType());
447    Value *IsLessThanInf =
448      Builder.CreateFCmpULT(Abs, ConstantFP::getInfinity(V->getType()),"isinf");
449    APFloat Smallest = APFloat::getSmallestNormalized(
450                   getContext().getFloatTypeSemantics(E->getArg(0)->getType()));
451    Value *IsNormal =
452      Builder.CreateFCmpUGE(Abs, ConstantFP::get(V->getContext(), Smallest),
453                            "isnormal");
454    V = Builder.CreateAnd(Eq, IsLessThanInf, "and");
455    V = Builder.CreateAnd(V, IsNormal, "and");
456    return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType())));
457  }
458
459  case Builtin::BI__builtin_isfinite: {
460    // isfinite(x) --> x == x && fabs(x) != infinity;
461    Value *V = EmitScalarExpr(E->getArg(0));
462    Value *Eq = Builder.CreateFCmpOEQ(V, V, "iseq");
463
464    Value *Abs = EmitFAbs(*this, V, E->getArg(0)->getType());
465    Value *IsNotInf =
466      Builder.CreateFCmpUNE(Abs, ConstantFP::getInfinity(V->getType()),"isinf");
467
468    V = Builder.CreateAnd(Eq, IsNotInf, "and");
469    return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType())));
470  }
471
472  case Builtin::BI__builtin_fpclassify: {
473    Value *V = EmitScalarExpr(E->getArg(5));
474    llvm::Type *Ty = ConvertType(E->getArg(5)->getType());
475
476    // Create Result
477    BasicBlock *Begin = Builder.GetInsertBlock();
478    BasicBlock *End = createBasicBlock("fpclassify_end", this->CurFn);
479    Builder.SetInsertPoint(End);
480    PHINode *Result =
481      Builder.CreatePHI(ConvertType(E->getArg(0)->getType()), 4,
482                        "fpclassify_result");
483
484    // if (V==0) return FP_ZERO
485    Builder.SetInsertPoint(Begin);
486    Value *IsZero = Builder.CreateFCmpOEQ(V, Constant::getNullValue(Ty),
487                                          "iszero");
488    Value *ZeroLiteral = EmitScalarExpr(E->getArg(4));
489    BasicBlock *NotZero = createBasicBlock("fpclassify_not_zero", this->CurFn);
490    Builder.CreateCondBr(IsZero, End, NotZero);
491    Result->addIncoming(ZeroLiteral, Begin);
492
493    // if (V != V) return FP_NAN
494    Builder.SetInsertPoint(NotZero);
495    Value *IsNan = Builder.CreateFCmpUNO(V, V, "cmp");
496    Value *NanLiteral = EmitScalarExpr(E->getArg(0));
497    BasicBlock *NotNan = createBasicBlock("fpclassify_not_nan", this->CurFn);
498    Builder.CreateCondBr(IsNan, End, NotNan);
499    Result->addIncoming(NanLiteral, NotZero);
500
501    // if (fabs(V) == infinity) return FP_INFINITY
502    Builder.SetInsertPoint(NotNan);
503    Value *VAbs = EmitFAbs(*this, V, E->getArg(5)->getType());
504    Value *IsInf =
505      Builder.CreateFCmpOEQ(VAbs, ConstantFP::getInfinity(V->getType()),
506                            "isinf");
507    Value *InfLiteral = EmitScalarExpr(E->getArg(1));
508    BasicBlock *NotInf = createBasicBlock("fpclassify_not_inf", this->CurFn);
509    Builder.CreateCondBr(IsInf, End, NotInf);
510    Result->addIncoming(InfLiteral, NotNan);
511
512    // if (fabs(V) >= MIN_NORMAL) return FP_NORMAL else FP_SUBNORMAL
513    Builder.SetInsertPoint(NotInf);
514    APFloat Smallest = APFloat::getSmallestNormalized(
515        getContext().getFloatTypeSemantics(E->getArg(5)->getType()));
516    Value *IsNormal =
517      Builder.CreateFCmpUGE(VAbs, ConstantFP::get(V->getContext(), Smallest),
518                            "isnormal");
519    Value *NormalResult =
520      Builder.CreateSelect(IsNormal, EmitScalarExpr(E->getArg(2)),
521                           EmitScalarExpr(E->getArg(3)));
522    Builder.CreateBr(End);
523    Result->addIncoming(NormalResult, NotInf);
524
525    // return Result
526    Builder.SetInsertPoint(End);
527    return RValue::get(Result);
528  }
529
530  case Builtin::BIalloca:
531  case Builtin::BI__builtin_alloca: {
532    Value *Size = EmitScalarExpr(E->getArg(0));
533    return RValue::get(Builder.CreateAlloca(Builder.getInt8Ty(), Size));
534  }
535  case Builtin::BIbzero:
536  case Builtin::BI__builtin_bzero: {
537    Value *Address = EmitScalarExpr(E->getArg(0));
538    Value *SizeVal = EmitScalarExpr(E->getArg(1));
539    Builder.CreateMemSet(Address, Builder.getInt8(0), SizeVal, 1, false);
540    return RValue::get(Address);
541  }
542  case Builtin::BImemcpy:
543  case Builtin::BI__builtin_memcpy: {
544    Value *Address = EmitScalarExpr(E->getArg(0));
545    Value *SrcAddr = EmitScalarExpr(E->getArg(1));
546    Value *SizeVal = EmitScalarExpr(E->getArg(2));
547    Builder.CreateMemCpy(Address, SrcAddr, SizeVal, 1, false);
548    return RValue::get(Address);
549  }
550
551  case Builtin::BI__builtin___memcpy_chk: {
552    // fold __builtin_memcpy_chk(x, y, cst1, cst2) to memset iff cst1<=cst2.
553    llvm::APSInt Size, DstSize;
554    if (!E->getArg(2)->EvaluateAsInt(Size, CGM.getContext()) ||
555        !E->getArg(3)->EvaluateAsInt(DstSize, CGM.getContext()))
556      break;
557    if (Size.ugt(DstSize))
558      break;
559    Value *Dest = EmitScalarExpr(E->getArg(0));
560    Value *Src = EmitScalarExpr(E->getArg(1));
561    Value *SizeVal = llvm::ConstantInt::get(Builder.getContext(), Size);
562    Builder.CreateMemCpy(Dest, Src, SizeVal, 1, false);
563    return RValue::get(Dest);
564  }
565
566  case Builtin::BI__builtin_objc_memmove_collectable: {
567    Value *Address = EmitScalarExpr(E->getArg(0));
568    Value *SrcAddr = EmitScalarExpr(E->getArg(1));
569    Value *SizeVal = EmitScalarExpr(E->getArg(2));
570    CGM.getObjCRuntime().EmitGCMemmoveCollectable(*this,
571                                                  Address, SrcAddr, SizeVal);
572    return RValue::get(Address);
573  }
574
575  case Builtin::BI__builtin___memmove_chk: {
576    // fold __builtin_memmove_chk(x, y, cst1, cst2) to memset iff cst1<=cst2.
577    llvm::APSInt Size, DstSize;
578    if (!E->getArg(2)->EvaluateAsInt(Size, CGM.getContext()) ||
579        !E->getArg(3)->EvaluateAsInt(DstSize, CGM.getContext()))
580      break;
581    if (Size.ugt(DstSize))
582      break;
583    Value *Dest = EmitScalarExpr(E->getArg(0));
584    Value *Src = EmitScalarExpr(E->getArg(1));
585    Value *SizeVal = llvm::ConstantInt::get(Builder.getContext(), Size);
586    Builder.CreateMemMove(Dest, Src, SizeVal, 1, false);
587    return RValue::get(Dest);
588  }
589
590  case Builtin::BImemmove:
591  case Builtin::BI__builtin_memmove: {
592    Value *Address = EmitScalarExpr(E->getArg(0));
593    Value *SrcAddr = EmitScalarExpr(E->getArg(1));
594    Value *SizeVal = EmitScalarExpr(E->getArg(2));
595    Builder.CreateMemMove(Address, SrcAddr, SizeVal, 1, false);
596    return RValue::get(Address);
597  }
598  case Builtin::BImemset:
599  case Builtin::BI__builtin_memset: {
600    Value *Address = EmitScalarExpr(E->getArg(0));
601    Value *ByteVal = Builder.CreateTrunc(EmitScalarExpr(E->getArg(1)),
602                                         Builder.getInt8Ty());
603    Value *SizeVal = EmitScalarExpr(E->getArg(2));
604    Builder.CreateMemSet(Address, ByteVal, SizeVal, 1, false);
605    return RValue::get(Address);
606  }
607  case Builtin::BI__builtin___memset_chk: {
608    // fold __builtin_memset_chk(x, y, cst1, cst2) to memset iff cst1<=cst2.
609    llvm::APSInt Size, DstSize;
610    if (!E->getArg(2)->EvaluateAsInt(Size, CGM.getContext()) ||
611        !E->getArg(3)->EvaluateAsInt(DstSize, CGM.getContext()))
612      break;
613    if (Size.ugt(DstSize))
614      break;
615    Value *Address = EmitScalarExpr(E->getArg(0));
616    Value *ByteVal = Builder.CreateTrunc(EmitScalarExpr(E->getArg(1)),
617                                         Builder.getInt8Ty());
618    Value *SizeVal = llvm::ConstantInt::get(Builder.getContext(), Size);
619    Builder.CreateMemSet(Address, ByteVal, SizeVal, 1, false);
620
621    return RValue::get(Address);
622  }
623  case Builtin::BI__builtin_dwarf_cfa: {
624    // The offset in bytes from the first argument to the CFA.
625    //
626    // Why on earth is this in the frontend?  Is there any reason at
627    // all that the backend can't reasonably determine this while
628    // lowering llvm.eh.dwarf.cfa()?
629    //
630    // TODO: If there's a satisfactory reason, add a target hook for
631    // this instead of hard-coding 0, which is correct for most targets.
632    int32_t Offset = 0;
633
634    Value *F = CGM.getIntrinsic(Intrinsic::eh_dwarf_cfa);
635    return RValue::get(Builder.CreateCall(F,
636                                      llvm::ConstantInt::get(Int32Ty, Offset)));
637  }
638  case Builtin::BI__builtin_return_address: {
639    Value *Depth = EmitScalarExpr(E->getArg(0));
640    Depth = Builder.CreateIntCast(Depth, Int32Ty, false);
641    Value *F = CGM.getIntrinsic(Intrinsic::returnaddress);
642    return RValue::get(Builder.CreateCall(F, Depth));
643  }
644  case Builtin::BI__builtin_frame_address: {
645    Value *Depth = EmitScalarExpr(E->getArg(0));
646    Depth = Builder.CreateIntCast(Depth, Int32Ty, false);
647    Value *F = CGM.getIntrinsic(Intrinsic::frameaddress);
648    return RValue::get(Builder.CreateCall(F, Depth));
649  }
650  case Builtin::BI__builtin_extract_return_addr: {
651    Value *Address = EmitScalarExpr(E->getArg(0));
652    Value *Result = getTargetHooks().decodeReturnAddress(*this, Address);
653    return RValue::get(Result);
654  }
655  case Builtin::BI__builtin_frob_return_addr: {
656    Value *Address = EmitScalarExpr(E->getArg(0));
657    Value *Result = getTargetHooks().encodeReturnAddress(*this, Address);
658    return RValue::get(Result);
659  }
660  case Builtin::BI__builtin_dwarf_sp_column: {
661    llvm::IntegerType *Ty
662      = cast<llvm::IntegerType>(ConvertType(E->getType()));
663    int Column = getTargetHooks().getDwarfEHStackPointer(CGM);
664    if (Column == -1) {
665      CGM.ErrorUnsupported(E, "__builtin_dwarf_sp_column");
666      return RValue::get(llvm::UndefValue::get(Ty));
667    }
668    return RValue::get(llvm::ConstantInt::get(Ty, Column, true));
669  }
670  case Builtin::BI__builtin_init_dwarf_reg_size_table: {
671    Value *Address = EmitScalarExpr(E->getArg(0));
672    if (getTargetHooks().initDwarfEHRegSizeTable(*this, Address))
673      CGM.ErrorUnsupported(E, "__builtin_init_dwarf_reg_size_table");
674    return RValue::get(llvm::UndefValue::get(ConvertType(E->getType())));
675  }
676  case Builtin::BI__builtin_eh_return: {
677    Value *Int = EmitScalarExpr(E->getArg(0));
678    Value *Ptr = EmitScalarExpr(E->getArg(1));
679
680    llvm::IntegerType *IntTy = cast<llvm::IntegerType>(Int->getType());
681    assert((IntTy->getBitWidth() == 32 || IntTy->getBitWidth() == 64) &&
682           "LLVM's __builtin_eh_return only supports 32- and 64-bit variants");
683    Value *F = CGM.getIntrinsic(IntTy->getBitWidth() == 32
684                                  ? Intrinsic::eh_return_i32
685                                  : Intrinsic::eh_return_i64);
686    Builder.CreateCall2(F, Int, Ptr);
687    Builder.CreateUnreachable();
688
689    // We do need to preserve an insertion point.
690    EmitBlock(createBasicBlock("builtin_eh_return.cont"));
691
692    return RValue::get(0);
693  }
694  case Builtin::BI__builtin_unwind_init: {
695    Value *F = CGM.getIntrinsic(Intrinsic::eh_unwind_init);
696    return RValue::get(Builder.CreateCall(F));
697  }
698  case Builtin::BI__builtin_extend_pointer: {
699    // Extends a pointer to the size of an _Unwind_Word, which is
700    // uint64_t on all platforms.  Generally this gets poked into a
701    // register and eventually used as an address, so if the
702    // addressing registers are wider than pointers and the platform
703    // doesn't implicitly ignore high-order bits when doing
704    // addressing, we need to make sure we zext / sext based on
705    // the platform's expectations.
706    //
707    // See: http://gcc.gnu.org/ml/gcc-bugs/2002-02/msg00237.html
708
709    // Cast the pointer to intptr_t.
710    Value *Ptr = EmitScalarExpr(E->getArg(0));
711    Value *Result = Builder.CreatePtrToInt(Ptr, IntPtrTy, "extend.cast");
712
713    // If that's 64 bits, we're done.
714    if (IntPtrTy->getBitWidth() == 64)
715      return RValue::get(Result);
716
717    // Otherwise, ask the codegen data what to do.
718    if (getTargetHooks().extendPointerWithSExt())
719      return RValue::get(Builder.CreateSExt(Result, Int64Ty, "extend.sext"));
720    else
721      return RValue::get(Builder.CreateZExt(Result, Int64Ty, "extend.zext"));
722  }
723  case Builtin::BI__builtin_setjmp: {
724    // Buffer is a void**.
725    Value *Buf = EmitScalarExpr(E->getArg(0));
726
727    // Store the frame pointer to the setjmp buffer.
728    Value *FrameAddr =
729      Builder.CreateCall(CGM.getIntrinsic(Intrinsic::frameaddress),
730                         ConstantInt::get(Int32Ty, 0));
731    Builder.CreateStore(FrameAddr, Buf);
732
733    // Store the stack pointer to the setjmp buffer.
734    Value *StackAddr =
735      Builder.CreateCall(CGM.getIntrinsic(Intrinsic::stacksave));
736    Value *StackSaveSlot =
737      Builder.CreateGEP(Buf, ConstantInt::get(Int32Ty, 2));
738    Builder.CreateStore(StackAddr, StackSaveSlot);
739
740    // Call LLVM's EH setjmp, which is lightweight.
741    Value *F = CGM.getIntrinsic(Intrinsic::eh_sjlj_setjmp);
742    Buf = Builder.CreateBitCast(Buf, Int8PtrTy);
743    return RValue::get(Builder.CreateCall(F, Buf));
744  }
745  case Builtin::BI__builtin_longjmp: {
746    Value *Buf = EmitScalarExpr(E->getArg(0));
747    Buf = Builder.CreateBitCast(Buf, Int8PtrTy);
748
749    // Call LLVM's EH longjmp, which is lightweight.
750    Builder.CreateCall(CGM.getIntrinsic(Intrinsic::eh_sjlj_longjmp), Buf);
751
752    // longjmp doesn't return; mark this as unreachable.
753    Builder.CreateUnreachable();
754
755    // We do need to preserve an insertion point.
756    EmitBlock(createBasicBlock("longjmp.cont"));
757
758    return RValue::get(0);
759  }
760  case Builtin::BI__sync_fetch_and_add:
761  case Builtin::BI__sync_fetch_and_sub:
762  case Builtin::BI__sync_fetch_and_or:
763  case Builtin::BI__sync_fetch_and_and:
764  case Builtin::BI__sync_fetch_and_xor:
765  case Builtin::BI__sync_add_and_fetch:
766  case Builtin::BI__sync_sub_and_fetch:
767  case Builtin::BI__sync_and_and_fetch:
768  case Builtin::BI__sync_or_and_fetch:
769  case Builtin::BI__sync_xor_and_fetch:
770  case Builtin::BI__sync_val_compare_and_swap:
771  case Builtin::BI__sync_bool_compare_and_swap:
772  case Builtin::BI__sync_lock_test_and_set:
773  case Builtin::BI__sync_lock_release:
774  case Builtin::BI__sync_swap:
775    llvm_unreachable("Shouldn't make it through sema");
776  case Builtin::BI__sync_fetch_and_add_1:
777  case Builtin::BI__sync_fetch_and_add_2:
778  case Builtin::BI__sync_fetch_and_add_4:
779  case Builtin::BI__sync_fetch_and_add_8:
780  case Builtin::BI__sync_fetch_and_add_16:
781    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Add, E);
782  case Builtin::BI__sync_fetch_and_sub_1:
783  case Builtin::BI__sync_fetch_and_sub_2:
784  case Builtin::BI__sync_fetch_and_sub_4:
785  case Builtin::BI__sync_fetch_and_sub_8:
786  case Builtin::BI__sync_fetch_and_sub_16:
787    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Sub, E);
788  case Builtin::BI__sync_fetch_and_or_1:
789  case Builtin::BI__sync_fetch_and_or_2:
790  case Builtin::BI__sync_fetch_and_or_4:
791  case Builtin::BI__sync_fetch_and_or_8:
792  case Builtin::BI__sync_fetch_and_or_16:
793    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Or, E);
794  case Builtin::BI__sync_fetch_and_and_1:
795  case Builtin::BI__sync_fetch_and_and_2:
796  case Builtin::BI__sync_fetch_and_and_4:
797  case Builtin::BI__sync_fetch_and_and_8:
798  case Builtin::BI__sync_fetch_and_and_16:
799    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::And, E);
800  case Builtin::BI__sync_fetch_and_xor_1:
801  case Builtin::BI__sync_fetch_and_xor_2:
802  case Builtin::BI__sync_fetch_and_xor_4:
803  case Builtin::BI__sync_fetch_and_xor_8:
804  case Builtin::BI__sync_fetch_and_xor_16:
805    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Xor, E);
806
807  // Clang extensions: not overloaded yet.
808  case Builtin::BI__sync_fetch_and_min:
809    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Min, E);
810  case Builtin::BI__sync_fetch_and_max:
811    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Max, E);
812  case Builtin::BI__sync_fetch_and_umin:
813    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::UMin, E);
814  case Builtin::BI__sync_fetch_and_umax:
815    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::UMax, E);
816
817  case Builtin::BI__sync_add_and_fetch_1:
818  case Builtin::BI__sync_add_and_fetch_2:
819  case Builtin::BI__sync_add_and_fetch_4:
820  case Builtin::BI__sync_add_and_fetch_8:
821  case Builtin::BI__sync_add_and_fetch_16:
822    return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Add, E,
823                                llvm::Instruction::Add);
824  case Builtin::BI__sync_sub_and_fetch_1:
825  case Builtin::BI__sync_sub_and_fetch_2:
826  case Builtin::BI__sync_sub_and_fetch_4:
827  case Builtin::BI__sync_sub_and_fetch_8:
828  case Builtin::BI__sync_sub_and_fetch_16:
829    return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Sub, E,
830                                llvm::Instruction::Sub);
831  case Builtin::BI__sync_and_and_fetch_1:
832  case Builtin::BI__sync_and_and_fetch_2:
833  case Builtin::BI__sync_and_and_fetch_4:
834  case Builtin::BI__sync_and_and_fetch_8:
835  case Builtin::BI__sync_and_and_fetch_16:
836    return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::And, E,
837                                llvm::Instruction::And);
838  case Builtin::BI__sync_or_and_fetch_1:
839  case Builtin::BI__sync_or_and_fetch_2:
840  case Builtin::BI__sync_or_and_fetch_4:
841  case Builtin::BI__sync_or_and_fetch_8:
842  case Builtin::BI__sync_or_and_fetch_16:
843    return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Or, E,
844                                llvm::Instruction::Or);
845  case Builtin::BI__sync_xor_and_fetch_1:
846  case Builtin::BI__sync_xor_and_fetch_2:
847  case Builtin::BI__sync_xor_and_fetch_4:
848  case Builtin::BI__sync_xor_and_fetch_8:
849  case Builtin::BI__sync_xor_and_fetch_16:
850    return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Xor, E,
851                                llvm::Instruction::Xor);
852
853  case Builtin::BI__sync_val_compare_and_swap_1:
854  case Builtin::BI__sync_val_compare_and_swap_2:
855  case Builtin::BI__sync_val_compare_and_swap_4:
856  case Builtin::BI__sync_val_compare_and_swap_8:
857  case Builtin::BI__sync_val_compare_and_swap_16: {
858    QualType T = E->getType();
859    llvm::Value *DestPtr = EmitScalarExpr(E->getArg(0));
860    unsigned AddrSpace =
861      cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace();
862
863    llvm::IntegerType *IntType =
864      llvm::IntegerType::get(getLLVMContext(),
865                             getContext().getTypeSize(T));
866    llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace);
867
868    Value *Args[3];
869    Args[0] = Builder.CreateBitCast(DestPtr, IntPtrType);
870    Args[1] = EmitScalarExpr(E->getArg(1));
871    llvm::Type *ValueType = Args[1]->getType();
872    Args[1] = EmitToInt(*this, Args[1], T, IntType);
873    Args[2] = EmitToInt(*this, EmitScalarExpr(E->getArg(2)), T, IntType);
874
875    Value *Result = Builder.CreateAtomicCmpXchg(Args[0], Args[1], Args[2],
876                                                llvm::SequentiallyConsistent);
877    Result = EmitFromInt(*this, Result, T, ValueType);
878    return RValue::get(Result);
879  }
880
881  case Builtin::BI__sync_bool_compare_and_swap_1:
882  case Builtin::BI__sync_bool_compare_and_swap_2:
883  case Builtin::BI__sync_bool_compare_and_swap_4:
884  case Builtin::BI__sync_bool_compare_and_swap_8:
885  case Builtin::BI__sync_bool_compare_and_swap_16: {
886    QualType T = E->getArg(1)->getType();
887    llvm::Value *DestPtr = EmitScalarExpr(E->getArg(0));
888    unsigned AddrSpace =
889      cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace();
890
891    llvm::IntegerType *IntType =
892      llvm::IntegerType::get(getLLVMContext(),
893                             getContext().getTypeSize(T));
894    llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace);
895
896    Value *Args[3];
897    Args[0] = Builder.CreateBitCast(DestPtr, IntPtrType);
898    Args[1] = EmitToInt(*this, EmitScalarExpr(E->getArg(1)), T, IntType);
899    Args[2] = EmitToInt(*this, EmitScalarExpr(E->getArg(2)), T, IntType);
900
901    Value *OldVal = Args[1];
902    Value *PrevVal = Builder.CreateAtomicCmpXchg(Args[0], Args[1], Args[2],
903                                                 llvm::SequentiallyConsistent);
904    Value *Result = Builder.CreateICmpEQ(PrevVal, OldVal);
905    // zext bool to int.
906    Result = Builder.CreateZExt(Result, ConvertType(E->getType()));
907    return RValue::get(Result);
908  }
909
910  case Builtin::BI__sync_swap_1:
911  case Builtin::BI__sync_swap_2:
912  case Builtin::BI__sync_swap_4:
913  case Builtin::BI__sync_swap_8:
914  case Builtin::BI__sync_swap_16:
915    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Xchg, E);
916
917  case Builtin::BI__sync_lock_test_and_set_1:
918  case Builtin::BI__sync_lock_test_and_set_2:
919  case Builtin::BI__sync_lock_test_and_set_4:
920  case Builtin::BI__sync_lock_test_and_set_8:
921  case Builtin::BI__sync_lock_test_and_set_16:
922    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Xchg, E);
923
924  case Builtin::BI__sync_lock_release_1:
925  case Builtin::BI__sync_lock_release_2:
926  case Builtin::BI__sync_lock_release_4:
927  case Builtin::BI__sync_lock_release_8:
928  case Builtin::BI__sync_lock_release_16: {
929    Value *Ptr = EmitScalarExpr(E->getArg(0));
930    llvm::Type *ElLLVMTy =
931      cast<llvm::PointerType>(Ptr->getType())->getElementType();
932    llvm::StoreInst *Store =
933      Builder.CreateStore(llvm::Constant::getNullValue(ElLLVMTy), Ptr);
934    QualType ElTy = E->getArg(0)->getType()->getPointeeType();
935    CharUnits StoreSize = getContext().getTypeSizeInChars(ElTy);
936    Store->setAlignment(StoreSize.getQuantity());
937    Store->setAtomic(llvm::Release);
938    return RValue::get(0);
939  }
940
941  case Builtin::BI__sync_synchronize: {
942    // We assume this is supposed to correspond to a C++0x-style
943    // sequentially-consistent fence (i.e. this is only usable for
944    // synchonization, not device I/O or anything like that). This intrinsic
945    // is really badly designed in the sense that in theory, there isn't
946    // any way to safely use it... but in practice, it mostly works
947    // to use it with non-atomic loads and stores to get acquire/release
948    // semantics.
949    Builder.CreateFence(llvm::SequentiallyConsistent);
950    return RValue::get(0);
951  }
952
953  case Builtin::BI__atomic_thread_fence:
954  case Builtin::BI__atomic_signal_fence: {
955    llvm::SynchronizationScope Scope;
956    if (BuiltinID == Builtin::BI__atomic_signal_fence)
957      Scope = llvm::SingleThread;
958    else
959      Scope = llvm::CrossThread;
960    Value *Order = EmitScalarExpr(E->getArg(0));
961    if (isa<llvm::ConstantInt>(Order)) {
962      int ord = cast<llvm::ConstantInt>(Order)->getZExtValue();
963      switch (ord) {
964      case 0:  // memory_order_relaxed
965      default: // invalid order
966        break;
967      case 1:  // memory_order_consume
968      case 2:  // memory_order_acquire
969        Builder.CreateFence(llvm::Acquire, Scope);
970        break;
971      case 3:  // memory_order_release
972        Builder.CreateFence(llvm::Release, Scope);
973        break;
974      case 4:  // memory_order_acq_rel
975        Builder.CreateFence(llvm::AcquireRelease, Scope);
976        break;
977      case 5:  // memory_order_seq_cst
978        Builder.CreateFence(llvm::SequentiallyConsistent, Scope);
979        break;
980      }
981      return RValue::get(0);
982    }
983
984    llvm::BasicBlock *AcquireBB, *ReleaseBB, *AcqRelBB, *SeqCstBB;
985    AcquireBB = createBasicBlock("acquire", CurFn);
986    ReleaseBB = createBasicBlock("release", CurFn);
987    AcqRelBB = createBasicBlock("acqrel", CurFn);
988    SeqCstBB = createBasicBlock("seqcst", CurFn);
989    llvm::BasicBlock *ContBB = createBasicBlock("atomic.continue", CurFn);
990
991    Order = Builder.CreateIntCast(Order, Builder.getInt32Ty(), false);
992    llvm::SwitchInst *SI = Builder.CreateSwitch(Order, ContBB);
993
994    Builder.SetInsertPoint(AcquireBB);
995    Builder.CreateFence(llvm::Acquire, Scope);
996    Builder.CreateBr(ContBB);
997    SI->addCase(Builder.getInt32(1), AcquireBB);
998    SI->addCase(Builder.getInt32(2), AcquireBB);
999
1000    Builder.SetInsertPoint(ReleaseBB);
1001    Builder.CreateFence(llvm::Release, Scope);
1002    Builder.CreateBr(ContBB);
1003    SI->addCase(Builder.getInt32(3), ReleaseBB);
1004
1005    Builder.SetInsertPoint(AcqRelBB);
1006    Builder.CreateFence(llvm::AcquireRelease, Scope);
1007    Builder.CreateBr(ContBB);
1008    SI->addCase(Builder.getInt32(4), AcqRelBB);
1009
1010    Builder.SetInsertPoint(SeqCstBB);
1011    Builder.CreateFence(llvm::SequentiallyConsistent, Scope);
1012    Builder.CreateBr(ContBB);
1013    SI->addCase(Builder.getInt32(5), SeqCstBB);
1014
1015    Builder.SetInsertPoint(ContBB);
1016    return RValue::get(0);
1017  }
1018
1019    // Library functions with special handling.
1020  case Builtin::BIsqrt:
1021  case Builtin::BIsqrtf:
1022  case Builtin::BIsqrtl: {
1023    // TODO: there is currently no set of optimizer flags
1024    // sufficient for us to rewrite sqrt to @llvm.sqrt.
1025    // -fmath-errno=0 is not good enough; we need finiteness.
1026    // We could probably precondition the call with an ult
1027    // against 0, but is that worth the complexity?
1028    break;
1029  }
1030
1031  case Builtin::BIpow:
1032  case Builtin::BIpowf:
1033  case Builtin::BIpowl: {
1034    // Rewrite sqrt to intrinsic if allowed.
1035    if (!FD->hasAttr<ConstAttr>())
1036      break;
1037    Value *Base = EmitScalarExpr(E->getArg(0));
1038    Value *Exponent = EmitScalarExpr(E->getArg(1));
1039    llvm::Type *ArgType = Base->getType();
1040    Value *F = CGM.getIntrinsic(Intrinsic::pow, ArgType);
1041    return RValue::get(Builder.CreateCall2(F, Base, Exponent));
1042  }
1043
1044  case Builtin::BIfma:
1045  case Builtin::BIfmaf:
1046  case Builtin::BIfmal:
1047  case Builtin::BI__builtin_fma:
1048  case Builtin::BI__builtin_fmaf:
1049  case Builtin::BI__builtin_fmal: {
1050    // Rewrite fma to intrinsic.
1051    Value *FirstArg = EmitScalarExpr(E->getArg(0));
1052    llvm::Type *ArgType = FirstArg->getType();
1053    Value *F = CGM.getIntrinsic(Intrinsic::fma, ArgType);
1054    return RValue::get(Builder.CreateCall3(F, FirstArg,
1055                                              EmitScalarExpr(E->getArg(1)),
1056                                              EmitScalarExpr(E->getArg(2))));
1057  }
1058
1059  case Builtin::BI__builtin_signbit:
1060  case Builtin::BI__builtin_signbitf:
1061  case Builtin::BI__builtin_signbitl: {
1062    LLVMContext &C = CGM.getLLVMContext();
1063
1064    Value *Arg = EmitScalarExpr(E->getArg(0));
1065    llvm::Type *ArgTy = Arg->getType();
1066    if (ArgTy->isPPC_FP128Ty())
1067      break; // FIXME: I'm not sure what the right implementation is here.
1068    int ArgWidth = ArgTy->getPrimitiveSizeInBits();
1069    llvm::Type *ArgIntTy = llvm::IntegerType::get(C, ArgWidth);
1070    Value *BCArg = Builder.CreateBitCast(Arg, ArgIntTy);
1071    Value *ZeroCmp = llvm::Constant::getNullValue(ArgIntTy);
1072    Value *Result = Builder.CreateICmpSLT(BCArg, ZeroCmp);
1073    return RValue::get(Builder.CreateZExt(Result, ConvertType(E->getType())));
1074  }
1075  case Builtin::BI__builtin_annotation: {
1076    llvm::Value *AnnVal = EmitScalarExpr(E->getArg(0));
1077    llvm::Value *F = CGM.getIntrinsic(llvm::Intrinsic::annotation,
1078                                      AnnVal->getType());
1079
1080    // Get the annotation string, go through casts. Sema requires this to be a
1081    // non-wide string literal, potentially casted, so the cast<> is safe.
1082    const Expr *AnnotationStrExpr = E->getArg(1)->IgnoreParenCasts();
1083    llvm::StringRef Str = cast<StringLiteral>(AnnotationStrExpr)->getString();
1084    return RValue::get(EmitAnnotationCall(F, AnnVal, Str, E->getExprLoc()));
1085  }
1086  }
1087
1088  // If this is an alias for a lib function (e.g. __builtin_sin), emit
1089  // the call using the normal call path, but using the unmangled
1090  // version of the function name.
1091  if (getContext().BuiltinInfo.isLibFunction(BuiltinID))
1092    return emitLibraryCall(*this, FD, E,
1093                           CGM.getBuiltinLibFunction(FD, BuiltinID));
1094
1095  // If this is a predefined lib function (e.g. malloc), emit the call
1096  // using exactly the normal call path.
1097  if (getContext().BuiltinInfo.isPredefinedLibFunction(BuiltinID))
1098    return emitLibraryCall(*this, FD, E, EmitScalarExpr(E->getCallee()));
1099
1100  // See if we have a target specific intrinsic.
1101  const char *Name = getContext().BuiltinInfo.GetName(BuiltinID);
1102  Intrinsic::ID IntrinsicID = Intrinsic::not_intrinsic;
1103  if (const char *Prefix =
1104      llvm::Triple::getArchTypePrefix(Target.getTriple().getArch()))
1105    IntrinsicID = Intrinsic::getIntrinsicForGCCBuiltin(Prefix, Name);
1106
1107  if (IntrinsicID != Intrinsic::not_intrinsic) {
1108    SmallVector<Value*, 16> Args;
1109
1110    // Find out if any arguments are required to be integer constant
1111    // expressions.
1112    unsigned ICEArguments = 0;
1113    ASTContext::GetBuiltinTypeError Error;
1114    getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
1115    assert(Error == ASTContext::GE_None && "Should not codegen an error");
1116
1117    Function *F = CGM.getIntrinsic(IntrinsicID);
1118    llvm::FunctionType *FTy = F->getFunctionType();
1119
1120    for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
1121      Value *ArgValue;
1122      // If this is a normal argument, just emit it as a scalar.
1123      if ((ICEArguments & (1 << i)) == 0) {
1124        ArgValue = EmitScalarExpr(E->getArg(i));
1125      } else {
1126        // If this is required to be a constant, constant fold it so that we
1127        // know that the generated intrinsic gets a ConstantInt.
1128        llvm::APSInt Result;
1129        bool IsConst = E->getArg(i)->isIntegerConstantExpr(Result,getContext());
1130        assert(IsConst && "Constant arg isn't actually constant?");
1131        (void)IsConst;
1132        ArgValue = llvm::ConstantInt::get(getLLVMContext(), Result);
1133      }
1134
1135      // If the intrinsic arg type is different from the builtin arg type
1136      // we need to do a bit cast.
1137      llvm::Type *PTy = FTy->getParamType(i);
1138      if (PTy != ArgValue->getType()) {
1139        assert(PTy->canLosslesslyBitCastTo(FTy->getParamType(i)) &&
1140               "Must be able to losslessly bit cast to param");
1141        ArgValue = Builder.CreateBitCast(ArgValue, PTy);
1142      }
1143
1144      Args.push_back(ArgValue);
1145    }
1146
1147    Value *V = Builder.CreateCall(F, Args);
1148    QualType BuiltinRetType = E->getType();
1149
1150    llvm::Type *RetTy = llvm::Type::getVoidTy(getLLVMContext());
1151    if (!BuiltinRetType->isVoidType()) RetTy = ConvertType(BuiltinRetType);
1152
1153    if (RetTy != V->getType()) {
1154      assert(V->getType()->canLosslesslyBitCastTo(RetTy) &&
1155             "Must be able to losslessly bit cast result type");
1156      V = Builder.CreateBitCast(V, RetTy);
1157    }
1158
1159    return RValue::get(V);
1160  }
1161
1162  // See if we have a target specific builtin that needs to be lowered.
1163  if (Value *V = EmitTargetBuiltinExpr(BuiltinID, E))
1164    return RValue::get(V);
1165
1166  ErrorUnsupported(E, "builtin function");
1167
1168  // Unknown builtin, for now just dump it out and return undef.
1169  if (hasAggregateLLVMType(E->getType()))
1170    return RValue::getAggregate(CreateMemTemp(E->getType()));
1171  return RValue::get(llvm::UndefValue::get(ConvertType(E->getType())));
1172}
1173
1174Value *CodeGenFunction::EmitTargetBuiltinExpr(unsigned BuiltinID,
1175                                              const CallExpr *E) {
1176  switch (Target.getTriple().getArch()) {
1177  case llvm::Triple::arm:
1178  case llvm::Triple::thumb:
1179    return EmitARMBuiltinExpr(BuiltinID, E);
1180  case llvm::Triple::x86:
1181  case llvm::Triple::x86_64:
1182    return EmitX86BuiltinExpr(BuiltinID, E);
1183  case llvm::Triple::ppc:
1184  case llvm::Triple::ppc64:
1185    return EmitPPCBuiltinExpr(BuiltinID, E);
1186  case llvm::Triple::hexagon:
1187    return EmitHexagonBuiltinExpr(BuiltinID, E);
1188  default:
1189    return 0;
1190  }
1191}
1192
1193static llvm::VectorType *GetNeonType(LLVMContext &C, NeonTypeFlags TypeFlags) {
1194  int IsQuad = TypeFlags.isQuad();
1195  switch (TypeFlags.getEltType()) {
1196  case NeonTypeFlags::Int8:
1197  case NeonTypeFlags::Poly8:
1198    return llvm::VectorType::get(llvm::Type::getInt8Ty(C), 8 << IsQuad);
1199  case NeonTypeFlags::Int16:
1200  case NeonTypeFlags::Poly16:
1201  case NeonTypeFlags::Float16:
1202    return llvm::VectorType::get(llvm::Type::getInt16Ty(C), 4 << IsQuad);
1203  case NeonTypeFlags::Int32:
1204    return llvm::VectorType::get(llvm::Type::getInt32Ty(C), 2 << IsQuad);
1205  case NeonTypeFlags::Int64:
1206    return llvm::VectorType::get(llvm::Type::getInt64Ty(C), 1 << IsQuad);
1207  case NeonTypeFlags::Float32:
1208    return llvm::VectorType::get(llvm::Type::getFloatTy(C), 2 << IsQuad);
1209  }
1210  llvm_unreachable("Invalid NeonTypeFlags element type!");
1211}
1212
1213Value *CodeGenFunction::EmitNeonSplat(Value *V, Constant *C) {
1214  unsigned nElts = cast<llvm::VectorType>(V->getType())->getNumElements();
1215  SmallVector<Constant*, 16> Indices(nElts, C);
1216  Value* SV = llvm::ConstantVector::get(Indices);
1217  return Builder.CreateShuffleVector(V, V, SV, "lane");
1218}
1219
1220Value *CodeGenFunction::EmitNeonCall(Function *F, SmallVectorImpl<Value*> &Ops,
1221                                     const char *name,
1222                                     unsigned shift, bool rightshift) {
1223  unsigned j = 0;
1224  for (Function::const_arg_iterator ai = F->arg_begin(), ae = F->arg_end();
1225       ai != ae; ++ai, ++j)
1226    if (shift > 0 && shift == j)
1227      Ops[j] = EmitNeonShiftVector(Ops[j], ai->getType(), rightshift);
1228    else
1229      Ops[j] = Builder.CreateBitCast(Ops[j], ai->getType(), name);
1230
1231  return Builder.CreateCall(F, Ops, name);
1232}
1233
1234Value *CodeGenFunction::EmitNeonShiftVector(Value *V, llvm::Type *Ty,
1235                                            bool neg) {
1236  ConstantInt *CI = cast<ConstantInt>(V);
1237  int SV = CI->getSExtValue();
1238
1239  llvm::VectorType *VTy = cast<llvm::VectorType>(Ty);
1240  llvm::Constant *C = ConstantInt::get(VTy->getElementType(), neg ? -SV : SV);
1241  SmallVector<llvm::Constant*, 16> CV(VTy->getNumElements(), C);
1242  return llvm::ConstantVector::get(CV);
1243}
1244
1245/// GetPointeeAlignment - Given an expression with a pointer type, find the
1246/// alignment of the type referenced by the pointer.  Skip over implicit
1247/// casts.
1248static Value *GetPointeeAlignment(CodeGenFunction &CGF, const Expr *Addr) {
1249  unsigned Align = 1;
1250  // Check if the type is a pointer.  The implicit cast operand might not be.
1251  while (Addr->getType()->isPointerType()) {
1252    QualType PtTy = Addr->getType()->getPointeeType();
1253    unsigned NewA = CGF.getContext().getTypeAlignInChars(PtTy).getQuantity();
1254    if (NewA > Align)
1255      Align = NewA;
1256
1257    // If the address is an implicit cast, repeat with the cast operand.
1258    if (const ImplicitCastExpr *CastAddr = dyn_cast<ImplicitCastExpr>(Addr)) {
1259      Addr = CastAddr->getSubExpr();
1260      continue;
1261    }
1262    break;
1263  }
1264  return llvm::ConstantInt::get(CGF.Int32Ty, Align);
1265}
1266
1267Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
1268                                           const CallExpr *E) {
1269  if (BuiltinID == ARM::BI__clear_cache) {
1270    const FunctionDecl *FD = E->getDirectCallee();
1271    // Oddly people write this call without args on occasion and gcc accepts
1272    // it - it's also marked as varargs in the description file.
1273    SmallVector<Value*, 2> Ops;
1274    for (unsigned i = 0; i < E->getNumArgs(); i++)
1275      Ops.push_back(EmitScalarExpr(E->getArg(i)));
1276    llvm::Type *Ty = CGM.getTypes().ConvertType(FD->getType());
1277    llvm::FunctionType *FTy = cast<llvm::FunctionType>(Ty);
1278    StringRef Name = FD->getName();
1279    return Builder.CreateCall(CGM.CreateRuntimeFunction(FTy, Name), Ops);
1280  }
1281
1282  if (BuiltinID == ARM::BI__builtin_arm_ldrexd) {
1283    Function *F = CGM.getIntrinsic(Intrinsic::arm_ldrexd);
1284
1285    Value *LdPtr = EmitScalarExpr(E->getArg(0));
1286    Value *Val = Builder.CreateCall(F, LdPtr, "ldrexd");
1287
1288    Value *Val0 = Builder.CreateExtractValue(Val, 1);
1289    Value *Val1 = Builder.CreateExtractValue(Val, 0);
1290    Val0 = Builder.CreateZExt(Val0, Int64Ty);
1291    Val1 = Builder.CreateZExt(Val1, Int64Ty);
1292
1293    Value *ShiftCst = llvm::ConstantInt::get(Int64Ty, 32);
1294    Val = Builder.CreateShl(Val0, ShiftCst, "shl", true /* nuw */);
1295    return Builder.CreateOr(Val, Val1);
1296  }
1297
1298  if (BuiltinID == ARM::BI__builtin_arm_strexd) {
1299    Function *F = CGM.getIntrinsic(Intrinsic::arm_strexd);
1300    llvm::Type *STy = llvm::StructType::get(Int32Ty, Int32Ty, NULL);
1301
1302    Value *One = llvm::ConstantInt::get(Int32Ty, 1);
1303    Value *Tmp = Builder.CreateAlloca(Int64Ty, One);
1304    Value *Val = EmitScalarExpr(E->getArg(0));
1305    Builder.CreateStore(Val, Tmp);
1306
1307    Value *LdPtr = Builder.CreateBitCast(Tmp,llvm::PointerType::getUnqual(STy));
1308    Val = Builder.CreateLoad(LdPtr);
1309
1310    Value *Arg0 = Builder.CreateExtractValue(Val, 0);
1311    Value *Arg1 = Builder.CreateExtractValue(Val, 1);
1312    Value *StPtr = EmitScalarExpr(E->getArg(1));
1313    return Builder.CreateCall3(F, Arg0, Arg1, StPtr, "strexd");
1314  }
1315
1316  SmallVector<Value*, 4> Ops;
1317  for (unsigned i = 0, e = E->getNumArgs() - 1; i != e; i++)
1318    Ops.push_back(EmitScalarExpr(E->getArg(i)));
1319
1320  // vget_lane and vset_lane are not overloaded and do not have an extra
1321  // argument that specifies the vector type.
1322  switch (BuiltinID) {
1323  default: break;
1324  case ARM::BI__builtin_neon_vget_lane_i8:
1325  case ARM::BI__builtin_neon_vget_lane_i16:
1326  case ARM::BI__builtin_neon_vget_lane_i32:
1327  case ARM::BI__builtin_neon_vget_lane_i64:
1328  case ARM::BI__builtin_neon_vget_lane_f32:
1329  case ARM::BI__builtin_neon_vgetq_lane_i8:
1330  case ARM::BI__builtin_neon_vgetq_lane_i16:
1331  case ARM::BI__builtin_neon_vgetq_lane_i32:
1332  case ARM::BI__builtin_neon_vgetq_lane_i64:
1333  case ARM::BI__builtin_neon_vgetq_lane_f32:
1334    return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)),
1335                                        "vget_lane");
1336  case ARM::BI__builtin_neon_vset_lane_i8:
1337  case ARM::BI__builtin_neon_vset_lane_i16:
1338  case ARM::BI__builtin_neon_vset_lane_i32:
1339  case ARM::BI__builtin_neon_vset_lane_i64:
1340  case ARM::BI__builtin_neon_vset_lane_f32:
1341  case ARM::BI__builtin_neon_vsetq_lane_i8:
1342  case ARM::BI__builtin_neon_vsetq_lane_i16:
1343  case ARM::BI__builtin_neon_vsetq_lane_i32:
1344  case ARM::BI__builtin_neon_vsetq_lane_i64:
1345  case ARM::BI__builtin_neon_vsetq_lane_f32:
1346    Ops.push_back(EmitScalarExpr(E->getArg(2)));
1347    return Builder.CreateInsertElement(Ops[1], Ops[0], Ops[2], "vset_lane");
1348  }
1349
1350  // Get the last argument, which specifies the vector type.
1351  llvm::APSInt Result;
1352  const Expr *Arg = E->getArg(E->getNumArgs()-1);
1353  if (!Arg->isIntegerConstantExpr(Result, getContext()))
1354    return 0;
1355
1356  if (BuiltinID == ARM::BI__builtin_arm_vcvtr_f ||
1357      BuiltinID == ARM::BI__builtin_arm_vcvtr_d) {
1358    // Determine the overloaded type of this builtin.
1359    llvm::Type *Ty;
1360    if (BuiltinID == ARM::BI__builtin_arm_vcvtr_f)
1361      Ty = llvm::Type::getFloatTy(getLLVMContext());
1362    else
1363      Ty = llvm::Type::getDoubleTy(getLLVMContext());
1364
1365    // Determine whether this is an unsigned conversion or not.
1366    bool usgn = Result.getZExtValue() == 1;
1367    unsigned Int = usgn ? Intrinsic::arm_vcvtru : Intrinsic::arm_vcvtr;
1368
1369    // Call the appropriate intrinsic.
1370    Function *F = CGM.getIntrinsic(Int, Ty);
1371    return Builder.CreateCall(F, Ops, "vcvtr");
1372  }
1373
1374  // Determine the type of this overloaded NEON intrinsic.
1375  NeonTypeFlags Type(Result.getZExtValue());
1376  bool usgn = Type.isUnsigned();
1377  bool quad = Type.isQuad();
1378  bool rightShift = false;
1379
1380  llvm::VectorType *VTy = GetNeonType(getLLVMContext(), Type);
1381  llvm::Type *Ty = VTy;
1382  if (!Ty)
1383    return 0;
1384
1385  unsigned Int;
1386  switch (BuiltinID) {
1387  default: return 0;
1388  case ARM::BI__builtin_neon_vabd_v:
1389  case ARM::BI__builtin_neon_vabdq_v:
1390    Int = usgn ? Intrinsic::arm_neon_vabdu : Intrinsic::arm_neon_vabds;
1391    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vabd");
1392  case ARM::BI__builtin_neon_vabs_v:
1393  case ARM::BI__builtin_neon_vabsq_v:
1394    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vabs, Ty),
1395                        Ops, "vabs");
1396  case ARM::BI__builtin_neon_vaddhn_v:
1397    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vaddhn, Ty),
1398                        Ops, "vaddhn");
1399  case ARM::BI__builtin_neon_vcale_v:
1400    std::swap(Ops[0], Ops[1]);
1401  case ARM::BI__builtin_neon_vcage_v: {
1402    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacged);
1403    return EmitNeonCall(F, Ops, "vcage");
1404  }
1405  case ARM::BI__builtin_neon_vcaleq_v:
1406    std::swap(Ops[0], Ops[1]);
1407  case ARM::BI__builtin_neon_vcageq_v: {
1408    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacgeq);
1409    return EmitNeonCall(F, Ops, "vcage");
1410  }
1411  case ARM::BI__builtin_neon_vcalt_v:
1412    std::swap(Ops[0], Ops[1]);
1413  case ARM::BI__builtin_neon_vcagt_v: {
1414    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacgtd);
1415    return EmitNeonCall(F, Ops, "vcagt");
1416  }
1417  case ARM::BI__builtin_neon_vcaltq_v:
1418    std::swap(Ops[0], Ops[1]);
1419  case ARM::BI__builtin_neon_vcagtq_v: {
1420    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacgtq);
1421    return EmitNeonCall(F, Ops, "vcagt");
1422  }
1423  case ARM::BI__builtin_neon_vcls_v:
1424  case ARM::BI__builtin_neon_vclsq_v: {
1425    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcls, Ty);
1426    return EmitNeonCall(F, Ops, "vcls");
1427  }
1428  case ARM::BI__builtin_neon_vclz_v:
1429  case ARM::BI__builtin_neon_vclzq_v: {
1430    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vclz, Ty);
1431    return EmitNeonCall(F, Ops, "vclz");
1432  }
1433  case ARM::BI__builtin_neon_vcnt_v:
1434  case ARM::BI__builtin_neon_vcntq_v: {
1435    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcnt, Ty);
1436    return EmitNeonCall(F, Ops, "vcnt");
1437  }
1438  case ARM::BI__builtin_neon_vcvt_f16_v: {
1439    assert(Type.getEltType() == NeonTypeFlags::Float16 && !quad &&
1440           "unexpected vcvt_f16_v builtin");
1441    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcvtfp2hf);
1442    return EmitNeonCall(F, Ops, "vcvt");
1443  }
1444  case ARM::BI__builtin_neon_vcvt_f32_f16: {
1445    assert(Type.getEltType() == NeonTypeFlags::Float16 && !quad &&
1446           "unexpected vcvt_f32_f16 builtin");
1447    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcvthf2fp);
1448    return EmitNeonCall(F, Ops, "vcvt");
1449  }
1450  case ARM::BI__builtin_neon_vcvt_f32_v:
1451  case ARM::BI__builtin_neon_vcvtq_f32_v:
1452    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1453    Ty = GetNeonType(getLLVMContext(),
1454                     NeonTypeFlags(NeonTypeFlags::Float32, false, quad));
1455    return usgn ? Builder.CreateUIToFP(Ops[0], Ty, "vcvt")
1456                : Builder.CreateSIToFP(Ops[0], Ty, "vcvt");
1457  case ARM::BI__builtin_neon_vcvt_s32_v:
1458  case ARM::BI__builtin_neon_vcvt_u32_v:
1459  case ARM::BI__builtin_neon_vcvtq_s32_v:
1460  case ARM::BI__builtin_neon_vcvtq_u32_v: {
1461    llvm::Type *FloatTy =
1462      GetNeonType(getLLVMContext(),
1463                  NeonTypeFlags(NeonTypeFlags::Float32, false, quad));
1464    Ops[0] = Builder.CreateBitCast(Ops[0], FloatTy);
1465    return usgn ? Builder.CreateFPToUI(Ops[0], Ty, "vcvt")
1466                : Builder.CreateFPToSI(Ops[0], Ty, "vcvt");
1467  }
1468  case ARM::BI__builtin_neon_vcvt_n_f32_v:
1469  case ARM::BI__builtin_neon_vcvtq_n_f32_v: {
1470    llvm::Type *FloatTy =
1471      GetNeonType(getLLVMContext(),
1472                  NeonTypeFlags(NeonTypeFlags::Float32, false, quad));
1473    llvm::Type *Tys[2] = { FloatTy, Ty };
1474    Int = usgn ? Intrinsic::arm_neon_vcvtfxu2fp
1475               : Intrinsic::arm_neon_vcvtfxs2fp;
1476    Function *F = CGM.getIntrinsic(Int, Tys);
1477    return EmitNeonCall(F, Ops, "vcvt_n");
1478  }
1479  case ARM::BI__builtin_neon_vcvt_n_s32_v:
1480  case ARM::BI__builtin_neon_vcvt_n_u32_v:
1481  case ARM::BI__builtin_neon_vcvtq_n_s32_v:
1482  case ARM::BI__builtin_neon_vcvtq_n_u32_v: {
1483    llvm::Type *FloatTy =
1484      GetNeonType(getLLVMContext(),
1485                  NeonTypeFlags(NeonTypeFlags::Float32, false, quad));
1486    llvm::Type *Tys[2] = { Ty, FloatTy };
1487    Int = usgn ? Intrinsic::arm_neon_vcvtfp2fxu
1488               : Intrinsic::arm_neon_vcvtfp2fxs;
1489    Function *F = CGM.getIntrinsic(Int, Tys);
1490    return EmitNeonCall(F, Ops, "vcvt_n");
1491  }
1492  case ARM::BI__builtin_neon_vext_v:
1493  case ARM::BI__builtin_neon_vextq_v: {
1494    int CV = cast<ConstantInt>(Ops[2])->getSExtValue();
1495    SmallVector<Constant*, 16> Indices;
1496    for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i)
1497      Indices.push_back(ConstantInt::get(Int32Ty, i+CV));
1498
1499    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1500    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1501    Value *SV = llvm::ConstantVector::get(Indices);
1502    return Builder.CreateShuffleVector(Ops[0], Ops[1], SV, "vext");
1503  }
1504  case ARM::BI__builtin_neon_vhadd_v:
1505  case ARM::BI__builtin_neon_vhaddq_v:
1506    Int = usgn ? Intrinsic::arm_neon_vhaddu : Intrinsic::arm_neon_vhadds;
1507    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vhadd");
1508  case ARM::BI__builtin_neon_vhsub_v:
1509  case ARM::BI__builtin_neon_vhsubq_v:
1510    Int = usgn ? Intrinsic::arm_neon_vhsubu : Intrinsic::arm_neon_vhsubs;
1511    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vhsub");
1512  case ARM::BI__builtin_neon_vld1_v:
1513  case ARM::BI__builtin_neon_vld1q_v:
1514    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1515    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vld1, Ty),
1516                        Ops, "vld1");
1517  case ARM::BI__builtin_neon_vld1_lane_v:
1518  case ARM::BI__builtin_neon_vld1q_lane_v:
1519    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1520    Ty = llvm::PointerType::getUnqual(VTy->getElementType());
1521    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1522    Ops[0] = Builder.CreateLoad(Ops[0]);
1523    return Builder.CreateInsertElement(Ops[1], Ops[0], Ops[2], "vld1_lane");
1524  case ARM::BI__builtin_neon_vld1_dup_v:
1525  case ARM::BI__builtin_neon_vld1q_dup_v: {
1526    Value *V = UndefValue::get(Ty);
1527    Ty = llvm::PointerType::getUnqual(VTy->getElementType());
1528    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1529    Ops[0] = Builder.CreateLoad(Ops[0]);
1530    llvm::Constant *CI = ConstantInt::get(Int32Ty, 0);
1531    Ops[0] = Builder.CreateInsertElement(V, Ops[0], CI);
1532    return EmitNeonSplat(Ops[0], CI);
1533  }
1534  case ARM::BI__builtin_neon_vld2_v:
1535  case ARM::BI__builtin_neon_vld2q_v: {
1536    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld2, Ty);
1537    Value *Align = GetPointeeAlignment(*this, E->getArg(1));
1538    Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld2");
1539    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1540    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1541    return Builder.CreateStore(Ops[1], Ops[0]);
1542  }
1543  case ARM::BI__builtin_neon_vld3_v:
1544  case ARM::BI__builtin_neon_vld3q_v: {
1545    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld3, Ty);
1546    Value *Align = GetPointeeAlignment(*this, E->getArg(1));
1547    Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld3");
1548    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1549    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1550    return Builder.CreateStore(Ops[1], Ops[0]);
1551  }
1552  case ARM::BI__builtin_neon_vld4_v:
1553  case ARM::BI__builtin_neon_vld4q_v: {
1554    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld4, Ty);
1555    Value *Align = GetPointeeAlignment(*this, E->getArg(1));
1556    Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld4");
1557    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1558    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1559    return Builder.CreateStore(Ops[1], Ops[0]);
1560  }
1561  case ARM::BI__builtin_neon_vld2_lane_v:
1562  case ARM::BI__builtin_neon_vld2q_lane_v: {
1563    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld2lane, Ty);
1564    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1565    Ops[3] = Builder.CreateBitCast(Ops[3], Ty);
1566    Ops.push_back(GetPointeeAlignment(*this, E->getArg(1)));
1567    Ops[1] = Builder.CreateCall(F, makeArrayRef(Ops).slice(1), "vld2_lane");
1568    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1569    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1570    return Builder.CreateStore(Ops[1], Ops[0]);
1571  }
1572  case ARM::BI__builtin_neon_vld3_lane_v:
1573  case ARM::BI__builtin_neon_vld3q_lane_v: {
1574    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld3lane, Ty);
1575    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1576    Ops[3] = Builder.CreateBitCast(Ops[3], Ty);
1577    Ops[4] = Builder.CreateBitCast(Ops[4], Ty);
1578    Ops.push_back(GetPointeeAlignment(*this, E->getArg(1)));
1579    Ops[1] = Builder.CreateCall(F, makeArrayRef(Ops).slice(1), "vld3_lane");
1580    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1581    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1582    return Builder.CreateStore(Ops[1], Ops[0]);
1583  }
1584  case ARM::BI__builtin_neon_vld4_lane_v:
1585  case ARM::BI__builtin_neon_vld4q_lane_v: {
1586    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld4lane, Ty);
1587    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1588    Ops[3] = Builder.CreateBitCast(Ops[3], Ty);
1589    Ops[4] = Builder.CreateBitCast(Ops[4], Ty);
1590    Ops[5] = Builder.CreateBitCast(Ops[5], Ty);
1591    Ops.push_back(GetPointeeAlignment(*this, E->getArg(1)));
1592    Ops[1] = Builder.CreateCall(F, makeArrayRef(Ops).slice(1), "vld3_lane");
1593    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1594    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1595    return Builder.CreateStore(Ops[1], Ops[0]);
1596  }
1597  case ARM::BI__builtin_neon_vld2_dup_v:
1598  case ARM::BI__builtin_neon_vld3_dup_v:
1599  case ARM::BI__builtin_neon_vld4_dup_v: {
1600    // Handle 64-bit elements as a special-case.  There is no "dup" needed.
1601    if (VTy->getElementType()->getPrimitiveSizeInBits() == 64) {
1602      switch (BuiltinID) {
1603      case ARM::BI__builtin_neon_vld2_dup_v:
1604        Int = Intrinsic::arm_neon_vld2;
1605        break;
1606      case ARM::BI__builtin_neon_vld3_dup_v:
1607        Int = Intrinsic::arm_neon_vld2;
1608        break;
1609      case ARM::BI__builtin_neon_vld4_dup_v:
1610        Int = Intrinsic::arm_neon_vld2;
1611        break;
1612      default: llvm_unreachable("unknown vld_dup intrinsic?");
1613      }
1614      Function *F = CGM.getIntrinsic(Int, Ty);
1615      Value *Align = GetPointeeAlignment(*this, E->getArg(1));
1616      Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld_dup");
1617      Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1618      Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1619      return Builder.CreateStore(Ops[1], Ops[0]);
1620    }
1621    switch (BuiltinID) {
1622    case ARM::BI__builtin_neon_vld2_dup_v:
1623      Int = Intrinsic::arm_neon_vld2lane;
1624      break;
1625    case ARM::BI__builtin_neon_vld3_dup_v:
1626      Int = Intrinsic::arm_neon_vld2lane;
1627      break;
1628    case ARM::BI__builtin_neon_vld4_dup_v:
1629      Int = Intrinsic::arm_neon_vld2lane;
1630      break;
1631    default: llvm_unreachable("unknown vld_dup intrinsic?");
1632    }
1633    Function *F = CGM.getIntrinsic(Int, Ty);
1634    llvm::StructType *STy = cast<llvm::StructType>(F->getReturnType());
1635
1636    SmallVector<Value*, 6> Args;
1637    Args.push_back(Ops[1]);
1638    Args.append(STy->getNumElements(), UndefValue::get(Ty));
1639
1640    llvm::Constant *CI = ConstantInt::get(Int32Ty, 0);
1641    Args.push_back(CI);
1642    Args.push_back(GetPointeeAlignment(*this, E->getArg(1)));
1643
1644    Ops[1] = Builder.CreateCall(F, Args, "vld_dup");
1645    // splat lane 0 to all elts in each vector of the result.
1646    for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1647      Value *Val = Builder.CreateExtractValue(Ops[1], i);
1648      Value *Elt = Builder.CreateBitCast(Val, Ty);
1649      Elt = EmitNeonSplat(Elt, CI);
1650      Elt = Builder.CreateBitCast(Elt, Val->getType());
1651      Ops[1] = Builder.CreateInsertValue(Ops[1], Elt, i);
1652    }
1653    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1654    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1655    return Builder.CreateStore(Ops[1], Ops[0]);
1656  }
1657  case ARM::BI__builtin_neon_vmax_v:
1658  case ARM::BI__builtin_neon_vmaxq_v:
1659    Int = usgn ? Intrinsic::arm_neon_vmaxu : Intrinsic::arm_neon_vmaxs;
1660    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vmax");
1661  case ARM::BI__builtin_neon_vmin_v:
1662  case ARM::BI__builtin_neon_vminq_v:
1663    Int = usgn ? Intrinsic::arm_neon_vminu : Intrinsic::arm_neon_vmins;
1664    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vmin");
1665  case ARM::BI__builtin_neon_vmovl_v: {
1666    llvm::Type *DTy =llvm::VectorType::getTruncatedElementVectorType(VTy);
1667    Ops[0] = Builder.CreateBitCast(Ops[0], DTy);
1668    if (usgn)
1669      return Builder.CreateZExt(Ops[0], Ty, "vmovl");
1670    return Builder.CreateSExt(Ops[0], Ty, "vmovl");
1671  }
1672  case ARM::BI__builtin_neon_vmovn_v: {
1673    llvm::Type *QTy = llvm::VectorType::getExtendedElementVectorType(VTy);
1674    Ops[0] = Builder.CreateBitCast(Ops[0], QTy);
1675    return Builder.CreateTrunc(Ops[0], Ty, "vmovn");
1676  }
1677  case ARM::BI__builtin_neon_vmul_v:
1678  case ARM::BI__builtin_neon_vmulq_v:
1679    assert(Type.isPoly() && "vmul builtin only supported for polynomial types");
1680    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vmulp, Ty),
1681                        Ops, "vmul");
1682  case ARM::BI__builtin_neon_vmull_v:
1683    Int = usgn ? Intrinsic::arm_neon_vmullu : Intrinsic::arm_neon_vmulls;
1684    Int = Type.isPoly() ? (unsigned)Intrinsic::arm_neon_vmullp : Int;
1685    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vmull");
1686  case ARM::BI__builtin_neon_vpadal_v:
1687  case ARM::BI__builtin_neon_vpadalq_v: {
1688    Int = usgn ? Intrinsic::arm_neon_vpadalu : Intrinsic::arm_neon_vpadals;
1689    // The source operand type has twice as many elements of half the size.
1690    unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits();
1691    llvm::Type *EltTy =
1692      llvm::IntegerType::get(getLLVMContext(), EltBits / 2);
1693    llvm::Type *NarrowTy =
1694      llvm::VectorType::get(EltTy, VTy->getNumElements() * 2);
1695    llvm::Type *Tys[2] = { Ty, NarrowTy };
1696    return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vpadal");
1697  }
1698  case ARM::BI__builtin_neon_vpadd_v:
1699    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vpadd, Ty),
1700                        Ops, "vpadd");
1701  case ARM::BI__builtin_neon_vpaddl_v:
1702  case ARM::BI__builtin_neon_vpaddlq_v: {
1703    Int = usgn ? Intrinsic::arm_neon_vpaddlu : Intrinsic::arm_neon_vpaddls;
1704    // The source operand type has twice as many elements of half the size.
1705    unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits();
1706    llvm::Type *EltTy = llvm::IntegerType::get(getLLVMContext(), EltBits / 2);
1707    llvm::Type *NarrowTy =
1708      llvm::VectorType::get(EltTy, VTy->getNumElements() * 2);
1709    llvm::Type *Tys[2] = { Ty, NarrowTy };
1710    return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vpaddl");
1711  }
1712  case ARM::BI__builtin_neon_vpmax_v:
1713    Int = usgn ? Intrinsic::arm_neon_vpmaxu : Intrinsic::arm_neon_vpmaxs;
1714    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vpmax");
1715  case ARM::BI__builtin_neon_vpmin_v:
1716    Int = usgn ? Intrinsic::arm_neon_vpminu : Intrinsic::arm_neon_vpmins;
1717    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vpmin");
1718  case ARM::BI__builtin_neon_vqabs_v:
1719  case ARM::BI__builtin_neon_vqabsq_v:
1720    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqabs, Ty),
1721                        Ops, "vqabs");
1722  case ARM::BI__builtin_neon_vqadd_v:
1723  case ARM::BI__builtin_neon_vqaddq_v:
1724    Int = usgn ? Intrinsic::arm_neon_vqaddu : Intrinsic::arm_neon_vqadds;
1725    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqadd");
1726  case ARM::BI__builtin_neon_vqdmlal_v:
1727    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmlal, Ty),
1728                        Ops, "vqdmlal");
1729  case ARM::BI__builtin_neon_vqdmlsl_v:
1730    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmlsl, Ty),
1731                        Ops, "vqdmlsl");
1732  case ARM::BI__builtin_neon_vqdmulh_v:
1733  case ARM::BI__builtin_neon_vqdmulhq_v:
1734    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmulh, Ty),
1735                        Ops, "vqdmulh");
1736  case ARM::BI__builtin_neon_vqdmull_v:
1737    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmull, Ty),
1738                        Ops, "vqdmull");
1739  case ARM::BI__builtin_neon_vqmovn_v:
1740    Int = usgn ? Intrinsic::arm_neon_vqmovnu : Intrinsic::arm_neon_vqmovns;
1741    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqmovn");
1742  case ARM::BI__builtin_neon_vqmovun_v:
1743    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqmovnsu, Ty),
1744                        Ops, "vqdmull");
1745  case ARM::BI__builtin_neon_vqneg_v:
1746  case ARM::BI__builtin_neon_vqnegq_v:
1747    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqneg, Ty),
1748                        Ops, "vqneg");
1749  case ARM::BI__builtin_neon_vqrdmulh_v:
1750  case ARM::BI__builtin_neon_vqrdmulhq_v:
1751    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqrdmulh, Ty),
1752                        Ops, "vqrdmulh");
1753  case ARM::BI__builtin_neon_vqrshl_v:
1754  case ARM::BI__builtin_neon_vqrshlq_v:
1755    Int = usgn ? Intrinsic::arm_neon_vqrshiftu : Intrinsic::arm_neon_vqrshifts;
1756    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqrshl");
1757  case ARM::BI__builtin_neon_vqrshrn_n_v:
1758    Int = usgn ? Intrinsic::arm_neon_vqrshiftnu : Intrinsic::arm_neon_vqrshiftns;
1759    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqrshrn_n",
1760                        1, true);
1761  case ARM::BI__builtin_neon_vqrshrun_n_v:
1762    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqrshiftnsu, Ty),
1763                        Ops, "vqrshrun_n", 1, true);
1764  case ARM::BI__builtin_neon_vqshl_v:
1765  case ARM::BI__builtin_neon_vqshlq_v:
1766    Int = usgn ? Intrinsic::arm_neon_vqshiftu : Intrinsic::arm_neon_vqshifts;
1767    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshl");
1768  case ARM::BI__builtin_neon_vqshl_n_v:
1769  case ARM::BI__builtin_neon_vqshlq_n_v:
1770    Int = usgn ? Intrinsic::arm_neon_vqshiftu : Intrinsic::arm_neon_vqshifts;
1771    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshl_n",
1772                        1, false);
1773  case ARM::BI__builtin_neon_vqshlu_n_v:
1774  case ARM::BI__builtin_neon_vqshluq_n_v:
1775    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqshiftsu, Ty),
1776                        Ops, "vqshlu", 1, false);
1777  case ARM::BI__builtin_neon_vqshrn_n_v:
1778    Int = usgn ? Intrinsic::arm_neon_vqshiftnu : Intrinsic::arm_neon_vqshiftns;
1779    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshrn_n",
1780                        1, true);
1781  case ARM::BI__builtin_neon_vqshrun_n_v:
1782    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqshiftnsu, Ty),
1783                        Ops, "vqshrun_n", 1, true);
1784  case ARM::BI__builtin_neon_vqsub_v:
1785  case ARM::BI__builtin_neon_vqsubq_v:
1786    Int = usgn ? Intrinsic::arm_neon_vqsubu : Intrinsic::arm_neon_vqsubs;
1787    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqsub");
1788  case ARM::BI__builtin_neon_vraddhn_v:
1789    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vraddhn, Ty),
1790                        Ops, "vraddhn");
1791  case ARM::BI__builtin_neon_vrecpe_v:
1792  case ARM::BI__builtin_neon_vrecpeq_v:
1793    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrecpe, Ty),
1794                        Ops, "vrecpe");
1795  case ARM::BI__builtin_neon_vrecps_v:
1796  case ARM::BI__builtin_neon_vrecpsq_v:
1797    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrecps, Ty),
1798                        Ops, "vrecps");
1799  case ARM::BI__builtin_neon_vrhadd_v:
1800  case ARM::BI__builtin_neon_vrhaddq_v:
1801    Int = usgn ? Intrinsic::arm_neon_vrhaddu : Intrinsic::arm_neon_vrhadds;
1802    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrhadd");
1803  case ARM::BI__builtin_neon_vrshl_v:
1804  case ARM::BI__builtin_neon_vrshlq_v:
1805    Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts;
1806    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshl");
1807  case ARM::BI__builtin_neon_vrshrn_n_v:
1808    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrshiftn, Ty),
1809                        Ops, "vrshrn_n", 1, true);
1810  case ARM::BI__builtin_neon_vrshr_n_v:
1811  case ARM::BI__builtin_neon_vrshrq_n_v:
1812    Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts;
1813    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshr_n", 1, true);
1814  case ARM::BI__builtin_neon_vrsqrte_v:
1815  case ARM::BI__builtin_neon_vrsqrteq_v:
1816    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrsqrte, Ty),
1817                        Ops, "vrsqrte");
1818  case ARM::BI__builtin_neon_vrsqrts_v:
1819  case ARM::BI__builtin_neon_vrsqrtsq_v:
1820    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrsqrts, Ty),
1821                        Ops, "vrsqrts");
1822  case ARM::BI__builtin_neon_vrsra_n_v:
1823  case ARM::BI__builtin_neon_vrsraq_n_v:
1824    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1825    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1826    Ops[2] = EmitNeonShiftVector(Ops[2], Ty, true);
1827    Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts;
1828    Ops[1] = Builder.CreateCall2(CGM.getIntrinsic(Int, Ty), Ops[1], Ops[2]);
1829    return Builder.CreateAdd(Ops[0], Ops[1], "vrsra_n");
1830  case ARM::BI__builtin_neon_vrsubhn_v:
1831    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrsubhn, Ty),
1832                        Ops, "vrsubhn");
1833  case ARM::BI__builtin_neon_vshl_v:
1834  case ARM::BI__builtin_neon_vshlq_v:
1835    Int = usgn ? Intrinsic::arm_neon_vshiftu : Intrinsic::arm_neon_vshifts;
1836    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vshl");
1837  case ARM::BI__builtin_neon_vshll_n_v:
1838    Int = usgn ? Intrinsic::arm_neon_vshiftlu : Intrinsic::arm_neon_vshiftls;
1839    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vshll", 1);
1840  case ARM::BI__builtin_neon_vshl_n_v:
1841  case ARM::BI__builtin_neon_vshlq_n_v:
1842    Ops[1] = EmitNeonShiftVector(Ops[1], Ty, false);
1843    return Builder.CreateShl(Builder.CreateBitCast(Ops[0],Ty), Ops[1], "vshl_n");
1844  case ARM::BI__builtin_neon_vshrn_n_v:
1845    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vshiftn, Ty),
1846                        Ops, "vshrn_n", 1, true);
1847  case ARM::BI__builtin_neon_vshr_n_v:
1848  case ARM::BI__builtin_neon_vshrq_n_v:
1849    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1850    Ops[1] = EmitNeonShiftVector(Ops[1], Ty, false);
1851    if (usgn)
1852      return Builder.CreateLShr(Ops[0], Ops[1], "vshr_n");
1853    else
1854      return Builder.CreateAShr(Ops[0], Ops[1], "vshr_n");
1855  case ARM::BI__builtin_neon_vsri_n_v:
1856  case ARM::BI__builtin_neon_vsriq_n_v:
1857    rightShift = true;
1858  case ARM::BI__builtin_neon_vsli_n_v:
1859  case ARM::BI__builtin_neon_vsliq_n_v:
1860    Ops[2] = EmitNeonShiftVector(Ops[2], Ty, rightShift);
1861    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vshiftins, Ty),
1862                        Ops, "vsli_n");
1863  case ARM::BI__builtin_neon_vsra_n_v:
1864  case ARM::BI__builtin_neon_vsraq_n_v:
1865    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1866    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1867    Ops[2] = EmitNeonShiftVector(Ops[2], Ty, false);
1868    if (usgn)
1869      Ops[1] = Builder.CreateLShr(Ops[1], Ops[2], "vsra_n");
1870    else
1871      Ops[1] = Builder.CreateAShr(Ops[1], Ops[2], "vsra_n");
1872    return Builder.CreateAdd(Ops[0], Ops[1]);
1873  case ARM::BI__builtin_neon_vst1_v:
1874  case ARM::BI__builtin_neon_vst1q_v:
1875    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1876    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst1, Ty),
1877                        Ops, "");
1878  case ARM::BI__builtin_neon_vst1_lane_v:
1879  case ARM::BI__builtin_neon_vst1q_lane_v:
1880    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1881    Ops[1] = Builder.CreateExtractElement(Ops[1], Ops[2]);
1882    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1883    return Builder.CreateStore(Ops[1], Builder.CreateBitCast(Ops[0], Ty));
1884  case ARM::BI__builtin_neon_vst2_v:
1885  case ARM::BI__builtin_neon_vst2q_v:
1886    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1887    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst2, Ty),
1888                        Ops, "");
1889  case ARM::BI__builtin_neon_vst2_lane_v:
1890  case ARM::BI__builtin_neon_vst2q_lane_v:
1891    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1892    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst2lane, Ty),
1893                        Ops, "");
1894  case ARM::BI__builtin_neon_vst3_v:
1895  case ARM::BI__builtin_neon_vst3q_v:
1896    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1897    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst3, Ty),
1898                        Ops, "");
1899  case ARM::BI__builtin_neon_vst3_lane_v:
1900  case ARM::BI__builtin_neon_vst3q_lane_v:
1901    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1902    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst3lane, Ty),
1903                        Ops, "");
1904  case ARM::BI__builtin_neon_vst4_v:
1905  case ARM::BI__builtin_neon_vst4q_v:
1906    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1907    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst4, Ty),
1908                        Ops, "");
1909  case ARM::BI__builtin_neon_vst4_lane_v:
1910  case ARM::BI__builtin_neon_vst4q_lane_v:
1911    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1912    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst4lane, Ty),
1913                        Ops, "");
1914  case ARM::BI__builtin_neon_vsubhn_v:
1915    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vsubhn, Ty),
1916                        Ops, "vsubhn");
1917  case ARM::BI__builtin_neon_vtbl1_v:
1918    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl1),
1919                        Ops, "vtbl1");
1920  case ARM::BI__builtin_neon_vtbl2_v:
1921    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl2),
1922                        Ops, "vtbl2");
1923  case ARM::BI__builtin_neon_vtbl3_v:
1924    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl3),
1925                        Ops, "vtbl3");
1926  case ARM::BI__builtin_neon_vtbl4_v:
1927    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl4),
1928                        Ops, "vtbl4");
1929  case ARM::BI__builtin_neon_vtbx1_v:
1930    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx1),
1931                        Ops, "vtbx1");
1932  case ARM::BI__builtin_neon_vtbx2_v:
1933    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx2),
1934                        Ops, "vtbx2");
1935  case ARM::BI__builtin_neon_vtbx3_v:
1936    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx3),
1937                        Ops, "vtbx3");
1938  case ARM::BI__builtin_neon_vtbx4_v:
1939    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx4),
1940                        Ops, "vtbx4");
1941  case ARM::BI__builtin_neon_vtst_v:
1942  case ARM::BI__builtin_neon_vtstq_v: {
1943    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1944    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1945    Ops[0] = Builder.CreateAnd(Ops[0], Ops[1]);
1946    Ops[0] = Builder.CreateICmp(ICmpInst::ICMP_NE, Ops[0],
1947                                ConstantAggregateZero::get(Ty));
1948    return Builder.CreateSExt(Ops[0], Ty, "vtst");
1949  }
1950  case ARM::BI__builtin_neon_vtrn_v:
1951  case ARM::BI__builtin_neon_vtrnq_v: {
1952    Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(Ty));
1953    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1954    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1955    Value *SV = 0;
1956
1957    for (unsigned vi = 0; vi != 2; ++vi) {
1958      SmallVector<Constant*, 16> Indices;
1959      for (unsigned i = 0, e = VTy->getNumElements(); i != e; i += 2) {
1960        Indices.push_back(ConstantInt::get(Int32Ty, i+vi));
1961        Indices.push_back(ConstantInt::get(Int32Ty, i+e+vi));
1962      }
1963      Value *Addr = Builder.CreateConstInBoundsGEP1_32(Ops[0], vi);
1964      SV = llvm::ConstantVector::get(Indices);
1965      SV = Builder.CreateShuffleVector(Ops[1], Ops[2], SV, "vtrn");
1966      SV = Builder.CreateStore(SV, Addr);
1967    }
1968    return SV;
1969  }
1970  case ARM::BI__builtin_neon_vuzp_v:
1971  case ARM::BI__builtin_neon_vuzpq_v: {
1972    Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(Ty));
1973    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1974    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1975    Value *SV = 0;
1976
1977    for (unsigned vi = 0; vi != 2; ++vi) {
1978      SmallVector<Constant*, 16> Indices;
1979      for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i)
1980        Indices.push_back(ConstantInt::get(Int32Ty, 2*i+vi));
1981
1982      Value *Addr = Builder.CreateConstInBoundsGEP1_32(Ops[0], vi);
1983      SV = llvm::ConstantVector::get(Indices);
1984      SV = Builder.CreateShuffleVector(Ops[1], Ops[2], SV, "vuzp");
1985      SV = Builder.CreateStore(SV, Addr);
1986    }
1987    return SV;
1988  }
1989  case ARM::BI__builtin_neon_vzip_v:
1990  case ARM::BI__builtin_neon_vzipq_v: {
1991    Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(Ty));
1992    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1993    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1994    Value *SV = 0;
1995
1996    for (unsigned vi = 0; vi != 2; ++vi) {
1997      SmallVector<Constant*, 16> Indices;
1998      for (unsigned i = 0, e = VTy->getNumElements(); i != e; i += 2) {
1999        Indices.push_back(ConstantInt::get(Int32Ty, (i + vi*e) >> 1));
2000        Indices.push_back(ConstantInt::get(Int32Ty, ((i + vi*e) >> 1)+e));
2001      }
2002      Value *Addr = Builder.CreateConstInBoundsGEP1_32(Ops[0], vi);
2003      SV = llvm::ConstantVector::get(Indices);
2004      SV = Builder.CreateShuffleVector(Ops[1], Ops[2], SV, "vzip");
2005      SV = Builder.CreateStore(SV, Addr);
2006    }
2007    return SV;
2008  }
2009  }
2010}
2011
2012llvm::Value *CodeGenFunction::
2013BuildVector(const SmallVectorImpl<llvm::Value*> &Ops) {
2014  assert((Ops.size() & (Ops.size() - 1)) == 0 &&
2015         "Not a power-of-two sized vector!");
2016  bool AllConstants = true;
2017  for (unsigned i = 0, e = Ops.size(); i != e && AllConstants; ++i)
2018    AllConstants &= isa<Constant>(Ops[i]);
2019
2020  // If this is a constant vector, create a ConstantVector.
2021  if (AllConstants) {
2022    std::vector<llvm::Constant*> CstOps;
2023    for (unsigned i = 0, e = Ops.size(); i != e; ++i)
2024      CstOps.push_back(cast<Constant>(Ops[i]));
2025    return llvm::ConstantVector::get(CstOps);
2026  }
2027
2028  // Otherwise, insertelement the values to build the vector.
2029  Value *Result =
2030    llvm::UndefValue::get(llvm::VectorType::get(Ops[0]->getType(), Ops.size()));
2031
2032  for (unsigned i = 0, e = Ops.size(); i != e; ++i)
2033    Result = Builder.CreateInsertElement(Result, Ops[i],
2034               llvm::ConstantInt::get(llvm::Type::getInt32Ty(getLLVMContext()), i));
2035
2036  return Result;
2037}
2038
2039Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
2040                                           const CallExpr *E) {
2041  SmallVector<Value*, 4> Ops;
2042
2043  // Find out if any arguments are required to be integer constant expressions.
2044  unsigned ICEArguments = 0;
2045  ASTContext::GetBuiltinTypeError Error;
2046  getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
2047  assert(Error == ASTContext::GE_None && "Should not codegen an error");
2048
2049  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
2050    // If this is a normal argument, just emit it as a scalar.
2051    if ((ICEArguments & (1 << i)) == 0) {
2052      Ops.push_back(EmitScalarExpr(E->getArg(i)));
2053      continue;
2054    }
2055
2056    // If this is required to be a constant, constant fold it so that we know
2057    // that the generated intrinsic gets a ConstantInt.
2058    llvm::APSInt Result;
2059    bool IsConst = E->getArg(i)->isIntegerConstantExpr(Result, getContext());
2060    assert(IsConst && "Constant arg isn't actually constant?"); (void)IsConst;
2061    Ops.push_back(llvm::ConstantInt::get(getLLVMContext(), Result));
2062  }
2063
2064  switch (BuiltinID) {
2065  default: return 0;
2066  case X86::BI__builtin_clzs: {
2067    Value *ArgValue = EmitScalarExpr(E->getArg(0));
2068
2069    llvm::Type *ArgType = ArgValue->getType();
2070    Value *F = CGM.getIntrinsic(Intrinsic::ctlz, ArgType);
2071
2072    llvm::Type *ResultType = ConvertType(E->getType());
2073    Value *Result = Builder.CreateCall2(F, ArgValue, Builder.getTrue());
2074    if (Result->getType() != ResultType)
2075      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
2076                                     "cast");
2077    return Result;
2078  }
2079  case X86::BI__builtin_ctzs: {
2080    Value *ArgValue = EmitScalarExpr(E->getArg(0));
2081
2082    llvm::Type *ArgType = ArgValue->getType();
2083    Value *F = CGM.getIntrinsic(Intrinsic::cttz, ArgType);
2084
2085    llvm::Type *ResultType = ConvertType(E->getType());
2086    Value *Result = Builder.CreateCall2(F, ArgValue, Builder.getTrue());
2087    if (Result->getType() != ResultType)
2088      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
2089                                     "cast");
2090    return Result;
2091  }
2092  case X86::BI__builtin_ia32_pslldi128:
2093  case X86::BI__builtin_ia32_psllqi128:
2094  case X86::BI__builtin_ia32_psllwi128:
2095  case X86::BI__builtin_ia32_psradi128:
2096  case X86::BI__builtin_ia32_psrawi128:
2097  case X86::BI__builtin_ia32_psrldi128:
2098  case X86::BI__builtin_ia32_psrlqi128:
2099  case X86::BI__builtin_ia32_psrlwi128: {
2100    Ops[1] = Builder.CreateZExt(Ops[1], Int64Ty, "zext");
2101    llvm::Type *Ty = llvm::VectorType::get(Int64Ty, 2);
2102    llvm::Value *Zero = llvm::ConstantInt::get(Int32Ty, 0);
2103    Ops[1] = Builder.CreateInsertElement(llvm::UndefValue::get(Ty),
2104                                         Ops[1], Zero, "insert");
2105    Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType(), "bitcast");
2106    const char *name = 0;
2107    Intrinsic::ID ID = Intrinsic::not_intrinsic;
2108
2109    switch (BuiltinID) {
2110    default: llvm_unreachable("Unsupported shift intrinsic!");
2111    case X86::BI__builtin_ia32_pslldi128:
2112      name = "pslldi";
2113      ID = Intrinsic::x86_sse2_psll_d;
2114      break;
2115    case X86::BI__builtin_ia32_psllqi128:
2116      name = "psllqi";
2117      ID = Intrinsic::x86_sse2_psll_q;
2118      break;
2119    case X86::BI__builtin_ia32_psllwi128:
2120      name = "psllwi";
2121      ID = Intrinsic::x86_sse2_psll_w;
2122      break;
2123    case X86::BI__builtin_ia32_psradi128:
2124      name = "psradi";
2125      ID = Intrinsic::x86_sse2_psra_d;
2126      break;
2127    case X86::BI__builtin_ia32_psrawi128:
2128      name = "psrawi";
2129      ID = Intrinsic::x86_sse2_psra_w;
2130      break;
2131    case X86::BI__builtin_ia32_psrldi128:
2132      name = "psrldi";
2133      ID = Intrinsic::x86_sse2_psrl_d;
2134      break;
2135    case X86::BI__builtin_ia32_psrlqi128:
2136      name = "psrlqi";
2137      ID = Intrinsic::x86_sse2_psrl_q;
2138      break;
2139    case X86::BI__builtin_ia32_psrlwi128:
2140      name = "psrlwi";
2141      ID = Intrinsic::x86_sse2_psrl_w;
2142      break;
2143    }
2144    llvm::Function *F = CGM.getIntrinsic(ID);
2145    return Builder.CreateCall(F, Ops, name);
2146  }
2147  case X86::BI__builtin_ia32_vec_init_v8qi:
2148  case X86::BI__builtin_ia32_vec_init_v4hi:
2149  case X86::BI__builtin_ia32_vec_init_v2si:
2150    return Builder.CreateBitCast(BuildVector(Ops),
2151                                 llvm::Type::getX86_MMXTy(getLLVMContext()));
2152  case X86::BI__builtin_ia32_vec_ext_v2si:
2153    return Builder.CreateExtractElement(Ops[0],
2154                                  llvm::ConstantInt::get(Ops[1]->getType(), 0));
2155  case X86::BI__builtin_ia32_pslldi:
2156  case X86::BI__builtin_ia32_psllqi:
2157  case X86::BI__builtin_ia32_psllwi:
2158  case X86::BI__builtin_ia32_psradi:
2159  case X86::BI__builtin_ia32_psrawi:
2160  case X86::BI__builtin_ia32_psrldi:
2161  case X86::BI__builtin_ia32_psrlqi:
2162  case X86::BI__builtin_ia32_psrlwi: {
2163    Ops[1] = Builder.CreateZExt(Ops[1], Int64Ty, "zext");
2164    llvm::Type *Ty = llvm::VectorType::get(Int64Ty, 1);
2165    Ops[1] = Builder.CreateBitCast(Ops[1], Ty, "bitcast");
2166    const char *name = 0;
2167    Intrinsic::ID ID = Intrinsic::not_intrinsic;
2168
2169    switch (BuiltinID) {
2170    default: llvm_unreachable("Unsupported shift intrinsic!");
2171    case X86::BI__builtin_ia32_pslldi:
2172      name = "pslldi";
2173      ID = Intrinsic::x86_mmx_psll_d;
2174      break;
2175    case X86::BI__builtin_ia32_psllqi:
2176      name = "psllqi";
2177      ID = Intrinsic::x86_mmx_psll_q;
2178      break;
2179    case X86::BI__builtin_ia32_psllwi:
2180      name = "psllwi";
2181      ID = Intrinsic::x86_mmx_psll_w;
2182      break;
2183    case X86::BI__builtin_ia32_psradi:
2184      name = "psradi";
2185      ID = Intrinsic::x86_mmx_psra_d;
2186      break;
2187    case X86::BI__builtin_ia32_psrawi:
2188      name = "psrawi";
2189      ID = Intrinsic::x86_mmx_psra_w;
2190      break;
2191    case X86::BI__builtin_ia32_psrldi:
2192      name = "psrldi";
2193      ID = Intrinsic::x86_mmx_psrl_d;
2194      break;
2195    case X86::BI__builtin_ia32_psrlqi:
2196      name = "psrlqi";
2197      ID = Intrinsic::x86_mmx_psrl_q;
2198      break;
2199    case X86::BI__builtin_ia32_psrlwi:
2200      name = "psrlwi";
2201      ID = Intrinsic::x86_mmx_psrl_w;
2202      break;
2203    }
2204    llvm::Function *F = CGM.getIntrinsic(ID);
2205    return Builder.CreateCall(F, Ops, name);
2206  }
2207  case X86::BI__builtin_ia32_cmpps: {
2208    llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse_cmp_ps);
2209    return Builder.CreateCall(F, Ops, "cmpps");
2210  }
2211  case X86::BI__builtin_ia32_cmpss: {
2212    llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse_cmp_ss);
2213    return Builder.CreateCall(F, Ops, "cmpss");
2214  }
2215  case X86::BI__builtin_ia32_ldmxcsr: {
2216    llvm::Type *PtrTy = Int8PtrTy;
2217    Value *One = llvm::ConstantInt::get(Int32Ty, 1);
2218    Value *Tmp = Builder.CreateAlloca(Int32Ty, One);
2219    Builder.CreateStore(Ops[0], Tmp);
2220    return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::x86_sse_ldmxcsr),
2221                              Builder.CreateBitCast(Tmp, PtrTy));
2222  }
2223  case X86::BI__builtin_ia32_stmxcsr: {
2224    llvm::Type *PtrTy = Int8PtrTy;
2225    Value *One = llvm::ConstantInt::get(Int32Ty, 1);
2226    Value *Tmp = Builder.CreateAlloca(Int32Ty, One);
2227    Builder.CreateCall(CGM.getIntrinsic(Intrinsic::x86_sse_stmxcsr),
2228                       Builder.CreateBitCast(Tmp, PtrTy));
2229    return Builder.CreateLoad(Tmp, "stmxcsr");
2230  }
2231  case X86::BI__builtin_ia32_cmppd: {
2232    llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse2_cmp_pd);
2233    return Builder.CreateCall(F, Ops, "cmppd");
2234  }
2235  case X86::BI__builtin_ia32_cmpsd: {
2236    llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse2_cmp_sd);
2237    return Builder.CreateCall(F, Ops, "cmpsd");
2238  }
2239  case X86::BI__builtin_ia32_storehps:
2240  case X86::BI__builtin_ia32_storelps: {
2241    llvm::Type *PtrTy = llvm::PointerType::getUnqual(Int64Ty);
2242    llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 2);
2243
2244    // cast val v2i64
2245    Ops[1] = Builder.CreateBitCast(Ops[1], VecTy, "cast");
2246
2247    // extract (0, 1)
2248    unsigned Index = BuiltinID == X86::BI__builtin_ia32_storelps ? 0 : 1;
2249    llvm::Value *Idx = llvm::ConstantInt::get(Int32Ty, Index);
2250    Ops[1] = Builder.CreateExtractElement(Ops[1], Idx, "extract");
2251
2252    // cast pointer to i64 & store
2253    Ops[0] = Builder.CreateBitCast(Ops[0], PtrTy);
2254    return Builder.CreateStore(Ops[1], Ops[0]);
2255  }
2256  case X86::BI__builtin_ia32_palignr: {
2257    unsigned shiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue();
2258
2259    // If palignr is shifting the pair of input vectors less than 9 bytes,
2260    // emit a shuffle instruction.
2261    if (shiftVal <= 8) {
2262      SmallVector<llvm::Constant*, 8> Indices;
2263      for (unsigned i = 0; i != 8; ++i)
2264        Indices.push_back(llvm::ConstantInt::get(Int32Ty, shiftVal + i));
2265
2266      Value* SV = llvm::ConstantVector::get(Indices);
2267      return Builder.CreateShuffleVector(Ops[1], Ops[0], SV, "palignr");
2268    }
2269
2270    // If palignr is shifting the pair of input vectors more than 8 but less
2271    // than 16 bytes, emit a logical right shift of the destination.
2272    if (shiftVal < 16) {
2273      // MMX has these as 1 x i64 vectors for some odd optimization reasons.
2274      llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 1);
2275
2276      Ops[0] = Builder.CreateBitCast(Ops[0], VecTy, "cast");
2277      Ops[1] = llvm::ConstantInt::get(VecTy, (shiftVal-8) * 8);
2278
2279      // create i32 constant
2280      llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_mmx_psrl_q);
2281      return Builder.CreateCall(F, makeArrayRef(&Ops[0], 2), "palignr");
2282    }
2283
2284    // If palignr is shifting the pair of vectors more than 16 bytes, emit zero.
2285    return llvm::Constant::getNullValue(ConvertType(E->getType()));
2286  }
2287  case X86::BI__builtin_ia32_palignr128: {
2288    unsigned shiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue();
2289
2290    // If palignr is shifting the pair of input vectors less than 17 bytes,
2291    // emit a shuffle instruction.
2292    if (shiftVal <= 16) {
2293      SmallVector<llvm::Constant*, 16> Indices;
2294      for (unsigned i = 0; i != 16; ++i)
2295        Indices.push_back(llvm::ConstantInt::get(Int32Ty, shiftVal + i));
2296
2297      Value* SV = llvm::ConstantVector::get(Indices);
2298      return Builder.CreateShuffleVector(Ops[1], Ops[0], SV, "palignr");
2299    }
2300
2301    // If palignr is shifting the pair of input vectors more than 16 but less
2302    // than 32 bytes, emit a logical right shift of the destination.
2303    if (shiftVal < 32) {
2304      llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 2);
2305
2306      Ops[0] = Builder.CreateBitCast(Ops[0], VecTy, "cast");
2307      Ops[1] = llvm::ConstantInt::get(Int32Ty, (shiftVal-16) * 8);
2308
2309      // create i32 constant
2310      llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse2_psrl_dq);
2311      return Builder.CreateCall(F, makeArrayRef(&Ops[0], 2), "palignr");
2312    }
2313
2314    // If palignr is shifting the pair of vectors more than 32 bytes, emit zero.
2315    return llvm::Constant::getNullValue(ConvertType(E->getType()));
2316  }
2317  case X86::BI__builtin_ia32_palignr256: {
2318    unsigned shiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue();
2319
2320    // If palignr is shifting the pair of input vectors less than 17 bytes,
2321    // emit a shuffle instruction.
2322    if (shiftVal <= 16) {
2323      SmallVector<llvm::Constant*, 32> Indices;
2324      // 256-bit palignr operates on 128-bit lanes so we need to handle that
2325      for (unsigned l = 0; l != 2; ++l) {
2326        unsigned LaneStart = l * 16;
2327        unsigned LaneEnd = (l+1) * 16;
2328        for (unsigned i = 0; i != 16; ++i) {
2329          unsigned Idx = shiftVal + i + LaneStart;
2330          if (Idx >= LaneEnd) Idx += 16; // end of lane, switch operand
2331          Indices.push_back(llvm::ConstantInt::get(Int32Ty, Idx));
2332        }
2333      }
2334
2335      Value* SV = llvm::ConstantVector::get(Indices);
2336      return Builder.CreateShuffleVector(Ops[1], Ops[0], SV, "palignr");
2337    }
2338
2339    // If palignr is shifting the pair of input vectors more than 16 but less
2340    // than 32 bytes, emit a logical right shift of the destination.
2341    if (shiftVal < 32) {
2342      llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 4);
2343
2344      Ops[0] = Builder.CreateBitCast(Ops[0], VecTy, "cast");
2345      Ops[1] = llvm::ConstantInt::get(Int32Ty, (shiftVal-16) * 8);
2346
2347      // create i32 constant
2348      llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_avx2_psrl_dq);
2349      return Builder.CreateCall(F, makeArrayRef(&Ops[0], 2), "palignr");
2350    }
2351
2352    // If palignr is shifting the pair of vectors more than 32 bytes, emit zero.
2353    return llvm::Constant::getNullValue(ConvertType(E->getType()));
2354  }
2355  case X86::BI__builtin_ia32_movntps:
2356  case X86::BI__builtin_ia32_movntpd:
2357  case X86::BI__builtin_ia32_movntdq:
2358  case X86::BI__builtin_ia32_movnti: {
2359    llvm::MDNode *Node = llvm::MDNode::get(getLLVMContext(),
2360                                           Builder.getInt32(1));
2361
2362    // Convert the type of the pointer to a pointer to the stored type.
2363    Value *BC = Builder.CreateBitCast(Ops[0],
2364                                llvm::PointerType::getUnqual(Ops[1]->getType()),
2365                                      "cast");
2366    StoreInst *SI = Builder.CreateStore(Ops[1], BC);
2367    SI->setMetadata(CGM.getModule().getMDKindID("nontemporal"), Node);
2368    SI->setAlignment(16);
2369    return SI;
2370  }
2371  // 3DNow!
2372  case X86::BI__builtin_ia32_pavgusb:
2373  case X86::BI__builtin_ia32_pf2id:
2374  case X86::BI__builtin_ia32_pfacc:
2375  case X86::BI__builtin_ia32_pfadd:
2376  case X86::BI__builtin_ia32_pfcmpeq:
2377  case X86::BI__builtin_ia32_pfcmpge:
2378  case X86::BI__builtin_ia32_pfcmpgt:
2379  case X86::BI__builtin_ia32_pfmax:
2380  case X86::BI__builtin_ia32_pfmin:
2381  case X86::BI__builtin_ia32_pfmul:
2382  case X86::BI__builtin_ia32_pfrcp:
2383  case X86::BI__builtin_ia32_pfrcpit1:
2384  case X86::BI__builtin_ia32_pfrcpit2:
2385  case X86::BI__builtin_ia32_pfrsqrt:
2386  case X86::BI__builtin_ia32_pfrsqit1:
2387  case X86::BI__builtin_ia32_pfrsqrtit1:
2388  case X86::BI__builtin_ia32_pfsub:
2389  case X86::BI__builtin_ia32_pfsubr:
2390  case X86::BI__builtin_ia32_pi2fd:
2391  case X86::BI__builtin_ia32_pmulhrw:
2392  case X86::BI__builtin_ia32_pf2iw:
2393  case X86::BI__builtin_ia32_pfnacc:
2394  case X86::BI__builtin_ia32_pfpnacc:
2395  case X86::BI__builtin_ia32_pi2fw:
2396  case X86::BI__builtin_ia32_pswapdsf:
2397  case X86::BI__builtin_ia32_pswapdsi: {
2398    const char *name = 0;
2399    Intrinsic::ID ID = Intrinsic::not_intrinsic;
2400    switch(BuiltinID) {
2401    case X86::BI__builtin_ia32_pavgusb:
2402      name = "pavgusb";
2403      ID = Intrinsic::x86_3dnow_pavgusb;
2404      break;
2405    case X86::BI__builtin_ia32_pf2id:
2406      name = "pf2id";
2407      ID = Intrinsic::x86_3dnow_pf2id;
2408      break;
2409    case X86::BI__builtin_ia32_pfacc:
2410      name = "pfacc";
2411      ID = Intrinsic::x86_3dnow_pfacc;
2412      break;
2413    case X86::BI__builtin_ia32_pfadd:
2414      name = "pfadd";
2415      ID = Intrinsic::x86_3dnow_pfadd;
2416      break;
2417    case X86::BI__builtin_ia32_pfcmpeq:
2418      name = "pfcmpeq";
2419      ID = Intrinsic::x86_3dnow_pfcmpeq;
2420      break;
2421    case X86::BI__builtin_ia32_pfcmpge:
2422      name = "pfcmpge";
2423      ID = Intrinsic::x86_3dnow_pfcmpge;
2424      break;
2425    case X86::BI__builtin_ia32_pfcmpgt:
2426      name = "pfcmpgt";
2427      ID = Intrinsic::x86_3dnow_pfcmpgt;
2428      break;
2429    case X86::BI__builtin_ia32_pfmax:
2430      name = "pfmax";
2431      ID = Intrinsic::x86_3dnow_pfmax;
2432      break;
2433    case X86::BI__builtin_ia32_pfmin:
2434      name = "pfmin";
2435      ID = Intrinsic::x86_3dnow_pfmin;
2436      break;
2437    case X86::BI__builtin_ia32_pfmul:
2438      name = "pfmul";
2439      ID = Intrinsic::x86_3dnow_pfmul;
2440      break;
2441    case X86::BI__builtin_ia32_pfrcp:
2442      name = "pfrcp";
2443      ID = Intrinsic::x86_3dnow_pfrcp;
2444      break;
2445    case X86::BI__builtin_ia32_pfrcpit1:
2446      name = "pfrcpit1";
2447      ID = Intrinsic::x86_3dnow_pfrcpit1;
2448      break;
2449    case X86::BI__builtin_ia32_pfrcpit2:
2450      name = "pfrcpit2";
2451      ID = Intrinsic::x86_3dnow_pfrcpit2;
2452      break;
2453    case X86::BI__builtin_ia32_pfrsqrt:
2454      name = "pfrsqrt";
2455      ID = Intrinsic::x86_3dnow_pfrsqrt;
2456      break;
2457    case X86::BI__builtin_ia32_pfrsqit1:
2458    case X86::BI__builtin_ia32_pfrsqrtit1:
2459      name = "pfrsqit1";
2460      ID = Intrinsic::x86_3dnow_pfrsqit1;
2461      break;
2462    case X86::BI__builtin_ia32_pfsub:
2463      name = "pfsub";
2464      ID = Intrinsic::x86_3dnow_pfsub;
2465      break;
2466    case X86::BI__builtin_ia32_pfsubr:
2467      name = "pfsubr";
2468      ID = Intrinsic::x86_3dnow_pfsubr;
2469      break;
2470    case X86::BI__builtin_ia32_pi2fd:
2471      name = "pi2fd";
2472      ID = Intrinsic::x86_3dnow_pi2fd;
2473      break;
2474    case X86::BI__builtin_ia32_pmulhrw:
2475      name = "pmulhrw";
2476      ID = Intrinsic::x86_3dnow_pmulhrw;
2477      break;
2478    case X86::BI__builtin_ia32_pf2iw:
2479      name = "pf2iw";
2480      ID = Intrinsic::x86_3dnowa_pf2iw;
2481      break;
2482    case X86::BI__builtin_ia32_pfnacc:
2483      name = "pfnacc";
2484      ID = Intrinsic::x86_3dnowa_pfnacc;
2485      break;
2486    case X86::BI__builtin_ia32_pfpnacc:
2487      name = "pfpnacc";
2488      ID = Intrinsic::x86_3dnowa_pfpnacc;
2489      break;
2490    case X86::BI__builtin_ia32_pi2fw:
2491      name = "pi2fw";
2492      ID = Intrinsic::x86_3dnowa_pi2fw;
2493      break;
2494    case X86::BI__builtin_ia32_pswapdsf:
2495    case X86::BI__builtin_ia32_pswapdsi:
2496      name = "pswapd";
2497      ID = Intrinsic::x86_3dnowa_pswapd;
2498      break;
2499    }
2500    llvm::Function *F = CGM.getIntrinsic(ID);
2501    return Builder.CreateCall(F, Ops, name);
2502  }
2503  }
2504}
2505
2506
2507Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
2508                                             const CallExpr *E) {
2509  llvm::SmallVector<Value*, 4> Ops;
2510
2511  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
2512    Ops.push_back(EmitScalarExpr(E->getArg(i)));
2513
2514  Intrinsic::ID ID = Intrinsic::not_intrinsic;
2515
2516  switch (BuiltinID) {
2517  default: return 0;
2518
2519  case Hexagon::BI__builtin_HEXAGON_C2_cmpeq:
2520    ID = Intrinsic::hexagon_C2_cmpeq; break;
2521
2522  case Hexagon::BI__builtin_HEXAGON_C2_cmpgt:
2523    ID = Intrinsic::hexagon_C2_cmpgt; break;
2524
2525  case Hexagon::BI__builtin_HEXAGON_C2_cmpgtu:
2526    ID = Intrinsic::hexagon_C2_cmpgtu; break;
2527
2528  case Hexagon::BI__builtin_HEXAGON_C2_cmpeqp:
2529    ID = Intrinsic::hexagon_C2_cmpeqp; break;
2530
2531  case Hexagon::BI__builtin_HEXAGON_C2_cmpgtp:
2532    ID = Intrinsic::hexagon_C2_cmpgtp; break;
2533
2534  case Hexagon::BI__builtin_HEXAGON_C2_cmpgtup:
2535    ID = Intrinsic::hexagon_C2_cmpgtup; break;
2536
2537  case Hexagon::BI__builtin_HEXAGON_C2_bitsset:
2538    ID = Intrinsic::hexagon_C2_bitsset; break;
2539
2540  case Hexagon::BI__builtin_HEXAGON_C2_bitsclr:
2541    ID = Intrinsic::hexagon_C2_bitsclr; break;
2542
2543  case Hexagon::BI__builtin_HEXAGON_C2_cmpeqi:
2544    ID = Intrinsic::hexagon_C2_cmpeqi; break;
2545
2546  case Hexagon::BI__builtin_HEXAGON_C2_cmpgti:
2547    ID = Intrinsic::hexagon_C2_cmpgti; break;
2548
2549  case Hexagon::BI__builtin_HEXAGON_C2_cmpgtui:
2550    ID = Intrinsic::hexagon_C2_cmpgtui; break;
2551
2552  case Hexagon::BI__builtin_HEXAGON_C2_cmpgei:
2553    ID = Intrinsic::hexagon_C2_cmpgei; break;
2554
2555  case Hexagon::BI__builtin_HEXAGON_C2_cmpgeui:
2556    ID = Intrinsic::hexagon_C2_cmpgeui; break;
2557
2558  case Hexagon::BI__builtin_HEXAGON_C2_cmplt:
2559    ID = Intrinsic::hexagon_C2_cmplt; break;
2560
2561  case Hexagon::BI__builtin_HEXAGON_C2_cmpltu:
2562    ID = Intrinsic::hexagon_C2_cmpltu; break;
2563
2564  case Hexagon::BI__builtin_HEXAGON_C2_bitsclri:
2565    ID = Intrinsic::hexagon_C2_bitsclri; break;
2566
2567  case Hexagon::BI__builtin_HEXAGON_C2_and:
2568    ID = Intrinsic::hexagon_C2_and; break;
2569
2570  case Hexagon::BI__builtin_HEXAGON_C2_or:
2571    ID = Intrinsic::hexagon_C2_or; break;
2572
2573  case Hexagon::BI__builtin_HEXAGON_C2_xor:
2574    ID = Intrinsic::hexagon_C2_xor; break;
2575
2576  case Hexagon::BI__builtin_HEXAGON_C2_andn:
2577    ID = Intrinsic::hexagon_C2_andn; break;
2578
2579  case Hexagon::BI__builtin_HEXAGON_C2_not:
2580    ID = Intrinsic::hexagon_C2_not; break;
2581
2582  case Hexagon::BI__builtin_HEXAGON_C2_orn:
2583    ID = Intrinsic::hexagon_C2_orn; break;
2584
2585  case Hexagon::BI__builtin_HEXAGON_C2_pxfer_map:
2586    ID = Intrinsic::hexagon_C2_pxfer_map; break;
2587
2588  case Hexagon::BI__builtin_HEXAGON_C2_any8:
2589    ID = Intrinsic::hexagon_C2_any8; break;
2590
2591  case Hexagon::BI__builtin_HEXAGON_C2_all8:
2592    ID = Intrinsic::hexagon_C2_all8; break;
2593
2594  case Hexagon::BI__builtin_HEXAGON_C2_vitpack:
2595    ID = Intrinsic::hexagon_C2_vitpack; break;
2596
2597  case Hexagon::BI__builtin_HEXAGON_C2_mux:
2598    ID = Intrinsic::hexagon_C2_mux; break;
2599
2600  case Hexagon::BI__builtin_HEXAGON_C2_muxii:
2601    ID = Intrinsic::hexagon_C2_muxii; break;
2602
2603  case Hexagon::BI__builtin_HEXAGON_C2_muxir:
2604    ID = Intrinsic::hexagon_C2_muxir; break;
2605
2606  case Hexagon::BI__builtin_HEXAGON_C2_muxri:
2607    ID = Intrinsic::hexagon_C2_muxri; break;
2608
2609  case Hexagon::BI__builtin_HEXAGON_C2_vmux:
2610    ID = Intrinsic::hexagon_C2_vmux; break;
2611
2612  case Hexagon::BI__builtin_HEXAGON_C2_mask:
2613    ID = Intrinsic::hexagon_C2_mask; break;
2614
2615  case Hexagon::BI__builtin_HEXAGON_A2_vcmpbeq:
2616    ID = Intrinsic::hexagon_A2_vcmpbeq; break;
2617
2618  case Hexagon::BI__builtin_HEXAGON_A2_vcmpbgtu:
2619    ID = Intrinsic::hexagon_A2_vcmpbgtu; break;
2620
2621  case Hexagon::BI__builtin_HEXAGON_A2_vcmpheq:
2622    ID = Intrinsic::hexagon_A2_vcmpheq; break;
2623
2624  case Hexagon::BI__builtin_HEXAGON_A2_vcmphgt:
2625    ID = Intrinsic::hexagon_A2_vcmphgt; break;
2626
2627  case Hexagon::BI__builtin_HEXAGON_A2_vcmphgtu:
2628    ID = Intrinsic::hexagon_A2_vcmphgtu; break;
2629
2630  case Hexagon::BI__builtin_HEXAGON_A2_vcmpweq:
2631    ID = Intrinsic::hexagon_A2_vcmpweq; break;
2632
2633  case Hexagon::BI__builtin_HEXAGON_A2_vcmpwgt:
2634    ID = Intrinsic::hexagon_A2_vcmpwgt; break;
2635
2636  case Hexagon::BI__builtin_HEXAGON_A2_vcmpwgtu:
2637    ID = Intrinsic::hexagon_A2_vcmpwgtu; break;
2638
2639  case Hexagon::BI__builtin_HEXAGON_C2_tfrpr:
2640    ID = Intrinsic::hexagon_C2_tfrpr; break;
2641
2642  case Hexagon::BI__builtin_HEXAGON_C2_tfrrp:
2643    ID = Intrinsic::hexagon_C2_tfrrp; break;
2644
2645  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hh_s0:
2646    ID = Intrinsic::hexagon_M2_mpy_acc_hh_s0; break;
2647
2648  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hh_s1:
2649    ID = Intrinsic::hexagon_M2_mpy_acc_hh_s1; break;
2650
2651  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hl_s0:
2652    ID = Intrinsic::hexagon_M2_mpy_acc_hl_s0; break;
2653
2654  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hl_s1:
2655    ID = Intrinsic::hexagon_M2_mpy_acc_hl_s1; break;
2656
2657  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_lh_s0:
2658    ID = Intrinsic::hexagon_M2_mpy_acc_lh_s0; break;
2659
2660  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_lh_s1:
2661    ID = Intrinsic::hexagon_M2_mpy_acc_lh_s1; break;
2662
2663  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_ll_s0:
2664    ID = Intrinsic::hexagon_M2_mpy_acc_ll_s0; break;
2665
2666  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_ll_s1:
2667    ID = Intrinsic::hexagon_M2_mpy_acc_ll_s1; break;
2668
2669  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hh_s0:
2670    ID = Intrinsic::hexagon_M2_mpy_nac_hh_s0; break;
2671
2672  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hh_s1:
2673    ID = Intrinsic::hexagon_M2_mpy_nac_hh_s1; break;
2674
2675  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hl_s0:
2676    ID = Intrinsic::hexagon_M2_mpy_nac_hl_s0; break;
2677
2678  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hl_s1:
2679    ID = Intrinsic::hexagon_M2_mpy_nac_hl_s1; break;
2680
2681  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_lh_s0:
2682    ID = Intrinsic::hexagon_M2_mpy_nac_lh_s0; break;
2683
2684  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_lh_s1:
2685    ID = Intrinsic::hexagon_M2_mpy_nac_lh_s1; break;
2686
2687  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_ll_s0:
2688    ID = Intrinsic::hexagon_M2_mpy_nac_ll_s0; break;
2689
2690  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_ll_s1:
2691    ID = Intrinsic::hexagon_M2_mpy_nac_ll_s1; break;
2692
2693  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hh_s0:
2694    ID = Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; break;
2695
2696  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hh_s1:
2697    ID = Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; break;
2698
2699  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hl_s0:
2700    ID = Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; break;
2701
2702  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hl_s1:
2703    ID = Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; break;
2704
2705  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_lh_s0:
2706    ID = Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; break;
2707
2708  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_lh_s1:
2709    ID = Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; break;
2710
2711  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_ll_s0:
2712    ID = Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; break;
2713
2714  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_ll_s1:
2715    ID = Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; break;
2716
2717  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hh_s0:
2718    ID = Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; break;
2719
2720  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1:
2721    ID = Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; break;
2722
2723  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0:
2724    ID = Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; break;
2725
2726  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1:
2727    ID = Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; break;
2728
2729  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0:
2730    ID = Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; break;
2731
2732  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1:
2733    ID = Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; break;
2734
2735  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0:
2736    ID = Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; break;
2737
2738  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1:
2739    ID = Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; break;
2740
2741  case Hexagon::BI__builtin_HEXAGON_M2_mpy_hh_s0:
2742    ID = Intrinsic::hexagon_M2_mpy_hh_s0; break;
2743
2744  case Hexagon::BI__builtin_HEXAGON_M2_mpy_hh_s1:
2745    ID = Intrinsic::hexagon_M2_mpy_hh_s1; break;
2746
2747  case Hexagon::BI__builtin_HEXAGON_M2_mpy_hl_s0:
2748    ID = Intrinsic::hexagon_M2_mpy_hl_s0; break;
2749
2750  case Hexagon::BI__builtin_HEXAGON_M2_mpy_hl_s1:
2751    ID = Intrinsic::hexagon_M2_mpy_hl_s1; break;
2752
2753  case Hexagon::BI__builtin_HEXAGON_M2_mpy_lh_s0:
2754    ID = Intrinsic::hexagon_M2_mpy_lh_s0; break;
2755
2756  case Hexagon::BI__builtin_HEXAGON_M2_mpy_lh_s1:
2757    ID = Intrinsic::hexagon_M2_mpy_lh_s1; break;
2758
2759  case Hexagon::BI__builtin_HEXAGON_M2_mpy_ll_s0:
2760    ID = Intrinsic::hexagon_M2_mpy_ll_s0; break;
2761
2762  case Hexagon::BI__builtin_HEXAGON_M2_mpy_ll_s1:
2763    ID = Intrinsic::hexagon_M2_mpy_ll_s1; break;
2764
2765  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hh_s0:
2766    ID = Intrinsic::hexagon_M2_mpy_sat_hh_s0; break;
2767
2768  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hh_s1:
2769    ID = Intrinsic::hexagon_M2_mpy_sat_hh_s1; break;
2770
2771  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hl_s0:
2772    ID = Intrinsic::hexagon_M2_mpy_sat_hl_s0; break;
2773
2774  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hl_s1:
2775    ID = Intrinsic::hexagon_M2_mpy_sat_hl_s1; break;
2776
2777  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_lh_s0:
2778    ID = Intrinsic::hexagon_M2_mpy_sat_lh_s0; break;
2779
2780  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_lh_s1:
2781    ID = Intrinsic::hexagon_M2_mpy_sat_lh_s1; break;
2782
2783  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_ll_s0:
2784    ID = Intrinsic::hexagon_M2_mpy_sat_ll_s0; break;
2785
2786  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_ll_s1:
2787    ID = Intrinsic::hexagon_M2_mpy_sat_ll_s1; break;
2788
2789  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hh_s0:
2790    ID = Intrinsic::hexagon_M2_mpy_rnd_hh_s0; break;
2791
2792  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hh_s1:
2793    ID = Intrinsic::hexagon_M2_mpy_rnd_hh_s1; break;
2794
2795  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hl_s0:
2796    ID = Intrinsic::hexagon_M2_mpy_rnd_hl_s0; break;
2797
2798  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hl_s1:
2799    ID = Intrinsic::hexagon_M2_mpy_rnd_hl_s1; break;
2800
2801  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_lh_s0:
2802    ID = Intrinsic::hexagon_M2_mpy_rnd_lh_s0; break;
2803
2804  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_lh_s1:
2805    ID = Intrinsic::hexagon_M2_mpy_rnd_lh_s1; break;
2806
2807  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_ll_s0:
2808    ID = Intrinsic::hexagon_M2_mpy_rnd_ll_s0; break;
2809
2810  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_ll_s1:
2811    ID = Intrinsic::hexagon_M2_mpy_rnd_ll_s1; break;
2812
2813  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0:
2814    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; break;
2815
2816  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1:
2817    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; break;
2818
2819  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0:
2820    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; break;
2821
2822  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1:
2823    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; break;
2824
2825  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0:
2826    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; break;
2827
2828  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1:
2829    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; break;
2830
2831  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0:
2832    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; break;
2833
2834  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1:
2835    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; break;
2836
2837  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hh_s0:
2838    ID = Intrinsic::hexagon_M2_mpyd_acc_hh_s0; break;
2839
2840  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hh_s1:
2841    ID = Intrinsic::hexagon_M2_mpyd_acc_hh_s1; break;
2842
2843  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hl_s0:
2844    ID = Intrinsic::hexagon_M2_mpyd_acc_hl_s0; break;
2845
2846  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hl_s1:
2847    ID = Intrinsic::hexagon_M2_mpyd_acc_hl_s1; break;
2848
2849  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_lh_s0:
2850    ID = Intrinsic::hexagon_M2_mpyd_acc_lh_s0; break;
2851
2852  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_lh_s1:
2853    ID = Intrinsic::hexagon_M2_mpyd_acc_lh_s1; break;
2854
2855  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_ll_s0:
2856    ID = Intrinsic::hexagon_M2_mpyd_acc_ll_s0; break;
2857
2858  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_ll_s1:
2859    ID = Intrinsic::hexagon_M2_mpyd_acc_ll_s1; break;
2860
2861  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hh_s0:
2862    ID = Intrinsic::hexagon_M2_mpyd_nac_hh_s0; break;
2863
2864  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hh_s1:
2865    ID = Intrinsic::hexagon_M2_mpyd_nac_hh_s1; break;
2866
2867  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hl_s0:
2868    ID = Intrinsic::hexagon_M2_mpyd_nac_hl_s0; break;
2869
2870  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hl_s1:
2871    ID = Intrinsic::hexagon_M2_mpyd_nac_hl_s1; break;
2872
2873  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_lh_s0:
2874    ID = Intrinsic::hexagon_M2_mpyd_nac_lh_s0; break;
2875
2876  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_lh_s1:
2877    ID = Intrinsic::hexagon_M2_mpyd_nac_lh_s1; break;
2878
2879  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_ll_s0:
2880    ID = Intrinsic::hexagon_M2_mpyd_nac_ll_s0; break;
2881
2882  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_ll_s1:
2883    ID = Intrinsic::hexagon_M2_mpyd_nac_ll_s1; break;
2884
2885  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hh_s0:
2886    ID = Intrinsic::hexagon_M2_mpyd_hh_s0; break;
2887
2888  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hh_s1:
2889    ID = Intrinsic::hexagon_M2_mpyd_hh_s1; break;
2890
2891  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hl_s0:
2892    ID = Intrinsic::hexagon_M2_mpyd_hl_s0; break;
2893
2894  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hl_s1:
2895    ID = Intrinsic::hexagon_M2_mpyd_hl_s1; break;
2896
2897  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_lh_s0:
2898    ID = Intrinsic::hexagon_M2_mpyd_lh_s0; break;
2899
2900  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_lh_s1:
2901    ID = Intrinsic::hexagon_M2_mpyd_lh_s1; break;
2902
2903  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_ll_s0:
2904    ID = Intrinsic::hexagon_M2_mpyd_ll_s0; break;
2905
2906  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_ll_s1:
2907    ID = Intrinsic::hexagon_M2_mpyd_ll_s1; break;
2908
2909  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hh_s0:
2910    ID = Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; break;
2911
2912  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hh_s1:
2913    ID = Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; break;
2914
2915  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hl_s0:
2916    ID = Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; break;
2917
2918  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hl_s1:
2919    ID = Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; break;
2920
2921  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_lh_s0:
2922    ID = Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; break;
2923
2924  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_lh_s1:
2925    ID = Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; break;
2926
2927  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_ll_s0:
2928    ID = Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; break;
2929
2930  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_ll_s1:
2931    ID = Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; break;
2932
2933  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hh_s0:
2934    ID = Intrinsic::hexagon_M2_mpyu_acc_hh_s0; break;
2935
2936  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hh_s1:
2937    ID = Intrinsic::hexagon_M2_mpyu_acc_hh_s1; break;
2938
2939  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hl_s0:
2940    ID = Intrinsic::hexagon_M2_mpyu_acc_hl_s0; break;
2941
2942  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hl_s1:
2943    ID = Intrinsic::hexagon_M2_mpyu_acc_hl_s1; break;
2944
2945  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_lh_s0:
2946    ID = Intrinsic::hexagon_M2_mpyu_acc_lh_s0; break;
2947
2948  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_lh_s1:
2949    ID = Intrinsic::hexagon_M2_mpyu_acc_lh_s1; break;
2950
2951  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_ll_s0:
2952    ID = Intrinsic::hexagon_M2_mpyu_acc_ll_s0; break;
2953
2954  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_ll_s1:
2955    ID = Intrinsic::hexagon_M2_mpyu_acc_ll_s1; break;
2956
2957  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hh_s0:
2958    ID = Intrinsic::hexagon_M2_mpyu_nac_hh_s0; break;
2959
2960  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hh_s1:
2961    ID = Intrinsic::hexagon_M2_mpyu_nac_hh_s1; break;
2962
2963  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hl_s0:
2964    ID = Intrinsic::hexagon_M2_mpyu_nac_hl_s0; break;
2965
2966  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hl_s1:
2967    ID = Intrinsic::hexagon_M2_mpyu_nac_hl_s1; break;
2968
2969  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_lh_s0:
2970    ID = Intrinsic::hexagon_M2_mpyu_nac_lh_s0; break;
2971
2972  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_lh_s1:
2973    ID = Intrinsic::hexagon_M2_mpyu_nac_lh_s1; break;
2974
2975  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_ll_s0:
2976    ID = Intrinsic::hexagon_M2_mpyu_nac_ll_s0; break;
2977
2978  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_ll_s1:
2979    ID = Intrinsic::hexagon_M2_mpyu_nac_ll_s1; break;
2980
2981  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hh_s0:
2982    ID = Intrinsic::hexagon_M2_mpyu_hh_s0; break;
2983
2984  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hh_s1:
2985    ID = Intrinsic::hexagon_M2_mpyu_hh_s1; break;
2986
2987  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hl_s0:
2988    ID = Intrinsic::hexagon_M2_mpyu_hl_s0; break;
2989
2990  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hl_s1:
2991    ID = Intrinsic::hexagon_M2_mpyu_hl_s1; break;
2992
2993  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_lh_s0:
2994    ID = Intrinsic::hexagon_M2_mpyu_lh_s0; break;
2995
2996  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_lh_s1:
2997    ID = Intrinsic::hexagon_M2_mpyu_lh_s1; break;
2998
2999  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_ll_s0:
3000    ID = Intrinsic::hexagon_M2_mpyu_ll_s0; break;
3001
3002  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_ll_s1:
3003    ID = Intrinsic::hexagon_M2_mpyu_ll_s1; break;
3004
3005  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hh_s0:
3006    ID = Intrinsic::hexagon_M2_mpyud_acc_hh_s0; break;
3007
3008  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hh_s1:
3009    ID = Intrinsic::hexagon_M2_mpyud_acc_hh_s1; break;
3010
3011  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hl_s0:
3012    ID = Intrinsic::hexagon_M2_mpyud_acc_hl_s0; break;
3013
3014  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hl_s1:
3015    ID = Intrinsic::hexagon_M2_mpyud_acc_hl_s1; break;
3016
3017  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_lh_s0:
3018    ID = Intrinsic::hexagon_M2_mpyud_acc_lh_s0; break;
3019
3020  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_lh_s1:
3021    ID = Intrinsic::hexagon_M2_mpyud_acc_lh_s1; break;
3022
3023  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_ll_s0:
3024    ID = Intrinsic::hexagon_M2_mpyud_acc_ll_s0; break;
3025
3026  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_ll_s1:
3027    ID = Intrinsic::hexagon_M2_mpyud_acc_ll_s1; break;
3028
3029  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hh_s0:
3030    ID = Intrinsic::hexagon_M2_mpyud_nac_hh_s0; break;
3031
3032  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hh_s1:
3033    ID = Intrinsic::hexagon_M2_mpyud_nac_hh_s1; break;
3034
3035  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hl_s0:
3036    ID = Intrinsic::hexagon_M2_mpyud_nac_hl_s0; break;
3037
3038  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hl_s1:
3039    ID = Intrinsic::hexagon_M2_mpyud_nac_hl_s1; break;
3040
3041  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_lh_s0:
3042    ID = Intrinsic::hexagon_M2_mpyud_nac_lh_s0; break;
3043
3044  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_lh_s1:
3045    ID = Intrinsic::hexagon_M2_mpyud_nac_lh_s1; break;
3046
3047  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_ll_s0:
3048    ID = Intrinsic::hexagon_M2_mpyud_nac_ll_s0; break;
3049
3050  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_ll_s1:
3051    ID = Intrinsic::hexagon_M2_mpyud_nac_ll_s1; break;
3052
3053  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hh_s0:
3054    ID = Intrinsic::hexagon_M2_mpyud_hh_s0; break;
3055
3056  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hh_s1:
3057    ID = Intrinsic::hexagon_M2_mpyud_hh_s1; break;
3058
3059  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hl_s0:
3060    ID = Intrinsic::hexagon_M2_mpyud_hl_s0; break;
3061
3062  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hl_s1:
3063    ID = Intrinsic::hexagon_M2_mpyud_hl_s1; break;
3064
3065  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_lh_s0:
3066    ID = Intrinsic::hexagon_M2_mpyud_lh_s0; break;
3067
3068  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_lh_s1:
3069    ID = Intrinsic::hexagon_M2_mpyud_lh_s1; break;
3070
3071  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_ll_s0:
3072    ID = Intrinsic::hexagon_M2_mpyud_ll_s0; break;
3073
3074  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_ll_s1:
3075    ID = Intrinsic::hexagon_M2_mpyud_ll_s1; break;
3076
3077  case Hexagon::BI__builtin_HEXAGON_M2_mpysmi:
3078    ID = Intrinsic::hexagon_M2_mpysmi; break;
3079
3080  case Hexagon::BI__builtin_HEXAGON_M2_macsip:
3081    ID = Intrinsic::hexagon_M2_macsip; break;
3082
3083  case Hexagon::BI__builtin_HEXAGON_M2_macsin:
3084    ID = Intrinsic::hexagon_M2_macsin; break;
3085
3086  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_s0:
3087    ID = Intrinsic::hexagon_M2_dpmpyss_s0; break;
3088
3089  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_acc_s0:
3090    ID = Intrinsic::hexagon_M2_dpmpyss_acc_s0; break;
3091
3092  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_nac_s0:
3093    ID = Intrinsic::hexagon_M2_dpmpyss_nac_s0; break;
3094
3095  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyuu_s0:
3096    ID = Intrinsic::hexagon_M2_dpmpyuu_s0; break;
3097
3098  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyuu_acc_s0:
3099    ID = Intrinsic::hexagon_M2_dpmpyuu_acc_s0; break;
3100
3101  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyuu_nac_s0:
3102    ID = Intrinsic::hexagon_M2_dpmpyuu_nac_s0; break;
3103
3104  case Hexagon::BI__builtin_HEXAGON_M2_mpy_up:
3105    ID = Intrinsic::hexagon_M2_mpy_up; break;
3106
3107  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_up:
3108    ID = Intrinsic::hexagon_M2_mpyu_up; break;
3109
3110  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_rnd_s0:
3111    ID = Intrinsic::hexagon_M2_dpmpyss_rnd_s0; break;
3112
3113  case Hexagon::BI__builtin_HEXAGON_M2_mpyi:
3114    ID = Intrinsic::hexagon_M2_mpyi; break;
3115
3116  case Hexagon::BI__builtin_HEXAGON_M2_mpyui:
3117    ID = Intrinsic::hexagon_M2_mpyui; break;
3118
3119  case Hexagon::BI__builtin_HEXAGON_M2_maci:
3120    ID = Intrinsic::hexagon_M2_maci; break;
3121
3122  case Hexagon::BI__builtin_HEXAGON_M2_acci:
3123    ID = Intrinsic::hexagon_M2_acci; break;
3124
3125  case Hexagon::BI__builtin_HEXAGON_M2_accii:
3126    ID = Intrinsic::hexagon_M2_accii; break;
3127
3128  case Hexagon::BI__builtin_HEXAGON_M2_nacci:
3129    ID = Intrinsic::hexagon_M2_nacci; break;
3130
3131  case Hexagon::BI__builtin_HEXAGON_M2_naccii:
3132    ID = Intrinsic::hexagon_M2_naccii; break;
3133
3134  case Hexagon::BI__builtin_HEXAGON_M2_subacc:
3135    ID = Intrinsic::hexagon_M2_subacc; break;
3136
3137  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s0:
3138    ID = Intrinsic::hexagon_M2_vmpy2s_s0; break;
3139
3140  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s1:
3141    ID = Intrinsic::hexagon_M2_vmpy2s_s1; break;
3142
3143  case Hexagon::BI__builtin_HEXAGON_M2_vmac2s_s0:
3144    ID = Intrinsic::hexagon_M2_vmac2s_s0; break;
3145
3146  case Hexagon::BI__builtin_HEXAGON_M2_vmac2s_s1:
3147    ID = Intrinsic::hexagon_M2_vmac2s_s1; break;
3148
3149  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s0pack:
3150    ID = Intrinsic::hexagon_M2_vmpy2s_s0pack; break;
3151
3152  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s1pack:
3153    ID = Intrinsic::hexagon_M2_vmpy2s_s1pack; break;
3154
3155  case Hexagon::BI__builtin_HEXAGON_M2_vmac2:
3156    ID = Intrinsic::hexagon_M2_vmac2; break;
3157
3158  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2es_s0:
3159    ID = Intrinsic::hexagon_M2_vmpy2es_s0; break;
3160
3161  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2es_s1:
3162    ID = Intrinsic::hexagon_M2_vmpy2es_s1; break;
3163
3164  case Hexagon::BI__builtin_HEXAGON_M2_vmac2es_s0:
3165    ID = Intrinsic::hexagon_M2_vmac2es_s0; break;
3166
3167  case Hexagon::BI__builtin_HEXAGON_M2_vmac2es_s1:
3168    ID = Intrinsic::hexagon_M2_vmac2es_s1; break;
3169
3170  case Hexagon::BI__builtin_HEXAGON_M2_vmac2es:
3171    ID = Intrinsic::hexagon_M2_vmac2es; break;
3172
3173  case Hexagon::BI__builtin_HEXAGON_M2_vrmac_s0:
3174    ID = Intrinsic::hexagon_M2_vrmac_s0; break;
3175
3176  case Hexagon::BI__builtin_HEXAGON_M2_vrmpy_s0:
3177    ID = Intrinsic::hexagon_M2_vrmpy_s0; break;
3178
3179  case Hexagon::BI__builtin_HEXAGON_M2_vdmpyrs_s0:
3180    ID = Intrinsic::hexagon_M2_vdmpyrs_s0; break;
3181
3182  case Hexagon::BI__builtin_HEXAGON_M2_vdmpyrs_s1:
3183    ID = Intrinsic::hexagon_M2_vdmpyrs_s1; break;
3184
3185  case Hexagon::BI__builtin_HEXAGON_M2_vdmacs_s0:
3186    ID = Intrinsic::hexagon_M2_vdmacs_s0; break;
3187
3188  case Hexagon::BI__builtin_HEXAGON_M2_vdmacs_s1:
3189    ID = Intrinsic::hexagon_M2_vdmacs_s1; break;
3190
3191  case Hexagon::BI__builtin_HEXAGON_M2_vdmpys_s0:
3192    ID = Intrinsic::hexagon_M2_vdmpys_s0; break;
3193
3194  case Hexagon::BI__builtin_HEXAGON_M2_vdmpys_s1:
3195    ID = Intrinsic::hexagon_M2_vdmpys_s1; break;
3196
3197  case Hexagon::BI__builtin_HEXAGON_M2_cmpyrs_s0:
3198    ID = Intrinsic::hexagon_M2_cmpyrs_s0; break;
3199
3200  case Hexagon::BI__builtin_HEXAGON_M2_cmpyrs_s1:
3201    ID = Intrinsic::hexagon_M2_cmpyrs_s1; break;
3202
3203  case Hexagon::BI__builtin_HEXAGON_M2_cmpyrsc_s0:
3204    ID = Intrinsic::hexagon_M2_cmpyrsc_s0; break;
3205
3206  case Hexagon::BI__builtin_HEXAGON_M2_cmpyrsc_s1:
3207    ID = Intrinsic::hexagon_M2_cmpyrsc_s1; break;
3208
3209  case Hexagon::BI__builtin_HEXAGON_M2_cmacs_s0:
3210    ID = Intrinsic::hexagon_M2_cmacs_s0; break;
3211
3212  case Hexagon::BI__builtin_HEXAGON_M2_cmacs_s1:
3213    ID = Intrinsic::hexagon_M2_cmacs_s1; break;
3214
3215  case Hexagon::BI__builtin_HEXAGON_M2_cmacsc_s0:
3216    ID = Intrinsic::hexagon_M2_cmacsc_s0; break;
3217
3218  case Hexagon::BI__builtin_HEXAGON_M2_cmacsc_s1:
3219    ID = Intrinsic::hexagon_M2_cmacsc_s1; break;
3220
3221  case Hexagon::BI__builtin_HEXAGON_M2_cmpys_s0:
3222    ID = Intrinsic::hexagon_M2_cmpys_s0; break;
3223
3224  case Hexagon::BI__builtin_HEXAGON_M2_cmpys_s1:
3225    ID = Intrinsic::hexagon_M2_cmpys_s1; break;
3226
3227  case Hexagon::BI__builtin_HEXAGON_M2_cmpysc_s0:
3228    ID = Intrinsic::hexagon_M2_cmpysc_s0; break;
3229
3230  case Hexagon::BI__builtin_HEXAGON_M2_cmpysc_s1:
3231    ID = Intrinsic::hexagon_M2_cmpysc_s1; break;
3232
3233  case Hexagon::BI__builtin_HEXAGON_M2_cnacs_s0:
3234    ID = Intrinsic::hexagon_M2_cnacs_s0; break;
3235
3236  case Hexagon::BI__builtin_HEXAGON_M2_cnacs_s1:
3237    ID = Intrinsic::hexagon_M2_cnacs_s1; break;
3238
3239  case Hexagon::BI__builtin_HEXAGON_M2_cnacsc_s0:
3240    ID = Intrinsic::hexagon_M2_cnacsc_s0; break;
3241
3242  case Hexagon::BI__builtin_HEXAGON_M2_cnacsc_s1:
3243    ID = Intrinsic::hexagon_M2_cnacsc_s1; break;
3244
3245  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpys_s1:
3246    ID = Intrinsic::hexagon_M2_vrcmpys_s1; break;
3247
3248  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpys_acc_s1:
3249    ID = Intrinsic::hexagon_M2_vrcmpys_acc_s1; break;
3250
3251  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpys_s1rp:
3252    ID = Intrinsic::hexagon_M2_vrcmpys_s1rp; break;
3253
3254  case Hexagon::BI__builtin_HEXAGON_M2_mmacls_s0:
3255    ID = Intrinsic::hexagon_M2_mmacls_s0; break;
3256
3257  case Hexagon::BI__builtin_HEXAGON_M2_mmacls_s1:
3258    ID = Intrinsic::hexagon_M2_mmacls_s1; break;
3259
3260  case Hexagon::BI__builtin_HEXAGON_M2_mmachs_s0:
3261    ID = Intrinsic::hexagon_M2_mmachs_s0; break;
3262
3263  case Hexagon::BI__builtin_HEXAGON_M2_mmachs_s1:
3264    ID = Intrinsic::hexagon_M2_mmachs_s1; break;
3265
3266  case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_s0:
3267    ID = Intrinsic::hexagon_M2_mmpyl_s0; break;
3268
3269  case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_s1:
3270    ID = Intrinsic::hexagon_M2_mmpyl_s1; break;
3271
3272  case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_s0:
3273    ID = Intrinsic::hexagon_M2_mmpyh_s0; break;
3274
3275  case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_s1:
3276    ID = Intrinsic::hexagon_M2_mmpyh_s1; break;
3277
3278  case Hexagon::BI__builtin_HEXAGON_M2_mmacls_rs0:
3279    ID = Intrinsic::hexagon_M2_mmacls_rs0; break;
3280
3281  case Hexagon::BI__builtin_HEXAGON_M2_mmacls_rs1:
3282    ID = Intrinsic::hexagon_M2_mmacls_rs1; break;
3283
3284  case Hexagon::BI__builtin_HEXAGON_M2_mmachs_rs0:
3285    ID = Intrinsic::hexagon_M2_mmachs_rs0; break;
3286
3287  case Hexagon::BI__builtin_HEXAGON_M2_mmachs_rs1:
3288    ID = Intrinsic::hexagon_M2_mmachs_rs1; break;
3289
3290  case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_rs0:
3291    ID = Intrinsic::hexagon_M2_mmpyl_rs0; break;
3292
3293  case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_rs1:
3294    ID = Intrinsic::hexagon_M2_mmpyl_rs1; break;
3295
3296  case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_rs0:
3297    ID = Intrinsic::hexagon_M2_mmpyh_rs0; break;
3298
3299  case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_rs1:
3300    ID = Intrinsic::hexagon_M2_mmpyh_rs1; break;
3301
3302  case Hexagon::BI__builtin_HEXAGON_M2_hmmpyl_rs1:
3303    ID = Intrinsic::hexagon_M2_hmmpyl_rs1; break;
3304
3305  case Hexagon::BI__builtin_HEXAGON_M2_hmmpyh_rs1:
3306    ID = Intrinsic::hexagon_M2_hmmpyh_rs1; break;
3307
3308  case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_s0:
3309    ID = Intrinsic::hexagon_M2_mmaculs_s0; break;
3310
3311  case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_s1:
3312    ID = Intrinsic::hexagon_M2_mmaculs_s1; break;
3313
3314  case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_s0:
3315    ID = Intrinsic::hexagon_M2_mmacuhs_s0; break;
3316
3317  case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_s1:
3318    ID = Intrinsic::hexagon_M2_mmacuhs_s1; break;
3319
3320  case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_s0:
3321    ID = Intrinsic::hexagon_M2_mmpyul_s0; break;
3322
3323  case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_s1:
3324    ID = Intrinsic::hexagon_M2_mmpyul_s1; break;
3325
3326  case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_s0:
3327    ID = Intrinsic::hexagon_M2_mmpyuh_s0; break;
3328
3329  case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_s1:
3330    ID = Intrinsic::hexagon_M2_mmpyuh_s1; break;
3331
3332  case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_rs0:
3333    ID = Intrinsic::hexagon_M2_mmaculs_rs0; break;
3334
3335  case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_rs1:
3336    ID = Intrinsic::hexagon_M2_mmaculs_rs1; break;
3337
3338  case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_rs0:
3339    ID = Intrinsic::hexagon_M2_mmacuhs_rs0; break;
3340
3341  case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_rs1:
3342    ID = Intrinsic::hexagon_M2_mmacuhs_rs1; break;
3343
3344  case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_rs0:
3345    ID = Intrinsic::hexagon_M2_mmpyul_rs0; break;
3346
3347  case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_rs1:
3348    ID = Intrinsic::hexagon_M2_mmpyul_rs1; break;
3349
3350  case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_rs0:
3351    ID = Intrinsic::hexagon_M2_mmpyuh_rs0; break;
3352
3353  case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_rs1:
3354    ID = Intrinsic::hexagon_M2_mmpyuh_rs1; break;
3355
3356  case Hexagon::BI__builtin_HEXAGON_M2_vrcmaci_s0:
3357    ID = Intrinsic::hexagon_M2_vrcmaci_s0; break;
3358
3359  case Hexagon::BI__builtin_HEXAGON_M2_vrcmacr_s0:
3360    ID = Intrinsic::hexagon_M2_vrcmacr_s0; break;
3361
3362  case Hexagon::BI__builtin_HEXAGON_M2_vrcmaci_s0c:
3363    ID = Intrinsic::hexagon_M2_vrcmaci_s0c; break;
3364
3365  case Hexagon::BI__builtin_HEXAGON_M2_vrcmacr_s0c:
3366    ID = Intrinsic::hexagon_M2_vrcmacr_s0c; break;
3367
3368  case Hexagon::BI__builtin_HEXAGON_M2_cmaci_s0:
3369    ID = Intrinsic::hexagon_M2_cmaci_s0; break;
3370
3371  case Hexagon::BI__builtin_HEXAGON_M2_cmacr_s0:
3372    ID = Intrinsic::hexagon_M2_cmacr_s0; break;
3373
3374  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyi_s0:
3375    ID = Intrinsic::hexagon_M2_vrcmpyi_s0; break;
3376
3377  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyr_s0:
3378    ID = Intrinsic::hexagon_M2_vrcmpyr_s0; break;
3379
3380  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyi_s0c:
3381    ID = Intrinsic::hexagon_M2_vrcmpyi_s0c; break;
3382
3383  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyr_s0c:
3384    ID = Intrinsic::hexagon_M2_vrcmpyr_s0c; break;
3385
3386  case Hexagon::BI__builtin_HEXAGON_M2_cmpyi_s0:
3387    ID = Intrinsic::hexagon_M2_cmpyi_s0; break;
3388
3389  case Hexagon::BI__builtin_HEXAGON_M2_cmpyr_s0:
3390    ID = Intrinsic::hexagon_M2_cmpyr_s0; break;
3391
3392  case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s0_sat_i:
3393    ID = Intrinsic::hexagon_M2_vcmpy_s0_sat_i; break;
3394
3395  case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s0_sat_r:
3396    ID = Intrinsic::hexagon_M2_vcmpy_s0_sat_r; break;
3397
3398  case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s1_sat_i:
3399    ID = Intrinsic::hexagon_M2_vcmpy_s1_sat_i; break;
3400
3401  case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s1_sat_r:
3402    ID = Intrinsic::hexagon_M2_vcmpy_s1_sat_r; break;
3403
3404  case Hexagon::BI__builtin_HEXAGON_M2_vcmac_s0_sat_i:
3405    ID = Intrinsic::hexagon_M2_vcmac_s0_sat_i; break;
3406
3407  case Hexagon::BI__builtin_HEXAGON_M2_vcmac_s0_sat_r:
3408    ID = Intrinsic::hexagon_M2_vcmac_s0_sat_r; break;
3409
3410  case Hexagon::BI__builtin_HEXAGON_S2_vcrotate:
3411    ID = Intrinsic::hexagon_S2_vcrotate; break;
3412
3413  case Hexagon::BI__builtin_HEXAGON_A2_add:
3414    ID = Intrinsic::hexagon_A2_add; break;
3415
3416  case Hexagon::BI__builtin_HEXAGON_A2_sub:
3417    ID = Intrinsic::hexagon_A2_sub; break;
3418
3419  case Hexagon::BI__builtin_HEXAGON_A2_addsat:
3420    ID = Intrinsic::hexagon_A2_addsat; break;
3421
3422  case Hexagon::BI__builtin_HEXAGON_A2_subsat:
3423    ID = Intrinsic::hexagon_A2_subsat; break;
3424
3425  case Hexagon::BI__builtin_HEXAGON_A2_addi:
3426    ID = Intrinsic::hexagon_A2_addi; break;
3427
3428  case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_ll:
3429    ID = Intrinsic::hexagon_A2_addh_l16_ll; break;
3430
3431  case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_hl:
3432    ID = Intrinsic::hexagon_A2_addh_l16_hl; break;
3433
3434  case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_sat_ll:
3435    ID = Intrinsic::hexagon_A2_addh_l16_sat_ll; break;
3436
3437  case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_sat_hl:
3438    ID = Intrinsic::hexagon_A2_addh_l16_sat_hl; break;
3439
3440  case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_ll:
3441    ID = Intrinsic::hexagon_A2_subh_l16_ll; break;
3442
3443  case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_hl:
3444    ID = Intrinsic::hexagon_A2_subh_l16_hl; break;
3445
3446  case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_sat_ll:
3447    ID = Intrinsic::hexagon_A2_subh_l16_sat_ll; break;
3448
3449  case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_sat_hl:
3450    ID = Intrinsic::hexagon_A2_subh_l16_sat_hl; break;
3451
3452  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_ll:
3453    ID = Intrinsic::hexagon_A2_addh_h16_ll; break;
3454
3455  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_lh:
3456    ID = Intrinsic::hexagon_A2_addh_h16_lh; break;
3457
3458  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_hl:
3459    ID = Intrinsic::hexagon_A2_addh_h16_hl; break;
3460
3461  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_hh:
3462    ID = Intrinsic::hexagon_A2_addh_h16_hh; break;
3463
3464  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_ll:
3465    ID = Intrinsic::hexagon_A2_addh_h16_sat_ll; break;
3466
3467  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_lh:
3468    ID = Intrinsic::hexagon_A2_addh_h16_sat_lh; break;
3469
3470  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_hl:
3471    ID = Intrinsic::hexagon_A2_addh_h16_sat_hl; break;
3472
3473  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_hh:
3474    ID = Intrinsic::hexagon_A2_addh_h16_sat_hh; break;
3475
3476  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_ll:
3477    ID = Intrinsic::hexagon_A2_subh_h16_ll; break;
3478
3479  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_lh:
3480    ID = Intrinsic::hexagon_A2_subh_h16_lh; break;
3481
3482  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_hl:
3483    ID = Intrinsic::hexagon_A2_subh_h16_hl; break;
3484
3485  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_hh:
3486    ID = Intrinsic::hexagon_A2_subh_h16_hh; break;
3487
3488  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_ll:
3489    ID = Intrinsic::hexagon_A2_subh_h16_sat_ll; break;
3490
3491  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_lh:
3492    ID = Intrinsic::hexagon_A2_subh_h16_sat_lh; break;
3493
3494  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_hl:
3495    ID = Intrinsic::hexagon_A2_subh_h16_sat_hl; break;
3496
3497  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_hh:
3498    ID = Intrinsic::hexagon_A2_subh_h16_sat_hh; break;
3499
3500  case Hexagon::BI__builtin_HEXAGON_A2_aslh:
3501    ID = Intrinsic::hexagon_A2_aslh; break;
3502
3503  case Hexagon::BI__builtin_HEXAGON_A2_asrh:
3504    ID = Intrinsic::hexagon_A2_asrh; break;
3505
3506  case Hexagon::BI__builtin_HEXAGON_A2_addp:
3507    ID = Intrinsic::hexagon_A2_addp; break;
3508
3509  case Hexagon::BI__builtin_HEXAGON_A2_addpsat:
3510    ID = Intrinsic::hexagon_A2_addpsat; break;
3511
3512  case Hexagon::BI__builtin_HEXAGON_A2_addsp:
3513    ID = Intrinsic::hexagon_A2_addsp; break;
3514
3515  case Hexagon::BI__builtin_HEXAGON_A2_subp:
3516    ID = Intrinsic::hexagon_A2_subp; break;
3517
3518  case Hexagon::BI__builtin_HEXAGON_A2_neg:
3519    ID = Intrinsic::hexagon_A2_neg; break;
3520
3521  case Hexagon::BI__builtin_HEXAGON_A2_negsat:
3522    ID = Intrinsic::hexagon_A2_negsat; break;
3523
3524  case Hexagon::BI__builtin_HEXAGON_A2_abs:
3525    ID = Intrinsic::hexagon_A2_abs; break;
3526
3527  case Hexagon::BI__builtin_HEXAGON_A2_abssat:
3528    ID = Intrinsic::hexagon_A2_abssat; break;
3529
3530  case Hexagon::BI__builtin_HEXAGON_A2_vconj:
3531    ID = Intrinsic::hexagon_A2_vconj; break;
3532
3533  case Hexagon::BI__builtin_HEXAGON_A2_negp:
3534    ID = Intrinsic::hexagon_A2_negp; break;
3535
3536  case Hexagon::BI__builtin_HEXAGON_A2_absp:
3537    ID = Intrinsic::hexagon_A2_absp; break;
3538
3539  case Hexagon::BI__builtin_HEXAGON_A2_max:
3540    ID = Intrinsic::hexagon_A2_max; break;
3541
3542  case Hexagon::BI__builtin_HEXAGON_A2_maxu:
3543    ID = Intrinsic::hexagon_A2_maxu; break;
3544
3545  case Hexagon::BI__builtin_HEXAGON_A2_min:
3546    ID = Intrinsic::hexagon_A2_min; break;
3547
3548  case Hexagon::BI__builtin_HEXAGON_A2_minu:
3549    ID = Intrinsic::hexagon_A2_minu; break;
3550
3551  case Hexagon::BI__builtin_HEXAGON_A2_maxp:
3552    ID = Intrinsic::hexagon_A2_maxp; break;
3553
3554  case Hexagon::BI__builtin_HEXAGON_A2_maxup:
3555    ID = Intrinsic::hexagon_A2_maxup; break;
3556
3557  case Hexagon::BI__builtin_HEXAGON_A2_minp:
3558    ID = Intrinsic::hexagon_A2_minp; break;
3559
3560  case Hexagon::BI__builtin_HEXAGON_A2_minup:
3561    ID = Intrinsic::hexagon_A2_minup; break;
3562
3563  case Hexagon::BI__builtin_HEXAGON_A2_tfr:
3564    ID = Intrinsic::hexagon_A2_tfr; break;
3565
3566  case Hexagon::BI__builtin_HEXAGON_A2_tfrsi:
3567    ID = Intrinsic::hexagon_A2_tfrsi; break;
3568
3569  case Hexagon::BI__builtin_HEXAGON_A2_tfrp:
3570    ID = Intrinsic::hexagon_A2_tfrp; break;
3571
3572  case Hexagon::BI__builtin_HEXAGON_A2_tfrpi:
3573    ID = Intrinsic::hexagon_A2_tfrpi; break;
3574
3575  case Hexagon::BI__builtin_HEXAGON_A2_zxtb:
3576    ID = Intrinsic::hexagon_A2_zxtb; break;
3577
3578  case Hexagon::BI__builtin_HEXAGON_A2_sxtb:
3579    ID = Intrinsic::hexagon_A2_sxtb; break;
3580
3581  case Hexagon::BI__builtin_HEXAGON_A2_zxth:
3582    ID = Intrinsic::hexagon_A2_zxth; break;
3583
3584  case Hexagon::BI__builtin_HEXAGON_A2_sxth:
3585    ID = Intrinsic::hexagon_A2_sxth; break;
3586
3587  case Hexagon::BI__builtin_HEXAGON_A2_combinew:
3588    ID = Intrinsic::hexagon_A2_combinew; break;
3589
3590  case Hexagon::BI__builtin_HEXAGON_A2_combineii:
3591    ID = Intrinsic::hexagon_A2_combineii; break;
3592
3593  case Hexagon::BI__builtin_HEXAGON_A2_combine_hh:
3594    ID = Intrinsic::hexagon_A2_combine_hh; break;
3595
3596  case Hexagon::BI__builtin_HEXAGON_A2_combine_hl:
3597    ID = Intrinsic::hexagon_A2_combine_hl; break;
3598
3599  case Hexagon::BI__builtin_HEXAGON_A2_combine_lh:
3600    ID = Intrinsic::hexagon_A2_combine_lh; break;
3601
3602  case Hexagon::BI__builtin_HEXAGON_A2_combine_ll:
3603    ID = Intrinsic::hexagon_A2_combine_ll; break;
3604
3605  case Hexagon::BI__builtin_HEXAGON_A2_tfril:
3606    ID = Intrinsic::hexagon_A2_tfril; break;
3607
3608  case Hexagon::BI__builtin_HEXAGON_A2_tfrih:
3609    ID = Intrinsic::hexagon_A2_tfrih; break;
3610
3611  case Hexagon::BI__builtin_HEXAGON_A2_and:
3612    ID = Intrinsic::hexagon_A2_and; break;
3613
3614  case Hexagon::BI__builtin_HEXAGON_A2_or:
3615    ID = Intrinsic::hexagon_A2_or; break;
3616
3617  case Hexagon::BI__builtin_HEXAGON_A2_xor:
3618    ID = Intrinsic::hexagon_A2_xor; break;
3619
3620  case Hexagon::BI__builtin_HEXAGON_A2_not:
3621    ID = Intrinsic::hexagon_A2_not; break;
3622
3623  case Hexagon::BI__builtin_HEXAGON_M2_xor_xacc:
3624    ID = Intrinsic::hexagon_M2_xor_xacc; break;
3625
3626  case Hexagon::BI__builtin_HEXAGON_A2_subri:
3627    ID = Intrinsic::hexagon_A2_subri; break;
3628
3629  case Hexagon::BI__builtin_HEXAGON_A2_andir:
3630    ID = Intrinsic::hexagon_A2_andir; break;
3631
3632  case Hexagon::BI__builtin_HEXAGON_A2_orir:
3633    ID = Intrinsic::hexagon_A2_orir; break;
3634
3635  case Hexagon::BI__builtin_HEXAGON_A2_andp:
3636    ID = Intrinsic::hexagon_A2_andp; break;
3637
3638  case Hexagon::BI__builtin_HEXAGON_A2_orp:
3639    ID = Intrinsic::hexagon_A2_orp; break;
3640
3641  case Hexagon::BI__builtin_HEXAGON_A2_xorp:
3642    ID = Intrinsic::hexagon_A2_xorp; break;
3643
3644  case Hexagon::BI__builtin_HEXAGON_A2_notp:
3645    ID = Intrinsic::hexagon_A2_notp; break;
3646
3647  case Hexagon::BI__builtin_HEXAGON_A2_sxtw:
3648    ID = Intrinsic::hexagon_A2_sxtw; break;
3649
3650  case Hexagon::BI__builtin_HEXAGON_A2_sat:
3651    ID = Intrinsic::hexagon_A2_sat; break;
3652
3653  case Hexagon::BI__builtin_HEXAGON_A2_sath:
3654    ID = Intrinsic::hexagon_A2_sath; break;
3655
3656  case Hexagon::BI__builtin_HEXAGON_A2_satuh:
3657    ID = Intrinsic::hexagon_A2_satuh; break;
3658
3659  case Hexagon::BI__builtin_HEXAGON_A2_satub:
3660    ID = Intrinsic::hexagon_A2_satub; break;
3661
3662  case Hexagon::BI__builtin_HEXAGON_A2_satb:
3663    ID = Intrinsic::hexagon_A2_satb; break;
3664
3665  case Hexagon::BI__builtin_HEXAGON_A2_vaddub:
3666    ID = Intrinsic::hexagon_A2_vaddub; break;
3667
3668  case Hexagon::BI__builtin_HEXAGON_A2_vaddubs:
3669    ID = Intrinsic::hexagon_A2_vaddubs; break;
3670
3671  case Hexagon::BI__builtin_HEXAGON_A2_vaddh:
3672    ID = Intrinsic::hexagon_A2_vaddh; break;
3673
3674  case Hexagon::BI__builtin_HEXAGON_A2_vaddhs:
3675    ID = Intrinsic::hexagon_A2_vaddhs; break;
3676
3677  case Hexagon::BI__builtin_HEXAGON_A2_vadduhs:
3678    ID = Intrinsic::hexagon_A2_vadduhs; break;
3679
3680  case Hexagon::BI__builtin_HEXAGON_A2_vaddw:
3681    ID = Intrinsic::hexagon_A2_vaddw; break;
3682
3683  case Hexagon::BI__builtin_HEXAGON_A2_vaddws:
3684    ID = Intrinsic::hexagon_A2_vaddws; break;
3685
3686  case Hexagon::BI__builtin_HEXAGON_A2_svavgh:
3687    ID = Intrinsic::hexagon_A2_svavgh; break;
3688
3689  case Hexagon::BI__builtin_HEXAGON_A2_svavghs:
3690    ID = Intrinsic::hexagon_A2_svavghs; break;
3691
3692  case Hexagon::BI__builtin_HEXAGON_A2_svnavgh:
3693    ID = Intrinsic::hexagon_A2_svnavgh; break;
3694
3695  case Hexagon::BI__builtin_HEXAGON_A2_svaddh:
3696    ID = Intrinsic::hexagon_A2_svaddh; break;
3697
3698  case Hexagon::BI__builtin_HEXAGON_A2_svaddhs:
3699    ID = Intrinsic::hexagon_A2_svaddhs; break;
3700
3701  case Hexagon::BI__builtin_HEXAGON_A2_svadduhs:
3702    ID = Intrinsic::hexagon_A2_svadduhs; break;
3703
3704  case Hexagon::BI__builtin_HEXAGON_A2_svsubh:
3705    ID = Intrinsic::hexagon_A2_svsubh; break;
3706
3707  case Hexagon::BI__builtin_HEXAGON_A2_svsubhs:
3708    ID = Intrinsic::hexagon_A2_svsubhs; break;
3709
3710  case Hexagon::BI__builtin_HEXAGON_A2_svsubuhs:
3711    ID = Intrinsic::hexagon_A2_svsubuhs; break;
3712
3713  case Hexagon::BI__builtin_HEXAGON_A2_vraddub:
3714    ID = Intrinsic::hexagon_A2_vraddub; break;
3715
3716  case Hexagon::BI__builtin_HEXAGON_A2_vraddub_acc:
3717    ID = Intrinsic::hexagon_A2_vraddub_acc; break;
3718
3719  case Hexagon::BI__builtin_HEXAGON_M2_vradduh:
3720    ID = Intrinsic::hexagon_M2_vradduh; break;
3721
3722  case Hexagon::BI__builtin_HEXAGON_A2_vsubub:
3723    ID = Intrinsic::hexagon_A2_vsubub; break;
3724
3725  case Hexagon::BI__builtin_HEXAGON_A2_vsububs:
3726    ID = Intrinsic::hexagon_A2_vsububs; break;
3727
3728  case Hexagon::BI__builtin_HEXAGON_A2_vsubh:
3729    ID = Intrinsic::hexagon_A2_vsubh; break;
3730
3731  case Hexagon::BI__builtin_HEXAGON_A2_vsubhs:
3732    ID = Intrinsic::hexagon_A2_vsubhs; break;
3733
3734  case Hexagon::BI__builtin_HEXAGON_A2_vsubuhs:
3735    ID = Intrinsic::hexagon_A2_vsubuhs; break;
3736
3737  case Hexagon::BI__builtin_HEXAGON_A2_vsubw:
3738    ID = Intrinsic::hexagon_A2_vsubw; break;
3739
3740  case Hexagon::BI__builtin_HEXAGON_A2_vsubws:
3741    ID = Intrinsic::hexagon_A2_vsubws; break;
3742
3743  case Hexagon::BI__builtin_HEXAGON_A2_vabsh:
3744    ID = Intrinsic::hexagon_A2_vabsh; break;
3745
3746  case Hexagon::BI__builtin_HEXAGON_A2_vabshsat:
3747    ID = Intrinsic::hexagon_A2_vabshsat; break;
3748
3749  case Hexagon::BI__builtin_HEXAGON_A2_vabsw:
3750    ID = Intrinsic::hexagon_A2_vabsw; break;
3751
3752  case Hexagon::BI__builtin_HEXAGON_A2_vabswsat:
3753    ID = Intrinsic::hexagon_A2_vabswsat; break;
3754
3755  case Hexagon::BI__builtin_HEXAGON_M2_vabsdiffw:
3756    ID = Intrinsic::hexagon_M2_vabsdiffw; break;
3757
3758  case Hexagon::BI__builtin_HEXAGON_M2_vabsdiffh:
3759    ID = Intrinsic::hexagon_M2_vabsdiffh; break;
3760
3761  case Hexagon::BI__builtin_HEXAGON_A2_vrsadub:
3762    ID = Intrinsic::hexagon_A2_vrsadub; break;
3763
3764  case Hexagon::BI__builtin_HEXAGON_A2_vrsadub_acc:
3765    ID = Intrinsic::hexagon_A2_vrsadub_acc; break;
3766
3767  case Hexagon::BI__builtin_HEXAGON_A2_vavgub:
3768    ID = Intrinsic::hexagon_A2_vavgub; break;
3769
3770  case Hexagon::BI__builtin_HEXAGON_A2_vavguh:
3771    ID = Intrinsic::hexagon_A2_vavguh; break;
3772
3773  case Hexagon::BI__builtin_HEXAGON_A2_vavgh:
3774    ID = Intrinsic::hexagon_A2_vavgh; break;
3775
3776  case Hexagon::BI__builtin_HEXAGON_A2_vnavgh:
3777    ID = Intrinsic::hexagon_A2_vnavgh; break;
3778
3779  case Hexagon::BI__builtin_HEXAGON_A2_vavgw:
3780    ID = Intrinsic::hexagon_A2_vavgw; break;
3781
3782  case Hexagon::BI__builtin_HEXAGON_A2_vnavgw:
3783    ID = Intrinsic::hexagon_A2_vnavgw; break;
3784
3785  case Hexagon::BI__builtin_HEXAGON_A2_vavgwr:
3786    ID = Intrinsic::hexagon_A2_vavgwr; break;
3787
3788  case Hexagon::BI__builtin_HEXAGON_A2_vnavgwr:
3789    ID = Intrinsic::hexagon_A2_vnavgwr; break;
3790
3791  case Hexagon::BI__builtin_HEXAGON_A2_vavgwcr:
3792    ID = Intrinsic::hexagon_A2_vavgwcr; break;
3793
3794  case Hexagon::BI__builtin_HEXAGON_A2_vnavgwcr:
3795    ID = Intrinsic::hexagon_A2_vnavgwcr; break;
3796
3797  case Hexagon::BI__builtin_HEXAGON_A2_vavghcr:
3798    ID = Intrinsic::hexagon_A2_vavghcr; break;
3799
3800  case Hexagon::BI__builtin_HEXAGON_A2_vnavghcr:
3801    ID = Intrinsic::hexagon_A2_vnavghcr; break;
3802
3803  case Hexagon::BI__builtin_HEXAGON_A2_vavguw:
3804    ID = Intrinsic::hexagon_A2_vavguw; break;
3805
3806  case Hexagon::BI__builtin_HEXAGON_A2_vavguwr:
3807    ID = Intrinsic::hexagon_A2_vavguwr; break;
3808
3809  case Hexagon::BI__builtin_HEXAGON_A2_vavgubr:
3810    ID = Intrinsic::hexagon_A2_vavgubr; break;
3811
3812  case Hexagon::BI__builtin_HEXAGON_A2_vavguhr:
3813    ID = Intrinsic::hexagon_A2_vavguhr; break;
3814
3815  case Hexagon::BI__builtin_HEXAGON_A2_vavghr:
3816    ID = Intrinsic::hexagon_A2_vavghr; break;
3817
3818  case Hexagon::BI__builtin_HEXAGON_A2_vnavghr:
3819    ID = Intrinsic::hexagon_A2_vnavghr; break;
3820
3821  case Hexagon::BI__builtin_HEXAGON_A2_vminh:
3822    ID = Intrinsic::hexagon_A2_vminh; break;
3823
3824  case Hexagon::BI__builtin_HEXAGON_A2_vmaxh:
3825    ID = Intrinsic::hexagon_A2_vmaxh; break;
3826
3827  case Hexagon::BI__builtin_HEXAGON_A2_vminub:
3828    ID = Intrinsic::hexagon_A2_vminub; break;
3829
3830  case Hexagon::BI__builtin_HEXAGON_A2_vmaxub:
3831    ID = Intrinsic::hexagon_A2_vmaxub; break;
3832
3833  case Hexagon::BI__builtin_HEXAGON_A2_vminuh:
3834    ID = Intrinsic::hexagon_A2_vminuh; break;
3835
3836  case Hexagon::BI__builtin_HEXAGON_A2_vmaxuh:
3837    ID = Intrinsic::hexagon_A2_vmaxuh; break;
3838
3839  case Hexagon::BI__builtin_HEXAGON_A2_vminw:
3840    ID = Intrinsic::hexagon_A2_vminw; break;
3841
3842  case Hexagon::BI__builtin_HEXAGON_A2_vmaxw:
3843    ID = Intrinsic::hexagon_A2_vmaxw; break;
3844
3845  case Hexagon::BI__builtin_HEXAGON_A2_vminuw:
3846    ID = Intrinsic::hexagon_A2_vminuw; break;
3847
3848  case Hexagon::BI__builtin_HEXAGON_A2_vmaxuw:
3849    ID = Intrinsic::hexagon_A2_vmaxuw; break;
3850
3851  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r:
3852    ID = Intrinsic::hexagon_S2_asr_r_r; break;
3853
3854  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r:
3855    ID = Intrinsic::hexagon_S2_asl_r_r; break;
3856
3857  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r:
3858    ID = Intrinsic::hexagon_S2_lsr_r_r; break;
3859
3860  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r:
3861    ID = Intrinsic::hexagon_S2_lsl_r_r; break;
3862
3863  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p:
3864    ID = Intrinsic::hexagon_S2_asr_r_p; break;
3865
3866  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p:
3867    ID = Intrinsic::hexagon_S2_asl_r_p; break;
3868
3869  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p:
3870    ID = Intrinsic::hexagon_S2_lsr_r_p; break;
3871
3872  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p:
3873    ID = Intrinsic::hexagon_S2_lsl_r_p; break;
3874
3875  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_acc:
3876    ID = Intrinsic::hexagon_S2_asr_r_r_acc; break;
3877
3878  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_acc:
3879    ID = Intrinsic::hexagon_S2_asl_r_r_acc; break;
3880
3881  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_acc:
3882    ID = Intrinsic::hexagon_S2_lsr_r_r_acc; break;
3883
3884  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_acc:
3885    ID = Intrinsic::hexagon_S2_lsl_r_r_acc; break;
3886
3887  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_acc:
3888    ID = Intrinsic::hexagon_S2_asr_r_p_acc; break;
3889
3890  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_acc:
3891    ID = Intrinsic::hexagon_S2_asl_r_p_acc; break;
3892
3893  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_acc:
3894    ID = Intrinsic::hexagon_S2_lsr_r_p_acc; break;
3895
3896  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_acc:
3897    ID = Intrinsic::hexagon_S2_lsl_r_p_acc; break;
3898
3899  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_nac:
3900    ID = Intrinsic::hexagon_S2_asr_r_r_nac; break;
3901
3902  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_nac:
3903    ID = Intrinsic::hexagon_S2_asl_r_r_nac; break;
3904
3905  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_nac:
3906    ID = Intrinsic::hexagon_S2_lsr_r_r_nac; break;
3907
3908  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_nac:
3909    ID = Intrinsic::hexagon_S2_lsl_r_r_nac; break;
3910
3911  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_nac:
3912    ID = Intrinsic::hexagon_S2_asr_r_p_nac; break;
3913
3914  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_nac:
3915    ID = Intrinsic::hexagon_S2_asl_r_p_nac; break;
3916
3917  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_nac:
3918    ID = Intrinsic::hexagon_S2_lsr_r_p_nac; break;
3919
3920  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_nac:
3921    ID = Intrinsic::hexagon_S2_lsl_r_p_nac; break;
3922
3923  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_and:
3924    ID = Intrinsic::hexagon_S2_asr_r_r_and; break;
3925
3926  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_and:
3927    ID = Intrinsic::hexagon_S2_asl_r_r_and; break;
3928
3929  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_and:
3930    ID = Intrinsic::hexagon_S2_lsr_r_r_and; break;
3931
3932  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_and:
3933    ID = Intrinsic::hexagon_S2_lsl_r_r_and; break;
3934
3935  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_or:
3936    ID = Intrinsic::hexagon_S2_asr_r_r_or; break;
3937
3938  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_or:
3939    ID = Intrinsic::hexagon_S2_asl_r_r_or; break;
3940
3941  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_or:
3942    ID = Intrinsic::hexagon_S2_lsr_r_r_or; break;
3943
3944  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_or:
3945    ID = Intrinsic::hexagon_S2_lsl_r_r_or; break;
3946
3947  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_and:
3948    ID = Intrinsic::hexagon_S2_asr_r_p_and; break;
3949
3950  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_and:
3951    ID = Intrinsic::hexagon_S2_asl_r_p_and; break;
3952
3953  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_and:
3954    ID = Intrinsic::hexagon_S2_lsr_r_p_and; break;
3955
3956  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_and:
3957    ID = Intrinsic::hexagon_S2_lsl_r_p_and; break;
3958
3959  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_or:
3960    ID = Intrinsic::hexagon_S2_asr_r_p_or; break;
3961
3962  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_or:
3963    ID = Intrinsic::hexagon_S2_asl_r_p_or; break;
3964
3965  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_or:
3966    ID = Intrinsic::hexagon_S2_lsr_r_p_or; break;
3967
3968  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_or:
3969    ID = Intrinsic::hexagon_S2_lsl_r_p_or; break;
3970
3971  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_sat:
3972    ID = Intrinsic::hexagon_S2_asr_r_r_sat; break;
3973
3974  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_sat:
3975    ID = Intrinsic::hexagon_S2_asl_r_r_sat; break;
3976
3977  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r:
3978    ID = Intrinsic::hexagon_S2_asr_i_r; break;
3979
3980  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r:
3981    ID = Intrinsic::hexagon_S2_lsr_i_r; break;
3982
3983  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r:
3984    ID = Intrinsic::hexagon_S2_asl_i_r; break;
3985
3986  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p:
3987    ID = Intrinsic::hexagon_S2_asr_i_p; break;
3988
3989  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p:
3990    ID = Intrinsic::hexagon_S2_lsr_i_p; break;
3991
3992  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p:
3993    ID = Intrinsic::hexagon_S2_asl_i_p; break;
3994
3995  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_acc:
3996    ID = Intrinsic::hexagon_S2_asr_i_r_acc; break;
3997
3998  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_acc:
3999    ID = Intrinsic::hexagon_S2_lsr_i_r_acc; break;
4000
4001  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_acc:
4002    ID = Intrinsic::hexagon_S2_asl_i_r_acc; break;
4003
4004  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_acc:
4005    ID = Intrinsic::hexagon_S2_asr_i_p_acc; break;
4006
4007  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_acc:
4008    ID = Intrinsic::hexagon_S2_lsr_i_p_acc; break;
4009
4010  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_acc:
4011    ID = Intrinsic::hexagon_S2_asl_i_p_acc; break;
4012
4013  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_nac:
4014    ID = Intrinsic::hexagon_S2_asr_i_r_nac; break;
4015
4016  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_nac:
4017    ID = Intrinsic::hexagon_S2_lsr_i_r_nac; break;
4018
4019  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_nac:
4020    ID = Intrinsic::hexagon_S2_asl_i_r_nac; break;
4021
4022  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_nac:
4023    ID = Intrinsic::hexagon_S2_asr_i_p_nac; break;
4024
4025  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_nac:
4026    ID = Intrinsic::hexagon_S2_lsr_i_p_nac; break;
4027
4028  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_nac:
4029    ID = Intrinsic::hexagon_S2_asl_i_p_nac; break;
4030
4031  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_xacc:
4032    ID = Intrinsic::hexagon_S2_lsr_i_r_xacc; break;
4033
4034  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_xacc:
4035    ID = Intrinsic::hexagon_S2_asl_i_r_xacc; break;
4036
4037  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_xacc:
4038    ID = Intrinsic::hexagon_S2_lsr_i_p_xacc; break;
4039
4040  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_xacc:
4041    ID = Intrinsic::hexagon_S2_asl_i_p_xacc; break;
4042
4043  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_and:
4044    ID = Intrinsic::hexagon_S2_asr_i_r_and; break;
4045
4046  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_and:
4047    ID = Intrinsic::hexagon_S2_lsr_i_r_and; break;
4048
4049  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_and:
4050    ID = Intrinsic::hexagon_S2_asl_i_r_and; break;
4051
4052  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_or:
4053    ID = Intrinsic::hexagon_S2_asr_i_r_or; break;
4054
4055  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_or:
4056    ID = Intrinsic::hexagon_S2_lsr_i_r_or; break;
4057
4058  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_or:
4059    ID = Intrinsic::hexagon_S2_asl_i_r_or; break;
4060
4061  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_and:
4062    ID = Intrinsic::hexagon_S2_asr_i_p_and; break;
4063
4064  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_and:
4065    ID = Intrinsic::hexagon_S2_lsr_i_p_and; break;
4066
4067  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_and:
4068    ID = Intrinsic::hexagon_S2_asl_i_p_and; break;
4069
4070  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_or:
4071    ID = Intrinsic::hexagon_S2_asr_i_p_or; break;
4072
4073  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_or:
4074    ID = Intrinsic::hexagon_S2_lsr_i_p_or; break;
4075
4076  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_or:
4077    ID = Intrinsic::hexagon_S2_asl_i_p_or; break;
4078
4079  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_sat:
4080    ID = Intrinsic::hexagon_S2_asl_i_r_sat; break;
4081
4082  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd:
4083    ID = Intrinsic::hexagon_S2_asr_i_r_rnd; break;
4084
4085  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax:
4086    ID = Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; break;
4087
4088  case Hexagon::BI__builtin_HEXAGON_S2_addasl_rrri:
4089    ID = Intrinsic::hexagon_S2_addasl_rrri; break;
4090
4091  case Hexagon::BI__builtin_HEXAGON_S2_valignib:
4092    ID = Intrinsic::hexagon_S2_valignib; break;
4093
4094  case Hexagon::BI__builtin_HEXAGON_S2_valignrb:
4095    ID = Intrinsic::hexagon_S2_valignrb; break;
4096
4097  case Hexagon::BI__builtin_HEXAGON_S2_vspliceib:
4098    ID = Intrinsic::hexagon_S2_vspliceib; break;
4099
4100  case Hexagon::BI__builtin_HEXAGON_S2_vsplicerb:
4101    ID = Intrinsic::hexagon_S2_vsplicerb; break;
4102
4103  case Hexagon::BI__builtin_HEXAGON_S2_vsplatrh:
4104    ID = Intrinsic::hexagon_S2_vsplatrh; break;
4105
4106  case Hexagon::BI__builtin_HEXAGON_S2_vsplatrb:
4107    ID = Intrinsic::hexagon_S2_vsplatrb; break;
4108
4109  case Hexagon::BI__builtin_HEXAGON_S2_insert:
4110    ID = Intrinsic::hexagon_S2_insert; break;
4111
4112  case Hexagon::BI__builtin_HEXAGON_S2_tableidxb_goodsyntax:
4113    ID = Intrinsic::hexagon_S2_tableidxb_goodsyntax; break;
4114
4115  case Hexagon::BI__builtin_HEXAGON_S2_tableidxh_goodsyntax:
4116    ID = Intrinsic::hexagon_S2_tableidxh_goodsyntax; break;
4117
4118  case Hexagon::BI__builtin_HEXAGON_S2_tableidxw_goodsyntax:
4119    ID = Intrinsic::hexagon_S2_tableidxw_goodsyntax; break;
4120
4121  case Hexagon::BI__builtin_HEXAGON_S2_tableidxd_goodsyntax:
4122    ID = Intrinsic::hexagon_S2_tableidxd_goodsyntax; break;
4123
4124  case Hexagon::BI__builtin_HEXAGON_S2_extractu:
4125    ID = Intrinsic::hexagon_S2_extractu; break;
4126
4127  case Hexagon::BI__builtin_HEXAGON_S2_insertp:
4128    ID = Intrinsic::hexagon_S2_insertp; break;
4129
4130  case Hexagon::BI__builtin_HEXAGON_S2_extractup:
4131    ID = Intrinsic::hexagon_S2_extractup; break;
4132
4133  case Hexagon::BI__builtin_HEXAGON_S2_insert_rp:
4134    ID = Intrinsic::hexagon_S2_insert_rp; break;
4135
4136  case Hexagon::BI__builtin_HEXAGON_S2_extractu_rp:
4137    ID = Intrinsic::hexagon_S2_extractu_rp; break;
4138
4139  case Hexagon::BI__builtin_HEXAGON_S2_insertp_rp:
4140    ID = Intrinsic::hexagon_S2_insertp_rp; break;
4141
4142  case Hexagon::BI__builtin_HEXAGON_S2_extractup_rp:
4143    ID = Intrinsic::hexagon_S2_extractup_rp; break;
4144
4145  case Hexagon::BI__builtin_HEXAGON_S2_tstbit_i:
4146    ID = Intrinsic::hexagon_S2_tstbit_i; break;
4147
4148  case Hexagon::BI__builtin_HEXAGON_S2_setbit_i:
4149    ID = Intrinsic::hexagon_S2_setbit_i; break;
4150
4151  case Hexagon::BI__builtin_HEXAGON_S2_togglebit_i:
4152    ID = Intrinsic::hexagon_S2_togglebit_i; break;
4153
4154  case Hexagon::BI__builtin_HEXAGON_S2_clrbit_i:
4155    ID = Intrinsic::hexagon_S2_clrbit_i; break;
4156
4157  case Hexagon::BI__builtin_HEXAGON_S2_tstbit_r:
4158    ID = Intrinsic::hexagon_S2_tstbit_r; break;
4159
4160  case Hexagon::BI__builtin_HEXAGON_S2_setbit_r:
4161    ID = Intrinsic::hexagon_S2_setbit_r; break;
4162
4163  case Hexagon::BI__builtin_HEXAGON_S2_togglebit_r:
4164    ID = Intrinsic::hexagon_S2_togglebit_r; break;
4165
4166  case Hexagon::BI__builtin_HEXAGON_S2_clrbit_r:
4167    ID = Intrinsic::hexagon_S2_clrbit_r; break;
4168
4169  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_vh:
4170    ID = Intrinsic::hexagon_S2_asr_i_vh; break;
4171
4172  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vh:
4173    ID = Intrinsic::hexagon_S2_lsr_i_vh; break;
4174
4175  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_vh:
4176    ID = Intrinsic::hexagon_S2_asl_i_vh; break;
4177
4178  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_vh:
4179    ID = Intrinsic::hexagon_S2_asr_r_vh; break;
4180
4181  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_vh:
4182    ID = Intrinsic::hexagon_S2_asl_r_vh; break;
4183
4184  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_vh:
4185    ID = Intrinsic::hexagon_S2_lsr_r_vh; break;
4186
4187  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_vh:
4188    ID = Intrinsic::hexagon_S2_lsl_r_vh; break;
4189
4190  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_vw:
4191    ID = Intrinsic::hexagon_S2_asr_i_vw; break;
4192
4193  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_svw_trun:
4194    ID = Intrinsic::hexagon_S2_asr_i_svw_trun; break;
4195
4196  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_svw_trun:
4197    ID = Intrinsic::hexagon_S2_asr_r_svw_trun; break;
4198
4199  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vw:
4200    ID = Intrinsic::hexagon_S2_lsr_i_vw; break;
4201
4202  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_vw:
4203    ID = Intrinsic::hexagon_S2_asl_i_vw; break;
4204
4205  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_vw:
4206    ID = Intrinsic::hexagon_S2_asr_r_vw; break;
4207
4208  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_vw:
4209    ID = Intrinsic::hexagon_S2_asl_r_vw; break;
4210
4211  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_vw:
4212    ID = Intrinsic::hexagon_S2_lsr_r_vw; break;
4213
4214  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_vw:
4215    ID = Intrinsic::hexagon_S2_lsl_r_vw; break;
4216
4217  case Hexagon::BI__builtin_HEXAGON_S2_vrndpackwh:
4218    ID = Intrinsic::hexagon_S2_vrndpackwh; break;
4219
4220  case Hexagon::BI__builtin_HEXAGON_S2_vrndpackwhs:
4221    ID = Intrinsic::hexagon_S2_vrndpackwhs; break;
4222
4223  case Hexagon::BI__builtin_HEXAGON_S2_vsxtbh:
4224    ID = Intrinsic::hexagon_S2_vsxtbh; break;
4225
4226  case Hexagon::BI__builtin_HEXAGON_S2_vzxtbh:
4227    ID = Intrinsic::hexagon_S2_vzxtbh; break;
4228
4229  case Hexagon::BI__builtin_HEXAGON_S2_vsathub:
4230    ID = Intrinsic::hexagon_S2_vsathub; break;
4231
4232  case Hexagon::BI__builtin_HEXAGON_S2_svsathub:
4233    ID = Intrinsic::hexagon_S2_svsathub; break;
4234
4235  case Hexagon::BI__builtin_HEXAGON_S2_svsathb:
4236    ID = Intrinsic::hexagon_S2_svsathb; break;
4237
4238  case Hexagon::BI__builtin_HEXAGON_S2_vsathb:
4239    ID = Intrinsic::hexagon_S2_vsathb; break;
4240
4241  case Hexagon::BI__builtin_HEXAGON_S2_vtrunohb:
4242    ID = Intrinsic::hexagon_S2_vtrunohb; break;
4243
4244  case Hexagon::BI__builtin_HEXAGON_S2_vtrunewh:
4245    ID = Intrinsic::hexagon_S2_vtrunewh; break;
4246
4247  case Hexagon::BI__builtin_HEXAGON_S2_vtrunowh:
4248    ID = Intrinsic::hexagon_S2_vtrunowh; break;
4249
4250  case Hexagon::BI__builtin_HEXAGON_S2_vtrunehb:
4251    ID = Intrinsic::hexagon_S2_vtrunehb; break;
4252
4253  case Hexagon::BI__builtin_HEXAGON_S2_vsxthw:
4254    ID = Intrinsic::hexagon_S2_vsxthw; break;
4255
4256  case Hexagon::BI__builtin_HEXAGON_S2_vzxthw:
4257    ID = Intrinsic::hexagon_S2_vzxthw; break;
4258
4259  case Hexagon::BI__builtin_HEXAGON_S2_vsatwh:
4260    ID = Intrinsic::hexagon_S2_vsatwh; break;
4261
4262  case Hexagon::BI__builtin_HEXAGON_S2_vsatwuh:
4263    ID = Intrinsic::hexagon_S2_vsatwuh; break;
4264
4265  case Hexagon::BI__builtin_HEXAGON_S2_packhl:
4266    ID = Intrinsic::hexagon_S2_packhl; break;
4267
4268  case Hexagon::BI__builtin_HEXAGON_A2_swiz:
4269    ID = Intrinsic::hexagon_A2_swiz; break;
4270
4271  case Hexagon::BI__builtin_HEXAGON_S2_vsathub_nopack:
4272    ID = Intrinsic::hexagon_S2_vsathub_nopack; break;
4273
4274  case Hexagon::BI__builtin_HEXAGON_S2_vsathb_nopack:
4275    ID = Intrinsic::hexagon_S2_vsathb_nopack; break;
4276
4277  case Hexagon::BI__builtin_HEXAGON_S2_vsatwh_nopack:
4278    ID = Intrinsic::hexagon_S2_vsatwh_nopack; break;
4279
4280  case Hexagon::BI__builtin_HEXAGON_S2_vsatwuh_nopack:
4281    ID = Intrinsic::hexagon_S2_vsatwuh_nopack; break;
4282
4283  case Hexagon::BI__builtin_HEXAGON_S2_shuffob:
4284    ID = Intrinsic::hexagon_S2_shuffob; break;
4285
4286  case Hexagon::BI__builtin_HEXAGON_S2_shuffeb:
4287    ID = Intrinsic::hexagon_S2_shuffeb; break;
4288
4289  case Hexagon::BI__builtin_HEXAGON_S2_shuffoh:
4290    ID = Intrinsic::hexagon_S2_shuffoh; break;
4291
4292  case Hexagon::BI__builtin_HEXAGON_S2_shuffeh:
4293    ID = Intrinsic::hexagon_S2_shuffeh; break;
4294
4295  case Hexagon::BI__builtin_HEXAGON_S2_parityp:
4296    ID = Intrinsic::hexagon_S2_parityp; break;
4297
4298  case Hexagon::BI__builtin_HEXAGON_S2_lfsp:
4299    ID = Intrinsic::hexagon_S2_lfsp; break;
4300
4301  case Hexagon::BI__builtin_HEXAGON_S2_clbnorm:
4302    ID = Intrinsic::hexagon_S2_clbnorm; break;
4303
4304  case Hexagon::BI__builtin_HEXAGON_S2_clb:
4305    ID = Intrinsic::hexagon_S2_clb; break;
4306
4307  case Hexagon::BI__builtin_HEXAGON_S2_cl0:
4308    ID = Intrinsic::hexagon_S2_cl0; break;
4309
4310  case Hexagon::BI__builtin_HEXAGON_S2_cl1:
4311    ID = Intrinsic::hexagon_S2_cl1; break;
4312
4313  case Hexagon::BI__builtin_HEXAGON_S2_clbp:
4314    ID = Intrinsic::hexagon_S2_clbp; break;
4315
4316  case Hexagon::BI__builtin_HEXAGON_S2_cl0p:
4317    ID = Intrinsic::hexagon_S2_cl0p; break;
4318
4319  case Hexagon::BI__builtin_HEXAGON_S2_cl1p:
4320    ID = Intrinsic::hexagon_S2_cl1p; break;
4321
4322  case Hexagon::BI__builtin_HEXAGON_S2_brev:
4323    ID = Intrinsic::hexagon_S2_brev; break;
4324
4325  case Hexagon::BI__builtin_HEXAGON_S2_ct0:
4326    ID = Intrinsic::hexagon_S2_ct0; break;
4327
4328  case Hexagon::BI__builtin_HEXAGON_S2_ct1:
4329    ID = Intrinsic::hexagon_S2_ct1; break;
4330
4331  case Hexagon::BI__builtin_HEXAGON_S2_interleave:
4332    ID = Intrinsic::hexagon_S2_interleave; break;
4333
4334  case Hexagon::BI__builtin_HEXAGON_S2_deinterleave:
4335    ID = Intrinsic::hexagon_S2_deinterleave; break;
4336
4337  case Hexagon::BI__builtin_SI_to_SXTHI_asrh:
4338    ID = Intrinsic::hexagon_SI_to_SXTHI_asrh; break;
4339
4340  case Hexagon::BI__builtin_HEXAGON_A4_orn:
4341    ID = Intrinsic::hexagon_A4_orn; break;
4342
4343  case Hexagon::BI__builtin_HEXAGON_A4_andn:
4344    ID = Intrinsic::hexagon_A4_andn; break;
4345
4346  case Hexagon::BI__builtin_HEXAGON_A4_ornp:
4347    ID = Intrinsic::hexagon_A4_ornp; break;
4348
4349  case Hexagon::BI__builtin_HEXAGON_A4_andnp:
4350    ID = Intrinsic::hexagon_A4_andnp; break;
4351
4352  case Hexagon::BI__builtin_HEXAGON_A4_combineir:
4353    ID = Intrinsic::hexagon_A4_combineir; break;
4354
4355  case Hexagon::BI__builtin_HEXAGON_A4_combineri:
4356    ID = Intrinsic::hexagon_A4_combineri; break;
4357
4358  case Hexagon::BI__builtin_HEXAGON_C4_cmpneqi:
4359    ID = Intrinsic::hexagon_C4_cmpneqi; break;
4360
4361  case Hexagon::BI__builtin_HEXAGON_C4_cmpneq:
4362    ID = Intrinsic::hexagon_C4_cmpneq; break;
4363
4364  case Hexagon::BI__builtin_HEXAGON_C4_cmpltei:
4365    ID = Intrinsic::hexagon_C4_cmpltei; break;
4366
4367  case Hexagon::BI__builtin_HEXAGON_C4_cmplte:
4368    ID = Intrinsic::hexagon_C4_cmplte; break;
4369
4370  case Hexagon::BI__builtin_HEXAGON_C4_cmplteui:
4371    ID = Intrinsic::hexagon_C4_cmplteui; break;
4372
4373  case Hexagon::BI__builtin_HEXAGON_C4_cmplteu:
4374    ID = Intrinsic::hexagon_C4_cmplteu; break;
4375
4376  case Hexagon::BI__builtin_HEXAGON_A4_rcmpneq:
4377    ID = Intrinsic::hexagon_A4_rcmpneq; break;
4378
4379  case Hexagon::BI__builtin_HEXAGON_A4_rcmpneqi:
4380    ID = Intrinsic::hexagon_A4_rcmpneqi; break;
4381
4382  case Hexagon::BI__builtin_HEXAGON_A4_rcmpeq:
4383    ID = Intrinsic::hexagon_A4_rcmpeq; break;
4384
4385  case Hexagon::BI__builtin_HEXAGON_A4_rcmpeqi:
4386    ID = Intrinsic::hexagon_A4_rcmpeqi; break;
4387
4388  case Hexagon::BI__builtin_HEXAGON_C4_fastcorner9:
4389    ID = Intrinsic::hexagon_C4_fastcorner9; break;
4390
4391  case Hexagon::BI__builtin_HEXAGON_C4_fastcorner9_not:
4392    ID = Intrinsic::hexagon_C4_fastcorner9_not; break;
4393
4394  case Hexagon::BI__builtin_HEXAGON_C4_and_andn:
4395    ID = Intrinsic::hexagon_C4_and_andn; break;
4396
4397  case Hexagon::BI__builtin_HEXAGON_C4_and_and:
4398    ID = Intrinsic::hexagon_C4_and_and; break;
4399
4400  case Hexagon::BI__builtin_HEXAGON_C4_and_orn:
4401    ID = Intrinsic::hexagon_C4_and_orn; break;
4402
4403  case Hexagon::BI__builtin_HEXAGON_C4_and_or:
4404    ID = Intrinsic::hexagon_C4_and_or; break;
4405
4406  case Hexagon::BI__builtin_HEXAGON_C4_or_andn:
4407    ID = Intrinsic::hexagon_C4_or_andn; break;
4408
4409  case Hexagon::BI__builtin_HEXAGON_C4_or_and:
4410    ID = Intrinsic::hexagon_C4_or_and; break;
4411
4412  case Hexagon::BI__builtin_HEXAGON_C4_or_orn:
4413    ID = Intrinsic::hexagon_C4_or_orn; break;
4414
4415  case Hexagon::BI__builtin_HEXAGON_C4_or_or:
4416    ID = Intrinsic::hexagon_C4_or_or; break;
4417
4418  case Hexagon::BI__builtin_HEXAGON_S4_addaddi:
4419    ID = Intrinsic::hexagon_S4_addaddi; break;
4420
4421  case Hexagon::BI__builtin_HEXAGON_S4_subaddi:
4422    ID = Intrinsic::hexagon_S4_subaddi; break;
4423
4424  case Hexagon::BI__builtin_HEXAGON_M4_xor_xacc:
4425    ID = Intrinsic::hexagon_M4_xor_xacc; break;
4426
4427  case Hexagon::BI__builtin_HEXAGON_M4_and_and:
4428    ID = Intrinsic::hexagon_M4_and_and; break;
4429
4430  case Hexagon::BI__builtin_HEXAGON_M4_and_or:
4431    ID = Intrinsic::hexagon_M4_and_or; break;
4432
4433  case Hexagon::BI__builtin_HEXAGON_M4_and_xor:
4434    ID = Intrinsic::hexagon_M4_and_xor; break;
4435
4436  case Hexagon::BI__builtin_HEXAGON_M4_and_andn:
4437    ID = Intrinsic::hexagon_M4_and_andn; break;
4438
4439  case Hexagon::BI__builtin_HEXAGON_M4_xor_and:
4440    ID = Intrinsic::hexagon_M4_xor_and; break;
4441
4442  case Hexagon::BI__builtin_HEXAGON_M4_xor_or:
4443    ID = Intrinsic::hexagon_M4_xor_or; break;
4444
4445  case Hexagon::BI__builtin_HEXAGON_M4_xor_andn:
4446    ID = Intrinsic::hexagon_M4_xor_andn; break;
4447
4448  case Hexagon::BI__builtin_HEXAGON_M4_or_and:
4449    ID = Intrinsic::hexagon_M4_or_and; break;
4450
4451  case Hexagon::BI__builtin_HEXAGON_M4_or_or:
4452    ID = Intrinsic::hexagon_M4_or_or; break;
4453
4454  case Hexagon::BI__builtin_HEXAGON_M4_or_xor:
4455    ID = Intrinsic::hexagon_M4_or_xor; break;
4456
4457  case Hexagon::BI__builtin_HEXAGON_M4_or_andn:
4458    ID = Intrinsic::hexagon_M4_or_andn; break;
4459
4460  case Hexagon::BI__builtin_HEXAGON_S4_or_andix:
4461    ID = Intrinsic::hexagon_S4_or_andix; break;
4462
4463  case Hexagon::BI__builtin_HEXAGON_S4_or_andi:
4464    ID = Intrinsic::hexagon_S4_or_andi; break;
4465
4466  case Hexagon::BI__builtin_HEXAGON_S4_or_ori:
4467    ID = Intrinsic::hexagon_S4_or_ori; break;
4468
4469  case Hexagon::BI__builtin_HEXAGON_A4_modwrapu:
4470    ID = Intrinsic::hexagon_A4_modwrapu; break;
4471
4472  case Hexagon::BI__builtin_HEXAGON_A4_cround_rr:
4473    ID = Intrinsic::hexagon_A4_cround_rr; break;
4474
4475  case Hexagon::BI__builtin_HEXAGON_A4_round_ri:
4476    ID = Intrinsic::hexagon_A4_round_ri; break;
4477
4478  case Hexagon::BI__builtin_HEXAGON_A4_round_rr:
4479    ID = Intrinsic::hexagon_A4_round_rr; break;
4480
4481  case Hexagon::BI__builtin_HEXAGON_A4_round_ri_sat:
4482    ID = Intrinsic::hexagon_A4_round_ri_sat; break;
4483
4484  case Hexagon::BI__builtin_HEXAGON_A4_round_rr_sat:
4485    ID = Intrinsic::hexagon_A4_round_rr_sat; break;
4486
4487  }
4488
4489  llvm::Function *F = CGM.getIntrinsic(ID);
4490  return Builder.CreateCall(F, Ops, "");
4491}
4492
4493Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
4494                                           const CallExpr *E) {
4495  SmallVector<Value*, 4> Ops;
4496
4497  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
4498    Ops.push_back(EmitScalarExpr(E->getArg(i)));
4499
4500  Intrinsic::ID ID = Intrinsic::not_intrinsic;
4501
4502  switch (BuiltinID) {
4503  default: return 0;
4504
4505  // vec_ld, vec_lvsl, vec_lvsr
4506  case PPC::BI__builtin_altivec_lvx:
4507  case PPC::BI__builtin_altivec_lvxl:
4508  case PPC::BI__builtin_altivec_lvebx:
4509  case PPC::BI__builtin_altivec_lvehx:
4510  case PPC::BI__builtin_altivec_lvewx:
4511  case PPC::BI__builtin_altivec_lvsl:
4512  case PPC::BI__builtin_altivec_lvsr:
4513  {
4514    Ops[1] = Builder.CreateBitCast(Ops[1], Int8PtrTy);
4515
4516    Ops[0] = Builder.CreateGEP(Ops[1], Ops[0]);
4517    Ops.pop_back();
4518
4519    switch (BuiltinID) {
4520    default: llvm_unreachable("Unsupported ld/lvsl/lvsr intrinsic!");
4521    case PPC::BI__builtin_altivec_lvx:
4522      ID = Intrinsic::ppc_altivec_lvx;
4523      break;
4524    case PPC::BI__builtin_altivec_lvxl:
4525      ID = Intrinsic::ppc_altivec_lvxl;
4526      break;
4527    case PPC::BI__builtin_altivec_lvebx:
4528      ID = Intrinsic::ppc_altivec_lvebx;
4529      break;
4530    case PPC::BI__builtin_altivec_lvehx:
4531      ID = Intrinsic::ppc_altivec_lvehx;
4532      break;
4533    case PPC::BI__builtin_altivec_lvewx:
4534      ID = Intrinsic::ppc_altivec_lvewx;
4535      break;
4536    case PPC::BI__builtin_altivec_lvsl:
4537      ID = Intrinsic::ppc_altivec_lvsl;
4538      break;
4539    case PPC::BI__builtin_altivec_lvsr:
4540      ID = Intrinsic::ppc_altivec_lvsr;
4541      break;
4542    }
4543    llvm::Function *F = CGM.getIntrinsic(ID);
4544    return Builder.CreateCall(F, Ops, "");
4545  }
4546
4547  // vec_st
4548  case PPC::BI__builtin_altivec_stvx:
4549  case PPC::BI__builtin_altivec_stvxl:
4550  case PPC::BI__builtin_altivec_stvebx:
4551  case PPC::BI__builtin_altivec_stvehx:
4552  case PPC::BI__builtin_altivec_stvewx:
4553  {
4554    Ops[2] = Builder.CreateBitCast(Ops[2], Int8PtrTy);
4555    Ops[1] = Builder.CreateGEP(Ops[2], Ops[1]);
4556    Ops.pop_back();
4557
4558    switch (BuiltinID) {
4559    default: llvm_unreachable("Unsupported st intrinsic!");
4560    case PPC::BI__builtin_altivec_stvx:
4561      ID = Intrinsic::ppc_altivec_stvx;
4562      break;
4563    case PPC::BI__builtin_altivec_stvxl:
4564      ID = Intrinsic::ppc_altivec_stvxl;
4565      break;
4566    case PPC::BI__builtin_altivec_stvebx:
4567      ID = Intrinsic::ppc_altivec_stvebx;
4568      break;
4569    case PPC::BI__builtin_altivec_stvehx:
4570      ID = Intrinsic::ppc_altivec_stvehx;
4571      break;
4572    case PPC::BI__builtin_altivec_stvewx:
4573      ID = Intrinsic::ppc_altivec_stvewx;
4574      break;
4575    }
4576    llvm::Function *F = CGM.getIntrinsic(ID);
4577    return Builder.CreateCall(F, Ops, "");
4578  }
4579  }
4580}
4581