builtins-mips.c revision cc83f26c48dfdc99ea5fbc3c28c9c9653bd71e8c
1// REQUIRES: mips-registered-target 2// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s -o - \ 3// RUN: | FileCheck %s 4 5typedef int q31; 6typedef int i32; 7typedef unsigned int ui32; 8typedef long long a64; 9 10typedef signed char v4i8 __attribute__ ((vector_size(4))); 11typedef short v2q15 __attribute__ ((vector_size(4))); 12 13void foo() { 14 v2q15 v2q15_r, v2q15_a, v2q15_b, v2q15_c; 15 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c; 16 q31 q31_r, q31_a, q31_b, q31_c; 17 i32 i32_r, i32_a, i32_b, i32_c; 18 ui32 ui32_r, ui32_a, ui32_b, ui32_c; 19 a64 a64_r, a64_a, a64_b; 20 21 // MIPS DSP Rev 1 22 23 v4i8_a = (v4i8) {1, 2, 3, 0xFF}; 24 v4i8_b = (v4i8) {2, 4, 6, 8}; 25 v4i8_r = __builtin_mips_addu_qb(v4i8_a, v4i8_b); 26// CHECK: call <4 x i8> @llvm.mips.addu.qb 27 v4i8_r = __builtin_mips_addu_s_qb(v4i8_a, v4i8_b); 28// CHECK: call <4 x i8> @llvm.mips.addu.s.qb 29 v4i8_r = __builtin_mips_subu_qb(v4i8_a, v4i8_b); 30// CHECK: call <4 x i8> @llvm.mips.subu.qb 31 v4i8_r = __builtin_mips_subu_s_qb(v4i8_a, v4i8_b); 32// CHECK: call <4 x i8> @llvm.mips.subu.s.qb 33 34 v2q15_a = (v2q15) {0x0000, 0x8000}; 35 v2q15_b = (v2q15) {0x8000, 0x8000}; 36 v2q15_r = __builtin_mips_addq_ph(v2q15_a, v2q15_b); 37// CHECK: call <2 x i16> @llvm.mips.addq.ph 38 v2q15_r = __builtin_mips_addq_s_ph(v2q15_a, v2q15_b); 39// CHECK: call <2 x i16> @llvm.mips.addq.s.ph 40 v2q15_r = __builtin_mips_subq_ph(v2q15_a, v2q15_b); 41// CHECK: call <2 x i16> @llvm.mips.subq.ph 42 v2q15_r = __builtin_mips_subq_s_ph(v2q15_a, v2q15_b); 43// CHECK: call <2 x i16> @llvm.mips.subq.s.ph 44 45 a64_a = 0x12345678; 46 i32_b = 0x80000000; 47 i32_c = 0x11112222; 48 a64_r = __builtin_mips_madd(a64_a, i32_b, i32_c); 49// CHECK: call i64 @llvm.mips.madd 50 a64_a = 0x12345678; 51 ui32_b = 0x80000000; 52 ui32_c = 0x11112222; 53 a64_r = __builtin_mips_maddu(a64_a, ui32_b, ui32_c); 54// CHECK: call i64 @llvm.mips.maddu 55 a64_a = 0x12345678; 56 i32_b = 0x80000000; 57 i32_c = 0x11112222; 58 a64_r = __builtin_mips_msub(a64_a, i32_b, i32_c); 59// CHECK: call i64 @llvm.mips.msub 60 a64_a = 0x12345678; 61 ui32_b = 0x80000000; 62 ui32_c = 0x11112222; 63 a64_r = __builtin_mips_msubu(a64_a, ui32_b, ui32_c); 64// CHECK: call i64 @llvm.mips.msubu 65 66 q31_a = 0x12345678; 67 q31_b = 0x7FFFFFFF; 68 q31_r = __builtin_mips_addq_s_w(q31_a, q31_b); 69// CHECK: call i32 @llvm.mips.addq.s.w 70 q31_r = __builtin_mips_subq_s_w(q31_a, q31_b); 71// CHECK: call i32 @llvm.mips.subq.s.w 72 73 i32_a = 0xFFFFFFFF; 74 i32_b = 1; 75 i32_r = __builtin_mips_addsc(i32_a, i32_b); 76// CHECK: call i32 @llvm.mips.addsc 77 i32_a = 0; 78 i32_b = 1; 79 i32_r = __builtin_mips_addwc(i32_a, i32_b); 80// CHECK: call i32 @llvm.mips.addwc 81 82 i32_a = 20; 83 i32_b = 0x1402; 84 i32_r = __builtin_mips_modsub(i32_a, i32_b); 85// CHECK: call i32 @llvm.mips.modsub 86 87 v4i8_a = (v4i8) {1, 2, 3, 4}; 88 i32_r = __builtin_mips_raddu_w_qb(v4i8_a); 89// CHECK: call i32 @llvm.mips.raddu.w.qb 90 91 v2q15_a = (v2q15) {0xFFFF, 0x8000}; 92 v2q15_r = __builtin_mips_absq_s_ph(v2q15_a); 93// CHECK: call <2 x i16> @llvm.mips.absq.s.ph 94 q31_a = 0x80000000; 95 q31_r = __builtin_mips_absq_s_w(q31_a); 96// CHECK: call i32 @llvm.mips.absq.s.w 97 98 v2q15_a = (v2q15) {0x1234, 0x5678}; 99 v2q15_b = (v2q15) {0x1111, 0x2222}; 100 v4i8_r = __builtin_mips_precrq_qb_ph(v2q15_a, v2q15_b); 101// CHECK: call <4 x i8> @llvm.mips.precrq.qb.ph 102 103 v2q15_a = (v2q15) {0x7F79, 0xFFFF}; 104 v2q15_b = (v2q15) {0x7F81, 0x2000}; 105 v4i8_r = __builtin_mips_precrqu_s_qb_ph(v2q15_a, v2q15_b); 106// CHECK: call <4 x i8> @llvm.mips.precrqu.s.qb.ph 107 q31_a = 0x12345678; 108 q31_b = 0x11112222; 109 v2q15_r = __builtin_mips_precrq_ph_w(q31_a, q31_b); 110// CHECK: call <2 x i16> @llvm.mips.precrq.ph.w 111 q31_a = 0x7000FFFF; 112 q31_b = 0x80000000; 113 v2q15_r = __builtin_mips_precrq_rs_ph_w(q31_a, q31_b); 114// CHECK: call <2 x i16> @llvm.mips.precrq.rs.ph.w 115 v2q15_a = (v2q15) {0x1234, 0x5678}; 116 q31_r = __builtin_mips_preceq_w_phl(v2q15_a); 117// CHECK: call i32 @llvm.mips.preceq.w.phl 118 q31_r = __builtin_mips_preceq_w_phr(v2q15_a); 119// CHECK: call i32 @llvm.mips.preceq.w.phr 120 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; 121 v2q15_r = __builtin_mips_precequ_ph_qbl(v4i8_a); 122// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbl 123 v2q15_r = __builtin_mips_precequ_ph_qbr(v4i8_a); 124// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbr 125 v2q15_r = __builtin_mips_precequ_ph_qbla(v4i8_a); 126// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbla 127 v2q15_r = __builtin_mips_precequ_ph_qbra(v4i8_a); 128// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbra 129 v2q15_r = __builtin_mips_preceu_ph_qbl(v4i8_a); 130// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbl 131 v2q15_r = __builtin_mips_preceu_ph_qbr(v4i8_a); 132// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbr 133 v2q15_r = __builtin_mips_preceu_ph_qbla(v4i8_a); 134// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbla 135 v2q15_r = __builtin_mips_preceu_ph_qbra(v4i8_a); 136// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbra 137 138 v4i8_a = (v4i8) {1, 2, 3, 4}; 139 v4i8_r = __builtin_mips_shll_qb(v4i8_a, 2); 140// CHECK: call <4 x i8> @llvm.mips.shll.qb 141 v4i8_a = (v4i8) {128, 64, 32, 16}; 142 v4i8_r = __builtin_mips_shrl_qb(v4i8_a, 2); 143// CHECK: call <4 x i8> @llvm.mips.shrl.qb 144 v2q15_a = (v2q15) {0x0001, 0x8000}; 145 v2q15_r = __builtin_mips_shll_ph(v2q15_a, 2); 146// CHECK: call <2 x i16> @llvm.mips.shll.ph 147 v2q15_r = __builtin_mips_shll_s_ph(v2q15_a, 2); 148// CHECK: call <2 x i16> @llvm.mips.shll.s.ph 149 v2q15_a = (v2q15) {0x7FFF, 0x8000}; 150 v2q15_r = __builtin_mips_shra_ph(v2q15_a, 2); 151// CHECK: call <2 x i16> @llvm.mips.shra.ph 152 v2q15_r = __builtin_mips_shra_r_ph(v2q15_a, 2); 153// CHECK: call <2 x i16> @llvm.mips.shra.r.ph 154 q31_a = 0x70000000; 155 q31_r = __builtin_mips_shll_s_w(q31_a, 2); 156// CHECK: call i32 @llvm.mips.shll.s.w 157 q31_a = 0x7FFFFFFF; 158 q31_r = __builtin_mips_shra_r_w(q31_a, 2); 159// CHECK: call i32 @llvm.mips.shra.r.w 160 a64_a = 0x1234567887654321LL; 161 a64_r = __builtin_mips_shilo(a64_a, -8); 162// CHECK: call i64 @llvm.mips.shilo 163 164 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7}; 165 v2q15_b = (v2q15) {0x1234, 0x5678}; 166 v2q15_r = __builtin_mips_muleu_s_ph_qbl(v4i8_a, v2q15_b); 167// CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbl 168 v2q15_r = __builtin_mips_muleu_s_ph_qbr(v4i8_a, v2q15_b); 169// CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbr 170 v2q15_a = (v2q15) {0x7FFF, 0x8000}; 171 v2q15_b = (v2q15) {0x7FFF, 0x8000}; 172 v2q15_r = __builtin_mips_mulq_rs_ph(v2q15_a, v2q15_b); 173// CHECK: call <2 x i16> @llvm.mips.mulq.rs.ph 174 v2q15_a = (v2q15) {0x1234, 0x8000}; 175 v2q15_b = (v2q15) {0x5678, 0x8000}; 176 q31_r = __builtin_mips_muleq_s_w_phl(v2q15_a, v2q15_b); 177// CHECK: call i32 @llvm.mips.muleq.s.w.phl 178 q31_r = __builtin_mips_muleq_s_w_phr(v2q15_a, v2q15_b); 179// CHECK: call i32 @llvm.mips.muleq.s.w.phr 180 a64_a = 0; 181 v2q15_a = (v2q15) {0x0001, 0x8000}; 182 v2q15_b = (v2q15) {0x0002, 0x8000}; 183 a64_r = __builtin_mips_mulsaq_s_w_ph(a64_a, v2q15_b, v2q15_c); 184// CHECK: call i64 @llvm.mips.mulsaq.s.w.ph 185 a64_a = 0; 186 v2q15_b = (v2q15) {0x0001, 0x8000}; 187 v2q15_c = (v2q15) {0x0002, 0x8000}; 188 a64_r = __builtin_mips_maq_s_w_phl(a64_a, v2q15_b, v2q15_c); 189// CHECK: call i64 @llvm.mips.maq.s.w.phl 190 a64_r = __builtin_mips_maq_s_w_phr(a64_a, v2q15_b, v2q15_c); 191// CHECK: call i64 @llvm.mips.maq.s.w.phr 192 a64_a = 0x7FFFFFF0; 193 a64_r = __builtin_mips_maq_sa_w_phl(a64_a, v2q15_b, v2q15_c); 194// CHECK: call i64 @llvm.mips.maq.sa.w.phl 195 a64_r = __builtin_mips_maq_sa_w_phr(a64_a, v2q15_b, v2q15_c); 196// CHECK: call i64 @llvm.mips.maq.sa.w.phr 197 i32_a = 0x80000000; 198 i32_b = 0x11112222; 199 a64_r = __builtin_mips_mult(i32_a, i32_b); 200// CHECK: call i64 @llvm.mips.mult 201 ui32_a = 0x80000000; 202 ui32_b = 0x11112222; 203 a64_r = __builtin_mips_multu(ui32_a, ui32_b); 204// CHECK: call i64 @llvm.mips.multu 205 206 a64_a = 0; 207 v4i8_b = (v4i8) {1, 2, 3, 4}; 208 v4i8_c = (v4i8) {4, 5, 6, 7}; 209 a64_r = __builtin_mips_dpau_h_qbl(a64_a, v4i8_b, v4i8_c); 210// CHECK: call i64 @llvm.mips.dpau.h.qbl 211 a64_r = __builtin_mips_dpau_h_qbr(a64_a, v4i8_b, v4i8_c); 212// CHECK: call i64 @llvm.mips.dpau.h.qbr 213 a64_r = __builtin_mips_dpsu_h_qbl(a64_a, v4i8_b, v4i8_c); 214// CHECK: call i64 @llvm.mips.dpsu.h.qbl 215 a64_r = __builtin_mips_dpsu_h_qbr(a64_a, v4i8_b, v4i8_c); 216// CHECK: call i64 @llvm.mips.dpsu.h.qbr 217 a64_a = 0; 218 v2q15_b = (v2q15) {0x0001, 0x8000}; 219 v2q15_c = (v2q15) {0x0002, 0x8000}; 220 a64_r = __builtin_mips_dpaq_s_w_ph(a64_a, v2q15_b, v2q15_c); 221// CHECK: call i64 @llvm.mips.dpaq.s.w.ph 222 a64_r = __builtin_mips_dpsq_s_w_ph(a64_a, v2q15_b, v2q15_c); 223// CHECK: call i64 @llvm.mips.dpsq.s.w.ph 224 a64_a = 0; 225 q31_b = 0x80000000; 226 q31_c = 0x80000000; 227 a64_r = __builtin_mips_dpaq_sa_l_w(a64_a, q31_b, q31_c); 228// CHECK: call i64 @llvm.mips.dpaq.sa.l.w 229 a64_r = __builtin_mips_dpsq_sa_l_w(a64_a, q31_b, q31_c); 230// CHECK: call i64 @llvm.mips.dpsq.sa.l.w 231 232 v4i8_a = (v4i8) {1, 4, 10, 8}; 233 v4i8_b = (v4i8) {1, 2, 100, 8}; 234 __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b); 235// CHECK: call void @llvm.mips.cmpu.eq.qb 236 __builtin_mips_cmpu_lt_qb(v4i8_a, v4i8_b); 237// CHECK: call void @llvm.mips.cmpu.lt.qb 238 __builtin_mips_cmpu_le_qb(v4i8_a, v4i8_b); 239// CHECK: call void @llvm.mips.cmpu.le.qb 240 i32_r = __builtin_mips_cmpgu_eq_qb(v4i8_a, v4i8_b); 241// CHECK: call i32 @llvm.mips.cmpgu.eq.qb 242 i32_r = __builtin_mips_cmpgu_lt_qb(v4i8_a, v4i8_b); 243// CHECK: call i32 @llvm.mips.cmpgu.lt.qb 244 i32_r = __builtin_mips_cmpgu_le_qb(v4i8_a, v4i8_b); 245// CHECK: call i32 @llvm.mips.cmpgu.le.qb 246 v2q15_a = (v2q15) {0x1111, 0x1234}; 247 v2q15_b = (v2q15) {0x4444, 0x1234}; 248 __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b); 249// CHECK: call void @llvm.mips.cmp.eq.ph 250 __builtin_mips_cmp_lt_ph(v2q15_a, v2q15_b); 251// CHECK: call void @llvm.mips.cmp.lt.ph 252 __builtin_mips_cmp_le_ph(v2q15_a, v2q15_b); 253// CHECK: call void @llvm.mips.cmp.le.ph 254 255 a64_a = 0xFFFFF81230000000LL; 256 i32_r = __builtin_mips_extr_s_h(a64_a, 4); 257// CHECK: call i32 @llvm.mips.extr.s.h 258 a64_a = 0x8123456712345678LL; 259 i32_r = __builtin_mips_extr_w(a64_a, 31); 260// CHECK: call i32 @llvm.mips.extr.w 261 i32_r = __builtin_mips_extr_rs_w(a64_a, 31); 262// CHECK: call i32 @llvm.mips.extr.rs.w 263 i32_r = __builtin_mips_extr_r_w(a64_a, 31); 264// CHECK: call i32 @llvm.mips.extr.r.w 265 a64_a = 0x1234567887654321LL; 266 i32_r = __builtin_mips_extp(a64_a, 3); 267// CHECK: call i32 @llvm.mips.extp 268 a64_a = 0x123456789ABCDEF0LL; 269 i32_r = __builtin_mips_extpdp(a64_a, 7); 270// CHECK: call i32 @llvm.mips.extpdp 271 272 __builtin_mips_wrdsp(2052, 3); 273// CHECK: call void @llvm.mips.wrdsp 274 i32_r = __builtin_mips_rddsp(3); 275// CHECK: call i32 @llvm.mips.rddsp 276 i32_a = 0xFFFFFFFF; 277 i32_b = 0x12345678; 278 __builtin_mips_wrdsp((16<<7) + 4, 3); 279// CHECK: call void @llvm.mips.wrdsp 280 i32_r = __builtin_mips_insv(i32_a, i32_b); 281// CHECK: call i32 @llvm.mips.insv 282 i32_a = 0x1234; 283 i32_r = __builtin_mips_bitrev(i32_a); 284// CHECK: call i32 @llvm.mips.bitrev 285 v2q15_a = (v2q15) {0x1111, 0x2222}; 286 v2q15_b = (v2q15) {0x3333, 0x4444}; 287 v2q15_r = __builtin_mips_packrl_ph(v2q15_a, v2q15_b); 288// CHECK: call <2 x i16> @llvm.mips.packrl.ph 289 i32_a = 100; 290 v4i8_r = __builtin_mips_repl_qb(i32_a); 291// CHECK: call <4 x i8> @llvm.mips.repl.qb 292 i32_a = 0x1234; 293 v2q15_r = __builtin_mips_repl_ph(i32_a); 294// CHECK: call <2 x i16> @llvm.mips.repl.ph 295 v4i8_a = (v4i8) {1, 4, 10, 8}; 296 v4i8_b = (v4i8) {1, 2, 100, 8}; 297 __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b); 298// CHECK: call void @llvm.mips.cmpu.eq.qb 299 v4i8_r = __builtin_mips_pick_qb(v4i8_a, v4i8_b); 300// CHECK: call <4 x i8> @llvm.mips.pick.qb 301 v2q15_a = (v2q15) {0x1111, 0x1234}; 302 v2q15_b = (v2q15) {0x4444, 0x1234}; 303 __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b); 304// CHECK: call void @llvm.mips.cmp.eq.ph 305 v2q15_r = __builtin_mips_pick_ph(v2q15_a, v2q15_b); 306// CHECK: call <2 x i16> @llvm.mips.pick.ph 307 a64_a = 0x1234567887654321LL; 308 i32_b = 0x11112222; 309 __builtin_mips_wrdsp(0, 1); 310// CHECK: call void @llvm.mips.wrdsp 311 a64_r = __builtin_mips_mthlip(a64_a, i32_b); 312// CHECK: call i64 @llvm.mips.mthlip 313 i32_r = __builtin_mips_bposge32(); 314// CHECK: call i32 @llvm.mips.bposge32 315 char array_a[100]; 316 i32_r = __builtin_mips_lbux(array_a, 20); 317// CHECK: call i32 @llvm.mips.lbux 318 short array_b[100]; 319 i32_r = __builtin_mips_lhx(array_b, 20); 320// CHECK: call i32 @llvm.mips.lhx 321 int array_c[100]; 322 i32_r = __builtin_mips_lwx(array_c, 20); 323// CHECK: call i32 @llvm.mips.lwx 324} 325