112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Copyright 2014 Advanced Micro Devices, Inc. 712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Permission is hereby granted, free of charge, to any person obtaining a 912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * copy of this software and associated documentation files (the "Software"), 1012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * to deal in the Software without restriction, including without limitation 1112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * and/or sell copies of the Software, and to permit persons to whom the 1312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Software is furnished to do so, subject to the following conditions: 1412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 1512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * The above copyright notice and this permission notice shall be included in 1612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * all copies or substantial portions of the Software. 1712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 1812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * OTHER DEALINGS IN THE SOFTWARE. 2512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 2612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Authors: 2712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Kevin E. Martin <martin@valinux.com> 2812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Gareth Hughes <gareth@valinux.com> 2912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Keith Whitwell <keith@tungstengraphics.com> 3012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 3112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 3212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#ifndef __AMDGPU_DRM_H__ 3312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define __AMDGPU_DRM_H__ 3412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 3512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#include "drm.h" 3612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 37ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#if defined(__cplusplus) 38ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferrisextern "C" { 39ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#endif 40ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris 4112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_CREATE 0x00 4212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_MMAP 0x01 4312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_CTX 0x02 4412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_BO_LIST 0x03 4512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_CS 0x04 4612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_INFO 0x05 4712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_METADATA 0x06 4812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 4912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_VA 0x08 5012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_WAIT_CS 0x09 5112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_OP 0x10 5212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_USERPTR 0x11 532fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris#define DRM_AMDGPU_WAIT_FENCES 0x12 5412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 5512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 5612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 5712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 5812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 5912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 6012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 6112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 6212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 6312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 6412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 6512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 6612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 672fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 6812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 6912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_CPU 0x1 7012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_GTT 0x2 7112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_VRAM 0x4 7212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_GDS 0x8 7312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_GWS 0x10 7412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_OA 0x20 7512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 7612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Flag that CPU access will be required for the case of VRAM domain */ 7712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 7812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Flag that CPU access will not work, this VRAM domain is invisible */ 7912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 8012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Flag that USWC attributes should be used for GTT */ 8112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 823318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris/* Flag that the memory should be in VRAM and cleared */ 833318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 843318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris/* Flag that create shadow bo(GTT) while allocating vram bo */ 853318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 862fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris/* Flag that allocating the BO should use linear VRAM */ 872fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 8812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 8912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_create_in { 9012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** the requested memory size */ 91ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 bo_size; 9212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** physical start_addr alignment in bytes for some HW requirements */ 93ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 alignment; 9412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** the requested memory domains */ 95ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 domains; 9612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** allocation flags */ 97ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 domain_flags; 9812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 9912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 10012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_create_out { 10112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** returned GEM object handle */ 102ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 103ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 10412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 10512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 10612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_gem_create { 10712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_create_in in; 10812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_create_out out; 10912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 11012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 11112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** Opcode to create new residency list. */ 11212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_BO_LIST_OP_CREATE 0 11312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** Opcode to destroy previously created residency list */ 11412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_BO_LIST_OP_DESTROY 1 11512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** Opcode to update resource information in the list */ 11612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_BO_LIST_OP_UPDATE 2 11712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 11812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_bo_list_in { 11912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Type of operation */ 120ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 operation; 12112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Handle of list or 0 if we want to create one */ 122ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 list_handle; 12312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Number of BOs in list */ 124ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 bo_number; 12512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Size of each element describing BO */ 126ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 bo_info_size; 12712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Pointer to array describing BOs */ 128ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 bo_info_ptr; 12912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 13012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 13112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_bo_list_entry { 13212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Handle of BO */ 133ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 bo_handle; 13412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** New (if specified) BO priority to be used during migration */ 135ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 bo_priority; 13612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 13712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 13812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_bo_list_out { 13912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Handle of resource list */ 140ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 list_handle; 141ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 14212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 14312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 14412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_bo_list { 14512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_bo_list_in in; 14612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_bo_list_out out; 14712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 14812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 14912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* context related */ 15012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_OP_ALLOC_CTX 1 15112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_OP_FREE_CTX 2 15212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_OP_QUERY_STATE 3 15312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 15412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* GPU reset status */ 15512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_NO_RESET 0 15612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* this the context caused it */ 15712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_GUILTY_RESET 1 15812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* some other context caused it */ 15912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_INNOCENT_RESET 2 16012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* unknown cause */ 16112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_UNKNOWN_RESET 3 16212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 16312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_ctx_in { 16412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_CTX_OP_* */ 165ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 op; 16612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** For future use, no flags defined so far */ 167ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 168ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ctx_id; 169ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 17012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 17112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 17212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_ctx_out { 17312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 174ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ctx_id; 175ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 17612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } alloc; 17712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 17812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 17912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** For future use, no flags defined so far */ 180ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 flags; 18112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Number of resets caused by this context so far. */ 182ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 hangs; 18312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Reset status since the last call of the ioctl. */ 184ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 reset_status; 18512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } state; 18612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 18712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 18812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_ctx { 18912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_ctx_in in; 19012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris union drm_amdgpu_ctx_out out; 19112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 19212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 19312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* 19412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * This is not a reliable API and you should expect it to fail for any 19512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * number of reasons and have fallback path that do not use userptr to 19612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * perform any operation. 19712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 19812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 19912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 20012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 20112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 20212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 20312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_userptr { 204ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 addr; 205ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 size; 20612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* AMDGPU_GEM_USERPTR_* */ 207ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 20812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Resulting GEM handle */ 209ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 21012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 21112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 21212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 21312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 21412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 21512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 21612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 21712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 21812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 21912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 22012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 22112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 22212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 22312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 22412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 22512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 22612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 22712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 22812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 22912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 23012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_SET(field, value) \ 23112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 23212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_GET(value, field) \ 23312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 23412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 23512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 23612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 23712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 23812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** The same structure is shared for input/output */ 23912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_metadata { 24012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GEM Object handle */ 241ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 24212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Do we want get or set metadata */ 243ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 op; 24412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 24512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** For future use, no flags defined so far */ 246ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 flags; 24712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** family specific tiling info */ 248ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 tiling_info; 249ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 data_size_bytes; 250ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 data[64]; 25112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } data; 25212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 25312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 25412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_mmap_in { 25512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** the GEM object handle */ 256ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 257ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 25812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 25912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 26012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_mmap_out { 26112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** mmap offset from the vma offset manager */ 262ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 addr_ptr; 26312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 26412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 26512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_gem_mmap { 26612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_mmap_in in; 26712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_mmap_out out; 26812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 26912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 27012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_wait_idle_in { 27112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GEM object handle */ 272ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 27312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** For future use, no flags defined so far */ 274ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 27512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Absolute timeout to wait */ 276ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 timeout; 27712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 27812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 27912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_wait_idle_out { 28012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** BO status: 0 - BO is idle, 1 - BO is busy */ 281ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 status; 28212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Returned current memory domain */ 283ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 domain; 28412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 28512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 28612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_gem_wait_idle { 28712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_wait_idle_in in; 28812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_wait_idle_out out; 28912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 29012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 29112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_wait_cs_in { 29212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Command submission handle */ 293ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 handle; 29412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Absolute timeout to wait */ 295ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 timeout; 296ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_type; 297ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_instance; 298ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ring; 299ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ctx_id; 30012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 30112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 30212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_wait_cs_out { 30312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** CS status: 0 - CS completed, 1 - CS still busy */ 304ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 status; 30512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 30612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 30712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_wait_cs { 30812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_wait_cs_in in; 30912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_wait_cs_out out; 31012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 31112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 3122fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferrisstruct drm_amdgpu_fence { 3132fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 ctx_id; 3142fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 ip_type; 3152fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 ip_instance; 3162fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 ring; 3172fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u64 seq_no; 3182fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris}; 3192fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 3202fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferrisstruct drm_amdgpu_wait_fences_in { 3212fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris /** This points to uint64_t * which points to fences */ 3222fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u64 fences; 3232fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 fence_count; 3242fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 wait_all; 3252fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u64 timeout_ns; 3262fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris}; 3272fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 3282fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferrisstruct drm_amdgpu_wait_fences_out { 3292fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 status; 3302fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 first_signaled; 3312fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris}; 3322fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 3332fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferrisunion drm_amdgpu_wait_fences { 3342fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris struct drm_amdgpu_wait_fences_in in; 3352fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris struct drm_amdgpu_wait_fences_out out; 3362fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris}; 3372fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 33812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 33912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_OP_SET_PLACEMENT 1 34012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 34112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Sets or returns a value associated with a buffer. */ 34212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_op { 34312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GEM object handle */ 344ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 34512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_GEM_OP_* */ 346ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 op; 34712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Input or return value */ 348ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 value; 34912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 35012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 35112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VA_OP_MAP 1 35212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VA_OP_UNMAP 2 35312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 35412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Delay the page table update till the next CS */ 35512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 35612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 35712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Mapping flags */ 35812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* readable mapping */ 35912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VM_PAGE_READABLE (1 << 1) 36012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* writable mapping */ 36112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 36212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* executable mapping, new for VI */ 36312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 36412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 36512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_va { 36612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GEM object handle */ 367ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 368ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 36912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_VA_OP_* */ 370ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 operation; 37112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_VM_PAGE_* */ 372ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 37312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** va address to assign . Must be correctly aligned.*/ 374ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 va_address; 37512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 376ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 offset_in_bo; 37712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Specify mapping size. Must be correctly aligned. */ 378ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 map_size; 37912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 38012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 38112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_GFX 0 38212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_COMPUTE 1 38312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_DMA 2 38412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_UVD 3 38512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_VCE 4 38612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_NUM 5 38712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 38812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 38912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 39012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CHUNK_ID_IB 0x01 39112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CHUNK_ID_FENCE 0x02 39212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 39312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 39412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_chunk { 395ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 chunk_id; 396ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 length_dw; 397ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 chunk_data; 39812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 39912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 40012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_in { 40112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Rendering context id */ 402ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ctx_id; 40312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Handle of resource list associated with CS */ 404ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 bo_list_handle; 405ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 num_chunks; 406ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 407ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris /** this points to __u64 * which point to cs chunks */ 408ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 chunks; 40912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 41012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 41112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_out { 412ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 handle; 41312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 41412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 41512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_cs { 41612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_cs_in in; 41712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_cs_out out; 41812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 41912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 42012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Specify flags to be used for IB */ 42112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 42212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* This IB should be submitted to CE */ 42312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_IB_FLAG_CE (1<<0) 42412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 42512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* CE Preamble */ 42612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 42712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 42812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_chunk_ib { 429ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 43012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_IB_FLAG_* */ 431ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 43212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Virtual address to begin IB execution */ 433ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 va_start; 43412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Size of submission */ 435ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ib_bytes; 43612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** HW IP to submit to */ 437ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_type; 43812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** HW IP index of the same type to submit to */ 439ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_instance; 44012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Ring index to submit to */ 441ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ring; 44212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 44312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 44412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_chunk_dep { 445ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_type; 446ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_instance; 447ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ring; 448ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ctx_id; 449ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 handle; 45012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 45112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 45212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_chunk_fence { 453ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 454ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 offset; 45512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 45612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 45712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_chunk_data { 45812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris union { 45912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_cs_chunk_ib ib_data; 46012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_cs_chunk_fence fence_data; 46112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris }; 46212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 46312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 46412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** 46512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 46612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 46712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 46812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_IDS_FLAGS_FUSION 0x1 4692fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 47012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 47112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* indicate if acceleration can be working */ 47212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_ACCEL_WORKING 0x00 47312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* get the crtc_id from the mode object id? */ 47412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_CRTC_FROM_ID 0x01 47512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* query hw IP info */ 47612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_HW_IP_INFO 0x02 47712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* query hw IP instance count for the specified type */ 47812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_HW_IP_COUNT 0x03 47912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* timestamp for GL_ARB_timer_query */ 48012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_TIMESTAMP 0x05 48112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Query the firmware version */ 48212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_FW_VERSION 0x0e 48312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query VCE firmware version */ 48412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_VCE 0x1 48512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query UVD firmware version */ 48612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_UVD 0x2 48712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GMC firmware version */ 48812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GMC 0x03 48912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GFX ME firmware version */ 49012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GFX_ME 0x04 49112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GFX PFP firmware version */ 49212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GFX_PFP 0x05 49312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GFX CE firmware version */ 49412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GFX_CE 0x06 49512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GFX RLC firmware version */ 49612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GFX_RLC 0x07 49712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GFX MEC firmware version */ 49812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GFX_MEC 0x08 49912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query SMC firmware version */ 50012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_SMC 0x0a 50112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query SDMA firmware version */ 50212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_SDMA 0x0b 50312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* number of bytes moved for TTM migration */ 50412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 50512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* the used VRAM size */ 50612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_VRAM_USAGE 0x10 50712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* the used GTT size */ 50812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_GTT_USAGE 0x11 50912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Information about GDS, etc. resource configuration */ 51012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_GDS_CONFIG 0x13 51112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Query information about VRAM and GTT domains */ 51212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_VRAM_GTT 0x14 51312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Query information about register in MMR address space*/ 51412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_READ_MMR_REG 0x15 51512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Query information about device: rev id, family, etc. */ 51612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_DEV_INFO 0x16 51712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* visible vram usage */ 51812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 5193318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris/* number of TTM buffer evictions */ 5203318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define AMDGPU_INFO_NUM_EVICTIONS 0x18 5212fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris/* Query memory about VRAM and GTT domains */ 5222fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris#define AMDGPU_INFO_MEMORY 0x19 5232fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris/* Query vce clock table */ 5242fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 5252fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris/* Query vbios related information */ 5262fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris#define AMDGPU_INFO_VBIOS 0x1B 5272fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris /* Subquery id: Query vbios size */ 5282fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris #define AMDGPU_INFO_VBIOS_SIZE 0x1 5292fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris /* Subquery id: Query vbios image */ 5302fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris #define AMDGPU_INFO_VBIOS_IMAGE 0x2 53112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 53212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 53312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 53412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 53512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 53612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 5376e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferrisstruct drm_amdgpu_query_fw { 5386e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris /** AMDGPU_INFO_FW_* */ 5396e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris __u32 fw_type; 5406e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris /** 5416e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris * Index of the IP if there are more IPs of 5426e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris * the same type. 5436e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris */ 5446e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris __u32 ip_instance; 5456e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris /** 5466e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris * Index of the engine. Whether this is used depends 5476e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris * on the firmware type. (e.g. MEC, SDMA) 5486e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris */ 5496e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris __u32 index; 5506e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris __u32 _pad; 5516e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris}; 5526e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris 55312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Input structure for the INFO ioctl */ 55412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info { 55512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Where the return value will be stored */ 556ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 return_pointer; 55712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* The size of the return value. Just like "size" in "snprintf", 55812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * it limits how many bytes the kernel can write. */ 559ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 return_size; 56012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* The query request id. */ 561ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 query; 56212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 56312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris union { 56412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 565ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 id; 566ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 56712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } mode_crtc; 56812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 56912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 57012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_HW_IP_* */ 571ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 type; 57212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** 57312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Index of the IP if there are more IPs of the same 57412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 57512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 576ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_instance; 57712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } query_hw_ip; 57812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 57912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 580ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 dword_offset; 58112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** number of registers to read */ 582ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 count; 583ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 instance; 58412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** For future use, no flags defined so far */ 585ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 58612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } read_mmr_reg; 58712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 5886e3550f2a1c3909fb75be068f7ae9009f7e8622aChristopher Ferris struct drm_amdgpu_query_fw query_fw; 5892fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 5902fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris struct { 5912fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 type; 5922fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 offset; 5932fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris } vbios_info; 59412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris }; 59512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 59612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 59712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info_gds { 59812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GDS GFX partition size */ 599ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gds_gfx_partition_size; 60012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GDS compute partition size */ 601ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 compute_partition_size; 60212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** total GDS memory size */ 603ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gds_total_size; 60412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GWS size per GFX partition */ 605ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gws_per_gfx_partition; 60612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GSW size per compute partition */ 607ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gws_per_compute_partition; 60812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** OA size per GFX partition */ 609ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 oa_per_gfx_partition; 61012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** OA size per compute partition */ 611ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 oa_per_compute_partition; 612ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 61312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 61412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 61512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info_vram_gtt { 616ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 vram_size; 617ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 vram_cpu_accessible_size; 618ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 gtt_size; 61912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 62012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 6212fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferrisstruct drm_amdgpu_heap_info { 6222fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris /** max. physical memory */ 6232fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u64 total_heap_size; 6242fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 6252fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris /** Theoretical max. available memory in the given heap */ 6262fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u64 usable_heap_size; 6272fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 6282fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris /** 6292fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris * Number of bytes allocated in the heap. This includes all processes 6302fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris * and private allocations in the kernel. It changes when new buffers 6312fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris * are allocated, freed, and moved. It cannot be larger than 6322fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris * heap_size. 6332fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris */ 6342fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u64 heap_usage; 6352fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 6362fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris /** 6372fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris * Theoretical possible max. size of buffer which 6382fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris * could be allocated in the given heap 6392fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris */ 6402fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u64 max_allocation; 6412fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris}; 6422fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 6432fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferrisstruct drm_amdgpu_memory_info { 6442fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris struct drm_amdgpu_heap_info vram; 6452fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris struct drm_amdgpu_heap_info cpu_accessible_vram; 6462fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris struct drm_amdgpu_heap_info gtt; 6472fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris}; 6482fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 64912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info_firmware { 650ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ver; 651ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 feature; 65212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 65312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 65412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_UNKNOWN 0 65512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_GDDR1 1 65612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_DDR2 2 65712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_GDDR3 3 65812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_GDDR4 4 65912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_GDDR5 5 66012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_HBM 6 66112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_DDR3 7 66212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 66312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info_device { 66412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** PCI Device ID */ 665ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 device_id; 66612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Internal chip revision: A0, A1, etc.) */ 667ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 chip_rev; 668ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 external_rev; 66912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Revision id in PCI Config space */ 670ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 pci_rev; 671ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 family; 672ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 num_shader_engines; 673ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 num_shader_arrays_per_engine; 67412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* in KHz */ 675ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gpu_counter_freq; 676ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 max_engine_clock; 677ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 max_memory_clock; 67812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* cu information */ 679ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 cu_active_number; 680ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 cu_ao_mask; 681ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 cu_bitmap[4][4]; 68212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Render backend pipe mask. One render backend is CB+DB. */ 683ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 enabled_rb_pipes_mask; 684ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 num_rb_pipes; 685ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 num_hw_gfx_contexts; 686ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 687ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 ids_flags; 68812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Starting virtual address for UMDs. */ 689ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 virtual_address_offset; 69012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** The maximum virtual address */ 691ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 virtual_address_max; 69212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Required alignment of virtual addresses. */ 693ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 virtual_address_alignment; 69412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Page table entry - fragment size */ 695ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 pte_fragment_size; 696ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gart_page_size; 69712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** constant engine ram size*/ 698ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ce_ram_size; 69912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** video memory type info*/ 700ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 vram_type; 70112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** video memory bit width*/ 702ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 vram_bit_width; 70312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* vce harvesting instance */ 704ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 vce_harvest_config; 70512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 70612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 70712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info_hw_ip { 70812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Version of h/w IP */ 709ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 hw_ip_version_major; 710ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 hw_ip_version_minor; 71112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Capabilities */ 712ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 capabilities_flags; 71312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** command buffer address start alignment*/ 714ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ib_start_alignment; 71512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** command buffer size alignment*/ 716ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ib_size_alignment; 71712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 718ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 available_rings; 719ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 72012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 72112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 7222fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 7232fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 7242fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferrisstruct drm_amdgpu_info_vce_clock_table_entry { 7252fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris /** System clock */ 7262fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 sclk; 7272fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris /** Memory clock */ 7282fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 mclk; 7292fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris /** VCE clock */ 7302fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 eclk; 7312fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 pad; 7322fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris}; 7332fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 7342fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferrisstruct drm_amdgpu_info_vce_clock_table { 7352fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 7362fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 num_valid_entries; 7372fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris __u32 pad; 7382fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris}; 7392fd4b3cf888b560db61afa9e50dd42039e07a8b2Christopher Ferris 74012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* 74112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Supported GPU families 74212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 74312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_FAMILY_UNKNOWN 0 7443318540b58f2d22ddaf211f3c8887785372e4e28Christopher Ferris#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 74512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 74612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 74712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 74812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 74912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 750ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#if defined(__cplusplus) 751ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris} 752ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#endif 753ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris 75412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#endif 755