amdgpu_drm.h revision ccfaccd726a369b7df72e251710755233d176e5a
112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Copyright 2014 Advanced Micro Devices, Inc. 712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Permission is hereby granted, free of charge, to any person obtaining a 912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * copy of this software and associated documentation files (the "Software"), 1012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * to deal in the Software without restriction, including without limitation 1112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * and/or sell copies of the Software, and to permit persons to whom the 1312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Software is furnished to do so, subject to the following conditions: 1412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 1512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * The above copyright notice and this permission notice shall be included in 1612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * all copies or substantial portions of the Software. 1712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 1812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * OTHER DEALINGS IN THE SOFTWARE. 2512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 2612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Authors: 2712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Kevin E. Martin <martin@valinux.com> 2812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Gareth Hughes <gareth@valinux.com> 2912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Keith Whitwell <keith@tungstengraphics.com> 3012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 3112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 3212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#ifndef __AMDGPU_DRM_H__ 3312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define __AMDGPU_DRM_H__ 3412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 3512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#include "drm.h" 3612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 37ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#if defined(__cplusplus) 38ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferrisextern "C" { 39ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#endif 40ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris 4112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_CREATE 0x00 4212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_MMAP 0x01 4312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_CTX 0x02 4412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_BO_LIST 0x03 4512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_CS 0x04 4612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_INFO 0x05 4712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_METADATA 0x06 4812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 4912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_VA 0x08 5012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_WAIT_CS 0x09 5112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_OP 0x10 5212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_AMDGPU_GEM_USERPTR 0x11 5312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 5412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 5512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 5612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 5712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 5812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 5912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 6012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 6112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 6212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 6312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 6412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 6512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 6612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 6712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_CPU 0x1 6812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_GTT 0x2 6912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_VRAM 0x4 7012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_GDS 0x8 7112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_GWS 0x10 7212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_DOMAIN_OA 0x20 7312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 7412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Flag that CPU access will be required for the case of VRAM domain */ 7512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 7612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Flag that CPU access will not work, this VRAM domain is invisible */ 7712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 7812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Flag that USWC attributes should be used for GTT */ 7912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 8012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 8112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_create_in { 8212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** the requested memory size */ 83ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 bo_size; 8412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** physical start_addr alignment in bytes for some HW requirements */ 85ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 alignment; 8612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** the requested memory domains */ 87ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 domains; 8812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** allocation flags */ 89ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 domain_flags; 9012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 9112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 9212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_create_out { 9312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** returned GEM object handle */ 94ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 95ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 9612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 9712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 9812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_gem_create { 9912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_create_in in; 10012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_create_out out; 10112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 10212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 10312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** Opcode to create new residency list. */ 10412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_BO_LIST_OP_CREATE 0 10512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** Opcode to destroy previously created residency list */ 10612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_BO_LIST_OP_DESTROY 1 10712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** Opcode to update resource information in the list */ 10812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_BO_LIST_OP_UPDATE 2 10912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 11012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_bo_list_in { 11112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Type of operation */ 112ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 operation; 11312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Handle of list or 0 if we want to create one */ 114ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 list_handle; 11512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Number of BOs in list */ 116ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 bo_number; 11712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Size of each element describing BO */ 118ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 bo_info_size; 11912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Pointer to array describing BOs */ 120ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 bo_info_ptr; 12112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 12212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 12312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_bo_list_entry { 12412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Handle of BO */ 125ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 bo_handle; 12612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** New (if specified) BO priority to be used during migration */ 127ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 bo_priority; 12812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 12912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 13012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_bo_list_out { 13112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Handle of resource list */ 132ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 list_handle; 133ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 13412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 13512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 13612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_bo_list { 13712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_bo_list_in in; 13812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_bo_list_out out; 13912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 14012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 14112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* context related */ 14212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_OP_ALLOC_CTX 1 14312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_OP_FREE_CTX 2 14412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_OP_QUERY_STATE 3 14512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 14612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* GPU reset status */ 14712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_NO_RESET 0 14812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* this the context caused it */ 14912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_GUILTY_RESET 1 15012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* some other context caused it */ 15112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_INNOCENT_RESET 2 15212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* unknown cause */ 15312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CTX_UNKNOWN_RESET 3 15412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 15512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_ctx_in { 15612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_CTX_OP_* */ 157ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 op; 15812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** For future use, no flags defined so far */ 159ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 160ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ctx_id; 161ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 16212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 16312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 16412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_ctx_out { 16512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 166ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ctx_id; 167ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 16812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } alloc; 16912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 17012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 17112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** For future use, no flags defined so far */ 172ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 flags; 17312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Number of resets caused by this context so far. */ 174ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 hangs; 17512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Reset status since the last call of the ioctl. */ 176ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 reset_status; 17712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } state; 17812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 17912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 18012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_ctx { 18112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_ctx_in in; 18212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris union drm_amdgpu_ctx_out out; 18312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 18412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 18512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* 18612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * This is not a reliable API and you should expect it to fail for any 18712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * number of reasons and have fallback path that do not use userptr to 18812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * perform any operation. 18912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 19012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 19112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 19212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 19312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 19412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 19512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_userptr { 196ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 addr; 197ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 size; 19812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* AMDGPU_GEM_USERPTR_* */ 199ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 20012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Resulting GEM handle */ 201ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 20212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 20312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 20412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 20512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 20612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 20712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 20812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 20912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 21012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 21112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 21212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 21312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 21412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 21512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 21612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 21712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 21812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 21912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 22012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 22112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 22212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_SET(field, value) \ 22312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 22412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_TILING_GET(value, field) \ 22512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 22612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 22712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 22812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 22912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 23012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** The same structure is shared for input/output */ 23112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_metadata { 23212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GEM Object handle */ 233ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 23412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Do we want get or set metadata */ 235ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 op; 23612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 23712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** For future use, no flags defined so far */ 238ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 flags; 23912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** family specific tiling info */ 240ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 tiling_info; 241ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 data_size_bytes; 242ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 data[64]; 24312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } data; 24412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 24512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 24612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_mmap_in { 24712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** the GEM object handle */ 248ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 249ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 25012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 25112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 25212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_mmap_out { 25312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** mmap offset from the vma offset manager */ 254ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 addr_ptr; 25512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 25612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 25712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_gem_mmap { 25812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_mmap_in in; 25912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_mmap_out out; 26012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 26112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 26212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_wait_idle_in { 26312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GEM object handle */ 264ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 26512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** For future use, no flags defined so far */ 266ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 26712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Absolute timeout to wait */ 268ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 timeout; 26912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 27012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 27112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_wait_idle_out { 27212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** BO status: 0 - BO is idle, 1 - BO is busy */ 273ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 status; 27412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Returned current memory domain */ 275ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 domain; 27612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 27712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 27812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_gem_wait_idle { 27912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_wait_idle_in in; 28012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_gem_wait_idle_out out; 28112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 28212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 28312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_wait_cs_in { 28412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Command submission handle */ 285ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 handle; 28612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Absolute timeout to wait */ 287ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 timeout; 288ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_type; 289ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_instance; 290ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ring; 291ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ctx_id; 29212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 29312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 29412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_wait_cs_out { 29512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** CS status: 0 - CS completed, 1 - CS still busy */ 296ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 status; 29712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 29812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 29912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_wait_cs { 30012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_wait_cs_in in; 30112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_wait_cs_out out; 30212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 30312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 30412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 30512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_GEM_OP_SET_PLACEMENT 1 30612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 30712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Sets or returns a value associated with a buffer. */ 30812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_op { 30912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GEM object handle */ 310ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 31112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_GEM_OP_* */ 312ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 op; 31312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Input or return value */ 314ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 value; 31512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 31612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 31712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VA_OP_MAP 1 31812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VA_OP_UNMAP 2 31912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 32012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Delay the page table update till the next CS */ 32112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 32212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 32312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Mapping flags */ 32412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* readable mapping */ 32512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VM_PAGE_READABLE (1 << 1) 32612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* writable mapping */ 32712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 32812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* executable mapping, new for VI */ 32912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 33012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 33112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_gem_va { 33212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GEM object handle */ 333ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 334ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 33512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_VA_OP_* */ 336ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 operation; 33712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_VM_PAGE_* */ 338ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 33912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** va address to assign . Must be correctly aligned.*/ 340ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 va_address; 34112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 342ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 offset_in_bo; 34312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Specify mapping size. Must be correctly aligned. */ 344ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 map_size; 34512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 34612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 34712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_GFX 0 34812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_COMPUTE 1 34912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_DMA 2 35012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_UVD 3 35112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_VCE 4 35212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_NUM 5 35312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 35412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 35512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 35612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CHUNK_ID_IB 0x01 35712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CHUNK_ID_FENCE 0x02 35812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 35912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 36012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_chunk { 361ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 chunk_id; 362ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 length_dw; 363ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 chunk_data; 36412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 36512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 36612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_in { 36712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Rendering context id */ 368ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ctx_id; 36912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Handle of resource list associated with CS */ 370ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 bo_list_handle; 371ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 num_chunks; 372ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 373ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris /** this points to __u64 * which point to cs chunks */ 374ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 chunks; 37512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 37612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 37712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_out { 378ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 handle; 37912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 38012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 38112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisunion drm_amdgpu_cs { 38212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_cs_in in; 38312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_cs_out out; 38412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 38512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 38612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Specify flags to be used for IB */ 38712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 38812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* This IB should be submitted to CE */ 38912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_IB_FLAG_CE (1<<0) 39012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 39112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* CE Preamble */ 39212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 39312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 39412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_chunk_ib { 395ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 39612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_IB_FLAG_* */ 397ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 39812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Virtual address to begin IB execution */ 399ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 va_start; 40012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Size of submission */ 401ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ib_bytes; 40212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** HW IP to submit to */ 403ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_type; 40412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** HW IP index of the same type to submit to */ 405ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_instance; 40612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Ring index to submit to */ 407ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ring; 40812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 40912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 41012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_chunk_dep { 411ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_type; 412ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_instance; 413ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ring; 414ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ctx_id; 415ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 handle; 41612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 41712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 41812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_chunk_fence { 419ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 handle; 420ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 offset; 42112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 42212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 42312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_cs_chunk_data { 42412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris union { 42512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_cs_chunk_ib ib_data; 42612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct drm_amdgpu_cs_chunk_fence fence_data; 42712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris }; 42812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 42912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 43012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/** 43112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 43212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * 43312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 43412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_IDS_FLAGS_FUSION 0x1 43512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 43612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* indicate if acceleration can be working */ 43712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_ACCEL_WORKING 0x00 43812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* get the crtc_id from the mode object id? */ 43912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_CRTC_FROM_ID 0x01 44012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* query hw IP info */ 44112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_HW_IP_INFO 0x02 44212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* query hw IP instance count for the specified type */ 44312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_HW_IP_COUNT 0x03 44412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* timestamp for GL_ARB_timer_query */ 44512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_TIMESTAMP 0x05 44612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Query the firmware version */ 44712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_FW_VERSION 0x0e 44812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query VCE firmware version */ 44912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_VCE 0x1 45012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query UVD firmware version */ 45112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_UVD 0x2 45212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GMC firmware version */ 45312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GMC 0x03 45412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GFX ME firmware version */ 45512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GFX_ME 0x04 45612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GFX PFP firmware version */ 45712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GFX_PFP 0x05 45812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GFX CE firmware version */ 45912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GFX_CE 0x06 46012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GFX RLC firmware version */ 46112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GFX_RLC 0x07 46212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query GFX MEC firmware version */ 46312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_GFX_MEC 0x08 46412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query SMC firmware version */ 46512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_SMC 0x0a 46612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Subquery id: Query SDMA firmware version */ 46712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris #define AMDGPU_INFO_FW_SDMA 0x0b 46812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* number of bytes moved for TTM migration */ 46912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 47012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* the used VRAM size */ 47112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_VRAM_USAGE 0x10 47212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* the used GTT size */ 47312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_GTT_USAGE 0x11 47412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Information about GDS, etc. resource configuration */ 47512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_GDS_CONFIG 0x13 47612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Query information about VRAM and GTT domains */ 47712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_VRAM_GTT 0x14 47812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Query information about register in MMR address space*/ 47912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_READ_MMR_REG 0x15 48012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Query information about device: rev id, family, etc. */ 48112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_DEV_INFO 0x16 48212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* visible vram usage */ 48312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 48412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 48512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 48612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 48712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 48812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 48912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 49012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* Input structure for the INFO ioctl */ 49112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info { 49212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* Where the return value will be stored */ 493ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 return_pointer; 49412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* The size of the return value. Just like "size" in "snprintf", 49512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * it limits how many bytes the kernel can write. */ 496ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 return_size; 49712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* The query request id. */ 498ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 query; 49912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 50012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris union { 50112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 502ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 id; 503ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 50412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } mode_crtc; 50512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 50612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 50712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_HW_IP_* */ 508ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 type; 50912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** 51012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Index of the IP if there are more IPs of the same 51112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 51212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 513ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_instance; 51412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } query_hw_ip; 51512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 51612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 517ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 dword_offset; 51812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** number of registers to read */ 519ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 count; 520ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 instance; 52112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** For future use, no flags defined so far */ 522ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 flags; 52312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } read_mmr_reg; 52412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 52512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris struct { 52612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** AMDGPU_INFO_FW_* */ 527ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 fw_type; 52812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** 52912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Index of the IP if there are more IPs of 53012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * the same type. 53112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 532ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ip_instance; 53312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** 53412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Index of the engine. Whether this is used depends 53512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * on the firmware type. (e.g. MEC, SDMA) 53612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 537ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 index; 538ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 53912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris } query_fw; 54012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris }; 54112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 54212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 54312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info_gds { 54412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GDS GFX partition size */ 545ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gds_gfx_partition_size; 54612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GDS compute partition size */ 547ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 compute_partition_size; 54812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** total GDS memory size */ 549ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gds_total_size; 55012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GWS size per GFX partition */ 551ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gws_per_gfx_partition; 55212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** GSW size per compute partition */ 553ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gws_per_compute_partition; 55412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** OA size per GFX partition */ 555ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 oa_per_gfx_partition; 55612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** OA size per compute partition */ 557ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 oa_per_compute_partition; 558ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 55912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 56012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 56112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info_vram_gtt { 562ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 vram_size; 563ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 vram_cpu_accessible_size; 564ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 gtt_size; 56512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 56612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 56712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info_firmware { 568ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ver; 569ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 feature; 57012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 57112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 57212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_UNKNOWN 0 57312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_GDDR1 1 57412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_DDR2 2 57512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_GDDR3 3 57612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_GDDR4 4 57712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_GDDR5 5 57812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_HBM 6 57912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_VRAM_TYPE_DDR3 7 58012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 58112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info_device { 58212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** PCI Device ID */ 583ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 device_id; 58412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Internal chip revision: A0, A1, etc.) */ 585ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 chip_rev; 586ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 external_rev; 58712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Revision id in PCI Config space */ 588ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 pci_rev; 589ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 family; 590ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 num_shader_engines; 591ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 num_shader_arrays_per_engine; 59212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* in KHz */ 593ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gpu_counter_freq; 594ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 max_engine_clock; 595ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 max_memory_clock; 59612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* cu information */ 597ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 cu_active_number; 598ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 cu_ao_mask; 599ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 cu_bitmap[4][4]; 60012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Render backend pipe mask. One render backend is CB+DB. */ 601ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 enabled_rb_pipes_mask; 602ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 num_rb_pipes; 603ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 num_hw_gfx_contexts; 604ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 605ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 ids_flags; 60612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Starting virtual address for UMDs. */ 607ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 virtual_address_offset; 60812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** The maximum virtual address */ 609ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 virtual_address_max; 61012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Required alignment of virtual addresses. */ 611ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 virtual_address_alignment; 61212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Page table entry - fragment size */ 613ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 pte_fragment_size; 614ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 gart_page_size; 61512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** constant engine ram size*/ 616ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ce_ram_size; 61712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** video memory type info*/ 618ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 vram_type; 61912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** video memory bit width*/ 620ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 vram_bit_width; 62112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /* vce harvesting instance */ 622ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 vce_harvest_config; 62312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 62412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 62512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferrisstruct drm_amdgpu_info_hw_ip { 62612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Version of h/w IP */ 627ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 hw_ip_version_major; 628ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 hw_ip_version_minor; 62912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Capabilities */ 630ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u64 capabilities_flags; 63112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** command buffer address start alignment*/ 632ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ib_start_alignment; 63312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** command buffer size alignment*/ 634ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 ib_size_alignment; 63512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 636ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 available_rings; 637ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris __u32 _pad; 63812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris}; 63912e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 64012e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris/* 64112e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris * Supported GPU families 64212e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris */ 64312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_FAMILY_UNKNOWN 0 64412e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 64512e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 64612e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 64712e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 64812e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris 649ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#if defined(__cplusplus) 650ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris} 651ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris#endif 652ccfaccd726a369b7df72e251710755233d176e5aChristopher Ferris 65312e1f28cce28271eb109a5bae818a804f0c3bb27Christopher Ferris#endif 654