1/* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#ifndef _UAPI_I915_DRM_H_ 28#define _UAPI_I915_DRM_H_ 29 30#include "drm.h" 31 32#if defined(__cplusplus) 33extern "C" { 34#endif 35 36/* Please note that modifications to all structs defined here are 37 * subject to backwards-compatibility constraints. 38 */ 39 40/** 41 * DOC: uevents generated by i915 on it's device node 42 * 43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44 * event from the gpu l3 cache. Additional information supplied is ROW, 45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 46 * track of these events and if a specific cache-line seems to have a 47 * persistent error remap it with the l3 remapping tool supplied in 48 * intel-gpu-tools. The value supplied with the event is always 1. 49 * 50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51 * hangcheck. The error detection event is a good indicator of when things 52 * began to go badly. The value supplied with the event is a 1 upon error 53 * detection, and a 0 upon reset completion, signifying no more error 54 * exists. NOTE: Disabling hangcheck or reset via module parameter will 55 * cause the related events to not be seen. 56 * 57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58 * the GPU. The value supplied with the event is always 1. NOTE: Disable 59 * reset via module parameter will cause this event to not be seen. 60 */ 61#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62#define I915_ERROR_UEVENT "ERROR" 63#define I915_RESET_UEVENT "RESET" 64 65/* 66 * MOCS indexes used for GPU surfaces, defining the cacheability of the 67 * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 68 */ 69enum i915_mocs_table_index { 70 /* 71 * Not cached anywhere, coherency between CPU and GPU accesses is 72 * guaranteed. 73 */ 74 I915_MOCS_UNCACHED, 75 /* 76 * Cacheability and coherency controlled by the kernel automatically 77 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 78 * usage of the surface (used for display scanout or not). 79 */ 80 I915_MOCS_PTE, 81 /* 82 * Cached in all GPU caches available on the platform. 83 * Coherency between CPU and GPU accesses to the surface is not 84 * guaranteed without extra synchronization. 85 */ 86 I915_MOCS_CACHED, 87}; 88 89/* Each region is a minimum of 16k, and there are at most 255 of them. 90 */ 91#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 92 * of chars for next/prev indices */ 93#define I915_LOG_MIN_TEX_REGION_SIZE 14 94 95typedef struct _drm_i915_init { 96 enum { 97 I915_INIT_DMA = 0x01, 98 I915_CLEANUP_DMA = 0x02, 99 I915_RESUME_DMA = 0x03 100 } func; 101 unsigned int mmio_offset; 102 int sarea_priv_offset; 103 unsigned int ring_start; 104 unsigned int ring_end; 105 unsigned int ring_size; 106 unsigned int front_offset; 107 unsigned int back_offset; 108 unsigned int depth_offset; 109 unsigned int w; 110 unsigned int h; 111 unsigned int pitch; 112 unsigned int pitch_bits; 113 unsigned int back_pitch; 114 unsigned int depth_pitch; 115 unsigned int cpp; 116 unsigned int chipset; 117} drm_i915_init_t; 118 119typedef struct _drm_i915_sarea { 120 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 121 int last_upload; /* last time texture was uploaded */ 122 int last_enqueue; /* last time a buffer was enqueued */ 123 int last_dispatch; /* age of the most recently dispatched buffer */ 124 int ctxOwner; /* last context to upload state */ 125 int texAge; 126 int pf_enabled; /* is pageflipping allowed? */ 127 int pf_active; 128 int pf_current_page; /* which buffer is being displayed? */ 129 int perf_boxes; /* performance boxes to be displayed */ 130 int width, height; /* screen size in pixels */ 131 132 drm_handle_t front_handle; 133 int front_offset; 134 int front_size; 135 136 drm_handle_t back_handle; 137 int back_offset; 138 int back_size; 139 140 drm_handle_t depth_handle; 141 int depth_offset; 142 int depth_size; 143 144 drm_handle_t tex_handle; 145 int tex_offset; 146 int tex_size; 147 int log_tex_granularity; 148 int pitch; 149 int rotation; /* 0, 90, 180 or 270 */ 150 int rotated_offset; 151 int rotated_size; 152 int rotated_pitch; 153 int virtualX, virtualY; 154 155 unsigned int front_tiled; 156 unsigned int back_tiled; 157 unsigned int depth_tiled; 158 unsigned int rotated_tiled; 159 unsigned int rotated2_tiled; 160 161 int pipeA_x; 162 int pipeA_y; 163 int pipeA_w; 164 int pipeA_h; 165 int pipeB_x; 166 int pipeB_y; 167 int pipeB_w; 168 int pipeB_h; 169 170 /* fill out some space for old userspace triple buffer */ 171 drm_handle_t unused_handle; 172 __u32 unused1, unused2, unused3; 173 174 /* buffer object handles for static buffers. May change 175 * over the lifetime of the client. 176 */ 177 __u32 front_bo_handle; 178 __u32 back_bo_handle; 179 __u32 unused_bo_handle; 180 __u32 depth_bo_handle; 181 182} drm_i915_sarea_t; 183 184/* due to userspace building against these headers we need some compat here */ 185#define planeA_x pipeA_x 186#define planeA_y pipeA_y 187#define planeA_w pipeA_w 188#define planeA_h pipeA_h 189#define planeB_x pipeB_x 190#define planeB_y pipeB_y 191#define planeB_w pipeB_w 192#define planeB_h pipeB_h 193 194/* Flags for perf_boxes 195 */ 196#define I915_BOX_RING_EMPTY 0x1 197#define I915_BOX_FLIP 0x2 198#define I915_BOX_WAIT 0x4 199#define I915_BOX_TEXTURE_LOAD 0x8 200#define I915_BOX_LOST_CONTEXT 0x10 201 202/* 203 * i915 specific ioctls. 204 * 205 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 206 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 207 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 208 */ 209#define DRM_I915_INIT 0x00 210#define DRM_I915_FLUSH 0x01 211#define DRM_I915_FLIP 0x02 212#define DRM_I915_BATCHBUFFER 0x03 213#define DRM_I915_IRQ_EMIT 0x04 214#define DRM_I915_IRQ_WAIT 0x05 215#define DRM_I915_GETPARAM 0x06 216#define DRM_I915_SETPARAM 0x07 217#define DRM_I915_ALLOC 0x08 218#define DRM_I915_FREE 0x09 219#define DRM_I915_INIT_HEAP 0x0a 220#define DRM_I915_CMDBUFFER 0x0b 221#define DRM_I915_DESTROY_HEAP 0x0c 222#define DRM_I915_SET_VBLANK_PIPE 0x0d 223#define DRM_I915_GET_VBLANK_PIPE 0x0e 224#define DRM_I915_VBLANK_SWAP 0x0f 225#define DRM_I915_HWS_ADDR 0x11 226#define DRM_I915_GEM_INIT 0x13 227#define DRM_I915_GEM_EXECBUFFER 0x14 228#define DRM_I915_GEM_PIN 0x15 229#define DRM_I915_GEM_UNPIN 0x16 230#define DRM_I915_GEM_BUSY 0x17 231#define DRM_I915_GEM_THROTTLE 0x18 232#define DRM_I915_GEM_ENTERVT 0x19 233#define DRM_I915_GEM_LEAVEVT 0x1a 234#define DRM_I915_GEM_CREATE 0x1b 235#define DRM_I915_GEM_PREAD 0x1c 236#define DRM_I915_GEM_PWRITE 0x1d 237#define DRM_I915_GEM_MMAP 0x1e 238#define DRM_I915_GEM_SET_DOMAIN 0x1f 239#define DRM_I915_GEM_SW_FINISH 0x20 240#define DRM_I915_GEM_SET_TILING 0x21 241#define DRM_I915_GEM_GET_TILING 0x22 242#define DRM_I915_GEM_GET_APERTURE 0x23 243#define DRM_I915_GEM_MMAP_GTT 0x24 244#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 245#define DRM_I915_GEM_MADVISE 0x26 246#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 247#define DRM_I915_OVERLAY_ATTRS 0x28 248#define DRM_I915_GEM_EXECBUFFER2 0x29 249#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 250#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 251#define DRM_I915_GEM_WAIT 0x2c 252#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 253#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 254#define DRM_I915_GEM_SET_CACHING 0x2f 255#define DRM_I915_GEM_GET_CACHING 0x30 256#define DRM_I915_REG_READ 0x31 257#define DRM_I915_GET_RESET_STATS 0x32 258#define DRM_I915_GEM_USERPTR 0x33 259#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 260#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 261 262#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 263#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 264#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 265#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 266#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 267#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 268#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 269#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 270#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 271#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 272#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 273#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 274#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 275#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 276#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 277#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 278#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 279#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 280#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 281#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 282#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 283#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 284#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 285#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 286#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 287#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 288#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 289#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 290#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 291#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 292#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 293#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 294#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 295#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 296#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 297#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 298#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 299#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 300#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 301#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 302#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 303#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 304#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 305#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 306#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 307#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 308#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 309#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 310#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 311#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 312#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 313#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 314 315/* Allow drivers to submit batchbuffers directly to hardware, relying 316 * on the security mechanisms provided by hardware. 317 */ 318typedef struct drm_i915_batchbuffer { 319 int start; /* agp offset */ 320 int used; /* nr bytes in use */ 321 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 322 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 323 int num_cliprects; /* mulitpass with multiple cliprects? */ 324 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 325} drm_i915_batchbuffer_t; 326 327/* As above, but pass a pointer to userspace buffer which can be 328 * validated by the kernel prior to sending to hardware. 329 */ 330typedef struct _drm_i915_cmdbuffer { 331 char __user *buf; /* pointer to userspace command buffer */ 332 int sz; /* nr bytes in buf */ 333 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 334 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 335 int num_cliprects; /* mulitpass with multiple cliprects? */ 336 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 337} drm_i915_cmdbuffer_t; 338 339/* Userspace can request & wait on irq's: 340 */ 341typedef struct drm_i915_irq_emit { 342 int __user *irq_seq; 343} drm_i915_irq_emit_t; 344 345typedef struct drm_i915_irq_wait { 346 int irq_seq; 347} drm_i915_irq_wait_t; 348 349/* Ioctl to query kernel params: 350 */ 351#define I915_PARAM_IRQ_ACTIVE 1 352#define I915_PARAM_ALLOW_BATCHBUFFER 2 353#define I915_PARAM_LAST_DISPATCH 3 354#define I915_PARAM_CHIPSET_ID 4 355#define I915_PARAM_HAS_GEM 5 356#define I915_PARAM_NUM_FENCES_AVAIL 6 357#define I915_PARAM_HAS_OVERLAY 7 358#define I915_PARAM_HAS_PAGEFLIPPING 8 359#define I915_PARAM_HAS_EXECBUF2 9 360#define I915_PARAM_HAS_BSD 10 361#define I915_PARAM_HAS_BLT 11 362#define I915_PARAM_HAS_RELAXED_FENCING 12 363#define I915_PARAM_HAS_COHERENT_RINGS 13 364#define I915_PARAM_HAS_EXEC_CONSTANTS 14 365#define I915_PARAM_HAS_RELAXED_DELTA 15 366#define I915_PARAM_HAS_GEN7_SOL_RESET 16 367#define I915_PARAM_HAS_LLC 17 368#define I915_PARAM_HAS_ALIASING_PPGTT 18 369#define I915_PARAM_HAS_WAIT_TIMEOUT 19 370#define I915_PARAM_HAS_SEMAPHORES 20 371#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 372#define I915_PARAM_HAS_VEBOX 22 373#define I915_PARAM_HAS_SECURE_BATCHES 23 374#define I915_PARAM_HAS_PINNED_BATCHES 24 375#define I915_PARAM_HAS_EXEC_NO_RELOC 25 376#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 377#define I915_PARAM_HAS_WT 27 378#define I915_PARAM_CMD_PARSER_VERSION 28 379#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 380#define I915_PARAM_MMAP_VERSION 30 381#define I915_PARAM_HAS_BSD2 31 382#define I915_PARAM_REVISION 32 383#define I915_PARAM_SUBSLICE_TOTAL 33 384#define I915_PARAM_EU_TOTAL 34 385#define I915_PARAM_HAS_GPU_RESET 35 386#define I915_PARAM_HAS_RESOURCE_STREAMER 36 387#define I915_PARAM_HAS_EXEC_SOFTPIN 37 388#define I915_PARAM_HAS_POOLED_EU 38 389#define I915_PARAM_MIN_EU_IN_POOL 39 390#define I915_PARAM_MMAP_GTT_VERSION 40 391 392/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 393 * priorities and the driver will attempt to execute batches in priority order. 394 */ 395#define I915_PARAM_HAS_SCHEDULER 41 396 397typedef struct drm_i915_getparam { 398 __s32 param; 399 /* 400 * WARNING: Using pointers instead of fixed-size u64 means we need to write 401 * compat32 code. Don't repeat this mistake. 402 */ 403 int __user *value; 404} drm_i915_getparam_t; 405 406/* Ioctl to set kernel params: 407 */ 408#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 409#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 410#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 411#define I915_SETPARAM_NUM_USED_FENCES 4 412 413typedef struct drm_i915_setparam { 414 int param; 415 int value; 416} drm_i915_setparam_t; 417 418/* A memory manager for regions of shared memory: 419 */ 420#define I915_MEM_REGION_AGP 1 421 422typedef struct drm_i915_mem_alloc { 423 int region; 424 int alignment; 425 int size; 426 int __user *region_offset; /* offset from start of fb or agp */ 427} drm_i915_mem_alloc_t; 428 429typedef struct drm_i915_mem_free { 430 int region; 431 int region_offset; 432} drm_i915_mem_free_t; 433 434typedef struct drm_i915_mem_init_heap { 435 int region; 436 int size; 437 int start; 438} drm_i915_mem_init_heap_t; 439 440/* Allow memory manager to be torn down and re-initialized (eg on 441 * rotate): 442 */ 443typedef struct drm_i915_mem_destroy_heap { 444 int region; 445} drm_i915_mem_destroy_heap_t; 446 447/* Allow X server to configure which pipes to monitor for vblank signals 448 */ 449#define DRM_I915_VBLANK_PIPE_A 1 450#define DRM_I915_VBLANK_PIPE_B 2 451 452typedef struct drm_i915_vblank_pipe { 453 int pipe; 454} drm_i915_vblank_pipe_t; 455 456/* Schedule buffer swap at given vertical blank: 457 */ 458typedef struct drm_i915_vblank_swap { 459 drm_drawable_t drawable; 460 enum drm_vblank_seq_type seqtype; 461 unsigned int sequence; 462} drm_i915_vblank_swap_t; 463 464typedef struct drm_i915_hws_addr { 465 __u64 addr; 466} drm_i915_hws_addr_t; 467 468struct drm_i915_gem_init { 469 /** 470 * Beginning offset in the GTT to be managed by the DRM memory 471 * manager. 472 */ 473 __u64 gtt_start; 474 /** 475 * Ending offset in the GTT to be managed by the DRM memory 476 * manager. 477 */ 478 __u64 gtt_end; 479}; 480 481struct drm_i915_gem_create { 482 /** 483 * Requested size for the object. 484 * 485 * The (page-aligned) allocated size for the object will be returned. 486 */ 487 __u64 size; 488 /** 489 * Returned handle for the object. 490 * 491 * Object handles are nonzero. 492 */ 493 __u32 handle; 494 __u32 pad; 495}; 496 497struct drm_i915_gem_pread { 498 /** Handle for the object being read. */ 499 __u32 handle; 500 __u32 pad; 501 /** Offset into the object to read from */ 502 __u64 offset; 503 /** Length of data to read */ 504 __u64 size; 505 /** 506 * Pointer to write the data into. 507 * 508 * This is a fixed-size type for 32/64 compatibility. 509 */ 510 __u64 data_ptr; 511}; 512 513struct drm_i915_gem_pwrite { 514 /** Handle for the object being written to. */ 515 __u32 handle; 516 __u32 pad; 517 /** Offset into the object to write to */ 518 __u64 offset; 519 /** Length of data to write */ 520 __u64 size; 521 /** 522 * Pointer to read the data from. 523 * 524 * This is a fixed-size type for 32/64 compatibility. 525 */ 526 __u64 data_ptr; 527}; 528 529struct drm_i915_gem_mmap { 530 /** Handle for the object being mapped. */ 531 __u32 handle; 532 __u32 pad; 533 /** Offset in the object to map. */ 534 __u64 offset; 535 /** 536 * Length of data to map. 537 * 538 * The value will be page-aligned. 539 */ 540 __u64 size; 541 /** 542 * Returned pointer the data was mapped at. 543 * 544 * This is a fixed-size type for 32/64 compatibility. 545 */ 546 __u64 addr_ptr; 547 548 /** 549 * Flags for extended behaviour. 550 * 551 * Added in version 2. 552 */ 553 __u64 flags; 554#define I915_MMAP_WC 0x1 555}; 556 557struct drm_i915_gem_mmap_gtt { 558 /** Handle for the object being mapped. */ 559 __u32 handle; 560 __u32 pad; 561 /** 562 * Fake offset to use for subsequent mmap call 563 * 564 * This is a fixed-size type for 32/64 compatibility. 565 */ 566 __u64 offset; 567}; 568 569struct drm_i915_gem_set_domain { 570 /** Handle for the object */ 571 __u32 handle; 572 573 /** New read domains */ 574 __u32 read_domains; 575 576 /** New write domain */ 577 __u32 write_domain; 578}; 579 580struct drm_i915_gem_sw_finish { 581 /** Handle for the object */ 582 __u32 handle; 583}; 584 585struct drm_i915_gem_relocation_entry { 586 /** 587 * Handle of the buffer being pointed to by this relocation entry. 588 * 589 * It's appealing to make this be an index into the mm_validate_entry 590 * list to refer to the buffer, but this allows the driver to create 591 * a relocation list for state buffers and not re-write it per 592 * exec using the buffer. 593 */ 594 __u32 target_handle; 595 596 /** 597 * Value to be added to the offset of the target buffer to make up 598 * the relocation entry. 599 */ 600 __u32 delta; 601 602 /** Offset in the buffer the relocation entry will be written into */ 603 __u64 offset; 604 605 /** 606 * Offset value of the target buffer that the relocation entry was last 607 * written as. 608 * 609 * If the buffer has the same offset as last time, we can skip syncing 610 * and writing the relocation. This value is written back out by 611 * the execbuffer ioctl when the relocation is written. 612 */ 613 __u64 presumed_offset; 614 615 /** 616 * Target memory domains read by this operation. 617 */ 618 __u32 read_domains; 619 620 /** 621 * Target memory domains written by this operation. 622 * 623 * Note that only one domain may be written by the whole 624 * execbuffer operation, so that where there are conflicts, 625 * the application will get -EINVAL back. 626 */ 627 __u32 write_domain; 628}; 629 630/** @{ 631 * Intel memory domains 632 * 633 * Most of these just align with the various caches in 634 * the system and are used to flush and invalidate as 635 * objects end up cached in different domains. 636 */ 637/** CPU cache */ 638#define I915_GEM_DOMAIN_CPU 0x00000001 639/** Render cache, used by 2D and 3D drawing */ 640#define I915_GEM_DOMAIN_RENDER 0x00000002 641/** Sampler cache, used by texture engine */ 642#define I915_GEM_DOMAIN_SAMPLER 0x00000004 643/** Command queue, used to load batch buffers */ 644#define I915_GEM_DOMAIN_COMMAND 0x00000008 645/** Instruction cache, used by shader programs */ 646#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 647/** Vertex address cache */ 648#define I915_GEM_DOMAIN_VERTEX 0x00000020 649/** GTT domain - aperture and scanout */ 650#define I915_GEM_DOMAIN_GTT 0x00000040 651/** @} */ 652 653struct drm_i915_gem_exec_object { 654 /** 655 * User's handle for a buffer to be bound into the GTT for this 656 * operation. 657 */ 658 __u32 handle; 659 660 /** Number of relocations to be performed on this buffer */ 661 __u32 relocation_count; 662 /** 663 * Pointer to array of struct drm_i915_gem_relocation_entry containing 664 * the relocations to be performed in this buffer. 665 */ 666 __u64 relocs_ptr; 667 668 /** Required alignment in graphics aperture */ 669 __u64 alignment; 670 671 /** 672 * Returned value of the updated offset of the object, for future 673 * presumed_offset writes. 674 */ 675 __u64 offset; 676}; 677 678struct drm_i915_gem_execbuffer { 679 /** 680 * List of buffers to be validated with their relocations to be 681 * performend on them. 682 * 683 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 684 * 685 * These buffers must be listed in an order such that all relocations 686 * a buffer is performing refer to buffers that have already appeared 687 * in the validate list. 688 */ 689 __u64 buffers_ptr; 690 __u32 buffer_count; 691 692 /** Offset in the batchbuffer to start execution from. */ 693 __u32 batch_start_offset; 694 /** Bytes used in batchbuffer from batch_start_offset */ 695 __u32 batch_len; 696 __u32 DR1; 697 __u32 DR4; 698 __u32 num_cliprects; 699 /** This is a struct drm_clip_rect *cliprects */ 700 __u64 cliprects_ptr; 701}; 702 703struct drm_i915_gem_exec_object2 { 704 /** 705 * User's handle for a buffer to be bound into the GTT for this 706 * operation. 707 */ 708 __u32 handle; 709 710 /** Number of relocations to be performed on this buffer */ 711 __u32 relocation_count; 712 /** 713 * Pointer to array of struct drm_i915_gem_relocation_entry containing 714 * the relocations to be performed in this buffer. 715 */ 716 __u64 relocs_ptr; 717 718 /** Required alignment in graphics aperture */ 719 __u64 alignment; 720 721 /** 722 * When the EXEC_OBJECT_PINNED flag is specified this is populated by 723 * the user with the GTT offset at which this object will be pinned. 724 * When the I915_EXEC_NO_RELOC flag is specified this must contain the 725 * presumed_offset of the object. 726 * During execbuffer2 the kernel populates it with the value of the 727 * current GTT offset of the object, for future presumed_offset writes. 728 */ 729 __u64 offset; 730 731#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 732#define EXEC_OBJECT_NEEDS_GTT (1<<1) 733#define EXEC_OBJECT_WRITE (1<<2) 734#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 735#define EXEC_OBJECT_PINNED (1<<4) 736#define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 737/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 738#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PAD_TO_SIZE<<1) 739 __u64 flags; 740 741 union { 742 __u64 rsvd1; 743 __u64 pad_to_size; 744 }; 745 __u64 rsvd2; 746}; 747 748struct drm_i915_gem_execbuffer2 { 749 /** 750 * List of gem_exec_object2 structs 751 */ 752 __u64 buffers_ptr; 753 __u32 buffer_count; 754 755 /** Offset in the batchbuffer to start execution from. */ 756 __u32 batch_start_offset; 757 /** Bytes used in batchbuffer from batch_start_offset */ 758 __u32 batch_len; 759 __u32 DR1; 760 __u32 DR4; 761 __u32 num_cliprects; 762 /** This is a struct drm_clip_rect *cliprects */ 763 __u64 cliprects_ptr; 764#define I915_EXEC_RING_MASK (7<<0) 765#define I915_EXEC_DEFAULT (0<<0) 766#define I915_EXEC_RENDER (1<<0) 767#define I915_EXEC_BSD (2<<0) 768#define I915_EXEC_BLT (3<<0) 769#define I915_EXEC_VEBOX (4<<0) 770 771/* Used for switching the constants addressing mode on gen4+ RENDER ring. 772 * Gen6+ only supports relative addressing to dynamic state (default) and 773 * absolute addressing. 774 * 775 * These flags are ignored for the BSD and BLT rings. 776 */ 777#define I915_EXEC_CONSTANTS_MASK (3<<6) 778#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 779#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 780#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 781 __u64 flags; 782 __u64 rsvd1; /* now used for context info */ 783 __u64 rsvd2; 784}; 785 786/** Resets the SO write offset registers for transform feedback on gen7. */ 787#define I915_EXEC_GEN7_SOL_RESET (1<<8) 788 789/** Request a privileged ("secure") batch buffer. Note only available for 790 * DRM_ROOT_ONLY | DRM_MASTER processes. 791 */ 792#define I915_EXEC_SECURE (1<<9) 793 794/** Inform the kernel that the batch is and will always be pinned. This 795 * negates the requirement for a workaround to be performed to avoid 796 * an incoherent CS (such as can be found on 830/845). If this flag is 797 * not passed, the kernel will endeavour to make sure the batch is 798 * coherent with the CS before execution. If this flag is passed, 799 * userspace assumes the responsibility for ensuring the same. 800 */ 801#define I915_EXEC_IS_PINNED (1<<10) 802 803/** Provide a hint to the kernel that the command stream and auxiliary 804 * state buffers already holds the correct presumed addresses and so the 805 * relocation process may be skipped if no buffers need to be moved in 806 * preparation for the execbuffer. 807 */ 808#define I915_EXEC_NO_RELOC (1<<11) 809 810/** Use the reloc.handle as an index into the exec object array rather 811 * than as the per-file handle. 812 */ 813#define I915_EXEC_HANDLE_LUT (1<<12) 814 815/** Used for switching BSD rings on the platforms with two BSD rings */ 816#define I915_EXEC_BSD_SHIFT (13) 817#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 818/* default ping-pong mode */ 819#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 820#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 821#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 822 823/** Tell the kernel that the batchbuffer is processed by 824 * the resource streamer. 825 */ 826#define I915_EXEC_RESOURCE_STREAMER (1<<15) 827 828#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) 829 830#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 831#define i915_execbuffer2_set_context_id(eb2, context) \ 832 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 833#define i915_execbuffer2_get_context_id(eb2) \ 834 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 835 836struct drm_i915_gem_pin { 837 /** Handle of the buffer to be pinned. */ 838 __u32 handle; 839 __u32 pad; 840 841 /** alignment required within the aperture */ 842 __u64 alignment; 843 844 /** Returned GTT offset of the buffer. */ 845 __u64 offset; 846}; 847 848struct drm_i915_gem_unpin { 849 /** Handle of the buffer to be unpinned. */ 850 __u32 handle; 851 __u32 pad; 852}; 853 854struct drm_i915_gem_busy { 855 /** Handle of the buffer to check for busy */ 856 __u32 handle; 857 858 /** Return busy status 859 * 860 * A return of 0 implies that the object is idle (after 861 * having flushed any pending activity), and a non-zero return that 862 * the object is still in-flight on the GPU. (The GPU has not yet 863 * signaled completion for all pending requests that reference the 864 * object.) An object is guaranteed to become idle eventually (so 865 * long as no new GPU commands are executed upon it). Due to the 866 * asynchronous nature of the hardware, an object reported 867 * as busy may become idle before the ioctl is completed. 868 * 869 * Furthermore, if the object is busy, which engine is busy is only 870 * provided as a guide. There are race conditions which prevent the 871 * report of which engines are busy from being always accurate. 872 * However, the converse is not true. If the object is idle, the 873 * result of the ioctl, that all engines are idle, is accurate. 874 * 875 * The returned dword is split into two fields to indicate both 876 * the engines on which the object is being read, and the 877 * engine on which it is currently being written (if any). 878 * 879 * The low word (bits 0:15) indicate if the object is being written 880 * to by any engine (there can only be one, as the GEM implicit 881 * synchronisation rules force writes to be serialised). Only the 882 * engine for the last write is reported. 883 * 884 * The high word (bits 16:31) are a bitmask of which engines are 885 * currently reading from the object. Multiple engines may be 886 * reading from the object simultaneously. 887 * 888 * The value of each engine is the same as specified in the 889 * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc. 890 * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to 891 * the I915_EXEC_RENDER engine for execution, and so it is never 892 * reported as active itself. Some hardware may have parallel 893 * execution engines, e.g. multiple media engines, which are 894 * mapped to the same identifier in the EXECBUFFER2 ioctl and 895 * so are not separately reported for busyness. 896 * 897 * Caveat emptor: 898 * Only the boolean result of this query is reliable; that is whether 899 * the object is idle or busy. The report of which engines are busy 900 * should be only used as a heuristic. 901 */ 902 __u32 busy; 903}; 904 905/** 906 * I915_CACHING_NONE 907 * 908 * GPU access is not coherent with cpu caches. Default for machines without an 909 * LLC. 910 */ 911#define I915_CACHING_NONE 0 912/** 913 * I915_CACHING_CACHED 914 * 915 * GPU access is coherent with cpu caches and furthermore the data is cached in 916 * last-level caches shared between cpu cores and the gpu GT. Default on 917 * machines with HAS_LLC. 918 */ 919#define I915_CACHING_CACHED 1 920/** 921 * I915_CACHING_DISPLAY 922 * 923 * Special GPU caching mode which is coherent with the scanout engines. 924 * Transparently falls back to I915_CACHING_NONE on platforms where no special 925 * cache mode (like write-through or gfdt flushing) is available. The kernel 926 * automatically sets this mode when using a buffer as a scanout target. 927 * Userspace can manually set this mode to avoid a costly stall and clflush in 928 * the hotpath of drawing the first frame. 929 */ 930#define I915_CACHING_DISPLAY 2 931 932struct drm_i915_gem_caching { 933 /** 934 * Handle of the buffer to set/get the caching level of. */ 935 __u32 handle; 936 937 /** 938 * Cacheing level to apply or return value 939 * 940 * bits0-15 are for generic caching control (i.e. the above defined 941 * values). bits16-31 are reserved for platform-specific variations 942 * (e.g. l3$ caching on gen7). */ 943 __u32 caching; 944}; 945 946#define I915_TILING_NONE 0 947#define I915_TILING_X 1 948#define I915_TILING_Y 2 949#define I915_TILING_LAST I915_TILING_Y 950 951#define I915_BIT_6_SWIZZLE_NONE 0 952#define I915_BIT_6_SWIZZLE_9 1 953#define I915_BIT_6_SWIZZLE_9_10 2 954#define I915_BIT_6_SWIZZLE_9_11 3 955#define I915_BIT_6_SWIZZLE_9_10_11 4 956/* Not seen by userland */ 957#define I915_BIT_6_SWIZZLE_UNKNOWN 5 958/* Seen by userland. */ 959#define I915_BIT_6_SWIZZLE_9_17 6 960#define I915_BIT_6_SWIZZLE_9_10_17 7 961 962struct drm_i915_gem_set_tiling { 963 /** Handle of the buffer to have its tiling state updated */ 964 __u32 handle; 965 966 /** 967 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 968 * I915_TILING_Y). 969 * 970 * This value is to be set on request, and will be updated by the 971 * kernel on successful return with the actual chosen tiling layout. 972 * 973 * The tiling mode may be demoted to I915_TILING_NONE when the system 974 * has bit 6 swizzling that can't be managed correctly by GEM. 975 * 976 * Buffer contents become undefined when changing tiling_mode. 977 */ 978 __u32 tiling_mode; 979 980 /** 981 * Stride in bytes for the object when in I915_TILING_X or 982 * I915_TILING_Y. 983 */ 984 __u32 stride; 985 986 /** 987 * Returned address bit 6 swizzling required for CPU access through 988 * mmap mapping. 989 */ 990 __u32 swizzle_mode; 991}; 992 993struct drm_i915_gem_get_tiling { 994 /** Handle of the buffer to get tiling state for. */ 995 __u32 handle; 996 997 /** 998 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 999 * I915_TILING_Y). 1000 */ 1001 __u32 tiling_mode; 1002 1003 /** 1004 * Returned address bit 6 swizzling required for CPU access through 1005 * mmap mapping. 1006 */ 1007 __u32 swizzle_mode; 1008 1009 /** 1010 * Returned address bit 6 swizzling required for CPU access through 1011 * mmap mapping whilst bound. 1012 */ 1013 __u32 phys_swizzle_mode; 1014}; 1015 1016struct drm_i915_gem_get_aperture { 1017 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1018 __u64 aper_size; 1019 1020 /** 1021 * Available space in the aperture used by i915_gem_execbuffer, in 1022 * bytes 1023 */ 1024 __u64 aper_available_size; 1025}; 1026 1027struct drm_i915_get_pipe_from_crtc_id { 1028 /** ID of CRTC being requested **/ 1029 __u32 crtc_id; 1030 1031 /** pipe of requested CRTC **/ 1032 __u32 pipe; 1033}; 1034 1035#define I915_MADV_WILLNEED 0 1036#define I915_MADV_DONTNEED 1 1037#define __I915_MADV_PURGED 2 /* internal state */ 1038 1039struct drm_i915_gem_madvise { 1040 /** Handle of the buffer to change the backing store advice */ 1041 __u32 handle; 1042 1043 /* Advice: either the buffer will be needed again in the near future, 1044 * or wont be and could be discarded under memory pressure. 1045 */ 1046 __u32 madv; 1047 1048 /** Whether the backing store still exists. */ 1049 __u32 retained; 1050}; 1051 1052/* flags */ 1053#define I915_OVERLAY_TYPE_MASK 0xff 1054#define I915_OVERLAY_YUV_PLANAR 0x01 1055#define I915_OVERLAY_YUV_PACKED 0x02 1056#define I915_OVERLAY_RGB 0x03 1057 1058#define I915_OVERLAY_DEPTH_MASK 0xff00 1059#define I915_OVERLAY_RGB24 0x1000 1060#define I915_OVERLAY_RGB16 0x2000 1061#define I915_OVERLAY_RGB15 0x3000 1062#define I915_OVERLAY_YUV422 0x0100 1063#define I915_OVERLAY_YUV411 0x0200 1064#define I915_OVERLAY_YUV420 0x0300 1065#define I915_OVERLAY_YUV410 0x0400 1066 1067#define I915_OVERLAY_SWAP_MASK 0xff0000 1068#define I915_OVERLAY_NO_SWAP 0x000000 1069#define I915_OVERLAY_UV_SWAP 0x010000 1070#define I915_OVERLAY_Y_SWAP 0x020000 1071#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1072 1073#define I915_OVERLAY_FLAGS_MASK 0xff000000 1074#define I915_OVERLAY_ENABLE 0x01000000 1075 1076struct drm_intel_overlay_put_image { 1077 /* various flags and src format description */ 1078 __u32 flags; 1079 /* source picture description */ 1080 __u32 bo_handle; 1081 /* stride values and offsets are in bytes, buffer relative */ 1082 __u16 stride_Y; /* stride for packed formats */ 1083 __u16 stride_UV; 1084 __u32 offset_Y; /* offset for packet formats */ 1085 __u32 offset_U; 1086 __u32 offset_V; 1087 /* in pixels */ 1088 __u16 src_width; 1089 __u16 src_height; 1090 /* to compensate the scaling factors for partially covered surfaces */ 1091 __u16 src_scan_width; 1092 __u16 src_scan_height; 1093 /* output crtc description */ 1094 __u32 crtc_id; 1095 __u16 dst_x; 1096 __u16 dst_y; 1097 __u16 dst_width; 1098 __u16 dst_height; 1099}; 1100 1101/* flags */ 1102#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1103#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1104#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1105struct drm_intel_overlay_attrs { 1106 __u32 flags; 1107 __u32 color_key; 1108 __s32 brightness; 1109 __u32 contrast; 1110 __u32 saturation; 1111 __u32 gamma0; 1112 __u32 gamma1; 1113 __u32 gamma2; 1114 __u32 gamma3; 1115 __u32 gamma4; 1116 __u32 gamma5; 1117}; 1118 1119/* 1120 * Intel sprite handling 1121 * 1122 * Color keying works with a min/mask/max tuple. Both source and destination 1123 * color keying is allowed. 1124 * 1125 * Source keying: 1126 * Sprite pixels within the min & max values, masked against the color channels 1127 * specified in the mask field, will be transparent. All other pixels will 1128 * be displayed on top of the primary plane. For RGB surfaces, only the min 1129 * and mask fields will be used; ranged compares are not allowed. 1130 * 1131 * Destination keying: 1132 * Primary plane pixels that match the min value, masked against the color 1133 * channels specified in the mask field, will be replaced by corresponding 1134 * pixels from the sprite plane. 1135 * 1136 * Note that source & destination keying are exclusive; only one can be 1137 * active on a given plane. 1138 */ 1139 1140#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1141#define I915_SET_COLORKEY_DESTINATION (1<<1) 1142#define I915_SET_COLORKEY_SOURCE (1<<2) 1143struct drm_intel_sprite_colorkey { 1144 __u32 plane_id; 1145 __u32 min_value; 1146 __u32 channel_mask; 1147 __u32 max_value; 1148 __u32 flags; 1149}; 1150 1151struct drm_i915_gem_wait { 1152 /** Handle of BO we shall wait on */ 1153 __u32 bo_handle; 1154 __u32 flags; 1155 /** Number of nanoseconds to wait, Returns time remaining. */ 1156 __s64 timeout_ns; 1157}; 1158 1159struct drm_i915_gem_context_create { 1160 /* output: id of new context*/ 1161 __u32 ctx_id; 1162 __u32 pad; 1163}; 1164 1165struct drm_i915_gem_context_destroy { 1166 __u32 ctx_id; 1167 __u32 pad; 1168}; 1169 1170struct drm_i915_reg_read { 1171 /* 1172 * Register offset. 1173 * For 64bit wide registers where the upper 32bits don't immediately 1174 * follow the lower 32bits, the offset of the lower 32bits must 1175 * be specified 1176 */ 1177 __u64 offset; 1178 __u64 val; /* Return value */ 1179}; 1180/* Known registers: 1181 * 1182 * Render engine timestamp - 0x2358 + 64bit - gen7+ 1183 * - Note this register returns an invalid value if using the default 1184 * single instruction 8byte read, in order to workaround that use 1185 * offset (0x2538 | 1) instead. 1186 * 1187 */ 1188 1189struct drm_i915_reset_stats { 1190 __u32 ctx_id; 1191 __u32 flags; 1192 1193 /* All resets since boot/module reload, for all contexts */ 1194 __u32 reset_count; 1195 1196 /* Number of batches lost when active in GPU, for this context */ 1197 __u32 batch_active; 1198 1199 /* Number of batches lost pending for execution, for this context */ 1200 __u32 batch_pending; 1201 1202 __u32 pad; 1203}; 1204 1205struct drm_i915_gem_userptr { 1206 __u64 user_ptr; 1207 __u64 user_size; 1208 __u32 flags; 1209#define I915_USERPTR_READ_ONLY 0x1 1210#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1211 /** 1212 * Returned handle for the object. 1213 * 1214 * Object handles are nonzero. 1215 */ 1216 __u32 handle; 1217}; 1218 1219struct drm_i915_gem_context_param { 1220 __u32 ctx_id; 1221 __u32 size; 1222 __u64 param; 1223#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1224#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1225#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1226#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 1227 __u64 value; 1228}; 1229 1230#if defined(__cplusplus) 1231} 1232#endif 1233 1234#endif /* _UAPI_I915_DRM_H_ */ 1235