1/************************************************************************** 2 * 3 * Copyright � 2007 Red Hat Inc. 4 * Copyright � 2007-2012 Intel Corporation 5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * The above copyright notice and this permission notice (including the 25 * next paragraph) shall be included in all copies or substantial portions 26 * of the Software. 27 * 28 * 29 **************************************************************************/ 30/* 31 * Authors: Thomas Hellstr�m <thomas-at-tungstengraphics-dot-com> 32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com> 33 * Eric Anholt <eric@anholt.net> 34 * Dave Airlie <airlied@linux.ie> 35 */ 36 37#ifdef HAVE_CONFIG_H 38#include "config.h" 39#endif 40 41#include <xf86drm.h> 42#include <xf86atomic.h> 43#include <fcntl.h> 44#include <stdio.h> 45#include <stdlib.h> 46#include <string.h> 47#include <unistd.h> 48#include <assert.h> 49#include <pthread.h> 50#include <sys/ioctl.h> 51#include <sys/stat.h> 52#include <sys/types.h> 53#include <stdbool.h> 54 55#include "errno.h" 56#ifndef ETIME 57#define ETIME ETIMEDOUT 58#endif 59#include "libdrm_macros.h" 60#include "libdrm_lists.h" 61#include "intel_bufmgr.h" 62#include "intel_bufmgr_priv.h" 63#include "intel_chipset.h" 64#include "string.h" 65 66#include "i915_drm.h" 67 68#ifdef HAVE_VALGRIND 69#include <valgrind.h> 70#include <memcheck.h> 71#define VG(x) x 72#else 73#define VG(x) 74#endif 75 76#define memclear(s) memset(&s, 0, sizeof(s)) 77 78#define DBG(...) do { \ 79 if (bufmgr_gem->bufmgr.debug) \ 80 fprintf(stderr, __VA_ARGS__); \ 81} while (0) 82 83#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 84#define MAX2(A, B) ((A) > (B) ? (A) : (B)) 85 86/** 87 * upper_32_bits - return bits 32-63 of a number 88 * @n: the number we're accessing 89 * 90 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 91 * the "right shift count >= width of type" warning when that quantity is 92 * 32-bits. 93 */ 94#define upper_32_bits(n) ((__u32)(((n) >> 16) >> 16)) 95 96/** 97 * lower_32_bits - return bits 0-31 of a number 98 * @n: the number we're accessing 99 */ 100#define lower_32_bits(n) ((__u32)(n)) 101 102typedef struct _drm_intel_bo_gem drm_intel_bo_gem; 103 104struct drm_intel_gem_bo_bucket { 105 drmMMListHead head; 106 unsigned long size; 107}; 108 109typedef struct _drm_intel_bufmgr_gem { 110 drm_intel_bufmgr bufmgr; 111 112 atomic_t refcount; 113 114 int fd; 115 116 int max_relocs; 117 118 pthread_mutex_t lock; 119 120 struct drm_i915_gem_exec_object *exec_objects; 121 struct drm_i915_gem_exec_object2 *exec2_objects; 122 drm_intel_bo **exec_bos; 123 int exec_size; 124 int exec_count; 125 126 /** Array of lists of cached gem objects of power-of-two sizes */ 127 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4]; 128 int num_buckets; 129 time_t time; 130 131 drmMMListHead managers; 132 133 drmMMListHead named; 134 drmMMListHead vma_cache; 135 int vma_count, vma_open, vma_max; 136 137 uint64_t gtt_size; 138 int available_fences; 139 int pci_device; 140 int gen; 141 unsigned int has_bsd : 1; 142 unsigned int has_blt : 1; 143 unsigned int has_relaxed_fencing : 1; 144 unsigned int has_llc : 1; 145 unsigned int has_wait_timeout : 1; 146 unsigned int bo_reuse : 1; 147 unsigned int no_exec : 1; 148 unsigned int has_vebox : 1; 149 bool fenced_relocs; 150 151 struct { 152 void *ptr; 153 uint32_t handle; 154 } userptr_active; 155 156} drm_intel_bufmgr_gem; 157 158#define DRM_INTEL_RELOC_FENCE (1<<0) 159 160typedef struct _drm_intel_reloc_target_info { 161 drm_intel_bo *bo; 162 int flags; 163} drm_intel_reloc_target; 164 165struct _drm_intel_bo_gem { 166 drm_intel_bo bo; 167 168 atomic_t refcount; 169 uint32_t gem_handle; 170 const char *name; 171 172 /** 173 * Kenel-assigned global name for this object 174 * 175 * List contains both flink named and prime fd'd objects 176 */ 177 unsigned int global_name; 178 drmMMListHead name_list; 179 180 /** 181 * Index of the buffer within the validation list while preparing a 182 * batchbuffer execution. 183 */ 184 int validate_index; 185 186 /** 187 * Current tiling mode 188 */ 189 uint32_t tiling_mode; 190 uint32_t swizzle_mode; 191 unsigned long stride; 192 193 time_t free_time; 194 195 /** Array passed to the DRM containing relocation information. */ 196 struct drm_i915_gem_relocation_entry *relocs; 197 /** 198 * Array of info structs corresponding to relocs[i].target_handle etc 199 */ 200 drm_intel_reloc_target *reloc_target_info; 201 /** Number of entries in relocs */ 202 int reloc_count; 203 /** Array of BOs that are referenced by this buffer and will be softpinned */ 204 drm_intel_bo **softpin_target; 205 /** Number softpinned BOs that are referenced by this buffer */ 206 int softpin_target_count; 207 /** Maximum amount of softpinned BOs that are referenced by this buffer */ 208 int softpin_target_size; 209 210 /** Mapped address for the buffer, saved across map/unmap cycles */ 211 void *mem_virtual; 212 /** GTT virtual address for the buffer, saved across map/unmap cycles */ 213 void *gtt_virtual; 214 /** 215 * Virtual address of the buffer allocated by user, used for userptr 216 * objects only. 217 */ 218 void *user_virtual; 219 int map_count; 220 drmMMListHead vma_list; 221 222 /** BO cache list */ 223 drmMMListHead head; 224 225 /** 226 * Boolean of whether this BO and its children have been included in 227 * the current drm_intel_bufmgr_check_aperture_space() total. 228 */ 229 bool included_in_check_aperture; 230 231 /** 232 * Boolean of whether this buffer has been used as a relocation 233 * target and had its size accounted for, and thus can't have any 234 * further relocations added to it. 235 */ 236 bool used_as_reloc_target; 237 238 /** 239 * Boolean of whether we have encountered an error whilst building the relocation tree. 240 */ 241 bool has_error; 242 243 /** 244 * Boolean of whether this buffer can be re-used 245 */ 246 bool reusable; 247 248 /** 249 * Boolean of whether the GPU is definitely not accessing the buffer. 250 * 251 * This is only valid when reusable, since non-reusable 252 * buffers are those that have been shared wth other 253 * processes, so we don't know their state. 254 */ 255 bool idle; 256 257 /** 258 * Boolean of whether this buffer was allocated with userptr 259 */ 260 bool is_userptr; 261 262 /** 263 * Boolean of whether this buffer can be placed in the full 48-bit 264 * address range on gen8+. 265 * 266 * By default, buffers will be keep in a 32-bit range, unless this 267 * flag is explicitly set. 268 */ 269 bool use_48b_address_range; 270 271 /** 272 * Whether this buffer is softpinned at offset specified by the user 273 */ 274 bool is_softpin; 275 276 /** 277 * Size in bytes of this buffer and its relocation descendents. 278 * 279 * Used to avoid costly tree walking in 280 * drm_intel_bufmgr_check_aperture in the common case. 281 */ 282 int reloc_tree_size; 283 284 /** 285 * Number of potential fence registers required by this buffer and its 286 * relocations. 287 */ 288 int reloc_tree_fences; 289 290 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */ 291 bool mapped_cpu_write; 292}; 293 294static unsigned int 295drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count); 296 297static unsigned int 298drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count); 299 300static int 301drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 302 uint32_t * swizzle_mode); 303 304static int 305drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo, 306 uint32_t tiling_mode, 307 uint32_t stride); 308 309static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo, 310 time_t time); 311 312static void drm_intel_gem_bo_unreference(drm_intel_bo *bo); 313 314static void drm_intel_gem_bo_free(drm_intel_bo *bo); 315 316static inline drm_intel_bo_gem *to_bo_gem(drm_intel_bo *bo) 317{ 318 return (drm_intel_bo_gem *)bo; 319} 320 321static unsigned long 322drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size, 323 uint32_t *tiling_mode) 324{ 325 unsigned long min_size, max_size; 326 unsigned long i; 327 328 if (*tiling_mode == I915_TILING_NONE) 329 return size; 330 331 /* 965+ just need multiples of page size for tiling */ 332 if (bufmgr_gem->gen >= 4) 333 return ROUND_UP_TO(size, 4096); 334 335 /* Older chips need powers of two, of at least 512k or 1M */ 336 if (bufmgr_gem->gen == 3) { 337 min_size = 1024*1024; 338 max_size = 128*1024*1024; 339 } else { 340 min_size = 512*1024; 341 max_size = 64*1024*1024; 342 } 343 344 if (size > max_size) { 345 *tiling_mode = I915_TILING_NONE; 346 return size; 347 } 348 349 /* Do we need to allocate every page for the fence? */ 350 if (bufmgr_gem->has_relaxed_fencing) 351 return ROUND_UP_TO(size, 4096); 352 353 for (i = min_size; i < size; i <<= 1) 354 ; 355 356 return i; 357} 358 359/* 360 * Round a given pitch up to the minimum required for X tiling on a 361 * given chip. We use 512 as the minimum to allow for a later tiling 362 * change. 363 */ 364static unsigned long 365drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem, 366 unsigned long pitch, uint32_t *tiling_mode) 367{ 368 unsigned long tile_width; 369 unsigned long i; 370 371 /* If untiled, then just align it so that we can do rendering 372 * to it with the 3D engine. 373 */ 374 if (*tiling_mode == I915_TILING_NONE) 375 return ALIGN(pitch, 64); 376 377 if (*tiling_mode == I915_TILING_X 378 || (IS_915(bufmgr_gem->pci_device) 379 && *tiling_mode == I915_TILING_Y)) 380 tile_width = 512; 381 else 382 tile_width = 128; 383 384 /* 965 is flexible */ 385 if (bufmgr_gem->gen >= 4) 386 return ROUND_UP_TO(pitch, tile_width); 387 388 /* The older hardware has a maximum pitch of 8192 with tiled 389 * surfaces, so fallback to untiled if it's too large. 390 */ 391 if (pitch > 8192) { 392 *tiling_mode = I915_TILING_NONE; 393 return ALIGN(pitch, 64); 394 } 395 396 /* Pre-965 needs power of two tile width */ 397 for (i = tile_width; i < pitch; i <<= 1) 398 ; 399 400 return i; 401} 402 403static struct drm_intel_gem_bo_bucket * 404drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem, 405 unsigned long size) 406{ 407 int i; 408 409 for (i = 0; i < bufmgr_gem->num_buckets; i++) { 410 struct drm_intel_gem_bo_bucket *bucket = 411 &bufmgr_gem->cache_bucket[i]; 412 if (bucket->size >= size) { 413 return bucket; 414 } 415 } 416 417 return NULL; 418} 419 420static void 421drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem) 422{ 423 int i, j; 424 425 for (i = 0; i < bufmgr_gem->exec_count; i++) { 426 drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; 427 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 428 429 if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL) { 430 DBG("%2d: %d %s(%s)\n", i, bo_gem->gem_handle, 431 bo_gem->is_softpin ? "*" : "", 432 bo_gem->name); 433 continue; 434 } 435 436 for (j = 0; j < bo_gem->reloc_count; j++) { 437 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo; 438 drm_intel_bo_gem *target_gem = 439 (drm_intel_bo_gem *) target_bo; 440 441 DBG("%2d: %d %s(%s)@0x%08x %08x -> " 442 "%d (%s)@0x%08x %08x + 0x%08x\n", 443 i, 444 bo_gem->gem_handle, 445 bo_gem->is_softpin ? "*" : "", 446 bo_gem->name, 447 upper_32_bits(bo_gem->relocs[j].offset), 448 lower_32_bits(bo_gem->relocs[j].offset), 449 target_gem->gem_handle, 450 target_gem->name, 451 upper_32_bits(target_bo->offset64), 452 lower_32_bits(target_bo->offset64), 453 bo_gem->relocs[j].delta); 454 } 455 456 for (j = 0; j < bo_gem->softpin_target_count; j++) { 457 drm_intel_bo *target_bo = bo_gem->softpin_target[j]; 458 drm_intel_bo_gem *target_gem = 459 (drm_intel_bo_gem *) target_bo; 460 DBG("%2d: %d %s(%s) -> " 461 "%d *(%s)@0x%08x %08x\n", 462 i, 463 bo_gem->gem_handle, 464 bo_gem->is_softpin ? "*" : "", 465 bo_gem->name, 466 target_gem->gem_handle, 467 target_gem->name, 468 upper_32_bits(target_bo->offset64), 469 lower_32_bits(target_bo->offset64)); 470 } 471 } 472} 473 474static inline void 475drm_intel_gem_bo_reference(drm_intel_bo *bo) 476{ 477 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 478 479 atomic_inc(&bo_gem->refcount); 480} 481 482/** 483 * Adds the given buffer to the list of buffers to be validated (moved into the 484 * appropriate memory type) with the next batch submission. 485 * 486 * If a buffer is validated multiple times in a batch submission, it ends up 487 * with the intersection of the memory type flags and the union of the 488 * access flags. 489 */ 490static void 491drm_intel_add_validate_buffer(drm_intel_bo *bo) 492{ 493 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 494 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 495 int index; 496 497 if (bo_gem->validate_index != -1) 498 return; 499 500 /* Extend the array of validation entries as necessary. */ 501 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) { 502 int new_size = bufmgr_gem->exec_size * 2; 503 504 if (new_size == 0) 505 new_size = 5; 506 507 bufmgr_gem->exec_objects = 508 realloc(bufmgr_gem->exec_objects, 509 sizeof(*bufmgr_gem->exec_objects) * new_size); 510 bufmgr_gem->exec_bos = 511 realloc(bufmgr_gem->exec_bos, 512 sizeof(*bufmgr_gem->exec_bos) * new_size); 513 bufmgr_gem->exec_size = new_size; 514 } 515 516 index = bufmgr_gem->exec_count; 517 bo_gem->validate_index = index; 518 /* Fill in array entry */ 519 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle; 520 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count; 521 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs; 522 bufmgr_gem->exec_objects[index].alignment = bo->align; 523 bufmgr_gem->exec_objects[index].offset = 0; 524 bufmgr_gem->exec_bos[index] = bo; 525 bufmgr_gem->exec_count++; 526} 527 528static void 529drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence) 530{ 531 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; 532 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; 533 int index; 534 int flags = 0; 535 536 if (need_fence) 537 flags |= EXEC_OBJECT_NEEDS_FENCE; 538 if (bo_gem->use_48b_address_range) 539 flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS; 540 if (bo_gem->is_softpin) 541 flags |= EXEC_OBJECT_PINNED; 542 543 if (bo_gem->validate_index != -1) { 544 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |= flags; 545 return; 546 } 547 548 /* Extend the array of validation entries as necessary. */ 549 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) { 550 int new_size = bufmgr_gem->exec_size * 2; 551 552 if (new_size == 0) 553 new_size = 5; 554 555 bufmgr_gem->exec2_objects = 556 realloc(bufmgr_gem->exec2_objects, 557 sizeof(*bufmgr_gem->exec2_objects) * new_size); 558 bufmgr_gem->exec_bos = 559 realloc(bufmgr_gem->exec_bos, 560 sizeof(*bufmgr_gem->exec_bos) * new_size); 561 bufmgr_gem->exec_size = new_size; 562 } 563 564 index = bufmgr_gem->exec_count; 565 bo_gem->validate_index = index; 566 /* Fill in array entry */ 567 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle; 568 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count; 569 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs; 570 bufmgr_gem->exec2_objects[index].alignment = bo->align; 571 bufmgr_gem->exec2_objects[index].offset = bo_gem->is_softpin ? 572 bo->offset64 : 0; 573 bufmgr_gem->exec_bos[index] = bo; 574 bufmgr_gem->exec2_objects[index].flags = flags; 575 bufmgr_gem->exec2_objects[index].rsvd1 = 0; 576 bufmgr_gem->exec2_objects[index].rsvd2 = 0; 577 bufmgr_gem->exec_count++; 578} 579 580#define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \ 581 sizeof(uint32_t)) 582 583static void 584drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem, 585 drm_intel_bo_gem *bo_gem, 586 unsigned int alignment) 587{ 588 unsigned int size; 589 590 assert(!bo_gem->used_as_reloc_target); 591 592 /* The older chipsets are far-less flexible in terms of tiling, 593 * and require tiled buffer to be size aligned in the aperture. 594 * This means that in the worst possible case we will need a hole 595 * twice as large as the object in order for it to fit into the 596 * aperture. Optimal packing is for wimps. 597 */ 598 size = bo_gem->bo.size; 599 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) { 600 unsigned int min_size; 601 602 if (bufmgr_gem->has_relaxed_fencing) { 603 if (bufmgr_gem->gen == 3) 604 min_size = 1024*1024; 605 else 606 min_size = 512*1024; 607 608 while (min_size < size) 609 min_size *= 2; 610 } else 611 min_size = size; 612 613 /* Account for worst-case alignment. */ 614 alignment = MAX2(alignment, min_size); 615 } 616 617 bo_gem->reloc_tree_size = size + alignment; 618} 619 620static int 621drm_intel_setup_reloc_list(drm_intel_bo *bo) 622{ 623 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 624 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 625 unsigned int max_relocs = bufmgr_gem->max_relocs; 626 627 if (bo->size / 4 < max_relocs) 628 max_relocs = bo->size / 4; 629 630 bo_gem->relocs = malloc(max_relocs * 631 sizeof(struct drm_i915_gem_relocation_entry)); 632 bo_gem->reloc_target_info = malloc(max_relocs * 633 sizeof(drm_intel_reloc_target)); 634 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) { 635 bo_gem->has_error = true; 636 637 free (bo_gem->relocs); 638 bo_gem->relocs = NULL; 639 640 free (bo_gem->reloc_target_info); 641 bo_gem->reloc_target_info = NULL; 642 643 return 1; 644 } 645 646 return 0; 647} 648 649static int 650drm_intel_gem_bo_busy(drm_intel_bo *bo) 651{ 652 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 653 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 654 struct drm_i915_gem_busy busy; 655 int ret; 656 657 if (bo_gem->reusable && bo_gem->idle) 658 return false; 659 660 memclear(busy); 661 busy.handle = bo_gem->gem_handle; 662 663 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy); 664 if (ret == 0) { 665 bo_gem->idle = !busy.busy; 666 return busy.busy; 667 } else { 668 return false; 669 } 670 return (ret == 0 && busy.busy); 671} 672 673static int 674drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem, 675 drm_intel_bo_gem *bo_gem, int state) 676{ 677 struct drm_i915_gem_madvise madv; 678 679 memclear(madv); 680 madv.handle = bo_gem->gem_handle; 681 madv.madv = state; 682 madv.retained = 1; 683 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv); 684 685 return madv.retained; 686} 687 688static int 689drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv) 690{ 691 return drm_intel_gem_bo_madvise_internal 692 ((drm_intel_bufmgr_gem *) bo->bufmgr, 693 (drm_intel_bo_gem *) bo, 694 madv); 695} 696 697/* drop the oldest entries that have been purged by the kernel */ 698static void 699drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem, 700 struct drm_intel_gem_bo_bucket *bucket) 701{ 702 while (!DRMLISTEMPTY(&bucket->head)) { 703 drm_intel_bo_gem *bo_gem; 704 705 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, 706 bucket->head.next, head); 707 if (drm_intel_gem_bo_madvise_internal 708 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED)) 709 break; 710 711 DRMLISTDEL(&bo_gem->head); 712 drm_intel_gem_bo_free(&bo_gem->bo); 713 } 714} 715 716static drm_intel_bo * 717drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, 718 const char *name, 719 unsigned long size, 720 unsigned long flags, 721 uint32_t tiling_mode, 722 unsigned long stride, 723 unsigned int alignment) 724{ 725 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; 726 drm_intel_bo_gem *bo_gem; 727 unsigned int page_size = getpagesize(); 728 int ret; 729 struct drm_intel_gem_bo_bucket *bucket; 730 bool alloc_from_cache; 731 unsigned long bo_size; 732 bool for_render = false; 733 734 if (flags & BO_ALLOC_FOR_RENDER) 735 for_render = true; 736 737 /* Round the allocated size up to a power of two number of pages. */ 738 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size); 739 740 /* If we don't have caching at this size, don't actually round the 741 * allocation up. 742 */ 743 if (bucket == NULL) { 744 bo_size = size; 745 if (bo_size < page_size) 746 bo_size = page_size; 747 } else { 748 bo_size = bucket->size; 749 } 750 751 pthread_mutex_lock(&bufmgr_gem->lock); 752 /* Get a buffer out of the cache if available */ 753retry: 754 alloc_from_cache = false; 755 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) { 756 if (for_render) { 757 /* Allocate new render-target BOs from the tail (MRU) 758 * of the list, as it will likely be hot in the GPU 759 * cache and in the aperture for us. 760 */ 761 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, 762 bucket->head.prev, head); 763 DRMLISTDEL(&bo_gem->head); 764 alloc_from_cache = true; 765 bo_gem->bo.align = alignment; 766 } else { 767 assert(alignment == 0); 768 /* For non-render-target BOs (where we're probably 769 * going to map it first thing in order to fill it 770 * with data), check if the last BO in the cache is 771 * unbusy, and only reuse in that case. Otherwise, 772 * allocating a new buffer is probably faster than 773 * waiting for the GPU to finish. 774 */ 775 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, 776 bucket->head.next, head); 777 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) { 778 alloc_from_cache = true; 779 DRMLISTDEL(&bo_gem->head); 780 } 781 } 782 783 if (alloc_from_cache) { 784 if (!drm_intel_gem_bo_madvise_internal 785 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) { 786 drm_intel_gem_bo_free(&bo_gem->bo); 787 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem, 788 bucket); 789 goto retry; 790 } 791 792 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo, 793 tiling_mode, 794 stride)) { 795 drm_intel_gem_bo_free(&bo_gem->bo); 796 goto retry; 797 } 798 } 799 } 800 pthread_mutex_unlock(&bufmgr_gem->lock); 801 802 if (!alloc_from_cache) { 803 struct drm_i915_gem_create create; 804 805 bo_gem = calloc(1, sizeof(*bo_gem)); 806 if (!bo_gem) 807 return NULL; 808 809 bo_gem->bo.size = bo_size; 810 811 memclear(create); 812 create.size = bo_size; 813 814 ret = drmIoctl(bufmgr_gem->fd, 815 DRM_IOCTL_I915_GEM_CREATE, 816 &create); 817 bo_gem->gem_handle = create.handle; 818 bo_gem->bo.handle = bo_gem->gem_handle; 819 if (ret != 0) { 820 free(bo_gem); 821 return NULL; 822 } 823 bo_gem->bo.bufmgr = bufmgr; 824 bo_gem->bo.align = alignment; 825 826 bo_gem->tiling_mode = I915_TILING_NONE; 827 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 828 bo_gem->stride = 0; 829 830 /* drm_intel_gem_bo_free calls DRMLISTDEL() for an uninitialized 831 list (vma_list), so better set the list head here */ 832 DRMINITLISTHEAD(&bo_gem->name_list); 833 DRMINITLISTHEAD(&bo_gem->vma_list); 834 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo, 835 tiling_mode, 836 stride)) { 837 drm_intel_gem_bo_free(&bo_gem->bo); 838 return NULL; 839 } 840 } 841 842 bo_gem->name = name; 843 atomic_set(&bo_gem->refcount, 1); 844 bo_gem->validate_index = -1; 845 bo_gem->reloc_tree_fences = 0; 846 bo_gem->used_as_reloc_target = false; 847 bo_gem->has_error = false; 848 bo_gem->reusable = true; 849 bo_gem->use_48b_address_range = false; 850 851 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, alignment); 852 853 DBG("bo_create: buf %d (%s) %ldb\n", 854 bo_gem->gem_handle, bo_gem->name, size); 855 856 return &bo_gem->bo; 857} 858 859static drm_intel_bo * 860drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, 861 const char *name, 862 unsigned long size, 863 unsigned int alignment) 864{ 865 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 866 BO_ALLOC_FOR_RENDER, 867 I915_TILING_NONE, 0, 868 alignment); 869} 870 871static drm_intel_bo * 872drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, 873 const char *name, 874 unsigned long size, 875 unsigned int alignment) 876{ 877 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0, 878 I915_TILING_NONE, 0, 0); 879} 880 881static drm_intel_bo * 882drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, 883 int x, int y, int cpp, uint32_t *tiling_mode, 884 unsigned long *pitch, unsigned long flags) 885{ 886 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; 887 unsigned long size, stride; 888 uint32_t tiling; 889 890 do { 891 unsigned long aligned_y, height_alignment; 892 893 tiling = *tiling_mode; 894 895 /* If we're tiled, our allocations are in 8 or 32-row blocks, 896 * so failure to align our height means that we won't allocate 897 * enough pages. 898 * 899 * If we're untiled, we still have to align to 2 rows high 900 * because the data port accesses 2x2 blocks even if the 901 * bottom row isn't to be rendered, so failure to align means 902 * we could walk off the end of the GTT and fault. This is 903 * documented on 965, and may be the case on older chipsets 904 * too so we try to be careful. 905 */ 906 aligned_y = y; 907 height_alignment = 2; 908 909 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE) 910 height_alignment = 16; 911 else if (tiling == I915_TILING_X 912 || (IS_915(bufmgr_gem->pci_device) 913 && tiling == I915_TILING_Y)) 914 height_alignment = 8; 915 else if (tiling == I915_TILING_Y) 916 height_alignment = 32; 917 aligned_y = ALIGN(y, height_alignment); 918 919 stride = x * cpp; 920 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode); 921 size = stride * aligned_y; 922 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode); 923 } while (*tiling_mode != tiling); 924 *pitch = stride; 925 926 if (tiling == I915_TILING_NONE) 927 stride = 0; 928 929 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags, 930 tiling, stride, 0); 931} 932 933static drm_intel_bo * 934drm_intel_gem_bo_alloc_userptr(drm_intel_bufmgr *bufmgr, 935 const char *name, 936 void *addr, 937 uint32_t tiling_mode, 938 uint32_t stride, 939 unsigned long size, 940 unsigned long flags) 941{ 942 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; 943 drm_intel_bo_gem *bo_gem; 944 int ret; 945 struct drm_i915_gem_userptr userptr; 946 947 /* Tiling with userptr surfaces is not supported 948 * on all hardware so refuse it for time being. 949 */ 950 if (tiling_mode != I915_TILING_NONE) 951 return NULL; 952 953 bo_gem = calloc(1, sizeof(*bo_gem)); 954 if (!bo_gem) 955 return NULL; 956 957 bo_gem->bo.size = size; 958 959 memclear(userptr); 960 userptr.user_ptr = (__u64)((unsigned long)addr); 961 userptr.user_size = size; 962 userptr.flags = flags; 963 964 ret = drmIoctl(bufmgr_gem->fd, 965 DRM_IOCTL_I915_GEM_USERPTR, 966 &userptr); 967 if (ret != 0) { 968 DBG("bo_create_userptr: " 969 "ioctl failed with user ptr %p size 0x%lx, " 970 "user flags 0x%lx\n", addr, size, flags); 971 free(bo_gem); 972 return NULL; 973 } 974 975 bo_gem->gem_handle = userptr.handle; 976 bo_gem->bo.handle = bo_gem->gem_handle; 977 bo_gem->bo.bufmgr = bufmgr; 978 bo_gem->is_userptr = true; 979 bo_gem->bo.virtual = addr; 980 /* Save the address provided by user */ 981 bo_gem->user_virtual = addr; 982 bo_gem->tiling_mode = I915_TILING_NONE; 983 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 984 bo_gem->stride = 0; 985 986 DRMINITLISTHEAD(&bo_gem->name_list); 987 DRMINITLISTHEAD(&bo_gem->vma_list); 988 989 bo_gem->name = name; 990 atomic_set(&bo_gem->refcount, 1); 991 bo_gem->validate_index = -1; 992 bo_gem->reloc_tree_fences = 0; 993 bo_gem->used_as_reloc_target = false; 994 bo_gem->has_error = false; 995 bo_gem->reusable = false; 996 bo_gem->use_48b_address_range = false; 997 998 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0); 999 1000 DBG("bo_create_userptr: " 1001 "ptr %p buf %d (%s) size %ldb, stride 0x%x, tile mode %d\n", 1002 addr, bo_gem->gem_handle, bo_gem->name, 1003 size, stride, tiling_mode); 1004 1005 return &bo_gem->bo; 1006} 1007 1008static bool 1009has_userptr(drm_intel_bufmgr_gem *bufmgr_gem) 1010{ 1011 int ret; 1012 void *ptr; 1013 long pgsz; 1014 struct drm_i915_gem_userptr userptr; 1015 1016 pgsz = sysconf(_SC_PAGESIZE); 1017 assert(pgsz > 0); 1018 1019 ret = posix_memalign(&ptr, pgsz, pgsz); 1020 if (ret) { 1021 DBG("Failed to get a page (%ld) for userptr detection!\n", 1022 pgsz); 1023 return false; 1024 } 1025 1026 memclear(userptr); 1027 userptr.user_ptr = (__u64)(unsigned long)ptr; 1028 userptr.user_size = pgsz; 1029 1030retry: 1031 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr); 1032 if (ret) { 1033 if (errno == ENODEV && userptr.flags == 0) { 1034 userptr.flags = I915_USERPTR_UNSYNCHRONIZED; 1035 goto retry; 1036 } 1037 free(ptr); 1038 return false; 1039 } 1040 1041 /* We don't release the userptr bo here as we want to keep the 1042 * kernel mm tracking alive for our lifetime. The first time we 1043 * create a userptr object the kernel has to install a mmu_notifer 1044 * which is a heavyweight operation (e.g. it requires taking all 1045 * mm_locks and stop_machine()). 1046 */ 1047 1048 bufmgr_gem->userptr_active.ptr = ptr; 1049 bufmgr_gem->userptr_active.handle = userptr.handle; 1050 1051 return true; 1052} 1053 1054static drm_intel_bo * 1055check_bo_alloc_userptr(drm_intel_bufmgr *bufmgr, 1056 const char *name, 1057 void *addr, 1058 uint32_t tiling_mode, 1059 uint32_t stride, 1060 unsigned long size, 1061 unsigned long flags) 1062{ 1063 if (has_userptr((drm_intel_bufmgr_gem *)bufmgr)) 1064 bufmgr->bo_alloc_userptr = drm_intel_gem_bo_alloc_userptr; 1065 else 1066 bufmgr->bo_alloc_userptr = NULL; 1067 1068 return drm_intel_bo_alloc_userptr(bufmgr, name, addr, 1069 tiling_mode, stride, size, flags); 1070} 1071 1072/** 1073 * Returns a drm_intel_bo wrapping the given buffer object handle. 1074 * 1075 * This can be used when one application needs to pass a buffer object 1076 * to another. 1077 */ 1078drm_intel_bo * 1079drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, 1080 const char *name, 1081 unsigned int handle) 1082{ 1083 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; 1084 drm_intel_bo_gem *bo_gem; 1085 int ret; 1086 struct drm_gem_open open_arg; 1087 struct drm_i915_gem_get_tiling get_tiling; 1088 drmMMListHead *list; 1089 1090 /* At the moment most applications only have a few named bo. 1091 * For instance, in a DRI client only the render buffers passed 1092 * between X and the client are named. And since X returns the 1093 * alternating names for the front/back buffer a linear search 1094 * provides a sufficiently fast match. 1095 */ 1096 pthread_mutex_lock(&bufmgr_gem->lock); 1097 for (list = bufmgr_gem->named.next; 1098 list != &bufmgr_gem->named; 1099 list = list->next) { 1100 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list); 1101 if (bo_gem->global_name == handle) { 1102 drm_intel_gem_bo_reference(&bo_gem->bo); 1103 pthread_mutex_unlock(&bufmgr_gem->lock); 1104 return &bo_gem->bo; 1105 } 1106 } 1107 1108 memclear(open_arg); 1109 open_arg.name = handle; 1110 ret = drmIoctl(bufmgr_gem->fd, 1111 DRM_IOCTL_GEM_OPEN, 1112 &open_arg); 1113 if (ret != 0) { 1114 DBG("Couldn't reference %s handle 0x%08x: %s\n", 1115 name, handle, strerror(errno)); 1116 pthread_mutex_unlock(&bufmgr_gem->lock); 1117 return NULL; 1118 } 1119 /* Now see if someone has used a prime handle to get this 1120 * object from the kernel before by looking through the list 1121 * again for a matching gem_handle 1122 */ 1123 for (list = bufmgr_gem->named.next; 1124 list != &bufmgr_gem->named; 1125 list = list->next) { 1126 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list); 1127 if (bo_gem->gem_handle == open_arg.handle) { 1128 drm_intel_gem_bo_reference(&bo_gem->bo); 1129 pthread_mutex_unlock(&bufmgr_gem->lock); 1130 return &bo_gem->bo; 1131 } 1132 } 1133 1134 bo_gem = calloc(1, sizeof(*bo_gem)); 1135 if (!bo_gem) { 1136 pthread_mutex_unlock(&bufmgr_gem->lock); 1137 return NULL; 1138 } 1139 1140 bo_gem->bo.size = open_arg.size; 1141 bo_gem->bo.offset = 0; 1142 bo_gem->bo.offset64 = 0; 1143 bo_gem->bo.virtual = NULL; 1144 bo_gem->bo.bufmgr = bufmgr; 1145 bo_gem->name = name; 1146 atomic_set(&bo_gem->refcount, 1); 1147 bo_gem->validate_index = -1; 1148 bo_gem->gem_handle = open_arg.handle; 1149 bo_gem->bo.handle = open_arg.handle; 1150 bo_gem->global_name = handle; 1151 bo_gem->reusable = false; 1152 bo_gem->use_48b_address_range = false; 1153 1154 memclear(get_tiling); 1155 get_tiling.handle = bo_gem->gem_handle; 1156 ret = drmIoctl(bufmgr_gem->fd, 1157 DRM_IOCTL_I915_GEM_GET_TILING, 1158 &get_tiling); 1159 if (ret != 0) { 1160 drm_intel_gem_bo_unreference(&bo_gem->bo); 1161 pthread_mutex_unlock(&bufmgr_gem->lock); 1162 return NULL; 1163 } 1164 bo_gem->tiling_mode = get_tiling.tiling_mode; 1165 bo_gem->swizzle_mode = get_tiling.swizzle_mode; 1166 /* XXX stride is unknown */ 1167 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0); 1168 1169 DRMINITLISTHEAD(&bo_gem->vma_list); 1170 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named); 1171 pthread_mutex_unlock(&bufmgr_gem->lock); 1172 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name); 1173 1174 return &bo_gem->bo; 1175} 1176 1177static void 1178drm_intel_gem_bo_free(drm_intel_bo *bo) 1179{ 1180 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1181 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1182 struct drm_gem_close close; 1183 int ret; 1184 1185 DRMLISTDEL(&bo_gem->vma_list); 1186 if (bo_gem->mem_virtual) { 1187 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0)); 1188 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size); 1189 bufmgr_gem->vma_count--; 1190 } 1191 if (bo_gem->gtt_virtual) { 1192 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size); 1193 bufmgr_gem->vma_count--; 1194 } 1195 1196 /* Close this object */ 1197 memclear(close); 1198 close.handle = bo_gem->gem_handle; 1199 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close); 1200 if (ret != 0) { 1201 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n", 1202 bo_gem->gem_handle, bo_gem->name, strerror(errno)); 1203 } 1204 free(bo); 1205} 1206 1207static void 1208drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo) 1209{ 1210#if HAVE_VALGRIND 1211 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1212 1213 if (bo_gem->mem_virtual) 1214 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size); 1215 1216 if (bo_gem->gtt_virtual) 1217 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size); 1218#endif 1219} 1220 1221/** Frees all cached buffers significantly older than @time. */ 1222static void 1223drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time) 1224{ 1225 int i; 1226 1227 if (bufmgr_gem->time == time) 1228 return; 1229 1230 for (i = 0; i < bufmgr_gem->num_buckets; i++) { 1231 struct drm_intel_gem_bo_bucket *bucket = 1232 &bufmgr_gem->cache_bucket[i]; 1233 1234 while (!DRMLISTEMPTY(&bucket->head)) { 1235 drm_intel_bo_gem *bo_gem; 1236 1237 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, 1238 bucket->head.next, head); 1239 if (time - bo_gem->free_time <= 1) 1240 break; 1241 1242 DRMLISTDEL(&bo_gem->head); 1243 1244 drm_intel_gem_bo_free(&bo_gem->bo); 1245 } 1246 } 1247 1248 bufmgr_gem->time = time; 1249} 1250 1251static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem) 1252{ 1253 int limit; 1254 1255 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__, 1256 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max); 1257 1258 if (bufmgr_gem->vma_max < 0) 1259 return; 1260 1261 /* We may need to evict a few entries in order to create new mmaps */ 1262 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open; 1263 if (limit < 0) 1264 limit = 0; 1265 1266 while (bufmgr_gem->vma_count > limit) { 1267 drm_intel_bo_gem *bo_gem; 1268 1269 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, 1270 bufmgr_gem->vma_cache.next, 1271 vma_list); 1272 assert(bo_gem->map_count == 0); 1273 DRMLISTDELINIT(&bo_gem->vma_list); 1274 1275 if (bo_gem->mem_virtual) { 1276 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size); 1277 bo_gem->mem_virtual = NULL; 1278 bufmgr_gem->vma_count--; 1279 } 1280 if (bo_gem->gtt_virtual) { 1281 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size); 1282 bo_gem->gtt_virtual = NULL; 1283 bufmgr_gem->vma_count--; 1284 } 1285 } 1286} 1287 1288static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem, 1289 drm_intel_bo_gem *bo_gem) 1290{ 1291 bufmgr_gem->vma_open--; 1292 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache); 1293 if (bo_gem->mem_virtual) 1294 bufmgr_gem->vma_count++; 1295 if (bo_gem->gtt_virtual) 1296 bufmgr_gem->vma_count++; 1297 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem); 1298} 1299 1300static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem, 1301 drm_intel_bo_gem *bo_gem) 1302{ 1303 bufmgr_gem->vma_open++; 1304 DRMLISTDEL(&bo_gem->vma_list); 1305 if (bo_gem->mem_virtual) 1306 bufmgr_gem->vma_count--; 1307 if (bo_gem->gtt_virtual) 1308 bufmgr_gem->vma_count--; 1309 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem); 1310} 1311 1312static void 1313drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time) 1314{ 1315 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1316 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1317 struct drm_intel_gem_bo_bucket *bucket; 1318 int i; 1319 1320 /* Unreference all the target buffers */ 1321 for (i = 0; i < bo_gem->reloc_count; i++) { 1322 if (bo_gem->reloc_target_info[i].bo != bo) { 1323 drm_intel_gem_bo_unreference_locked_timed(bo_gem-> 1324 reloc_target_info[i].bo, 1325 time); 1326 } 1327 } 1328 for (i = 0; i < bo_gem->softpin_target_count; i++) 1329 drm_intel_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i], 1330 time); 1331 bo_gem->reloc_count = 0; 1332 bo_gem->used_as_reloc_target = false; 1333 bo_gem->softpin_target_count = 0; 1334 1335 DBG("bo_unreference final: %d (%s)\n", 1336 bo_gem->gem_handle, bo_gem->name); 1337 1338 /* release memory associated with this object */ 1339 if (bo_gem->reloc_target_info) { 1340 free(bo_gem->reloc_target_info); 1341 bo_gem->reloc_target_info = NULL; 1342 } 1343 if (bo_gem->relocs) { 1344 free(bo_gem->relocs); 1345 bo_gem->relocs = NULL; 1346 } 1347 if (bo_gem->softpin_target) { 1348 free(bo_gem->softpin_target); 1349 bo_gem->softpin_target = NULL; 1350 bo_gem->softpin_target_size = 0; 1351 } 1352 1353 /* Clear any left-over mappings */ 1354 if (bo_gem->map_count) { 1355 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count); 1356 bo_gem->map_count = 0; 1357 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); 1358 drm_intel_gem_bo_mark_mmaps_incoherent(bo); 1359 } 1360 1361 DRMLISTDEL(&bo_gem->name_list); 1362 1363 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size); 1364 /* Put the buffer into our internal cache for reuse if we can. */ 1365 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL && 1366 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem, 1367 I915_MADV_DONTNEED)) { 1368 bo_gem->free_time = time; 1369 1370 bo_gem->name = NULL; 1371 bo_gem->validate_index = -1; 1372 1373 DRMLISTADDTAIL(&bo_gem->head, &bucket->head); 1374 } else { 1375 drm_intel_gem_bo_free(bo); 1376 } 1377} 1378 1379static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo, 1380 time_t time) 1381{ 1382 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1383 1384 assert(atomic_read(&bo_gem->refcount) > 0); 1385 if (atomic_dec_and_test(&bo_gem->refcount)) 1386 drm_intel_gem_bo_unreference_final(bo, time); 1387} 1388 1389static void drm_intel_gem_bo_unreference(drm_intel_bo *bo) 1390{ 1391 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1392 1393 assert(atomic_read(&bo_gem->refcount) > 0); 1394 1395 if (atomic_add_unless(&bo_gem->refcount, -1, 1)) { 1396 drm_intel_bufmgr_gem *bufmgr_gem = 1397 (drm_intel_bufmgr_gem *) bo->bufmgr; 1398 struct timespec time; 1399 1400 clock_gettime(CLOCK_MONOTONIC, &time); 1401 1402 pthread_mutex_lock(&bufmgr_gem->lock); 1403 1404 if (atomic_dec_and_test(&bo_gem->refcount)) { 1405 drm_intel_gem_bo_unreference_final(bo, time.tv_sec); 1406 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec); 1407 } 1408 1409 pthread_mutex_unlock(&bufmgr_gem->lock); 1410 } 1411} 1412 1413static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable) 1414{ 1415 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1416 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1417 struct drm_i915_gem_set_domain set_domain; 1418 int ret; 1419 1420 if (bo_gem->is_userptr) { 1421 /* Return the same user ptr */ 1422 bo->virtual = bo_gem->user_virtual; 1423 return 0; 1424 } 1425 1426 pthread_mutex_lock(&bufmgr_gem->lock); 1427 1428 if (bo_gem->map_count++ == 0) 1429 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem); 1430 1431 if (!bo_gem->mem_virtual) { 1432 struct drm_i915_gem_mmap mmap_arg; 1433 1434 DBG("bo_map: %d (%s), map_count=%d\n", 1435 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count); 1436 1437 memclear(mmap_arg); 1438 mmap_arg.handle = bo_gem->gem_handle; 1439 mmap_arg.size = bo->size; 1440 ret = drmIoctl(bufmgr_gem->fd, 1441 DRM_IOCTL_I915_GEM_MMAP, 1442 &mmap_arg); 1443 if (ret != 0) { 1444 ret = -errno; 1445 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n", 1446 __FILE__, __LINE__, bo_gem->gem_handle, 1447 bo_gem->name, strerror(errno)); 1448 if (--bo_gem->map_count == 0) 1449 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); 1450 pthread_mutex_unlock(&bufmgr_gem->lock); 1451 return ret; 1452 } 1453 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1)); 1454 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr; 1455 } 1456 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, 1457 bo_gem->mem_virtual); 1458 bo->virtual = bo_gem->mem_virtual; 1459 1460 memclear(set_domain); 1461 set_domain.handle = bo_gem->gem_handle; 1462 set_domain.read_domains = I915_GEM_DOMAIN_CPU; 1463 if (write_enable) 1464 set_domain.write_domain = I915_GEM_DOMAIN_CPU; 1465 else 1466 set_domain.write_domain = 0; 1467 ret = drmIoctl(bufmgr_gem->fd, 1468 DRM_IOCTL_I915_GEM_SET_DOMAIN, 1469 &set_domain); 1470 if (ret != 0) { 1471 DBG("%s:%d: Error setting to CPU domain %d: %s\n", 1472 __FILE__, __LINE__, bo_gem->gem_handle, 1473 strerror(errno)); 1474 } 1475 1476 if (write_enable) 1477 bo_gem->mapped_cpu_write = true; 1478 1479 drm_intel_gem_bo_mark_mmaps_incoherent(bo); 1480 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size)); 1481 pthread_mutex_unlock(&bufmgr_gem->lock); 1482 1483 return 0; 1484} 1485 1486static int 1487map_gtt(drm_intel_bo *bo) 1488{ 1489 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1490 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1491 int ret; 1492 1493 if (bo_gem->is_userptr) 1494 return -EINVAL; 1495 1496 if (bo_gem->map_count++ == 0) 1497 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem); 1498 1499 /* Get a mapping of the buffer if we haven't before. */ 1500 if (bo_gem->gtt_virtual == NULL) { 1501 struct drm_i915_gem_mmap_gtt mmap_arg; 1502 1503 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n", 1504 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count); 1505 1506 memclear(mmap_arg); 1507 mmap_arg.handle = bo_gem->gem_handle; 1508 1509 /* Get the fake offset back... */ 1510 ret = drmIoctl(bufmgr_gem->fd, 1511 DRM_IOCTL_I915_GEM_MMAP_GTT, 1512 &mmap_arg); 1513 if (ret != 0) { 1514 ret = -errno; 1515 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n", 1516 __FILE__, __LINE__, 1517 bo_gem->gem_handle, bo_gem->name, 1518 strerror(errno)); 1519 if (--bo_gem->map_count == 0) 1520 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); 1521 return ret; 1522 } 1523 1524 /* and mmap it */ 1525 bo_gem->gtt_virtual = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE, 1526 MAP_SHARED, bufmgr_gem->fd, 1527 mmap_arg.offset); 1528 if (bo_gem->gtt_virtual == MAP_FAILED) { 1529 bo_gem->gtt_virtual = NULL; 1530 ret = -errno; 1531 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n", 1532 __FILE__, __LINE__, 1533 bo_gem->gem_handle, bo_gem->name, 1534 strerror(errno)); 1535 if (--bo_gem->map_count == 0) 1536 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); 1537 return ret; 1538 } 1539 } 1540 1541 bo->virtual = bo_gem->gtt_virtual; 1542 1543 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, 1544 bo_gem->gtt_virtual); 1545 1546 return 0; 1547} 1548 1549int 1550drm_intel_gem_bo_map_gtt(drm_intel_bo *bo) 1551{ 1552 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1553 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1554 struct drm_i915_gem_set_domain set_domain; 1555 int ret; 1556 1557 pthread_mutex_lock(&bufmgr_gem->lock); 1558 1559 ret = map_gtt(bo); 1560 if (ret) { 1561 pthread_mutex_unlock(&bufmgr_gem->lock); 1562 return ret; 1563 } 1564 1565 /* Now move it to the GTT domain so that the GPU and CPU 1566 * caches are flushed and the GPU isn't actively using the 1567 * buffer. 1568 * 1569 * The pagefault handler does this domain change for us when 1570 * it has unbound the BO from the GTT, but it's up to us to 1571 * tell it when we're about to use things if we had done 1572 * rendering and it still happens to be bound to the GTT. 1573 */ 1574 memclear(set_domain); 1575 set_domain.handle = bo_gem->gem_handle; 1576 set_domain.read_domains = I915_GEM_DOMAIN_GTT; 1577 set_domain.write_domain = I915_GEM_DOMAIN_GTT; 1578 ret = drmIoctl(bufmgr_gem->fd, 1579 DRM_IOCTL_I915_GEM_SET_DOMAIN, 1580 &set_domain); 1581 if (ret != 0) { 1582 DBG("%s:%d: Error setting domain %d: %s\n", 1583 __FILE__, __LINE__, bo_gem->gem_handle, 1584 strerror(errno)); 1585 } 1586 1587 drm_intel_gem_bo_mark_mmaps_incoherent(bo); 1588 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size)); 1589 pthread_mutex_unlock(&bufmgr_gem->lock); 1590 1591 return 0; 1592} 1593 1594/** 1595 * Performs a mapping of the buffer object like the normal GTT 1596 * mapping, but avoids waiting for the GPU to be done reading from or 1597 * rendering to the buffer. 1598 * 1599 * This is used in the implementation of GL_ARB_map_buffer_range: The 1600 * user asks to create a buffer, then does a mapping, fills some 1601 * space, runs a drawing command, then asks to map it again without 1602 * synchronizing because it guarantees that it won't write over the 1603 * data that the GPU is busy using (or, more specifically, that if it 1604 * does write over the data, it acknowledges that rendering is 1605 * undefined). 1606 */ 1607 1608int 1609drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo) 1610{ 1611 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1612#ifdef HAVE_VALGRIND 1613 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1614#endif 1615 int ret; 1616 1617 /* If the CPU cache isn't coherent with the GTT, then use a 1618 * regular synchronized mapping. The problem is that we don't 1619 * track where the buffer was last used on the CPU side in 1620 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so 1621 * we would potentially corrupt the buffer even when the user 1622 * does reasonable things. 1623 */ 1624 if (!bufmgr_gem->has_llc) 1625 return drm_intel_gem_bo_map_gtt(bo); 1626 1627 pthread_mutex_lock(&bufmgr_gem->lock); 1628 1629 ret = map_gtt(bo); 1630 if (ret == 0) { 1631 drm_intel_gem_bo_mark_mmaps_incoherent(bo); 1632 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size)); 1633 } 1634 1635 pthread_mutex_unlock(&bufmgr_gem->lock); 1636 1637 return ret; 1638} 1639 1640static int drm_intel_gem_bo_unmap(drm_intel_bo *bo) 1641{ 1642 drm_intel_bufmgr_gem *bufmgr_gem; 1643 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1644 int ret = 0; 1645 1646 if (bo == NULL) 1647 return 0; 1648 1649 if (bo_gem->is_userptr) 1650 return 0; 1651 1652 bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1653 1654 pthread_mutex_lock(&bufmgr_gem->lock); 1655 1656 if (bo_gem->map_count <= 0) { 1657 DBG("attempted to unmap an unmapped bo\n"); 1658 pthread_mutex_unlock(&bufmgr_gem->lock); 1659 /* Preserve the old behaviour of just treating this as a 1660 * no-op rather than reporting the error. 1661 */ 1662 return 0; 1663 } 1664 1665 if (bo_gem->mapped_cpu_write) { 1666 struct drm_i915_gem_sw_finish sw_finish; 1667 1668 /* Cause a flush to happen if the buffer's pinned for 1669 * scanout, so the results show up in a timely manner. 1670 * Unlike GTT set domains, this only does work if the 1671 * buffer should be scanout-related. 1672 */ 1673 memclear(sw_finish); 1674 sw_finish.handle = bo_gem->gem_handle; 1675 ret = drmIoctl(bufmgr_gem->fd, 1676 DRM_IOCTL_I915_GEM_SW_FINISH, 1677 &sw_finish); 1678 ret = ret == -1 ? -errno : 0; 1679 1680 bo_gem->mapped_cpu_write = false; 1681 } 1682 1683 /* We need to unmap after every innovation as we cannot track 1684 * an open vma for every bo as that will exhaasut the system 1685 * limits and cause later failures. 1686 */ 1687 if (--bo_gem->map_count == 0) { 1688 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); 1689 drm_intel_gem_bo_mark_mmaps_incoherent(bo); 1690 bo->virtual = NULL; 1691 } 1692 pthread_mutex_unlock(&bufmgr_gem->lock); 1693 1694 return ret; 1695} 1696 1697int 1698drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo) 1699{ 1700 return drm_intel_gem_bo_unmap(bo); 1701} 1702 1703static int 1704drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset, 1705 unsigned long size, const void *data) 1706{ 1707 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1708 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1709 struct drm_i915_gem_pwrite pwrite; 1710 int ret; 1711 1712 if (bo_gem->is_userptr) 1713 return -EINVAL; 1714 1715 memclear(pwrite); 1716 pwrite.handle = bo_gem->gem_handle; 1717 pwrite.offset = offset; 1718 pwrite.size = size; 1719 pwrite.data_ptr = (uint64_t) (uintptr_t) data; 1720 ret = drmIoctl(bufmgr_gem->fd, 1721 DRM_IOCTL_I915_GEM_PWRITE, 1722 &pwrite); 1723 if (ret != 0) { 1724 ret = -errno; 1725 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n", 1726 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset, 1727 (int)size, strerror(errno)); 1728 } 1729 1730 return ret; 1731} 1732 1733static int 1734drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id) 1735{ 1736 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; 1737 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id; 1738 int ret; 1739 1740 memclear(get_pipe_from_crtc_id); 1741 get_pipe_from_crtc_id.crtc_id = crtc_id; 1742 ret = drmIoctl(bufmgr_gem->fd, 1743 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID, 1744 &get_pipe_from_crtc_id); 1745 if (ret != 0) { 1746 /* We return -1 here to signal that we don't 1747 * know which pipe is associated with this crtc. 1748 * This lets the caller know that this information 1749 * isn't available; using the wrong pipe for 1750 * vblank waiting can cause the chipset to lock up 1751 */ 1752 return -1; 1753 } 1754 1755 return get_pipe_from_crtc_id.pipe; 1756} 1757 1758static int 1759drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, 1760 unsigned long size, void *data) 1761{ 1762 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1763 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1764 struct drm_i915_gem_pread pread; 1765 int ret; 1766 1767 if (bo_gem->is_userptr) 1768 return -EINVAL; 1769 1770 memclear(pread); 1771 pread.handle = bo_gem->gem_handle; 1772 pread.offset = offset; 1773 pread.size = size; 1774 pread.data_ptr = (uint64_t) (uintptr_t) data; 1775 ret = drmIoctl(bufmgr_gem->fd, 1776 DRM_IOCTL_I915_GEM_PREAD, 1777 &pread); 1778 if (ret != 0) { 1779 ret = -errno; 1780 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n", 1781 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset, 1782 (int)size, strerror(errno)); 1783 } 1784 1785 return ret; 1786} 1787 1788/** Waits for all GPU rendering with the object to have completed. */ 1789static void 1790drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo) 1791{ 1792 drm_intel_gem_bo_start_gtt_access(bo, 1); 1793} 1794 1795/** 1796 * Waits on a BO for the given amount of time. 1797 * 1798 * @bo: buffer object to wait for 1799 * @timeout_ns: amount of time to wait in nanoseconds. 1800 * If value is less than 0, an infinite wait will occur. 1801 * 1802 * Returns 0 if the wait was successful ie. the last batch referencing the 1803 * object has completed within the allotted time. Otherwise some negative return 1804 * value describes the error. Of particular interest is -ETIME when the wait has 1805 * failed to yield the desired result. 1806 * 1807 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows 1808 * the operation to give up after a certain amount of time. Another subtle 1809 * difference is the internal locking semantics are different (this variant does 1810 * not hold the lock for the duration of the wait). This makes the wait subject 1811 * to a larger userspace race window. 1812 * 1813 * The implementation shall wait until the object is no longer actively 1814 * referenced within a batch buffer at the time of the call. The wait will 1815 * not guarantee that the buffer is re-issued via another thread, or an flinked 1816 * handle. Userspace must make sure this race does not occur if such precision 1817 * is important. 1818 * 1819 * Note that some kernels have broken the inifite wait for negative values 1820 * promise, upgrade to latest stable kernels if this is the case. 1821 */ 1822int 1823drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns) 1824{ 1825 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1826 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1827 struct drm_i915_gem_wait wait; 1828 int ret; 1829 1830 if (!bufmgr_gem->has_wait_timeout) { 1831 DBG("%s:%d: Timed wait is not supported. Falling back to " 1832 "infinite wait\n", __FILE__, __LINE__); 1833 if (timeout_ns) { 1834 drm_intel_gem_bo_wait_rendering(bo); 1835 return 0; 1836 } else { 1837 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0; 1838 } 1839 } 1840 1841 memclear(wait); 1842 wait.bo_handle = bo_gem->gem_handle; 1843 wait.timeout_ns = timeout_ns; 1844 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait); 1845 if (ret == -1) 1846 return -errno; 1847 1848 return ret; 1849} 1850 1851/** 1852 * Sets the object to the GTT read and possibly write domain, used by the X 1853 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt(). 1854 * 1855 * In combination with drm_intel_gem_bo_pin() and manual fence management, we 1856 * can do tiled pixmaps this way. 1857 */ 1858void 1859drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable) 1860{ 1861 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1862 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1863 struct drm_i915_gem_set_domain set_domain; 1864 int ret; 1865 1866 memclear(set_domain); 1867 set_domain.handle = bo_gem->gem_handle; 1868 set_domain.read_domains = I915_GEM_DOMAIN_GTT; 1869 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0; 1870 ret = drmIoctl(bufmgr_gem->fd, 1871 DRM_IOCTL_I915_GEM_SET_DOMAIN, 1872 &set_domain); 1873 if (ret != 0) { 1874 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n", 1875 __FILE__, __LINE__, bo_gem->gem_handle, 1876 set_domain.read_domains, set_domain.write_domain, 1877 strerror(errno)); 1878 } 1879} 1880 1881static void 1882drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr) 1883{ 1884 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; 1885 struct drm_gem_close close_bo; 1886 int i, ret; 1887 1888 free(bufmgr_gem->exec2_objects); 1889 free(bufmgr_gem->exec_objects); 1890 free(bufmgr_gem->exec_bos); 1891 1892 pthread_mutex_destroy(&bufmgr_gem->lock); 1893 1894 /* Free any cached buffer objects we were going to reuse */ 1895 for (i = 0; i < bufmgr_gem->num_buckets; i++) { 1896 struct drm_intel_gem_bo_bucket *bucket = 1897 &bufmgr_gem->cache_bucket[i]; 1898 drm_intel_bo_gem *bo_gem; 1899 1900 while (!DRMLISTEMPTY(&bucket->head)) { 1901 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, 1902 bucket->head.next, head); 1903 DRMLISTDEL(&bo_gem->head); 1904 1905 drm_intel_gem_bo_free(&bo_gem->bo); 1906 } 1907 } 1908 1909 /* Release userptr bo kept hanging around for optimisation. */ 1910 if (bufmgr_gem->userptr_active.ptr) { 1911 memclear(close_bo); 1912 close_bo.handle = bufmgr_gem->userptr_active.handle; 1913 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close_bo); 1914 free(bufmgr_gem->userptr_active.ptr); 1915 if (ret) 1916 fprintf(stderr, 1917 "Failed to release test userptr object! (%d) " 1918 "i915 kernel driver may not be sane!\n", errno); 1919 } 1920 1921 free(bufmgr); 1922} 1923 1924/** 1925 * Adds the target buffer to the validation list and adds the relocation 1926 * to the reloc_buffer's relocation list. 1927 * 1928 * The relocation entry at the given offset must already contain the 1929 * precomputed relocation value, because the kernel will optimize out 1930 * the relocation entry write when the buffer hasn't moved from the 1931 * last known offset in target_bo. 1932 */ 1933static int 1934do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, 1935 drm_intel_bo *target_bo, uint32_t target_offset, 1936 uint32_t read_domains, uint32_t write_domain, 1937 bool need_fence) 1938{ 1939 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1940 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1941 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo; 1942 bool fenced_command; 1943 1944 if (bo_gem->has_error) 1945 return -ENOMEM; 1946 1947 if (target_bo_gem->has_error) { 1948 bo_gem->has_error = true; 1949 return -ENOMEM; 1950 } 1951 1952 /* We never use HW fences for rendering on 965+ */ 1953 if (bufmgr_gem->gen >= 4) 1954 need_fence = false; 1955 1956 fenced_command = need_fence; 1957 if (target_bo_gem->tiling_mode == I915_TILING_NONE) 1958 need_fence = false; 1959 1960 /* Create a new relocation list if needed */ 1961 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo)) 1962 return -ENOMEM; 1963 1964 /* Check overflow */ 1965 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs); 1966 1967 /* Check args */ 1968 assert(offset <= bo->size - 4); 1969 assert((write_domain & (write_domain - 1)) == 0); 1970 1971 /* An object needing a fence is a tiled buffer, so it won't have 1972 * relocs to other buffers. 1973 */ 1974 if (need_fence) { 1975 assert(target_bo_gem->reloc_count == 0); 1976 target_bo_gem->reloc_tree_fences = 1; 1977 } 1978 1979 /* Make sure that we're not adding a reloc to something whose size has 1980 * already been accounted for. 1981 */ 1982 assert(!bo_gem->used_as_reloc_target); 1983 if (target_bo_gem != bo_gem) { 1984 target_bo_gem->used_as_reloc_target = true; 1985 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size; 1986 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences; 1987 } 1988 1989 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo; 1990 if (target_bo != bo) 1991 drm_intel_gem_bo_reference(target_bo); 1992 if (fenced_command) 1993 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 1994 DRM_INTEL_RELOC_FENCE; 1995 else 1996 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0; 1997 1998 bo_gem->relocs[bo_gem->reloc_count].offset = offset; 1999 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset; 2000 bo_gem->relocs[bo_gem->reloc_count].target_handle = 2001 target_bo_gem->gem_handle; 2002 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains; 2003 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain; 2004 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64; 2005 bo_gem->reloc_count++; 2006 2007 return 0; 2008} 2009 2010static void 2011drm_intel_gem_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable) 2012{ 2013 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2014 bo_gem->use_48b_address_range = enable; 2015} 2016 2017static int 2018drm_intel_gem_bo_add_softpin_target(drm_intel_bo *bo, drm_intel_bo *target_bo) 2019{ 2020 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 2021 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2022 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo; 2023 if (bo_gem->has_error) 2024 return -ENOMEM; 2025 2026 if (target_bo_gem->has_error) { 2027 bo_gem->has_error = true; 2028 return -ENOMEM; 2029 } 2030 2031 if (!target_bo_gem->is_softpin) 2032 return -EINVAL; 2033 if (target_bo_gem == bo_gem) 2034 return -EINVAL; 2035 2036 if (bo_gem->softpin_target_count == bo_gem->softpin_target_size) { 2037 int new_size = bo_gem->softpin_target_size * 2; 2038 if (new_size == 0) 2039 new_size = bufmgr_gem->max_relocs; 2040 2041 bo_gem->softpin_target = realloc(bo_gem->softpin_target, new_size * 2042 sizeof(drm_intel_bo *)); 2043 if (!bo_gem->softpin_target) 2044 return -ENOMEM; 2045 2046 bo_gem->softpin_target_size = new_size; 2047 } 2048 bo_gem->softpin_target[bo_gem->softpin_target_count] = target_bo; 2049 drm_intel_gem_bo_reference(target_bo); 2050 bo_gem->softpin_target_count++; 2051 2052 return 0; 2053} 2054 2055static int 2056drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, 2057 drm_intel_bo *target_bo, uint32_t target_offset, 2058 uint32_t read_domains, uint32_t write_domain) 2059{ 2060 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; 2061 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *)target_bo; 2062 2063 if (target_bo_gem->is_softpin) 2064 return drm_intel_gem_bo_add_softpin_target(bo, target_bo); 2065 else 2066 return do_bo_emit_reloc(bo, offset, target_bo, target_offset, 2067 read_domains, write_domain, 2068 !bufmgr_gem->fenced_relocs); 2069} 2070 2071static int 2072drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, 2073 drm_intel_bo *target_bo, 2074 uint32_t target_offset, 2075 uint32_t read_domains, uint32_t write_domain) 2076{ 2077 return do_bo_emit_reloc(bo, offset, target_bo, target_offset, 2078 read_domains, write_domain, true); 2079} 2080 2081int 2082drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo) 2083{ 2084 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2085 2086 return bo_gem->reloc_count; 2087} 2088 2089/** 2090 * Removes existing relocation entries in the BO after "start". 2091 * 2092 * This allows a user to avoid a two-step process for state setup with 2093 * counting up all the buffer objects and doing a 2094 * drm_intel_bufmgr_check_aperture_space() before emitting any of the 2095 * relocations for the state setup. Instead, save the state of the 2096 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the 2097 * state, and then check if it still fits in the aperture. 2098 * 2099 * Any further drm_intel_bufmgr_check_aperture_space() queries 2100 * involving this buffer in the tree are undefined after this call. 2101 * 2102 * This also removes all softpinned targets being referenced by the BO. 2103 */ 2104void 2105drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start) 2106{ 2107 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 2108 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2109 int i; 2110 struct timespec time; 2111 2112 clock_gettime(CLOCK_MONOTONIC, &time); 2113 2114 assert(bo_gem->reloc_count >= start); 2115 2116 /* Unreference the cleared target buffers */ 2117 pthread_mutex_lock(&bufmgr_gem->lock); 2118 2119 for (i = start; i < bo_gem->reloc_count; i++) { 2120 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo; 2121 if (&target_bo_gem->bo != bo) { 2122 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences; 2123 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo, 2124 time.tv_sec); 2125 } 2126 } 2127 bo_gem->reloc_count = start; 2128 2129 for (i = 0; i < bo_gem->softpin_target_count; i++) { 2130 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->softpin_target[i]; 2131 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo, time.tv_sec); 2132 } 2133 bo_gem->softpin_target_count = 0; 2134 2135 pthread_mutex_unlock(&bufmgr_gem->lock); 2136 2137} 2138 2139/** 2140 * Walk the tree of relocations rooted at BO and accumulate the list of 2141 * validations to be performed and update the relocation buffers with 2142 * index values into the validation list. 2143 */ 2144static void 2145drm_intel_gem_bo_process_reloc(drm_intel_bo *bo) 2146{ 2147 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2148 int i; 2149 2150 if (bo_gem->relocs == NULL) 2151 return; 2152 2153 for (i = 0; i < bo_gem->reloc_count; i++) { 2154 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo; 2155 2156 if (target_bo == bo) 2157 continue; 2158 2159 drm_intel_gem_bo_mark_mmaps_incoherent(bo); 2160 2161 /* Continue walking the tree depth-first. */ 2162 drm_intel_gem_bo_process_reloc(target_bo); 2163 2164 /* Add the target to the validate list */ 2165 drm_intel_add_validate_buffer(target_bo); 2166 } 2167} 2168 2169static void 2170drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo) 2171{ 2172 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; 2173 int i; 2174 2175 if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL) 2176 return; 2177 2178 for (i = 0; i < bo_gem->reloc_count; i++) { 2179 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo; 2180 int need_fence; 2181 2182 if (target_bo == bo) 2183 continue; 2184 2185 drm_intel_gem_bo_mark_mmaps_incoherent(bo); 2186 2187 /* Continue walking the tree depth-first. */ 2188 drm_intel_gem_bo_process_reloc2(target_bo); 2189 2190 need_fence = (bo_gem->reloc_target_info[i].flags & 2191 DRM_INTEL_RELOC_FENCE); 2192 2193 /* Add the target to the validate list */ 2194 drm_intel_add_validate_buffer2(target_bo, need_fence); 2195 } 2196 2197 for (i = 0; i < bo_gem->softpin_target_count; i++) { 2198 drm_intel_bo *target_bo = bo_gem->softpin_target[i]; 2199 2200 if (target_bo == bo) 2201 continue; 2202 2203 drm_intel_gem_bo_mark_mmaps_incoherent(bo); 2204 drm_intel_gem_bo_process_reloc2(target_bo); 2205 drm_intel_add_validate_buffer2(target_bo, false); 2206 } 2207} 2208 2209 2210static void 2211drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem) 2212{ 2213 int i; 2214 2215 for (i = 0; i < bufmgr_gem->exec_count; i++) { 2216 drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; 2217 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2218 2219 /* Update the buffer offset */ 2220 if (bufmgr_gem->exec_objects[i].offset != bo->offset64) { 2221 DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n", 2222 bo_gem->gem_handle, bo_gem->name, 2223 upper_32_bits(bo->offset64), 2224 lower_32_bits(bo->offset64), 2225 upper_32_bits(bufmgr_gem->exec_objects[i].offset), 2226 lower_32_bits(bufmgr_gem->exec_objects[i].offset)); 2227 bo->offset64 = bufmgr_gem->exec_objects[i].offset; 2228 bo->offset = bufmgr_gem->exec_objects[i].offset; 2229 } 2230 } 2231} 2232 2233static void 2234drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem) 2235{ 2236 int i; 2237 2238 for (i = 0; i < bufmgr_gem->exec_count; i++) { 2239 drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; 2240 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; 2241 2242 /* Update the buffer offset */ 2243 if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) { 2244 /* If we're seeing softpinned object here it means that the kernel 2245 * has relocated our object... Indicating a programming error 2246 */ 2247 assert(!bo_gem->is_softpin); 2248 DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n", 2249 bo_gem->gem_handle, bo_gem->name, 2250 upper_32_bits(bo->offset64), 2251 lower_32_bits(bo->offset64), 2252 upper_32_bits(bufmgr_gem->exec2_objects[i].offset), 2253 lower_32_bits(bufmgr_gem->exec2_objects[i].offset)); 2254 bo->offset64 = bufmgr_gem->exec2_objects[i].offset; 2255 bo->offset = bufmgr_gem->exec2_objects[i].offset; 2256 } 2257 } 2258} 2259 2260void 2261drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo, 2262 int x1, int y1, int width, int height, 2263 enum aub_dump_bmp_format format, 2264 int pitch, int offset) 2265{ 2266} 2267 2268static int 2269drm_intel_gem_bo_exec(drm_intel_bo *bo, int used, 2270 drm_clip_rect_t * cliprects, int num_cliprects, int DR4) 2271{ 2272 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 2273 struct drm_i915_gem_execbuffer execbuf; 2274 int ret, i; 2275 2276 if (to_bo_gem(bo)->has_error) 2277 return -ENOMEM; 2278 2279 pthread_mutex_lock(&bufmgr_gem->lock); 2280 /* Update indices and set up the validate list. */ 2281 drm_intel_gem_bo_process_reloc(bo); 2282 2283 /* Add the batch buffer to the validation list. There are no 2284 * relocations pointing to it. 2285 */ 2286 drm_intel_add_validate_buffer(bo); 2287 2288 memclear(execbuf); 2289 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects; 2290 execbuf.buffer_count = bufmgr_gem->exec_count; 2291 execbuf.batch_start_offset = 0; 2292 execbuf.batch_len = used; 2293 execbuf.cliprects_ptr = (uintptr_t) cliprects; 2294 execbuf.num_cliprects = num_cliprects; 2295 execbuf.DR1 = 0; 2296 execbuf.DR4 = DR4; 2297 2298 ret = drmIoctl(bufmgr_gem->fd, 2299 DRM_IOCTL_I915_GEM_EXECBUFFER, 2300 &execbuf); 2301 if (ret != 0) { 2302 ret = -errno; 2303 if (errno == ENOSPC) { 2304 DBG("Execbuffer fails to pin. " 2305 "Estimate: %u. Actual: %u. Available: %u\n", 2306 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos, 2307 bufmgr_gem-> 2308 exec_count), 2309 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos, 2310 bufmgr_gem-> 2311 exec_count), 2312 (unsigned int)bufmgr_gem->gtt_size); 2313 } 2314 } 2315 drm_intel_update_buffer_offsets(bufmgr_gem); 2316 2317 if (bufmgr_gem->bufmgr.debug) 2318 drm_intel_gem_dump_validation_list(bufmgr_gem); 2319 2320 for (i = 0; i < bufmgr_gem->exec_count; i++) { 2321 drm_intel_bo_gem *bo_gem = to_bo_gem(bufmgr_gem->exec_bos[i]); 2322 2323 bo_gem->idle = false; 2324 2325 /* Disconnect the buffer from the validate list */ 2326 bo_gem->validate_index = -1; 2327 bufmgr_gem->exec_bos[i] = NULL; 2328 } 2329 bufmgr_gem->exec_count = 0; 2330 pthread_mutex_unlock(&bufmgr_gem->lock); 2331 2332 return ret; 2333} 2334 2335static int 2336do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx, 2337 drm_clip_rect_t *cliprects, int num_cliprects, int DR4, 2338 unsigned int flags) 2339{ 2340 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; 2341 struct drm_i915_gem_execbuffer2 execbuf; 2342 int ret = 0; 2343 int i; 2344 2345 if (to_bo_gem(bo)->has_error) 2346 return -ENOMEM; 2347 2348 switch (flags & 0x7) { 2349 default: 2350 return -EINVAL; 2351 case I915_EXEC_BLT: 2352 if (!bufmgr_gem->has_blt) 2353 return -EINVAL; 2354 break; 2355 case I915_EXEC_BSD: 2356 if (!bufmgr_gem->has_bsd) 2357 return -EINVAL; 2358 break; 2359 case I915_EXEC_VEBOX: 2360 if (!bufmgr_gem->has_vebox) 2361 return -EINVAL; 2362 break; 2363 case I915_EXEC_RENDER: 2364 case I915_EXEC_DEFAULT: 2365 break; 2366 } 2367 2368 pthread_mutex_lock(&bufmgr_gem->lock); 2369 /* Update indices and set up the validate list. */ 2370 drm_intel_gem_bo_process_reloc2(bo); 2371 2372 /* Add the batch buffer to the validation list. There are no relocations 2373 * pointing to it. 2374 */ 2375 drm_intel_add_validate_buffer2(bo, 0); 2376 2377 memclear(execbuf); 2378 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects; 2379 execbuf.buffer_count = bufmgr_gem->exec_count; 2380 execbuf.batch_start_offset = 0; 2381 execbuf.batch_len = used; 2382 execbuf.cliprects_ptr = (uintptr_t)cliprects; 2383 execbuf.num_cliprects = num_cliprects; 2384 execbuf.DR1 = 0; 2385 execbuf.DR4 = DR4; 2386 execbuf.flags = flags; 2387 if (ctx == NULL) 2388 i915_execbuffer2_set_context_id(execbuf, 0); 2389 else 2390 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id); 2391 execbuf.rsvd2 = 0; 2392 2393 if (bufmgr_gem->no_exec) 2394 goto skip_execution; 2395 2396 ret = drmIoctl(bufmgr_gem->fd, 2397 DRM_IOCTL_I915_GEM_EXECBUFFER2, 2398 &execbuf); 2399 if (ret != 0) { 2400 ret = -errno; 2401 if (ret == -ENOSPC) { 2402 DBG("Execbuffer fails to pin. " 2403 "Estimate: %u. Actual: %u. Available: %u\n", 2404 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos, 2405 bufmgr_gem->exec_count), 2406 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos, 2407 bufmgr_gem->exec_count), 2408 (unsigned int) bufmgr_gem->gtt_size); 2409 } 2410 } 2411 drm_intel_update_buffer_offsets2(bufmgr_gem); 2412 2413skip_execution: 2414 if (bufmgr_gem->bufmgr.debug) 2415 drm_intel_gem_dump_validation_list(bufmgr_gem); 2416 2417 for (i = 0; i < bufmgr_gem->exec_count; i++) { 2418 drm_intel_bo_gem *bo_gem = to_bo_gem(bufmgr_gem->exec_bos[i]); 2419 2420 bo_gem->idle = false; 2421 2422 /* Disconnect the buffer from the validate list */ 2423 bo_gem->validate_index = -1; 2424 bufmgr_gem->exec_bos[i] = NULL; 2425 } 2426 bufmgr_gem->exec_count = 0; 2427 pthread_mutex_unlock(&bufmgr_gem->lock); 2428 2429 return ret; 2430} 2431 2432static int 2433drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used, 2434 drm_clip_rect_t *cliprects, int num_cliprects, 2435 int DR4) 2436{ 2437 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4, 2438 I915_EXEC_RENDER); 2439} 2440 2441static int 2442drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, 2443 drm_clip_rect_t *cliprects, int num_cliprects, int DR4, 2444 unsigned int flags) 2445{ 2446 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4, 2447 flags); 2448} 2449 2450int 2451drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx, 2452 int used, unsigned int flags) 2453{ 2454 return do_exec2(bo, used, ctx, NULL, 0, 0, flags); 2455} 2456 2457static int 2458drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment) 2459{ 2460 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 2461 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2462 struct drm_i915_gem_pin pin; 2463 int ret; 2464 2465 memclear(pin); 2466 pin.handle = bo_gem->gem_handle; 2467 pin.alignment = alignment; 2468 2469 ret = drmIoctl(bufmgr_gem->fd, 2470 DRM_IOCTL_I915_GEM_PIN, 2471 &pin); 2472 if (ret != 0) 2473 return -errno; 2474 2475 bo->offset64 = pin.offset; 2476 bo->offset = pin.offset; 2477 return 0; 2478} 2479 2480static int 2481drm_intel_gem_bo_unpin(drm_intel_bo *bo) 2482{ 2483 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 2484 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2485 struct drm_i915_gem_unpin unpin; 2486 int ret; 2487 2488 memclear(unpin); 2489 unpin.handle = bo_gem->gem_handle; 2490 2491 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin); 2492 if (ret != 0) 2493 return -errno; 2494 2495 return 0; 2496} 2497 2498static int 2499drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo, 2500 uint32_t tiling_mode, 2501 uint32_t stride) 2502{ 2503 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 2504 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2505 struct drm_i915_gem_set_tiling set_tiling; 2506 int ret; 2507 2508 if (bo_gem->global_name == 0 && 2509 tiling_mode == bo_gem->tiling_mode && 2510 stride == bo_gem->stride) 2511 return 0; 2512 2513 memset(&set_tiling, 0, sizeof(set_tiling)); 2514 do { 2515 /* set_tiling is slightly broken and overwrites the 2516 * input on the error path, so we have to open code 2517 * rmIoctl. 2518 */ 2519 set_tiling.handle = bo_gem->gem_handle; 2520 set_tiling.tiling_mode = tiling_mode; 2521 set_tiling.stride = stride; 2522 2523 ret = ioctl(bufmgr_gem->fd, 2524 DRM_IOCTL_I915_GEM_SET_TILING, 2525 &set_tiling); 2526 } while (ret == -1 && (errno == EINTR || errno == EAGAIN)); 2527 if (ret == -1) 2528 return -errno; 2529 2530 bo_gem->tiling_mode = set_tiling.tiling_mode; 2531 bo_gem->swizzle_mode = set_tiling.swizzle_mode; 2532 bo_gem->stride = set_tiling.stride; 2533 return 0; 2534} 2535 2536static int 2537drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 2538 uint32_t stride) 2539{ 2540 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 2541 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2542 int ret; 2543 2544 /* Tiling with userptr surfaces is not supported 2545 * on all hardware so refuse it for time being. 2546 */ 2547 if (bo_gem->is_userptr) 2548 return -EINVAL; 2549 2550 /* Linear buffers have no stride. By ensuring that we only ever use 2551 * stride 0 with linear buffers, we simplify our code. 2552 */ 2553 if (*tiling_mode == I915_TILING_NONE) 2554 stride = 0; 2555 2556 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride); 2557 if (ret == 0) 2558 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0); 2559 2560 *tiling_mode = bo_gem->tiling_mode; 2561 return ret; 2562} 2563 2564static int 2565drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 2566 uint32_t * swizzle_mode) 2567{ 2568 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2569 2570 *tiling_mode = bo_gem->tiling_mode; 2571 *swizzle_mode = bo_gem->swizzle_mode; 2572 return 0; 2573} 2574 2575static int 2576drm_intel_gem_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset) 2577{ 2578 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2579 2580 bo_gem->is_softpin = true; 2581 bo->offset64 = offset; 2582 bo->offset = offset; 2583 return 0; 2584} 2585 2586drm_intel_bo * 2587drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size) 2588{ 2589 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; 2590 int ret; 2591 uint32_t handle; 2592 drm_intel_bo_gem *bo_gem; 2593 struct drm_i915_gem_get_tiling get_tiling; 2594 drmMMListHead *list; 2595 2596 pthread_mutex_lock(&bufmgr_gem->lock); 2597 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle); 2598 if (ret) { 2599 DBG("create_from_prime: failed to obtain handle from fd: %s\n", strerror(errno)); 2600 pthread_mutex_unlock(&bufmgr_gem->lock); 2601 return NULL; 2602 } 2603 2604 /* 2605 * See if the kernel has already returned this buffer to us. Just as 2606 * for named buffers, we must not create two bo's pointing at the same 2607 * kernel object 2608 */ 2609 for (list = bufmgr_gem->named.next; 2610 list != &bufmgr_gem->named; 2611 list = list->next) { 2612 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list); 2613 if (bo_gem->gem_handle == handle) { 2614 drm_intel_gem_bo_reference(&bo_gem->bo); 2615 pthread_mutex_unlock(&bufmgr_gem->lock); 2616 return &bo_gem->bo; 2617 } 2618 } 2619 2620 bo_gem = calloc(1, sizeof(*bo_gem)); 2621 if (!bo_gem) { 2622 pthread_mutex_unlock(&bufmgr_gem->lock); 2623 return NULL; 2624 } 2625 /* Determine size of bo. The fd-to-handle ioctl really should 2626 * return the size, but it doesn't. If we have kernel 3.12 or 2627 * later, we can lseek on the prime fd to get the size. Older 2628 * kernels will just fail, in which case we fall back to the 2629 * provided (estimated or guess size). */ 2630 ret = lseek(prime_fd, 0, SEEK_END); 2631 if (ret != -1) 2632 bo_gem->bo.size = ret; 2633 else 2634 bo_gem->bo.size = size; 2635 2636 bo_gem->bo.handle = handle; 2637 bo_gem->bo.bufmgr = bufmgr; 2638 2639 bo_gem->gem_handle = handle; 2640 2641 atomic_set(&bo_gem->refcount, 1); 2642 2643 bo_gem->name = "prime"; 2644 bo_gem->validate_index = -1; 2645 bo_gem->reloc_tree_fences = 0; 2646 bo_gem->used_as_reloc_target = false; 2647 bo_gem->has_error = false; 2648 bo_gem->reusable = false; 2649 bo_gem->use_48b_address_range = false; 2650 2651 DRMINITLISTHEAD(&bo_gem->vma_list); 2652 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named); 2653 pthread_mutex_unlock(&bufmgr_gem->lock); 2654 2655 memclear(get_tiling); 2656 get_tiling.handle = bo_gem->gem_handle; 2657 ret = drmIoctl(bufmgr_gem->fd, 2658 DRM_IOCTL_I915_GEM_GET_TILING, 2659 &get_tiling); 2660 if (ret != 0) { 2661 DBG("create_from_prime: failed to get tiling: %s\n", strerror(errno)); 2662 drm_intel_gem_bo_unreference(&bo_gem->bo); 2663 return NULL; 2664 } 2665 bo_gem->tiling_mode = get_tiling.tiling_mode; 2666 bo_gem->swizzle_mode = get_tiling.swizzle_mode; 2667 /* XXX stride is unknown */ 2668 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0); 2669 2670 return &bo_gem->bo; 2671} 2672 2673int 2674drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd) 2675{ 2676 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 2677 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2678 2679 pthread_mutex_lock(&bufmgr_gem->lock); 2680 if (DRMLISTEMPTY(&bo_gem->name_list)) 2681 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named); 2682 pthread_mutex_unlock(&bufmgr_gem->lock); 2683 2684 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle, 2685 DRM_CLOEXEC, prime_fd) != 0) 2686 return -errno; 2687 2688 bo_gem->reusable = false; 2689 2690 return 0; 2691} 2692 2693static int 2694drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name) 2695{ 2696 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 2697 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2698 int ret; 2699 2700 if (!bo_gem->global_name) { 2701 struct drm_gem_flink flink; 2702 2703 memclear(flink); 2704 flink.handle = bo_gem->gem_handle; 2705 2706 pthread_mutex_lock(&bufmgr_gem->lock); 2707 2708 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink); 2709 if (ret != 0) { 2710 pthread_mutex_unlock(&bufmgr_gem->lock); 2711 return -errno; 2712 } 2713 2714 bo_gem->global_name = flink.name; 2715 bo_gem->reusable = false; 2716 2717 if (DRMLISTEMPTY(&bo_gem->name_list)) 2718 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named); 2719 pthread_mutex_unlock(&bufmgr_gem->lock); 2720 } 2721 2722 *name = bo_gem->global_name; 2723 return 0; 2724} 2725 2726/** 2727 * Enables unlimited caching of buffer objects for reuse. 2728 * 2729 * This is potentially very memory expensive, as the cache at each bucket 2730 * size is only bounded by how many buffers of that size we've managed to have 2731 * in flight at once. 2732 */ 2733void 2734drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr) 2735{ 2736 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; 2737 2738 bufmgr_gem->bo_reuse = true; 2739} 2740 2741/** 2742 * Enable use of fenced reloc type. 2743 * 2744 * New code should enable this to avoid unnecessary fence register 2745 * allocation. If this option is not enabled, all relocs will have fence 2746 * register allocated. 2747 */ 2748void 2749drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr) 2750{ 2751 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; 2752 2753 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2) 2754 bufmgr_gem->fenced_relocs = true; 2755} 2756 2757/** 2758 * Return the additional aperture space required by the tree of buffer objects 2759 * rooted at bo. 2760 */ 2761static int 2762drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo) 2763{ 2764 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2765 int i; 2766 int total = 0; 2767 2768 if (bo == NULL || bo_gem->included_in_check_aperture) 2769 return 0; 2770 2771 total += bo->size; 2772 bo_gem->included_in_check_aperture = true; 2773 2774 for (i = 0; i < bo_gem->reloc_count; i++) 2775 total += 2776 drm_intel_gem_bo_get_aperture_space(bo_gem-> 2777 reloc_target_info[i].bo); 2778 2779 return total; 2780} 2781 2782/** 2783 * Count the number of buffers in this list that need a fence reg 2784 * 2785 * If the count is greater than the number of available regs, we'll have 2786 * to ask the caller to resubmit a batch with fewer tiled buffers. 2787 * 2788 * This function over-counts if the same buffer is used multiple times. 2789 */ 2790static unsigned int 2791drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count) 2792{ 2793 int i; 2794 unsigned int total = 0; 2795 2796 for (i = 0; i < count; i++) { 2797 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i]; 2798 2799 if (bo_gem == NULL) 2800 continue; 2801 2802 total += bo_gem->reloc_tree_fences; 2803 } 2804 return total; 2805} 2806 2807/** 2808 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready 2809 * for the next drm_intel_bufmgr_check_aperture_space() call. 2810 */ 2811static void 2812drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo) 2813{ 2814 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2815 int i; 2816 2817 if (bo == NULL || !bo_gem->included_in_check_aperture) 2818 return; 2819 2820 bo_gem->included_in_check_aperture = false; 2821 2822 for (i = 0; i < bo_gem->reloc_count; i++) 2823 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem-> 2824 reloc_target_info[i].bo); 2825} 2826 2827/** 2828 * Return a conservative estimate for the amount of aperture required 2829 * for a collection of buffers. This may double-count some buffers. 2830 */ 2831static unsigned int 2832drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count) 2833{ 2834 int i; 2835 unsigned int total = 0; 2836 2837 for (i = 0; i < count; i++) { 2838 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i]; 2839 if (bo_gem != NULL) 2840 total += bo_gem->reloc_tree_size; 2841 } 2842 return total; 2843} 2844 2845/** 2846 * Return the amount of aperture needed for a collection of buffers. 2847 * This avoids double counting any buffers, at the cost of looking 2848 * at every buffer in the set. 2849 */ 2850static unsigned int 2851drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count) 2852{ 2853 int i; 2854 unsigned int total = 0; 2855 2856 for (i = 0; i < count; i++) { 2857 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]); 2858 /* For the first buffer object in the array, we get an 2859 * accurate count back for its reloc_tree size (since nothing 2860 * had been flagged as being counted yet). We can save that 2861 * value out as a more conservative reloc_tree_size that 2862 * avoids double-counting target buffers. Since the first 2863 * buffer happens to usually be the batch buffer in our 2864 * callers, this can pull us back from doing the tree 2865 * walk on every new batch emit. 2866 */ 2867 if (i == 0) { 2868 drm_intel_bo_gem *bo_gem = 2869 (drm_intel_bo_gem *) bo_array[i]; 2870 bo_gem->reloc_tree_size = total; 2871 } 2872 } 2873 2874 for (i = 0; i < count; i++) 2875 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]); 2876 return total; 2877} 2878 2879/** 2880 * Return -1 if the batchbuffer should be flushed before attempting to 2881 * emit rendering referencing the buffers pointed to by bo_array. 2882 * 2883 * This is required because if we try to emit a batchbuffer with relocations 2884 * to a tree of buffers that won't simultaneously fit in the aperture, 2885 * the rendering will return an error at a point where the software is not 2886 * prepared to recover from it. 2887 * 2888 * However, we also want to emit the batchbuffer significantly before we reach 2889 * the limit, as a series of batchbuffers each of which references buffers 2890 * covering almost all of the aperture means that at each emit we end up 2891 * waiting to evict a buffer from the last rendering, and we get synchronous 2892 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to 2893 * get better parallelism. 2894 */ 2895static int 2896drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count) 2897{ 2898 drm_intel_bufmgr_gem *bufmgr_gem = 2899 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr; 2900 unsigned int total = 0; 2901 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4; 2902 int total_fences; 2903 2904 /* Check for fence reg constraints if necessary */ 2905 if (bufmgr_gem->available_fences) { 2906 total_fences = drm_intel_gem_total_fences(bo_array, count); 2907 if (total_fences > bufmgr_gem->available_fences) 2908 return -ENOSPC; 2909 } 2910 2911 total = drm_intel_gem_estimate_batch_space(bo_array, count); 2912 2913 if (total > threshold) 2914 total = drm_intel_gem_compute_batch_space(bo_array, count); 2915 2916 if (total > threshold) { 2917 DBG("check_space: overflowed available aperture, " 2918 "%dkb vs %dkb\n", 2919 total / 1024, (int)bufmgr_gem->gtt_size / 1024); 2920 return -ENOSPC; 2921 } else { 2922 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024, 2923 (int)bufmgr_gem->gtt_size / 1024); 2924 return 0; 2925 } 2926} 2927 2928/* 2929 * Disable buffer reuse for objects which are shared with the kernel 2930 * as scanout buffers 2931 */ 2932static int 2933drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo) 2934{ 2935 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2936 2937 bo_gem->reusable = false; 2938 return 0; 2939} 2940 2941static int 2942drm_intel_gem_bo_is_reusable(drm_intel_bo *bo) 2943{ 2944 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2945 2946 return bo_gem->reusable; 2947} 2948 2949static int 2950_drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) 2951{ 2952 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 2953 int i; 2954 2955 for (i = 0; i < bo_gem->reloc_count; i++) { 2956 if (bo_gem->reloc_target_info[i].bo == target_bo) 2957 return 1; 2958 if (bo == bo_gem->reloc_target_info[i].bo) 2959 continue; 2960 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo, 2961 target_bo)) 2962 return 1; 2963 } 2964 2965 for (i = 0; i< bo_gem->softpin_target_count; i++) { 2966 if (bo_gem->softpin_target[i] == target_bo) 2967 return 1; 2968 if (_drm_intel_gem_bo_references(bo_gem->softpin_target[i], target_bo)) 2969 return 1; 2970 } 2971 2972 return 0; 2973} 2974 2975/** Return true if target_bo is referenced by bo's relocation tree. */ 2976static int 2977drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) 2978{ 2979 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo; 2980 2981 if (bo == NULL || target_bo == NULL) 2982 return 0; 2983 if (target_bo_gem->used_as_reloc_target) 2984 return _drm_intel_gem_bo_references(bo, target_bo); 2985 return 0; 2986} 2987 2988static void 2989add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size) 2990{ 2991 unsigned int i = bufmgr_gem->num_buckets; 2992 2993 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket)); 2994 2995 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head); 2996 bufmgr_gem->cache_bucket[i].size = size; 2997 bufmgr_gem->num_buckets++; 2998} 2999 3000static void 3001init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem) 3002{ 3003 unsigned long size, cache_max_size = 64 * 1024 * 1024; 3004 3005 /* OK, so power of two buckets was too wasteful of memory. 3006 * Give 3 other sizes between each power of two, to hopefully 3007 * cover things accurately enough. (The alternative is 3008 * probably to just go for exact matching of sizes, and assume 3009 * that for things like composited window resize the tiled 3010 * width/height alignment and rounding of sizes to pages will 3011 * get us useful cache hit rates anyway) 3012 */ 3013 add_bucket(bufmgr_gem, 4096); 3014 add_bucket(bufmgr_gem, 4096 * 2); 3015 add_bucket(bufmgr_gem, 4096 * 3); 3016 3017 /* Initialize the linked lists for BO reuse cache. */ 3018 for (size = 4 * 4096; size <= cache_max_size; size *= 2) { 3019 add_bucket(bufmgr_gem, size); 3020 3021 add_bucket(bufmgr_gem, size + size * 1 / 4); 3022 add_bucket(bufmgr_gem, size + size * 2 / 4); 3023 add_bucket(bufmgr_gem, size + size * 3 / 4); 3024 } 3025} 3026 3027void 3028drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit) 3029{ 3030 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; 3031 3032 bufmgr_gem->vma_max = limit; 3033 3034 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem); 3035} 3036 3037/** 3038 * Get the PCI ID for the device. This can be overridden by setting the 3039 * INTEL_DEVID_OVERRIDE environment variable to the desired ID. 3040 */ 3041static int 3042get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem) 3043{ 3044 char *devid_override; 3045 int devid = 0; 3046 int ret; 3047 drm_i915_getparam_t gp; 3048 3049 if (geteuid() == getuid()) { 3050 devid_override = getenv("INTEL_DEVID_OVERRIDE"); 3051 if (devid_override) { 3052 bufmgr_gem->no_exec = true; 3053 return strtod(devid_override, NULL); 3054 } 3055 } 3056 3057 memclear(gp); 3058 gp.param = I915_PARAM_CHIPSET_ID; 3059 gp.value = &devid; 3060 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3061 if (ret) { 3062 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno); 3063 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value); 3064 } 3065 return devid; 3066} 3067 3068int 3069drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr) 3070{ 3071 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; 3072 3073 return bufmgr_gem->pci_device; 3074} 3075 3076/** 3077 * Sets the AUB filename. 3078 * 3079 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump() 3080 * for it to have any effect. 3081 */ 3082void 3083drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr, 3084 const char *filename) 3085{ 3086} 3087 3088/** 3089 * Sets up AUB dumping. 3090 * 3091 * This is a trace file format that can be used with the simulator. 3092 * Packets are emitted in a format somewhat like GPU command packets. 3093 * You can set up a GTT and upload your objects into the referenced 3094 * space, then send off batchbuffers and get BMPs out the other end. 3095 */ 3096void 3097drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable) 3098{ 3099 fprintf(stderr, "libdrm aub dumping is deprecated.\n\n" 3100 "Use intel_aubdump from intel-gpu-tools instead. Install intel-gpu-tools,\n" 3101 "then run (for example)\n\n" 3102 "\t$ intel_aubdump --output=trace.aub glxgears -geometry 500x500\n\n" 3103 "See the intel_aubdump man page for more details.\n"); 3104} 3105 3106drm_intel_context * 3107drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr) 3108{ 3109 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; 3110 struct drm_i915_gem_context_create create; 3111 drm_intel_context *context = NULL; 3112 int ret; 3113 3114 context = calloc(1, sizeof(*context)); 3115 if (!context) 3116 return NULL; 3117 3118 memclear(create); 3119 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create); 3120 if (ret != 0) { 3121 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", 3122 strerror(errno)); 3123 free(context); 3124 return NULL; 3125 } 3126 3127 context->ctx_id = create.ctx_id; 3128 context->bufmgr = bufmgr; 3129 3130 return context; 3131} 3132 3133void 3134drm_intel_gem_context_destroy(drm_intel_context *ctx) 3135{ 3136 drm_intel_bufmgr_gem *bufmgr_gem; 3137 struct drm_i915_gem_context_destroy destroy; 3138 int ret; 3139 3140 if (ctx == NULL) 3141 return; 3142 3143 memclear(destroy); 3144 3145 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr; 3146 destroy.ctx_id = ctx->ctx_id; 3147 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY, 3148 &destroy); 3149 if (ret != 0) 3150 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n", 3151 strerror(errno)); 3152 3153 free(ctx); 3154} 3155 3156int 3157drm_intel_get_reset_stats(drm_intel_context *ctx, 3158 uint32_t *reset_count, 3159 uint32_t *active, 3160 uint32_t *pending) 3161{ 3162 drm_intel_bufmgr_gem *bufmgr_gem; 3163 struct drm_i915_reset_stats stats; 3164 int ret; 3165 3166 if (ctx == NULL) 3167 return -EINVAL; 3168 3169 memclear(stats); 3170 3171 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr; 3172 stats.ctx_id = ctx->ctx_id; 3173 ret = drmIoctl(bufmgr_gem->fd, 3174 DRM_IOCTL_I915_GET_RESET_STATS, 3175 &stats); 3176 if (ret == 0) { 3177 if (reset_count != NULL) 3178 *reset_count = stats.reset_count; 3179 3180 if (active != NULL) 3181 *active = stats.batch_active; 3182 3183 if (pending != NULL) 3184 *pending = stats.batch_pending; 3185 } 3186 3187 return ret; 3188} 3189 3190int 3191drm_intel_reg_read(drm_intel_bufmgr *bufmgr, 3192 uint32_t offset, 3193 uint64_t *result) 3194{ 3195 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; 3196 struct drm_i915_reg_read reg_read; 3197 int ret; 3198 3199 memclear(reg_read); 3200 reg_read.offset = offset; 3201 3202 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read); 3203 3204 *result = reg_read.val; 3205 return ret; 3206} 3207 3208int 3209drm_intel_get_subslice_total(int fd, unsigned int *subslice_total) 3210{ 3211 drm_i915_getparam_t gp; 3212 int ret; 3213 3214 memclear(gp); 3215 gp.value = (int*)subslice_total; 3216 gp.param = I915_PARAM_SUBSLICE_TOTAL; 3217 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp); 3218 if (ret) 3219 return -errno; 3220 3221 return 0; 3222} 3223 3224int 3225drm_intel_get_eu_total(int fd, unsigned int *eu_total) 3226{ 3227 drm_i915_getparam_t gp; 3228 int ret; 3229 3230 memclear(gp); 3231 gp.value = (int*)eu_total; 3232 gp.param = I915_PARAM_EU_TOTAL; 3233 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp); 3234 if (ret) 3235 return -errno; 3236 3237 return 0; 3238} 3239 3240/** 3241 * Annotate the given bo for use in aub dumping. 3242 * 3243 * \param annotations is an array of drm_intel_aub_annotation objects 3244 * describing the type of data in various sections of the bo. Each 3245 * element of the array specifies the type and subtype of a section of 3246 * the bo, and the past-the-end offset of that section. The elements 3247 * of \c annotations must be sorted so that ending_offset is 3248 * increasing. 3249 * 3250 * \param count is the number of elements in the \c annotations array. 3251 * If \c count is zero, then \c annotations will not be dereferenced. 3252 * 3253 * Annotations are copied into a private data structure, so caller may 3254 * re-use the memory pointed to by \c annotations after the call 3255 * returns. 3256 * 3257 * Annotations are stored for the lifetime of the bo; to reset to the 3258 * default state (no annotations), call this function with a \c count 3259 * of zero. 3260 */ 3261void 3262drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo, 3263 drm_intel_aub_annotation *annotations, 3264 unsigned count) 3265{ 3266} 3267 3268static pthread_mutex_t bufmgr_list_mutex = PTHREAD_MUTEX_INITIALIZER; 3269static drmMMListHead bufmgr_list = { &bufmgr_list, &bufmgr_list }; 3270 3271static drm_intel_bufmgr_gem * 3272drm_intel_bufmgr_gem_find(int fd) 3273{ 3274 drm_intel_bufmgr_gem *bufmgr_gem; 3275 3276 DRMLISTFOREACHENTRY(bufmgr_gem, &bufmgr_list, managers) { 3277 if (bufmgr_gem->fd == fd) { 3278 atomic_inc(&bufmgr_gem->refcount); 3279 return bufmgr_gem; 3280 } 3281 } 3282 3283 return NULL; 3284} 3285 3286static void 3287drm_intel_bufmgr_gem_unref(drm_intel_bufmgr *bufmgr) 3288{ 3289 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; 3290 3291 if (atomic_add_unless(&bufmgr_gem->refcount, -1, 1)) { 3292 pthread_mutex_lock(&bufmgr_list_mutex); 3293 3294 if (atomic_dec_and_test(&bufmgr_gem->refcount)) { 3295 DRMLISTDEL(&bufmgr_gem->managers); 3296 drm_intel_bufmgr_gem_destroy(bufmgr); 3297 } 3298 3299 pthread_mutex_unlock(&bufmgr_list_mutex); 3300 } 3301} 3302 3303/** 3304 * Initializes the GEM buffer manager, which uses the kernel to allocate, map, 3305 * and manage map buffer objections. 3306 * 3307 * \param fd File descriptor of the opened DRM device. 3308 */ 3309drm_intel_bufmgr * 3310drm_intel_bufmgr_gem_init(int fd, int batch_size) 3311{ 3312 drm_intel_bufmgr_gem *bufmgr_gem; 3313 struct drm_i915_gem_get_aperture aperture; 3314 drm_i915_getparam_t gp; 3315 int ret, tmp; 3316 bool exec2 = false; 3317 3318 pthread_mutex_lock(&bufmgr_list_mutex); 3319 3320 bufmgr_gem = drm_intel_bufmgr_gem_find(fd); 3321 if (bufmgr_gem) 3322 goto exit; 3323 3324 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem)); 3325 if (bufmgr_gem == NULL) 3326 goto exit; 3327 3328 bufmgr_gem->fd = fd; 3329 atomic_set(&bufmgr_gem->refcount, 1); 3330 3331 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) { 3332 free(bufmgr_gem); 3333 bufmgr_gem = NULL; 3334 goto exit; 3335 } 3336 3337 memclear(aperture); 3338 ret = drmIoctl(bufmgr_gem->fd, 3339 DRM_IOCTL_I915_GEM_GET_APERTURE, 3340 &aperture); 3341 3342 if (ret == 0) 3343 bufmgr_gem->gtt_size = aperture.aper_available_size; 3344 else { 3345 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n", 3346 strerror(errno)); 3347 bufmgr_gem->gtt_size = 128 * 1024 * 1024; 3348 fprintf(stderr, "Assuming %dkB available aperture size.\n" 3349 "May lead to reduced performance or incorrect " 3350 "rendering.\n", 3351 (int)bufmgr_gem->gtt_size / 1024); 3352 } 3353 3354 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem); 3355 3356 if (IS_GEN2(bufmgr_gem->pci_device)) 3357 bufmgr_gem->gen = 2; 3358 else if (IS_GEN3(bufmgr_gem->pci_device)) 3359 bufmgr_gem->gen = 3; 3360 else if (IS_GEN4(bufmgr_gem->pci_device)) 3361 bufmgr_gem->gen = 4; 3362 else if (IS_GEN5(bufmgr_gem->pci_device)) 3363 bufmgr_gem->gen = 5; 3364 else if (IS_GEN6(bufmgr_gem->pci_device)) 3365 bufmgr_gem->gen = 6; 3366 else if (IS_GEN7(bufmgr_gem->pci_device)) 3367 bufmgr_gem->gen = 7; 3368 else if (IS_GEN8(bufmgr_gem->pci_device)) 3369 bufmgr_gem->gen = 8; 3370 else if (IS_GEN9(bufmgr_gem->pci_device)) 3371 bufmgr_gem->gen = 9; 3372 else { 3373 free(bufmgr_gem); 3374 bufmgr_gem = NULL; 3375 goto exit; 3376 } 3377 3378 if (IS_GEN3(bufmgr_gem->pci_device) && 3379 bufmgr_gem->gtt_size > 256*1024*1024) { 3380 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't 3381 * be used for tiled blits. To simplify the accounting, just 3382 * substract the unmappable part (fixed to 256MB on all known 3383 * gen3 devices) if the kernel advertises it. */ 3384 bufmgr_gem->gtt_size -= 256*1024*1024; 3385 } 3386 3387 memclear(gp); 3388 gp.value = &tmp; 3389 3390 gp.param = I915_PARAM_HAS_EXECBUF2; 3391 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3392 if (!ret) 3393 exec2 = true; 3394 3395 gp.param = I915_PARAM_HAS_BSD; 3396 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3397 bufmgr_gem->has_bsd = ret == 0; 3398 3399 gp.param = I915_PARAM_HAS_BLT; 3400 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3401 bufmgr_gem->has_blt = ret == 0; 3402 3403 gp.param = I915_PARAM_HAS_RELAXED_FENCING; 3404 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3405 bufmgr_gem->has_relaxed_fencing = ret == 0; 3406 3407 bufmgr_gem->bufmgr.bo_alloc_userptr = check_bo_alloc_userptr; 3408 3409 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT; 3410 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3411 bufmgr_gem->has_wait_timeout = ret == 0; 3412 3413 gp.param = I915_PARAM_HAS_LLC; 3414 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3415 if (ret != 0) { 3416 /* Kernel does not supports HAS_LLC query, fallback to GPU 3417 * generation detection and assume that we have LLC on GEN6/7 3418 */ 3419 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) | 3420 IS_GEN7(bufmgr_gem->pci_device)); 3421 } else 3422 bufmgr_gem->has_llc = *gp.value; 3423 3424 gp.param = I915_PARAM_HAS_VEBOX; 3425 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3426 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0); 3427 3428 gp.param = I915_PARAM_HAS_EXEC_SOFTPIN; 3429 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3430 if (ret == 0 && *gp.value > 0) 3431 bufmgr_gem->bufmgr.bo_set_softpin_offset = drm_intel_gem_bo_set_softpin_offset; 3432 3433 if (bufmgr_gem->gen < 4) { 3434 gp.param = I915_PARAM_NUM_FENCES_AVAIL; 3435 gp.value = &bufmgr_gem->available_fences; 3436 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3437 if (ret) { 3438 fprintf(stderr, "get fences failed: %d [%d]\n", ret, 3439 errno); 3440 fprintf(stderr, "param: %d, val: %d\n", gp.param, 3441 *gp.value); 3442 bufmgr_gem->available_fences = 0; 3443 } else { 3444 /* XXX The kernel reports the total number of fences, 3445 * including any that may be pinned. 3446 * 3447 * We presume that there will be at least one pinned 3448 * fence for the scanout buffer, but there may be more 3449 * than one scanout and the user may be manually 3450 * pinning buffers. Let's move to execbuffer2 and 3451 * thereby forget the insanity of using fences... 3452 */ 3453 bufmgr_gem->available_fences -= 2; 3454 if (bufmgr_gem->available_fences < 0) 3455 bufmgr_gem->available_fences = 0; 3456 } 3457 } 3458 3459 if (bufmgr_gem->gen >= 8) { 3460 gp.param = I915_PARAM_HAS_ALIASING_PPGTT; 3461 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3462 if (ret == 0 && *gp.value == 3) 3463 bufmgr_gem->bufmgr.bo_use_48b_address_range = drm_intel_gem_bo_use_48b_address_range; 3464 } 3465 3466 /* Let's go with one relocation per every 2 dwords (but round down a bit 3467 * since a power of two will mean an extra page allocation for the reloc 3468 * buffer). 3469 * 3470 * Every 4 was too few for the blender benchmark. 3471 */ 3472 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2; 3473 3474 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc; 3475 bufmgr_gem->bufmgr.bo_alloc_for_render = 3476 drm_intel_gem_bo_alloc_for_render; 3477 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled; 3478 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference; 3479 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference; 3480 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map; 3481 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap; 3482 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata; 3483 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata; 3484 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering; 3485 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc; 3486 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence; 3487 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin; 3488 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin; 3489 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling; 3490 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling; 3491 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink; 3492 /* Use the new one if available */ 3493 if (exec2) { 3494 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2; 3495 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2; 3496 } else 3497 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec; 3498 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy; 3499 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise; 3500 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_unref; 3501 bufmgr_gem->bufmgr.debug = 0; 3502 bufmgr_gem->bufmgr.check_aperture_space = 3503 drm_intel_gem_check_aperture_space; 3504 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse; 3505 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable; 3506 bufmgr_gem->bufmgr.get_pipe_from_crtc_id = 3507 drm_intel_gem_get_pipe_from_crtc_id; 3508 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references; 3509 3510 DRMINITLISTHEAD(&bufmgr_gem->named); 3511 init_cache_buckets(bufmgr_gem); 3512 3513 DRMINITLISTHEAD(&bufmgr_gem->vma_cache); 3514 bufmgr_gem->vma_max = -1; /* unlimited by default */ 3515 3516 DRMLISTADD(&bufmgr_gem->managers, &bufmgr_list); 3517 3518exit: 3519 pthread_mutex_unlock(&bufmgr_list_mutex); 3520 3521 return bufmgr_gem != NULL ? &bufmgr_gem->bufmgr : NULL; 3522} 3523