10d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@/***************************************************************************** 20d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 30d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore 40d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 50d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* Licensed under the Apache License, Version 2.0 (the "License"); 60d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* you may not use this file except in compliance with the License. 70d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* You may obtain a copy of the License at: 80d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 90d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* http://www.apache.org/licenses/LICENSE-2.0 100d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 110d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* Unless required by applicable law or agreed to in writing, software 120d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* distributed under the License is distributed on an "AS IS" BASIS, 130d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 140d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* See the License for the specific language governing permissions and 150d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* limitations under the License. 160d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 170d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@*****************************************************************************/ 180d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@/** 190d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@/** 200d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@******************************************************************************* 210d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 220d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @brief 230d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* interprediction luma function for copy 240d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 250d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @par description: 260d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* copies the array of width 'wd' and height 'ht' from the location pointed 270d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* by 'src' to the location pointed by 'dst' 280d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 290d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @param[in] pu1_src 300d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* uword8 pointer to the source 310d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 320d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @param[out] pu1_dst 330d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* uword8 pointer to the destination 340d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 350d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @param[in] src_strd 360d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* integer source stride 370d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 380d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @param[in] dst_strd 390d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* integer destination stride 400d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 410d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @param[in] pi1_coeff 420d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* word8 pointer to the filter coefficients 430d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 440d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @param[in] ht 450d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* integer height of the array 460d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 470d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @param[in] wd 480d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* integer width of the array 490d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 500d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @returns 510d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 520d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* @remarks 530d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* none 540d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@* 550d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@******************************************************************************* 560d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@*/ 570d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 580d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@void ihevc_inter_pred_luma_copy_w16out ( 590d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ uword8 *pu1_src, 600d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ word16 *pi2_dst, 610d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ word32 src_strd, 620d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ word32 dst_strd, 630d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ word8 *pi1_coeff, 640d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ word32 ht, 650d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ word32 wd ) 660d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 670d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@**************variables vs registers***************************************** 680d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ r0 => *pu1_src 690d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ r1 => *pi2_dst 700d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ r2 => src_strd 710d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ r3 => dst_strd 720d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ r7 => ht 730d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar@ r12 => wd 740d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 750d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar.text 760d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar.align 4 770d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 780d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 790d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 800d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 810d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar.globl ihevc_inter_pred_luma_copy_w16out_a9q 820d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 830d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar.type ihevc_inter_pred_luma_copy_w16out_a9q, %function 840d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 850d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakarihevc_inter_pred_luma_copy_w16out_a9q: 860d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 870d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments 880d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar ldr r12,[sp,#48] @loads wd 890d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar ldr r7,[sp,#44] @loads ht 900d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar cmp r7,#0 @ht condition(ht == 0) 910d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar ble end_loops @loop 920d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar tst r12,#7 @conditional check for wd (multiples) 930d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar beq core_loop_wd_8 940d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar sub r11,r12,#4 950d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar lsls r6,r3,#1 960d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 970d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakarouter_loop_wd_4: 980d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar subs r4,r12,#0 @wd conditional subtract 990d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar ble end_inner_loop_wd_4 1000d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1010d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakarinner_loop_wd_4: 1020d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d0},[r0] @vld1_u8(pu1_src_tmp) 1030d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar add r5,r0,r2 @pu1_src +src_strd 1040d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q0,d0 @vmovl_u8(vld1_u8(pu1_src_tmp) 1050d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar add r10,r1,r6 1060d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar subs r4,r4,#4 @wd - 4 1070d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i64 q0,q0,#6 @vshlq_n_s64(temp, 6) 1080d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d22},[r5],r2 @vld1_u8(pu1_src_tmp) 1090d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar add r0,r0,#4 @pu1_src += 4 1100d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.64 {d0},[r1] @vst1q_lane_s64(pi2_dst_tmp, temp, 0) 1110d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar add r1,r1,#8 1120d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q11,d22 @vmovl_u8(vld1_u8(pu1_src_tmp) 1130d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d24},[r5],r2 @vld1_u8(pu1_src_tmp) 1140d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i64 q11,q11,#6 @vshlq_n_s64(temp, 6) 1150d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q12,d24 @vmovl_u8(vld1_u8(pu1_src_tmp) 1160d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.64 {d22},[r10],r6 @vst1q_lane_s64(pi2_dst_tmp, temp, 0) 1170d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i64 q12,q12,#6 @vshlq_n_s64(temp, 6) 1180d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d26},[r5],r2 @vld1_u8(pu1_src_tmp) 1190d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.64 {d24},[r10],r6 @vst1q_lane_s64(pi2_dst_tmp, temp, 0) 1200d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q13,d26 @vmovl_u8(vld1_u8(pu1_src_tmp) 1210d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i64 q13,q13,#6 @vshlq_n_s64(temp, 6) 1220d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.64 {d26},[r10],r6 @vst1q_lane_s64(pi2_dst_tmp, temp, 0) 1230d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar bgt inner_loop_wd_4 1240d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1250d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakarend_inner_loop_wd_4: 1260d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar subs r7,r7,#4 @ht + 4 1270d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar sub r0,r5,r11 1280d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar sub r1,r10,r11,lsl #1 1290d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar bgt outer_loop_wd_4 1300d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1310d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakarend_loops: 1320d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar ldmfd sp!,{r4-r12,r15} @reload the registers from sp 1330d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1340d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1350d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakarcore_loop_wd_8: 1360d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar @sub r11,r12,#8 1370d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar lsls r5,r3,#1 1380d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar rsb r11,r12,r3, lsl #2 @ r11 = (dst_strd * 4) - width 1390d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar rsb r8,r12,r2,lsl #2 @r2->src_strd 1400d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar mov r4,r12, lsr #3 @ divide by 8 1410d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar mul r7, r4 1420d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar sub r4,r12,#0 @wd conditional check 1430d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar sub r7,r7,#4 @subtract one for epilog 1440d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1450d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakarprolog: 1460d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar add r6,r0,r2 @pu1_src_tmp += src_strd 1470d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar add r10,r1,r5 1480d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d8},[r0]! @vld1_u8(pu1_src_tmp) 1490d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d10},[r6],r2 @vld1_u8(pu1_src_tmp) 1500d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d12},[r6],r2 @vld1_u8(pu1_src_tmp) 1510d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d14},[r6],r2 @vld1_u8(pu1_src_tmp) 1520d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q8,d8 @vmovl_u8(vld1_u8(pu1_src_tmp)) 1530d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q9,d10 @vmovl_u8(vld1_u8(pu1_src_tmp) 1540d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q10,d12 @vmovl_u8(vld1_u8(pu1_src_tmp) 1550d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q11,d14 @vmovl_u8(vld1_u8(pu1_src_tmp) 1560d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar subs r4,r4,#8 @wd decrements by 8 1570d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q0,q8,#6 @vshlq_n_s16(tmp, 6) 1580d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q1,q9,#6 @vshlq_n_s16(tmp, 6) 1590d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q2,q10,#6 @vshlq_n_s16(tmp, 6) 1600d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q3,q11,#6 @vshlq_n_s16(tmp, 6) 1610d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar addle r0,r0,r8 1620d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar add r6,r0,r2 @pu1_src_tmp += src_strd 1630d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d8},[r0]! @vld1_u8(pu1_src_tmp) 1640d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d10},[r6],r2 @vld1_u8(pu1_src_tmp) 1650d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d12},[r6],r2 @vld1_u8(pu1_src_tmp) 1660d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d14},[r6],r2 @vld1_u8(pu1_src_tmp) 1670d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1680d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d0,d1},[r1]! @vst1q_s16(pi2_dst_tmp, tmp) 1690d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar addle r1,r1,r11,lsl #1 1700d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar suble r4,r12,#0 @wd conditional check 1710d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1720d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar subs r7,r7,#4 @ht - 4 1730d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1740d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar blt epilog_end @jumps to epilog_end 1750d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar beq epilog @jumps to epilog 1760d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1770d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1780d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1790d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakarouter_loop_wd_8: 1800d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1810d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d2,d3},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp) 1820d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q8,d8 @vmovl_u8(vld1_u8(pu1_src_tmp)) 1830d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1840d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d4,d5},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp) 1850d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q9,d10 @vmovl_u8(vld1_u8(pu1_src_tmp) 1860d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1870d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d6,d7},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp) 1880d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q10,d12 @vmovl_u8(vld1_u8(pu1_src_tmp) 1890d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1900d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q11,d14 @vmovl_u8(vld1_u8(pu1_src_tmp) 1910d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1920d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar subs r4,r4,#8 @wd decrements by 8 1930d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar addle r0,r0,r8 1940d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1950d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar add r6,r0,r2 @pu1_src_tmp += src_strd 1960d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 1970d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d8},[r0]! @vld1_u8(pu1_src_tmp) 1980d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q0,q8,#6 @vshlq_n_s16(tmp, 6) 1990d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2000d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d10},[r6],r2 @vld1_u8(pu1_src_tmp) 2010d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q1,q9,#6 @vshlq_n_s16(tmp, 6) 2020d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2030d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d12},[r6],r2 @vld1_u8(pu1_src_tmp) 2040d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q2,q10,#6 @vshlq_n_s16(tmp, 6) 2050d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2060d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vld1.8 {d14},[r6],r2 @vld1_u8(pu1_src_tmp) 2070d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar add r10,r1,r5 2080d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2090d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q3,q11,#6 @vshlq_n_s16(tmp, 6) 2100d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2110d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d0,d1},[r1]! @vst1q_s16(pi2_dst_tmp, tmp) 2120d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2130d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar addle r1,r1,r11,lsl #1 2140d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar suble r4,r12,#0 @wd conditional check 2150d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2160d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar subs r7,r7,#4 @ht - 4 2170d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar bgt outer_loop_wd_8 2180d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2190d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakarepilog: 2200d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d2,d3},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp) 2210d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q8,d8 @vmovl_u8(vld1_u8(pu1_src_tmp)) 2220d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2230d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d4,d5},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp) 2240d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q9,d10 @vmovl_u8(vld1_u8(pu1_src_tmp) 2250d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2260d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d6,d7},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp) 2270d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q10,d12 @vmovl_u8(vld1_u8(pu1_src_tmp) 2280d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2290d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vmovl.u8 q11,d14 @vmovl_u8(vld1_u8(pu1_src_tmp) 2300d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar @add r6,r0,r2 @pu1_src_tmp += src_strd 2310d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2320d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q0,q8,#6 @vshlq_n_s16(tmp, 6) 2330d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q1,q9,#6 @vshlq_n_s16(tmp, 6) 2340d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q2,q10,#6 @vshlq_n_s16(tmp, 6) 2350d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar add r10,r1,r5 2360d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vshl.i16 q3,q11,#6 @vshlq_n_s16(tmp, 6) 2370d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2380d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d0,d1},[r1]! @vst1q_s16(pi2_dst_tmp, tmp) 2390d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakarepilog_end: 2400d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d2,d3},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp) 2410d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d4,d5},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp) 2420d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar vst1.16 {d6,d7},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp) 2430d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2440d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2450d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar ldmfd sp!,{r4-r12,r15} @reload the registers from sp 2460d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2470d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2480d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 2490d8951cef4b1a1dbf4ff5ba3e8796cf1d4503098Harish Mahendrakar 250