MachineRegisterInfo.h revision ce049437d6986cfb4c0dba6bf99cadd8c301351a
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include "llvm/ADT/iterator.h" 20#include <vector> 21 22namespace llvm { 23 24/// MachineRegisterInfo - Keep track of information for virtual and physical 25/// registers, including vreg register classes, use/def chains for registers, 26/// etc. 27class MachineRegisterInfo { 28 /// VRegInfo - Information we keep for each virtual register. The entries in 29 /// this vector are actually converted to vreg numbers by adding the 30 /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 31 /// 32 /// Each element in this list contains the register class of the vreg and the 33 /// start of the use/def list for the register. 34 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 35 36 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 37 /// physical registers. 38 MachineOperand **PhysRegUseDefLists; 39 40 /// UsedPhysRegs - This is a bit vector that is computed and set by the 41 /// register allocator, and must be kept up to date by passes that run after 42 /// register allocation (though most don't modify this). This is used 43 /// so that the code generator knows which callee save registers to save and 44 /// for other target specific uses. 45 BitVector UsedPhysRegs; 46 47 /// LiveIns/LiveOuts - Keep track of the physical registers that are 48 /// livein/liveout of the function. Live in values are typically arguments in 49 /// registers, live out values are typically return values in registers. 50 /// LiveIn values are allowed to have virtual registers associated with them, 51 /// stored in the second element. 52 std::vector<std::pair<unsigned, unsigned> > LiveIns; 53 std::vector<unsigned> LiveOuts; 54 55 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 56 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 57public: 58 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 59 ~MachineRegisterInfo(); 60 61 //===--------------------------------------------------------------------===// 62 // Register Info 63 //===--------------------------------------------------------------------===// 64 65 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 66 /// and uses of a register within the MachineFunction that corresponds to this 67 /// MachineRegisterInfo object. 68 template<bool Uses, bool Defs> 69 class defusechain_iterator; 70 71 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 72 /// register. 73 typedef defusechain_iterator<true,true> reg_iterator; 74 reg_iterator reg_begin(unsigned RegNo) const { 75 return reg_iterator(getRegUseDefListHead(RegNo)); 76 } 77 static reg_iterator reg_end() { return reg_iterator(0); } 78 79 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 80 typedef defusechain_iterator<false,true> def_iterator; 81 def_iterator def_begin(unsigned RegNo) const { 82 return def_iterator(getRegUseDefListHead(RegNo)); 83 } 84 static def_iterator def_end() { return def_iterator(0); } 85 86 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 87 typedef defusechain_iterator<true,false> use_iterator; 88 use_iterator use_begin(unsigned RegNo) const { 89 return use_iterator(getRegUseDefListHead(RegNo)); 90 } 91 static use_iterator use_end() { return use_iterator(0); } 92 93 /// use_empty - Return true if there are no instructions using the specified 94 /// register. 95 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 96 97 98 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 99 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 100 /// except that it also changes any definitions of the register as well. 101 void replaceRegWith(unsigned FromReg, unsigned ToReg); 102 103 /// getRegUseDefListHead - Return the head pointer for the register use/def 104 /// list for the specified virtual or physical register. 105 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 106 if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 107 return PhysRegUseDefLists[RegNo]; 108 RegNo -= TargetRegisterInfo::FirstVirtualRegister; 109 return VRegInfo[RegNo].second; 110 } 111 112 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 113 if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 114 return PhysRegUseDefLists[RegNo]; 115 RegNo -= TargetRegisterInfo::FirstVirtualRegister; 116 return VRegInfo[RegNo].second; 117 } 118 119 /// getVRegDef - Return the machine instr that defines the specified virtual 120 /// register or null if none is found. This assumes that the code is in SSA 121 /// form, so there should only be one definition. 122 MachineInstr *getVRegDef(unsigned Reg) const; 123 124#ifndef NDEBUG 125 void dumpUses(unsigned RegNo) const; 126#endif 127 128 //===--------------------------------------------------------------------===// 129 // Virtual Register Info 130 //===--------------------------------------------------------------------===// 131 132 /// getRegClass - Return the register class of the specified virtual register. 133 const TargetRegisterClass *getRegClass(unsigned Reg) const { 134 Reg -= TargetRegisterInfo::FirstVirtualRegister; 135 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 136 return VRegInfo[Reg].first; 137 } 138 139 /// createVirtualRegister - Create and return a new virtual register in the 140 /// function with the specified register class. 141 /// 142 unsigned createVirtualRegister(const TargetRegisterClass *RegClass) { 143 assert(RegClass && "Cannot create register without RegClass!"); 144 // Add a reg, but keep track of whether the vector reallocated or not. 145 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0]; 146 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 147 148 if (&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1) 149 return getLastVirtReg(); 150 151 // Otherwise, the vector reallocated, handle this now. 152 HandleVRegListReallocation(); 153 return getLastVirtReg(); 154 } 155 156 /// getLastVirtReg - Return the highest currently assigned virtual register. 157 /// 158 unsigned getLastVirtReg() const { 159 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 160 } 161 162 163 //===--------------------------------------------------------------------===// 164 // Physical Register Use Info 165 //===--------------------------------------------------------------------===// 166 167 /// isPhysRegUsed - Return true if the specified register is used in this 168 /// function. This only works after register allocation. 169 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 170 171 /// setPhysRegUsed - Mark the specified register used in this function. 172 /// This should only be called during and after register allocation. 173 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 174 175 /// setPhysRegUnused - Mark the specified register unused in this function. 176 /// This should only be called during and after register allocation. 177 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 178 179 180 //===--------------------------------------------------------------------===// 181 // LiveIn/LiveOut Management 182 //===--------------------------------------------------------------------===// 183 184 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 185 /// is an error to add the same register to the same set more than once. 186 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 187 LiveIns.push_back(std::make_pair(Reg, vreg)); 188 } 189 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 190 191 // Iteration support for live in/out sets. These sets are kept in sorted 192 // order by their register number. 193 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 194 livein_iterator; 195 typedef std::vector<unsigned>::const_iterator liveout_iterator; 196 livein_iterator livein_begin() const { return LiveIns.begin(); } 197 livein_iterator livein_end() const { return LiveIns.end(); } 198 bool livein_empty() const { return LiveIns.empty(); } 199 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 200 liveout_iterator liveout_end() const { return LiveOuts.end(); } 201 bool liveout_empty() const { return LiveOuts.empty(); } 202private: 203 void HandleVRegListReallocation(); 204 205public: 206 /// defusechain_iterator - This class provides iterator support for machine 207 /// operands in the function that use or define a specific register. If 208 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 209 /// returns defs. If neither are true then you are silly and it always 210 /// returns end(). 211 template<bool ReturnUses, bool ReturnDefs> 212 class defusechain_iterator 213 : public forward_iterator<MachineInstr, ptrdiff_t> { 214 MachineOperand *Op; 215 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 216 // If the first node isn't one we're interested in, advance to one that 217 // we are interested in. 218 if (op) { 219 if ((!ReturnUses && op->isUse()) || 220 (!ReturnDefs && op->isDef())) 221 ++*this; 222 } 223 } 224 friend class MachineRegisterInfo; 225 public: 226 typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference; 227 typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer; 228 229 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 230 defusechain_iterator() : Op(0) {} 231 232 bool operator==(const defusechain_iterator &x) const { 233 return Op == x.Op; 234 } 235 bool operator!=(const defusechain_iterator &x) const { 236 return !operator==(x); 237 } 238 239 /// atEnd - return true if this iterator is equal to reg_end() on the value. 240 bool atEnd() const { return Op == 0; } 241 242 // Iterator traversal: forward iteration only 243 defusechain_iterator &operator++() { // Preincrement 244 assert(Op && "Cannot increment end iterator!"); 245 Op = Op->getNextOperandForReg(); 246 247 // If this is an operand we don't care about, skip it. 248 while (Op && ((!ReturnUses && Op->isUse()) || 249 (!ReturnDefs && Op->isDef()))) 250 Op = Op->getNextOperandForReg(); 251 252 return *this; 253 } 254 defusechain_iterator operator++(int) { // Postincrement 255 defusechain_iterator tmp = *this; ++*this; return tmp; 256 } 257 258 MachineOperand &getOperand() const { 259 assert(Op && "Cannot dereference end iterator!"); 260 return *Op; 261 } 262 263 /// getOperandNo - Return the operand # of this MachineOperand in its 264 /// MachineInstr. 265 unsigned getOperandNo() const { 266 assert(Op && "Cannot dereference end iterator!"); 267 return Op - &Op->getParent()->getOperand(0); 268 } 269 270 // Retrieve a reference to the current operand. 271 MachineInstr &operator*() const { 272 assert(Op && "Cannot dereference end iterator!"); 273 return *Op->getParent(); 274 } 275 276 MachineInstr *operator->() const { 277 assert(Op && "Cannot dereference end iterator!"); 278 return Op->getParent(); 279 } 280 }; 281 282}; 283 284} // End llvm namespace 285 286#endif 287