17f8f3f7f6400291d30531c88a98511f9fc626b4cChad Rosier//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 3d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// The LLVM Compiler Infrastructure 4d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 5d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// This file is distributed under the University of Illinois Open Source 6d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// License. See LICENSE.TXT for details. 7d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 8d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 9d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 1022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng// This file defines the MCOperandInfo and MCInstrDesc classes, which 110ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach// are used to describe target instructions and their operands. 12d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 13d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 14d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 15e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#ifndef LLVM_MC_MCINSTRDESC_H 16e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#define LLVM_MC_MCINSTRDESC_H 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 18f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar#include "llvm/MC/MCRegisterInfo.h" 1958a2cbef4aac9ee7d530dfb690c78d6fc11a2371Chandler Carruth#include "llvm/Support/DataTypes.h" 206948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar#include <string> 2199405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes 22d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnernamespace llvm { 236948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar class MCInst; 246948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar class MCSubtargetInfo; 256948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar class FeatureBitset; 26d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 27d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 28d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Operand Flags and Description 29d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 300ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 31e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCOI { 326948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar// Operand constraints 336948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarenum OperandConstraint { 346948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar TIED_TO = 0, // Must be allocated the same register as. 356948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar EARLY_CLOBBER // Operand is an early clobber register operand 366948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar}; 376948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 386948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// \brief These are flags set on operands, but should be considered 396948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// private, all access should go through the MCOperandInfo accessors. 406948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// See the accessors for a description of what these are. 416948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarenum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef }; 426948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 436948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// \brief Operands are tagged with one of the values of this enum. 446948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarenum OperandType { 456948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar OPERAND_UNKNOWN = 0, 466948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar OPERAND_IMMEDIATE = 1, 476948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar OPERAND_REGISTER = 2, 486948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar OPERAND_MEMORY = 3, 496948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar OPERAND_PCREL = 4, 506948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar OPERAND_FIRST_TARGET = 5 516948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar}; 52d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 53d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 546948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// \brief This holds information about one operand of a machine instruction, 556948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// indicating the register class for register operands, etc. 56e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCOperandInfo { 57d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 586948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief This specifies the register class enumeration of the operand 59cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// if the operand is a register. If isLookupPtrRegClass is set, then this is 60cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 61cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// get a dynamic register class. 6239bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper int16_t RegClass; 630ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 646948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief These are flags from the MCOI::OperandFlags enum. 6539bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint8_t Flags; 6639bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper 676948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Information about the type of the operand. 6839bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint8_t OperandType; 696948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief The lower 16 bits are used to specify which constraints are set. 706948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// The higher 16 bits are used to specify the value of constraints (4 bits 716948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// each). 7239bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint32_t Constraints; 730ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 746948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Set if this operand is a pointer value and it requires a callback 756948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// to look up its register class. 766948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isLookupPtrRegClass() const { 776948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar return Flags & (1 << MCOI::LookupPtrRegClass); 786948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar } 790ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 806948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Set if this is one of the operands that made up of the predicate 816948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// operand that controls an isPredicable() instruction. 82e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 830ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 846948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Set if this operand is a optional def. 85e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 86d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 87d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 88d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 89d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Instruction Flags and Description 90d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 91d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 92e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCID { 936948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// \brief These should be considered private to the implementation of the 946948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc, 956948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// not use these directly. These all correspond to bitfields in the 966948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// MCInstrDesc::Flags field. 976948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarenum Flag { 986948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Variadic = 0, 996948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar HasOptionalDef, 1006948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Pseudo, 1016948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Return, 1026948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Call, 1036948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Barrier, 1046948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Terminator, 1056948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Branch, 1066948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar IndirectBranch, 1076948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Compare, 1086948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar MoveImm, 1096948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Bitcast, 1106948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Select, 1116948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar DelaySlot, 1126948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar FoldableAsLoad, 1136948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar MayLoad, 1146948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar MayStore, 1156948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Predicable, 1166948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar NotDuplicable, 1176948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar UnmodeledSideEffects, 1186948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Commutable, 1196948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar ConvertibleTo3Addr, 1206948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar UsesCustomInserter, 1216948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar HasPostISelHook, 1226948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Rematerializable, 1236948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar CheapAsAMove, 1246948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar ExtraSrcRegAllocReq, 1256948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar ExtraDefRegAllocReq, 1266948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar RegSequence, 1276948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar ExtractSubreg, 1286948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar InsertSubreg, 1296948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar Convergent 1306948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar}; 131d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 132d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 1336948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// \brief Describe properties that are true of each instruction in the target 1346948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// description file. This captures information about side effects, register 1356948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// use and many other things. There is one instance of this struct for each 1366948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// target instruction class, and the MachineInstr class points to this struct 1376948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar/// directly to describe itself. 138e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCInstrDesc { 139d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 140f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned short Opcode; // The opcode number 141f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned short NumOperands; // Num of args (may be more if variable_ops) 142f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned char NumDefs; // Num of args that are definitions 143f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned char Size; // Number of bytes in encoding. 144f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned short SchedClass; // enum identifying instr sched class 145f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar uint64_t Flags; // Flags identifying machine instr class 146f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar uint64_t TSFlags; // Target Specific Flag values 147f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr 148f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr 149f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 1506948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar // Subtarget feature that this is deprecated on, if any 1516948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar // -1 implies this is not deprecated by any single feature. It may still be 1526948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar // deprecated due to a "complex" reason, below. 1536948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar int64_t DeprecatedFeature; 1546948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 155715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly // A complex method to determine is a certain is deprecated or not, and return 156715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly // the reason for deprecation. 157f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &, 158f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar std::string &); 159d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 16046367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns the value of the specific constraint if 161d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// it is set. Returns -1 if it is not set. 162d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner int getOperandConstraint(unsigned OpNum, 163e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCOI::OperandConstraint Constraint) const { 164d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner if (OpNum < NumOperands && 165d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner (OpInfo[OpNum].Constraints & (1 << Constraint))) { 166d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned Pos = 16 + Constraint * 4; 167d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 168d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 169d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return -1; 170d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 171d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 172715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly /// \brief Returns true if a certain instruction is deprecated and if so 173715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly /// returns the reason in \p Info. 174f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI, 1756948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar std::string &Info) const; 176715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly 17746367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the opcode number for this descriptor. 1786948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar unsigned getOpcode() const { return Opcode; } 1790ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 18046367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of declared MachineOperands for this 181d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// MachineInstruction. Note that variadic (isVariadic() returns true) 182d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions may have additional operands at the end of the list, and note 183d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// that the machine instruction may include implicit register def/uses as 184d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// well. 1856948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar unsigned getNumOperands() const { return NumOperands; } 1860ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 18746367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of MachineOperands that are register 1880ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// definitions. Register definitions always occur at the start of the 189b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// machine operand list. This is the number of "outs" in the .td file, 190b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// and does not include implicit defs. 1916948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar unsigned getNumDefs() const { return NumDefs; } 1920ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 19346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return flags of this instruction. 1945a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getFlags() const { return Flags; } 1957c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng 19646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction can have a variable number of 197d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands. In this case, the variable operands will be after the normal 198d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands but before the implicit definitions and uses (if any are 199d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// present). 2006948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isVariadic() const { return Flags & (1 << MCID::Variadic); } 2010ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 20246367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Set if this instruction has an optional definition, e.g. 203d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// ARM instructions which can set condition code if 's' bit is set. 2046948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool hasOptionalDef() const { return Flags & (1 << MCID::HasOptionalDef); } 2050ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 20646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a pseudo instruction that doesn't 207c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// correspond to a real machine instruction. 2086948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isPseudo() const { return Flags & (1 << MCID::Pseudo); } 209c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen 21046367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if the instruction is a return. 2116948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isReturn() const { return Flags & (1 << MCID::Return); } 2120ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 21346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if the instruction is a call. 2146948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isCall() const { return Flags & (1 << MCID::Call); } 2150ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 21646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns true if the specified instruction stops control flow 217d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// from executing the instruction immediately following it. Examples include 218d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// unconditional branches and return instructions. 2196948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isBarrier() const { return Flags & (1 << MCID::Barrier); } 2200ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 22146367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns true if this instruction part of the terminator for 222d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// a basic block. Typically this is things like return and branch 223d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions. 224d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 225d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Various passes use this to insert code into the bottom of a basic block, 226d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// but before control flow occurs. 2276948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isTerminator() const { return Flags & (1 << MCID::Terminator); } 2280ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 22946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns true if this is a conditional, unconditional, or 230d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// indirect branch. Predicates below can be used to discriminate between 231d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 232d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// get more information. 2336948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isBranch() const { return Flags & (1 << MCID::Branch); } 234d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 23546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is an indirect branch, such as a 236d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// branch through a register. 2376948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isIndirectBranch() const { return Flags & (1 << MCID::IndirectBranch); } 23873739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling 23946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a branch which may fall 240d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// through to the next instruction or may transfer control flow to some other 241d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 242d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// information about this branch. 243d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConditionalBranch() const { 244d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & !isBarrier() & !isIndirectBranch(); 245d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2460ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 24746367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a branch which always 248d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transfers control flow to some other block. The 249d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 250d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// about this branch. 251d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isUnconditionalBranch() const { 252d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & isBarrier() & !isIndirectBranch(); 253d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2540ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 25546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a branch or an instruction which directly 256fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach /// writes to the program counter. Considered 'may' affect rather than 257fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach /// 'does' affect as things like predication are not taken into account. 2586948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const; 259fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach 26046367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction has a predicate operand 261dd2fa5195ea2d98b2b4ee18f9894ad674f132a40Jim Grosbach /// that controls execution. It may be set to 'always', or may be set to other 262dd2fa5195ea2d98b2b4ee18f9894ad674f132a40Jim Grosbach /// values. There are various methods in TargetInstrInfo that can be used to 263d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// control and modify the predicate in this instruction. 2646948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isPredicable() const { return Flags & (1 << MCID::Predicable); } 2650ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 26646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction is a comparison. 2676948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isCompare() const { return Flags & (1 << MCID::Compare); } 2680ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 26946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction is a move immediate 2700ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// (including conditional moves) instruction. 2716948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isMoveImmediate() const { return Flags & (1 << MCID::MoveImm); } 2720f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng 27346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction is a bitcast instruction. 2746948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isBitcast() const { return Flags & (1 << MCID::Bitcast); } 2750ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 27646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a select instruction. 2776948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isSelect() const { return Flags & (1 << MCID::Select); } 278f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen 27946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction cannot be safely 280d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// duplicated. For example, if the instruction has a unique labels attached 281d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// to it, duplicating it would cause multiple definition errors. 2826948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isNotDuplicable() const { return Flags & (1 << MCID::NotDuplicable); } 2830ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 2846948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Returns true if the specified instruction has a delay slot which 2856948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// must be filled by the code generator. 2866948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool hasDelaySlot() const { return Flags & (1 << MCID::DelaySlot); } 2870ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 2886948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Return true for instructions that can be folded as memory operands 2896948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// in other instructions. The most common use for this is instructions that 2906948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// are simple loads from memory that don't modify the loaded value in any 2916948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// way, but it can also be used for instructions that can be expressed as 2926948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be 2936948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// folded when it is beneficial. This should only be set on instructions 2946948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// that return a value in their only virtual register definition. 2956948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool canFoldAsLoad() const { return Flags & (1 << MCID::FoldableAsLoad); } 2960ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 29737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// \brief Return true if this instruction behaves 29837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// the same way as the generic REG_SEQUENCE instructions. 29937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// E.g., on ARM, 30037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// dX VMOVDRR rY, rZ 30137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// is equivalent to 30237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. 30337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// 30437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// Note that for the optimizers to be able to take advantage of 30537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be 30637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// override accordingly. 30737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines bool isRegSequenceLike() const { return Flags & (1 << MCID::RegSequence); } 30837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 30937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// \brief Return true if this instruction behaves 31037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// the same way as the generic EXTRACT_SUBREG instructions. 31137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// E.g., on ARM, 31237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// rX, rY VMOVRRD dZ 31337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// is equivalent to two EXTRACT_SUBREG: 31437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// rX = EXTRACT_SUBREG dZ, ssub_0 31537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// rY = EXTRACT_SUBREG dZ, ssub_1 31637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// 31737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// Note that for the optimizers to be able to take advantage of 31837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be 31937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// override accordingly. 32037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines bool isExtractSubregLike() const { 32137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return Flags & (1 << MCID::ExtractSubreg); 32237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines } 32337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 32437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// \brief Return true if this instruction behaves 32537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// the same way as the generic INSERT_SUBREG instructions. 32637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// E.g., on ARM, 32737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// dX = VSETLNi32 dY, rZ, Imm 32837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// is equivalent to a INSERT_SUBREG: 32937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) 33037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// 33137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// Note that for the optimizers to be able to take advantage of 33237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be 33337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// override accordingly. 3346948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isInsertSubregLike() const { return Flags & (1 << MCID::InsertSubreg); } 3356948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 3366948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 3376948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Return true if this instruction is convergent. 3386948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// 339f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar /// Convergent instructions may not be made control-dependent on any 340f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar /// additional values. 3416948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isConvergent() const { return Flags & (1 << MCID::Convergent); } 34237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 343d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 344d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Side Effect Analysis 345d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 346dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner 34746367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction could possibly read memory. 348dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// Instructions with this flag set are not necessarily simple load 349dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// instructions, they may load a value and modify it, for example. 3506948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool mayLoad() const { return Flags & (1 << MCID::MayLoad); } 3510ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 35246367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction could possibly modify memory. 353d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Instructions with this flag set are not necessarily simple store 354d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions, they may store a modified value based on their operands, or 355d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// may not actually modify anything, for example. 3566948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool mayStore() const { return Flags & (1 << MCID::MayStore); } 3570ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 3586948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Return true if this instruction has side 359a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// effects that are not modeled by other flags. This does not return true 360a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// for instructions whose effects are captured by: 361d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 362a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 1. Their operand list and implicit definition/use list. Register use/def 363a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// info is explicit for instructions. 364a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 2. Memory accesses. Use mayLoad/mayStore. 365a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 366d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 367a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// Examples of side effects would be modifying 'invisible' machine state like 368a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// a control register, flushing a cache, modifying a register invisible to 369a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// LLVM, etc. 370a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner bool hasUnmodeledSideEffects() const { 371e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UnmodeledSideEffects); 372d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3730ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 374d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 375d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Flags that indicate whether an instruction can be modified by a method. 376d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 3770ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 3786948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Return true if this may be a 2- or 3-address instruction (of the 3796948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are 3806948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// exchanged. If this flag is set, then the 381d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::commuteInstruction method may be used to hack on the 382d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction. 383d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 384d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Note that this flag may be set on instructions that are only commutable 385d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// sometimes. In these cases, the call to commuteInstruction will fail. 386d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Also note that some instructions require non-trivial modification to 387d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// commute them. 3886948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isCommutable() const { return Flags & (1 << MCID::Commutable); } 3896948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 3906948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Return true if this is a 2-address instruction which can be changed 3916948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// into a 3-address instruction if needed. Doing this transformation can be 3926948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// profitable in the register allocator, because it means that the 3936948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// instruction can use a 2-address form if possible, but degrade into a less 3946948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// efficient form if the source and dest register cannot be assigned to the 3956948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// same register. For example, this allows the x86 backend to turn a "shl 3966948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// reg, 3" instruction into an LEA instruction, which is the same speed as 3976948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// the shift but has bigger code size. 398d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 399d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this returns true, then the target must implement the 400d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 401d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is allowed to fail if the transformation isn't valid for this specific 402d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (e.g. shl reg, 4 on x86). 403d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 404d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConvertibleTo3Addr() const { 405e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ConvertibleTo3Addr); 406d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4070ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 4086948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Return true if this instruction requires custom insertion support 4096948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// when the DAG scheduler is inserting it into a machine basic block. If 4106948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// this is true for the instruction, it basically means that it is a pseudo 4116948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// instruction used at SelectionDAG time that is expanded out into magic code 4126948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// by the target when MachineInstrs are formed. 413d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 414d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 415d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is used to insert this into the MachineBasicBlock. 416533297b58da8c74bec65551e1aface9801fc2259Dan Gohman bool usesCustomInsertionHook() const { 417e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UsesCustomInserter); 418d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4190ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 4206948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Return true if this instruction requires *adjustment* after 4216948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// instruction selection by calling a target hook. For example, this can be 4226948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// used to fill in ARM 's' optional operand depending on whether the 4236948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// conditional flag register is used. 4246948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool hasPostISelHook() const { return Flags & (1 << MCID::HasPostISelHook); } 42583a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick 4266948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Returns true if this instruction is a candidate for remat. This 4276948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// flag is only used in TargetInstrInfo method isTriviallyRematerializable. 428bfc2d688b591c574c0cc788348c74545ce894efaStephen Hines /// 429bfc2d688b591c574c0cc788348c74545ce894efaStephen Hines /// If this flag is set, the isReallyTriviallyReMaterializable() 430bfc2d688b591c574c0cc788348c74545ce894efaStephen Hines /// or isReallyTriviallyReMaterializableGeneric methods are called to verify 431bfc2d688b591c574c0cc788348c74545ce894efaStephen Hines /// the instruction is really rematable. 432d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isRematerializable() const { 433e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Rematerializable); 434d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4358370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling 4366948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Returns true if this instruction has the same cost (or less) than a 4376948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// move instruction. This is useful during certain types of optimizations 4386948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// (e.g., remat during two-address conversion or machine licm) where we would 4396948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// like to remat or hoist the instruction, but not if it costs more than 4406948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// moving the instruction into the appropriate register. Note, we are not 4416948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// marking copies from and to the same register class with this flag. 442bfc2d688b591c574c0cc788348c74545ce894efaStephen Hines /// 443bfc2d688b591c574c0cc788348c74545ce894efaStephen Hines /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove 444bfc2d688b591c574c0cc788348c74545ce894efaStephen Hines /// for different subtargets. 4456948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isAsCheapAsAMove() const { return Flags & (1 << MCID::CheapAsAMove); } 4466948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 4476948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Returns true if this instruction source operands have special 4486948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// register allocation requirements that are not captured by the operand 4496948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// register classes. e.g. ARM::STRD's two source registers must be an even / 4506948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// odd pair, ARM::STM registers have to be in ascending order. Post-register 4516948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// allocation passes should not attempt to change allocations for sources of 4526948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// instructions with this flag. 453799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraSrcRegAllocReq() const { 454e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraSrcRegAllocReq); 455799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 456799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 4576948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Returns true if this instruction def operands have special register 4586948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// allocation requirements that are not captured by the operand register 4596948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair, 4606948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// ARM::LDM registers have to be in ascending order. Post-register 4616948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// allocation passes should not attempt to change allocations for definitions 4626948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// of instructions with this flag. 463799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraDefRegAllocReq() const { 464e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraDefRegAllocReq); 465799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 4665a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4676948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Return a list of registers that are potentially read by any 4686948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// instance of this machine instruction. For example, on X86, the "adc" 4696948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// instruction adds two register operands and adds the carry bit in from the 4706948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// flags register. In this case, the instruction is marked as implicitly 4716948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// reading the flags. Likewise, the variable shift instruction on X86 is 4726948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// marked as implicitly reading the 'CL' register, which it always does. 4735a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// 4745a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// This method returns null if the instruction has no implicit uses. 475f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MCPhysReg *getImplicitUses() const { return ImplicitUses; } 4765a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4770eaf5a503e291cfd6d3ad27b6cc3956be2d4b914Jim Grosbach /// \brief Return the number of implicit uses this instruction has. 4785a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getNumImplicitUses() const { 4796948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar if (!ImplicitUses) 4806948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar return 0; 4815a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned i = 0; 4826948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar for (; ImplicitUses[i]; ++i) /*empty*/ 4836948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar ; 4845a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 4855a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 4865a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4876948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Return a list of registers that are potentially written by any 4886948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// instance of this machine instruction. For example, on X86, many 4896948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// instructions implicitly set the flags register. In this case, they are 4906948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// marked as setting the FLAGS. Likewise, many instructions always deposit 4916948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// their result in a physical register. For example, the X86 divide 4925a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// instruction always deposits the quotient and remainder in the EAX/EDX 4935a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// registers. For that instruction, this will return a list containing the 4945a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// EAX/EDX/EFLAGS registers. 4955a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// 4965a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// This method returns null if the instruction has no implicit defs. 497f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } 4985a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 49946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of implicit defs this instruct has. 5005a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getNumImplicitDefs() const { 5016948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar if (!ImplicitDefs) 5026948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar return 0; 5035a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned i = 0; 5046948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar for (; ImplicitDefs[i]; ++i) /*empty*/ 5056948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar ; 5065a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 5075a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5085a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 50946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction implicitly 5105a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// uses the specified physical register. 5115a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool hasImplicitUseOfPhysReg(unsigned Reg) const { 512f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (const MCPhysReg *ImpUses = ImplicitUses) 5135a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; *ImpUses; ++ImpUses) 5146948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar if (*ImpUses == Reg) 5156948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar return true; 5165a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return false; 5175a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5185a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 51946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction implicitly 5205a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// defines the specified physical register. 521fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach bool hasImplicitDefOfPhysReg(unsigned Reg, 5226948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar const MCRegisterInfo *MRI = nullptr) const; 523fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach 52446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the scheduling class for this instruction. The 5255a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// scheduling class is an index into the InstrItineraryData table. This 5265a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// returns zero if there is no known scheduling information for the 5275a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// instruction. 5286948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar unsigned getSchedClass() const { return SchedClass; } 5295a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 53046367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of bytes in the encoding of this instruction, 5315a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// or zero if the encoding size cannot be known from the opcode. 5326948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar unsigned getSize() const { return Size; } 5335a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 53446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Find the index of the first operand in the 5355a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// operand list that is used to represent the predicate. It returns -1 if 5365a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// none is found. 5375a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng int findFirstPredOperandIdx() const { 5385a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (isPredicable()) { 5395a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5405a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (OpInfo[i].isPredicate()) 5415a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 5425a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5435a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return -1; 5445a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5456948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 5466948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarprivate: 5476948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 5486948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// \brief Return true if this instruction defines the specified physical 5496948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// register, either explicitly or implicitly. 5506948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, 5516948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar const MCRegisterInfo &RI) const; 552d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 553d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 554d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} // end namespace llvm 555d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 556d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#endif 557