PHIElimination.cpp revision 1dd35b4c35ef149a48c511283331f49c04351cae
1//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass eliminates machine instruction PHI nodes by inserting copy 11// instructions. This destroys SSA information, but is the desired input for 12// some register allocators. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "phielim" 17#include "llvm/BasicBlock.h" 18#include "llvm/Instructions.h" 19#include "llvm/CodeGen/LiveVariables.h" 20#include "llvm/CodeGen/Passes.h" 21#include "llvm/CodeGen/MachineFunctionPass.h" 22#include "llvm/CodeGen/MachineInstr.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/ADT/SmallPtrSet.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/ADT/Statistic.h" 30#include "llvm/Support/Compiler.h" 31#include <algorithm> 32#include <map> 33using namespace llvm; 34 35STATISTIC(NumAtomic, "Number of atomic phis lowered"); 36 37namespace { 38 class VISIBILITY_HIDDEN PNE : public MachineFunctionPass { 39 MachineRegisterInfo *MRI; // Machine register information 40 41 public: 42 static char ID; // Pass identification, replacement for typeid 43 PNE() : MachineFunctionPass(&ID) {} 44 45 virtual bool runOnMachineFunction(MachineFunction &Fn); 46 47 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 48 AU.addPreserved<LiveVariables>(); 49 AU.addPreservedID(MachineLoopInfoID); 50 AU.addPreservedID(MachineDominatorsID); 51 MachineFunctionPass::getAnalysisUsage(AU); 52 } 53 54 private: 55 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions 56 /// in predecessor basic blocks. 57 /// 58 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB); 59 void LowerAtomicPHINode(MachineBasicBlock &MBB, 60 MachineBasicBlock::iterator AfterPHIsIt); 61 62 /// analyzePHINodes - Gather information about the PHI nodes in 63 /// here. In particular, we want to map the number of uses of a virtual 64 /// register which is used in a PHI node. We map that to the BB the 65 /// vreg is coming from. This is used later to determine when the vreg 66 /// is killed in the BB. 67 /// 68 void analyzePHINodes(const MachineFunction& Fn); 69 70 // FindCopyInsertPoint - Find a safe place in MBB to insert a copy from 71 // SrcReg. This needs to be after any def or uses of SrcReg, but before 72 // any subsequent point where control flow might jump out of the basic 73 // block. 74 MachineBasicBlock::iterator FindCopyInsertPoint(MachineBasicBlock &MBB, 75 unsigned SrcReg); 76 77 // SkipPHIsAndLabels - Copies need to be inserted after phi nodes and 78 // also after any exception handling labels: in landing pads execution 79 // starts at the label, so any copies placed before it won't be executed! 80 MachineBasicBlock::iterator SkipPHIsAndLabels(MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator I) { 82 // Rather than assuming that EH labels come before other kinds of labels, 83 // just skip all labels. 84 while (I != MBB.end() && 85 (I->getOpcode() == TargetInstrInfo::PHI || I->isLabel())) 86 ++I; 87 return I; 88 } 89 90 typedef std::pair<const MachineBasicBlock*, unsigned> BBVRegPair; 91 typedef std::map<BBVRegPair, unsigned> VRegPHIUse; 92 93 VRegPHIUse VRegPHIUseCount; 94 95 // Defs of PHI sources which are implicit_def. 96 SmallPtrSet<MachineInstr*, 4> ImpDefs; 97 }; 98} 99 100char PNE::ID = 0; 101static RegisterPass<PNE> 102X("phi-node-elimination", "Eliminate PHI nodes for register allocation"); 103 104const PassInfo *const llvm::PHIEliminationID = &X; 105 106bool PNE::runOnMachineFunction(MachineFunction &Fn) { 107 MRI = &Fn.getRegInfo(); 108 109 analyzePHINodes(Fn); 110 111 bool Changed = false; 112 113 // Eliminate PHI instructions by inserting copies into predecessor blocks. 114 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 115 Changed |= EliminatePHINodes(Fn, *I); 116 117 // Remove dead IMPLICIT_DEF instructions. 118 for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(), 119 E = ImpDefs.end(); I != E; ++I) { 120 MachineInstr *DefMI = *I; 121 unsigned DefReg = DefMI->getOperand(0).getReg(); 122 if (MRI->use_empty(DefReg)) 123 DefMI->eraseFromParent(); 124 } 125 126 ImpDefs.clear(); 127 VRegPHIUseCount.clear(); 128 return Changed; 129} 130 131 132/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in 133/// predecessor basic blocks. 134/// 135bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) { 136 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI) 137 return false; // Quick exit for basic blocks without PHIs. 138 139 // Get an iterator to the first instruction after the last PHI node (this may 140 // also be the end of the basic block). 141 MachineBasicBlock::iterator AfterPHIsIt = SkipPHIsAndLabels(MBB, MBB.begin()); 142 143 while (MBB.front().getOpcode() == TargetInstrInfo::PHI) 144 LowerAtomicPHINode(MBB, AfterPHIsIt); 145 146 return true; 147} 148 149/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node 150/// are implicit_def's. 151static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, 152 const MachineRegisterInfo *MRI) { 153 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) { 154 unsigned SrcReg = MPhi->getOperand(i).getReg(); 155 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 156 if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) 157 return false; 158 } 159 return true; 160} 161 162// FindCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg. 163// This needs to be after any def or uses of SrcReg, but before any subsequent 164// point where control flow might jump out of the basic block. 165MachineBasicBlock::iterator PNE::FindCopyInsertPoint(MachineBasicBlock &MBB, 166 unsigned SrcReg) { 167 // Handle the trivial case trivially. 168 if (MBB.empty()) 169 return MBB.begin(); 170 171 // If this basic block does not contain an invoke, then control flow always 172 // reaches the end of it, so place the copy there. 173 // If the terminator is a branch depending upon the side effects of a 174 // previous cmp; a copy can not be inserted here if the copy insn also 175 // side effects. We don't have access to the attributes of copy insn here; 176 // so just play safe by finding a safe locations for branch terminators. 177 // 178 // The logic below works in this case too, but is more expensive. 179 const TerminatorInst *TermInst = MBB.getBasicBlock()->getTerminator(); 180 if (!(isa<InvokeInst>(TermInst) || isa<BranchInst>(TermInst))) 181 return MBB.getFirstTerminator(); 182 183 // Discover any definition/uses in this basic block. 184 SmallPtrSet<MachineInstr*, 8> DefUsesInMBB; 185 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), 186 RE = MRI->reg_end(); RI != RE; ++RI) { 187 MachineInstr *DefUseMI = &*RI; 188 if (DefUseMI->getParent() == &MBB) 189 DefUsesInMBB.insert(DefUseMI); 190 } 191 192 MachineBasicBlock::iterator InsertPoint; 193 if (DefUsesInMBB.empty()) { 194 // No def/uses. Insert the copy at the start of the basic block. 195 InsertPoint = MBB.begin(); 196 } else if (DefUsesInMBB.size() == 1) { 197 // Insert the copy immediately after the definition/use. 198 InsertPoint = *DefUsesInMBB.begin(); 199 ++InsertPoint; 200 } else { 201 // Insert the copy immediately after the last definition/use. 202 InsertPoint = MBB.end(); 203 while (!DefUsesInMBB.count(&*--InsertPoint)) {} 204 ++InsertPoint; 205 } 206 207 // Make sure the copy goes after any phi nodes however. 208 return SkipPHIsAndLabels(MBB, InsertPoint); 209} 210 211/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block, 212/// under the assuption that it needs to be lowered in a way that supports 213/// atomic execution of PHIs. This lowering method is always correct all of the 214/// time. 215/// 216void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, 217 MachineBasicBlock::iterator AfterPHIsIt) { 218 // Unlink the PHI node from the basic block, but don't delete the PHI yet. 219 MachineInstr *MPhi = MBB.remove(MBB.begin()); 220 221 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2; 222 unsigned DestReg = MPhi->getOperand(0).getReg(); 223 bool isDead = MPhi->getOperand(0).isDead(); 224 225 // Create a new register for the incoming PHI arguments. 226 MachineFunction &MF = *MBB.getParent(); 227 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); 228 unsigned IncomingReg = 0; 229 230 // Insert a register to register copy at the top of the current block (but 231 // after any remaining phi nodes) which copies the new incoming register 232 // into the phi node destination. 233 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); 234 if (isSourceDefinedByImplicitDef(MPhi, MRI)) 235 // If all sources of a PHI node are implicit_def, just emit an 236 // implicit_def instead of a copy. 237 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), 238 TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg); 239 else { 240 IncomingReg = MF.getRegInfo().createVirtualRegister(RC); 241 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); 242 } 243 244 // Update live variable information if there is any. 245 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>(); 246 if (LV) { 247 MachineInstr *PHICopy = prior(AfterPHIsIt); 248 249 if (IncomingReg) { 250 // Increment use count of the newly created virtual register. 251 LV->getVarInfo(IncomingReg).NumUses++; 252 253 // Add information to LiveVariables to know that the incoming value is 254 // killed. Note that because the value is defined in several places (once 255 // each for each incoming block), the "def" block and instruction fields 256 // for the VarInfo is not filled in. 257 LV->addVirtualRegisterKilled(IncomingReg, PHICopy); 258 } 259 260 // Since we are going to be deleting the PHI node, if it is the last use of 261 // any registers, or if the value itself is dead, we need to move this 262 // information over to the new copy we just inserted. 263 LV->removeVirtualRegistersKilled(MPhi); 264 265 // If the result is dead, update LV. 266 if (isDead) { 267 LV->addVirtualRegisterDead(DestReg, PHICopy); 268 LV->removeVirtualRegisterDead(DestReg, MPhi); 269 } 270 } 271 272 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node. 273 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) 274 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(), 275 MPhi->getOperand(i).getReg())]; 276 277 // Now loop over all of the incoming arguments, changing them to copy into the 278 // IncomingReg register in the corresponding predecessor basic block. 279 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto; 280 for (int i = NumSrcs - 1; i >= 0; --i) { 281 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); 282 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && 283 "Machine PHI Operands must all be virtual registers!"); 284 285 // If source is defined by an implicit def, there is no need to insert a 286 // copy. 287 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 288 if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) { 289 ImpDefs.insert(DefMI); 290 continue; 291 } 292 293 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source 294 // path the PHI. 295 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB(); 296 297 // Check to make sure we haven't already emitted the copy for this block. 298 // This can happen because PHI nodes may have multiple entries for the same 299 // basic block. 300 if (!MBBsInsertedInto.insert(&opBlock)) 301 continue; // If the copy has already been emitted, we're done. 302 303 // Find a safe location to insert the copy, this may be the first terminator 304 // in the block (or end()). 305 MachineBasicBlock::iterator InsertPos = FindCopyInsertPoint(opBlock, SrcReg); 306 307 // Insert the copy. 308 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC); 309 310 // Now update live variable information if we have it. Otherwise we're done 311 if (!LV) continue; 312 313 // We want to be able to insert a kill of the register if this PHI (aka, the 314 // copy we just inserted) is the last use of the source value. Live 315 // variable analysis conservatively handles this by saying that the value is 316 // live until the end of the block the PHI entry lives in. If the value 317 // really is dead at the PHI copy, there will be no successor blocks which 318 // have the value live-in. 319 // 320 // Check to see if the copy is the last use, and if so, update the live 321 // variables information so that it knows the copy source instruction kills 322 // the incoming value. 323 LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg); 324 325 // Loop over all of the successors of the basic block, checking to see if 326 // the value is either live in the block, or if it is killed in the block. 327 // Also check to see if this register is in use by another PHI node which 328 // has not yet been eliminated. If so, it will be killed at an appropriate 329 // point later. 330 331 // Is it used by any PHI instructions in this block? 332 bool ValueIsLive = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0; 333 334 std::vector<MachineBasicBlock*> OpSuccBlocks; 335 336 // Otherwise, scan successors, including the BB the PHI node lives in. 337 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(), 338 E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) { 339 MachineBasicBlock *SuccMBB = *SI; 340 341 // Is it alive in this successor? 342 unsigned SuccIdx = SuccMBB->getNumber(); 343 if (InRegVI.AliveBlocks.test(SuccIdx)) { 344 ValueIsLive = true; 345 break; 346 } 347 348 OpSuccBlocks.push_back(SuccMBB); 349 } 350 351 // Check to see if this value is live because there is a use in a successor 352 // that kills it. 353 if (!ValueIsLive) { 354 switch (OpSuccBlocks.size()) { 355 case 1: { 356 MachineBasicBlock *MBB = OpSuccBlocks[0]; 357 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i) 358 if (InRegVI.Kills[i]->getParent() == MBB) { 359 ValueIsLive = true; 360 break; 361 } 362 break; 363 } 364 case 2: { 365 MachineBasicBlock *MBB1 = OpSuccBlocks[0], *MBB2 = OpSuccBlocks[1]; 366 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i) 367 if (InRegVI.Kills[i]->getParent() == MBB1 || 368 InRegVI.Kills[i]->getParent() == MBB2) { 369 ValueIsLive = true; 370 break; 371 } 372 break; 373 } 374 default: 375 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end()); 376 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i) 377 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(), 378 InRegVI.Kills[i]->getParent())) { 379 ValueIsLive = true; 380 break; 381 } 382 } 383 } 384 385 // Okay, if we now know that the value is not live out of the block, we can 386 // add a kill marker in this block saying that it kills the incoming value! 387 if (!ValueIsLive) { 388 // In our final twist, we have to decide which instruction kills the 389 // register. In most cases this is the copy, however, the first 390 // terminator instruction at the end of the block may also use the value. 391 // In this case, we should mark *it* as being the killing block, not the 392 // copy. 393 MachineBasicBlock::iterator KillInst = prior(InsertPos); 394 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator(); 395 if (Term != opBlock.end()) { 396 if (Term->readsRegister(SrcReg)) 397 KillInst = Term; 398 399 // Check that no other terminators use values. 400#ifndef NDEBUG 401 for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end(); 402 ++TI) { 403 assert(!TI->readsRegister(SrcReg) && 404 "Terminator instructions cannot use virtual registers unless" 405 "they are the first terminator in a block!"); 406 } 407#endif 408 } 409 410 // Finally, mark it killed. 411 LV->addVirtualRegisterKilled(SrcReg, KillInst); 412 413 // This vreg no longer lives all of the way through opBlock. 414 unsigned opBlockNum = opBlock.getNumber(); 415 InRegVI.AliveBlocks.reset(opBlockNum); 416 } 417 } 418 419 // Really delete the PHI instruction now! 420 MF.DeleteMachineInstr(MPhi); 421 ++NumAtomic; 422} 423 424/// analyzePHINodes - Gather information about the PHI nodes in here. In 425/// particular, we want to map the number of uses of a virtual register which is 426/// used in a PHI node. We map that to the BB the vreg is coming from. This is 427/// used later to determine when the vreg is killed in the BB. 428/// 429void PNE::analyzePHINodes(const MachineFunction& Fn) { 430 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end(); 431 I != E; ++I) 432 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); 433 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) 434 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) 435 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(), 436 BBI->getOperand(i).getReg())]; 437} 438