DAGCombiner.cpp revision 05d92fe7c4310340335512a3a7de97d3cf07d68d
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/CodeGen/SelectionDAG.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/Target/TargetData.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include "llvm/ADT/Statistic.h" 40#include "llvm/Support/Compiler.h" 41#include "llvm/Support/CommandLine.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Support/MathExtras.h" 44#include <algorithm> 45using namespace llvm; 46 47STATISTIC(NodesCombined , "Number of dag nodes combined"); 48STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 49STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 50 51namespace { 52#ifndef NDEBUG 53 static cl::opt<bool> 54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 55 cl::desc("Pop up a window to show dags before the first " 56 "dag combine pass")); 57 static cl::opt<bool> 58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 59 cl::desc("Pop up a window to show dags before the second " 60 "dag combine pass")); 61#else 62 static const bool ViewDAGCombine1 = false; 63 static const bool ViewDAGCombine2 = false; 64#endif 65 66 static cl::opt<bool> 67 CombinerAA("combiner-alias-analysis", cl::Hidden, 68 cl::desc("Turn on alias analysis during testing")); 69 70 static cl::opt<bool> 71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 72 cl::desc("Include global information in alias analysis")); 73 74//------------------------------ DAGCombiner ---------------------------------// 75 76 class VISIBILITY_HIDDEN DAGCombiner { 77 SelectionDAG &DAG; 78 TargetLowering &TLI; 79 bool AfterLegalize; 80 81 // Worklist of all of the nodes that need to be simplified. 82 std::vector<SDNode*> WorkList; 83 84 // AA - Used for DAG load/store alias analysis. 85 AliasAnalysis &AA; 86 87 /// AddUsersToWorkList - When an instruction is simplified, add all users of 88 /// the instruction to the work lists because they might get more simplified 89 /// now. 90 /// 91 void AddUsersToWorkList(SDNode *N) { 92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 93 UI != UE; ++UI) 94 AddToWorkList(*UI); 95 } 96 97 /// removeFromWorkList - remove all instances of N from the worklist. 98 /// 99 void removeFromWorkList(SDNode *N) { 100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 101 WorkList.end()); 102 } 103 104 public: 105 /// AddToWorkList - Add to the work list making sure it's instance is at the 106 /// the back (next to be processed.) 107 void AddToWorkList(SDNode *N) { 108 removeFromWorkList(N); 109 WorkList.push_back(N); 110 } 111 112 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 113 bool AddTo = true) { 114 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 115 ++NodesCombined; 116 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 117 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 118 DOUT << " and " << NumTo-1 << " other values\n"; 119 std::vector<SDNode*> NowDead; 120 DAG.ReplaceAllUsesWith(N, To, &NowDead); 121 122 if (AddTo) { 123 // Push the new nodes and any users onto the worklist 124 for (unsigned i = 0, e = NumTo; i != e; ++i) { 125 AddToWorkList(To[i].Val); 126 AddUsersToWorkList(To[i].Val); 127 } 128 } 129 130 // Nodes can be reintroduced into the worklist. Make sure we do not 131 // process a node that has been replaced. 132 removeFromWorkList(N); 133 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 134 removeFromWorkList(NowDead[i]); 135 136 // Finally, since the node is now dead, remove it from the graph. 137 DAG.DeleteNode(N); 138 return SDOperand(N, 0); 139 } 140 141 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 142 return CombineTo(N, &Res, 1, AddTo); 143 } 144 145 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 146 bool AddTo = true) { 147 SDOperand To[] = { Res0, Res1 }; 148 return CombineTo(N, To, 2, AddTo); 149 } 150 private: 151 152 /// SimplifyDemandedBits - Check the specified integer node value to see if 153 /// it can be simplified or if things it uses can be simplified by bit 154 /// propagation. If so, return true. 155 bool SimplifyDemandedBits(SDOperand Op) { 156 TargetLowering::TargetLoweringOpt TLO(DAG); 157 uint64_t KnownZero, KnownOne; 158 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 159 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 160 return false; 161 162 // Revisit the node. 163 AddToWorkList(Op.Val); 164 165 // Replace the old value with the new one. 166 ++NodesCombined; 167 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 168 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 169 DOUT << '\n'; 170 171 std::vector<SDNode*> NowDead; 172 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 173 174 // Push the new node and any (possibly new) users onto the worklist. 175 AddToWorkList(TLO.New.Val); 176 AddUsersToWorkList(TLO.New.Val); 177 178 // Nodes can end up on the worklist more than once. Make sure we do 179 // not process a node that has been replaced. 180 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 181 removeFromWorkList(NowDead[i]); 182 183 // Finally, if the node is now dead, remove it from the graph. The node 184 // may not be dead if the replacement process recursively simplified to 185 // something else needing this node. 186 if (TLO.Old.Val->use_empty()) { 187 removeFromWorkList(TLO.Old.Val); 188 189 // If the operands of this node are only used by the node, they will now 190 // be dead. Make sure to visit them first to delete dead nodes early. 191 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 192 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 193 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 194 195 DAG.DeleteNode(TLO.Old.Val); 196 } 197 return true; 198 } 199 200 bool CombineToPreIndexedLoadStore(SDNode *N); 201 bool CombineToPostIndexedLoadStore(SDNode *N); 202 203 204 /// visit - call the node-specific routine that knows how to fold each 205 /// particular type of node. 206 SDOperand visit(SDNode *N); 207 208 // Visitation implementation - Implement dag node combining for different 209 // node types. The semantics are as follows: 210 // Return Value: 211 // SDOperand.Val == 0 - No change was made 212 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 213 // otherwise - N should be replaced by the returned Operand. 214 // 215 SDOperand visitTokenFactor(SDNode *N); 216 SDOperand visitADD(SDNode *N); 217 SDOperand visitSUB(SDNode *N); 218 SDOperand visitADDC(SDNode *N); 219 SDOperand visitADDE(SDNode *N); 220 SDOperand visitMUL(SDNode *N); 221 SDOperand visitSDIV(SDNode *N); 222 SDOperand visitUDIV(SDNode *N); 223 SDOperand visitSREM(SDNode *N); 224 SDOperand visitUREM(SDNode *N); 225 SDOperand visitMULHU(SDNode *N); 226 SDOperand visitMULHS(SDNode *N); 227 SDOperand visitAND(SDNode *N); 228 SDOperand visitOR(SDNode *N); 229 SDOperand visitXOR(SDNode *N); 230 SDOperand SimplifyVBinOp(SDNode *N); 231 SDOperand visitSHL(SDNode *N); 232 SDOperand visitSRA(SDNode *N); 233 SDOperand visitSRL(SDNode *N); 234 SDOperand visitCTLZ(SDNode *N); 235 SDOperand visitCTTZ(SDNode *N); 236 SDOperand visitCTPOP(SDNode *N); 237 SDOperand visitSELECT(SDNode *N); 238 SDOperand visitSELECT_CC(SDNode *N); 239 SDOperand visitSETCC(SDNode *N); 240 SDOperand visitSIGN_EXTEND(SDNode *N); 241 SDOperand visitZERO_EXTEND(SDNode *N); 242 SDOperand visitANY_EXTEND(SDNode *N); 243 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 244 SDOperand visitTRUNCATE(SDNode *N); 245 SDOperand visitBIT_CONVERT(SDNode *N); 246 SDOperand visitFADD(SDNode *N); 247 SDOperand visitFSUB(SDNode *N); 248 SDOperand visitFMUL(SDNode *N); 249 SDOperand visitFDIV(SDNode *N); 250 SDOperand visitFREM(SDNode *N); 251 SDOperand visitFCOPYSIGN(SDNode *N); 252 SDOperand visitSINT_TO_FP(SDNode *N); 253 SDOperand visitUINT_TO_FP(SDNode *N); 254 SDOperand visitFP_TO_SINT(SDNode *N); 255 SDOperand visitFP_TO_UINT(SDNode *N); 256 SDOperand visitFP_ROUND(SDNode *N); 257 SDOperand visitFP_ROUND_INREG(SDNode *N); 258 SDOperand visitFP_EXTEND(SDNode *N); 259 SDOperand visitFNEG(SDNode *N); 260 SDOperand visitFABS(SDNode *N); 261 SDOperand visitBRCOND(SDNode *N); 262 SDOperand visitBR_CC(SDNode *N); 263 SDOperand visitLOAD(SDNode *N); 264 SDOperand visitSTORE(SDNode *N); 265 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 266 SDOperand visitBUILD_VECTOR(SDNode *N); 267 SDOperand visitCONCAT_VECTORS(SDNode *N); 268 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 269 270 SDOperand XformToShuffleWithZero(SDNode *N); 271 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 272 273 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 274 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 275 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 276 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 277 SDOperand N3, ISD::CondCode CC, 278 bool NotExtCompare = false); 279 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 280 ISD::CondCode Cond, bool foldBooleans = true); 281 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 282 SDOperand BuildSDIV(SDNode *N); 283 SDOperand BuildUDIV(SDNode *N); 284 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 285 SDOperand ReduceLoadWidth(SDNode *N); 286 287 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 288 /// looking for aliasing nodes and adding them to the Aliases vector. 289 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 290 SmallVector<SDOperand, 8> &Aliases); 291 292 /// isAlias - Return true if there is any possibility that the two addresses 293 /// overlap. 294 bool isAlias(SDOperand Ptr1, int64_t Size1, 295 const Value *SrcValue1, int SrcValueOffset1, 296 SDOperand Ptr2, int64_t Size2, 297 const Value *SrcValue2, int SrcValueOffset2); 298 299 /// FindAliasInfo - Extracts the relevant alias information from the memory 300 /// node. Returns true if the operand was a load. 301 bool FindAliasInfo(SDNode *N, 302 SDOperand &Ptr, int64_t &Size, 303 const Value *&SrcValue, int &SrcValueOffset); 304 305 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 306 /// looking for a better chain (aliasing node.) 307 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 308 309public: 310 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 311 : DAG(D), 312 TLI(D.getTargetLoweringInfo()), 313 AfterLegalize(false), 314 AA(A) {} 315 316 /// Run - runs the dag combiner on all nodes in the work list 317 void Run(bool RunningAfterLegalize); 318 }; 319} 320 321//===----------------------------------------------------------------------===// 322// TargetLowering::DAGCombinerInfo implementation 323//===----------------------------------------------------------------------===// 324 325void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 326 ((DAGCombiner*)DC)->AddToWorkList(N); 327} 328 329SDOperand TargetLowering::DAGCombinerInfo:: 330CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 331 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 332} 333 334SDOperand TargetLowering::DAGCombinerInfo:: 335CombineTo(SDNode *N, SDOperand Res) { 336 return ((DAGCombiner*)DC)->CombineTo(N, Res); 337} 338 339 340SDOperand TargetLowering::DAGCombinerInfo:: 341CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 342 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 343} 344 345 346//===----------------------------------------------------------------------===// 347// Helper Functions 348//===----------------------------------------------------------------------===// 349 350/// isNegatibleForFree - Return 1 if we can compute the negated form of the 351/// specified expression for the same cost as the expression itself, or 2 if we 352/// can compute the negated form more cheaply than the expression itself. 353static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 354 // fneg is removable even if it has multiple uses. 355 if (Op.getOpcode() == ISD::FNEG) return 2; 356 357 // Don't allow anything with multiple uses. 358 if (!Op.hasOneUse()) return 0; 359 360 // Don't recurse exponentially. 361 if (Depth > 6) return 0; 362 363 switch (Op.getOpcode()) { 364 default: return false; 365 case ISD::ConstantFP: 366 return 1; 367 case ISD::FADD: 368 // FIXME: determine better conditions for this xform. 369 if (!UnsafeFPMath) return 0; 370 371 // -(A+B) -> -A - B 372 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 373 return V; 374 // -(A+B) -> -B - A 375 return isNegatibleForFree(Op.getOperand(1), Depth+1); 376 case ISD::FSUB: 377 // We can't turn -(A-B) into B-A when we honor signed zeros. 378 if (!UnsafeFPMath) return 0; 379 380 // -(A-B) -> B-A 381 return 1; 382 383 case ISD::FMUL: 384 case ISD::FDIV: 385 if (HonorSignDependentRoundingFPMath()) return 0; 386 387 // -(X*Y) -> (-X * Y) or (X*-Y) 388 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 389 return V; 390 391 return isNegatibleForFree(Op.getOperand(1), Depth+1); 392 393 case ISD::FP_EXTEND: 394 case ISD::FP_ROUND: 395 case ISD::FSIN: 396 return isNegatibleForFree(Op.getOperand(0), Depth+1); 397 } 398} 399 400/// GetNegatedExpression - If isNegatibleForFree returns true, this function 401/// returns the newly negated expression. 402static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 403 unsigned Depth = 0) { 404 // fneg is removable even if it has multiple uses. 405 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 406 407 // Don't allow anything with multiple uses. 408 assert(Op.hasOneUse() && "Unknown reuse!"); 409 410 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 411 switch (Op.getOpcode()) { 412 default: assert(0 && "Unknown code"); 413 case ISD::ConstantFP: 414 return DAG.getConstantFP(-cast<ConstantFPSDNode>(Op)->getValue(), 415 Op.getValueType()); 416 case ISD::FADD: 417 // FIXME: determine better conditions for this xform. 418 assert(UnsafeFPMath); 419 420 // -(A+B) -> -A - B 421 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 422 return DAG.getNode(ISD::FSUB, Op.getValueType(), 423 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 424 Op.getOperand(1)); 425 // -(A+B) -> -B - A 426 return DAG.getNode(ISD::FSUB, Op.getValueType(), 427 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 428 Op.getOperand(0)); 429 case ISD::FSUB: 430 // We can't turn -(A-B) into B-A when we honor signed zeros. 431 assert(UnsafeFPMath); 432 433 // -(0-B) -> B 434 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 435 if (N0CFP->getValue() == 0.0) 436 return Op.getOperand(1); 437 438 // -(A-B) -> B-A 439 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 440 Op.getOperand(0)); 441 442 case ISD::FMUL: 443 case ISD::FDIV: 444 assert(!HonorSignDependentRoundingFPMath()); 445 446 // -(X*Y) -> -X * Y 447 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 448 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 449 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 450 Op.getOperand(1)); 451 452 // -(X*Y) -> X * -Y 453 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 454 Op.getOperand(0), 455 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 456 457 case ISD::FP_EXTEND: 458 case ISD::FP_ROUND: 459 case ISD::FSIN: 460 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 461 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 462 } 463} 464 465 466// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 467// that selects between the values 1 and 0, making it equivalent to a setcc. 468// Also, set the incoming LHS, RHS, and CC references to the appropriate 469// nodes based on the type of node we are checking. This simplifies life a 470// bit for the callers. 471static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 472 SDOperand &CC) { 473 if (N.getOpcode() == ISD::SETCC) { 474 LHS = N.getOperand(0); 475 RHS = N.getOperand(1); 476 CC = N.getOperand(2); 477 return true; 478 } 479 if (N.getOpcode() == ISD::SELECT_CC && 480 N.getOperand(2).getOpcode() == ISD::Constant && 481 N.getOperand(3).getOpcode() == ISD::Constant && 482 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 483 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 484 LHS = N.getOperand(0); 485 RHS = N.getOperand(1); 486 CC = N.getOperand(4); 487 return true; 488 } 489 return false; 490} 491 492// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 493// one use. If this is true, it allows the users to invert the operation for 494// free when it is profitable to do so. 495static bool isOneUseSetCC(SDOperand N) { 496 SDOperand N0, N1, N2; 497 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 498 return true; 499 return false; 500} 501 502SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 503 MVT::ValueType VT = N0.getValueType(); 504 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 506 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 507 if (isa<ConstantSDNode>(N1)) { 508 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 509 AddToWorkList(OpNode.Val); 510 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 511 } else if (N0.hasOneUse()) { 512 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 513 AddToWorkList(OpNode.Val); 514 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 515 } 516 } 517 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 518 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 519 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 520 if (isa<ConstantSDNode>(N0)) { 521 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 522 AddToWorkList(OpNode.Val); 523 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 524 } else if (N1.hasOneUse()) { 525 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 526 AddToWorkList(OpNode.Val); 527 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 528 } 529 } 530 return SDOperand(); 531} 532 533//===----------------------------------------------------------------------===// 534// Main DAG Combiner implementation 535//===----------------------------------------------------------------------===// 536 537void DAGCombiner::Run(bool RunningAfterLegalize) { 538 // set the instance variable, so that the various visit routines may use it. 539 AfterLegalize = RunningAfterLegalize; 540 541 // Add all the dag nodes to the worklist. 542 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 543 E = DAG.allnodes_end(); I != E; ++I) 544 WorkList.push_back(I); 545 546 // Create a dummy node (which is not added to allnodes), that adds a reference 547 // to the root node, preventing it from being deleted, and tracking any 548 // changes of the root. 549 HandleSDNode Dummy(DAG.getRoot()); 550 551 // The root of the dag may dangle to deleted nodes until the dag combiner is 552 // done. Set it to null to avoid confusion. 553 DAG.setRoot(SDOperand()); 554 555 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 556 TargetLowering::DAGCombinerInfo 557 DagCombineInfo(DAG, !RunningAfterLegalize, false, this); 558 559 // while the worklist isn't empty, inspect the node on the end of it and 560 // try and combine it. 561 while (!WorkList.empty()) { 562 SDNode *N = WorkList.back(); 563 WorkList.pop_back(); 564 565 // If N has no uses, it is dead. Make sure to revisit all N's operands once 566 // N is deleted from the DAG, since they too may now be dead or may have a 567 // reduced number of uses, allowing other xforms. 568 if (N->use_empty() && N != &Dummy) { 569 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 570 AddToWorkList(N->getOperand(i).Val); 571 572 DAG.DeleteNode(N); 573 continue; 574 } 575 576 SDOperand RV = visit(N); 577 578 // If nothing happened, try a target-specific DAG combine. 579 if (RV.Val == 0) { 580 assert(N->getOpcode() != ISD::DELETED_NODE && 581 "Node was deleted but visit returned NULL!"); 582 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 583 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 584 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 585 } 586 587 if (RV.Val) { 588 ++NodesCombined; 589 // If we get back the same node we passed in, rather than a new node or 590 // zero, we know that the node must have defined multiple values and 591 // CombineTo was used. Since CombineTo takes care of the worklist 592 // mechanics for us, we have no work to do in this case. 593 if (RV.Val != N) { 594 assert(N->getOpcode() != ISD::DELETED_NODE && 595 RV.Val->getOpcode() != ISD::DELETED_NODE && 596 "Node was deleted but visit returned new node!"); 597 598 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 599 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 600 DOUT << '\n'; 601 std::vector<SDNode*> NowDead; 602 if (N->getNumValues() == RV.Val->getNumValues()) 603 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 604 else { 605 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 606 SDOperand OpV = RV; 607 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 608 } 609 610 // Push the new node and any users onto the worklist 611 AddToWorkList(RV.Val); 612 AddUsersToWorkList(RV.Val); 613 614 // Nodes can be reintroduced into the worklist. Make sure we do not 615 // process a node that has been replaced. 616 removeFromWorkList(N); 617 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 618 removeFromWorkList(NowDead[i]); 619 620 // Finally, since the node is now dead, remove it from the graph. 621 DAG.DeleteNode(N); 622 } 623 } 624 } 625 626 // If the root changed (e.g. it was a dead load, update the root). 627 DAG.setRoot(Dummy.getValue()); 628} 629 630SDOperand DAGCombiner::visit(SDNode *N) { 631 switch(N->getOpcode()) { 632 default: break; 633 case ISD::TokenFactor: return visitTokenFactor(N); 634 case ISD::ADD: return visitADD(N); 635 case ISD::SUB: return visitSUB(N); 636 case ISD::ADDC: return visitADDC(N); 637 case ISD::ADDE: return visitADDE(N); 638 case ISD::MUL: return visitMUL(N); 639 case ISD::SDIV: return visitSDIV(N); 640 case ISD::UDIV: return visitUDIV(N); 641 case ISD::SREM: return visitSREM(N); 642 case ISD::UREM: return visitUREM(N); 643 case ISD::MULHU: return visitMULHU(N); 644 case ISD::MULHS: return visitMULHS(N); 645 case ISD::AND: return visitAND(N); 646 case ISD::OR: return visitOR(N); 647 case ISD::XOR: return visitXOR(N); 648 case ISD::SHL: return visitSHL(N); 649 case ISD::SRA: return visitSRA(N); 650 case ISD::SRL: return visitSRL(N); 651 case ISD::CTLZ: return visitCTLZ(N); 652 case ISD::CTTZ: return visitCTTZ(N); 653 case ISD::CTPOP: return visitCTPOP(N); 654 case ISD::SELECT: return visitSELECT(N); 655 case ISD::SELECT_CC: return visitSELECT_CC(N); 656 case ISD::SETCC: return visitSETCC(N); 657 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 658 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 659 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 660 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 661 case ISD::TRUNCATE: return visitTRUNCATE(N); 662 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 663 case ISD::FADD: return visitFADD(N); 664 case ISD::FSUB: return visitFSUB(N); 665 case ISD::FMUL: return visitFMUL(N); 666 case ISD::FDIV: return visitFDIV(N); 667 case ISD::FREM: return visitFREM(N); 668 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 669 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 670 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 671 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 672 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 673 case ISD::FP_ROUND: return visitFP_ROUND(N); 674 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 675 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 676 case ISD::FNEG: return visitFNEG(N); 677 case ISD::FABS: return visitFABS(N); 678 case ISD::BRCOND: return visitBRCOND(N); 679 case ISD::BR_CC: return visitBR_CC(N); 680 case ISD::LOAD: return visitLOAD(N); 681 case ISD::STORE: return visitSTORE(N); 682 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 683 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 684 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 685 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 686 } 687 return SDOperand(); 688} 689 690/// getInputChainForNode - Given a node, return its input chain if it has one, 691/// otherwise return a null sd operand. 692static SDOperand getInputChainForNode(SDNode *N) { 693 if (unsigned NumOps = N->getNumOperands()) { 694 if (N->getOperand(0).getValueType() == MVT::Other) 695 return N->getOperand(0); 696 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 697 return N->getOperand(NumOps-1); 698 for (unsigned i = 1; i < NumOps-1; ++i) 699 if (N->getOperand(i).getValueType() == MVT::Other) 700 return N->getOperand(i); 701 } 702 return SDOperand(0, 0); 703} 704 705SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 706 // If N has two operands, where one has an input chain equal to the other, 707 // the 'other' chain is redundant. 708 if (N->getNumOperands() == 2) { 709 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 710 return N->getOperand(0); 711 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 712 return N->getOperand(1); 713 } 714 715 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 716 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 717 SmallPtrSet<SDNode*, 16> SeenOps; 718 bool Changed = false; // If we should replace this token factor. 719 720 // Start out with this token factor. 721 TFs.push_back(N); 722 723 // Iterate through token factors. The TFs grows when new token factors are 724 // encountered. 725 for (unsigned i = 0; i < TFs.size(); ++i) { 726 SDNode *TF = TFs[i]; 727 728 // Check each of the operands. 729 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 730 SDOperand Op = TF->getOperand(i); 731 732 switch (Op.getOpcode()) { 733 case ISD::EntryToken: 734 // Entry tokens don't need to be added to the list. They are 735 // rededundant. 736 Changed = true; 737 break; 738 739 case ISD::TokenFactor: 740 if ((CombinerAA || Op.hasOneUse()) && 741 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 742 // Queue up for processing. 743 TFs.push_back(Op.Val); 744 // Clean up in case the token factor is removed. 745 AddToWorkList(Op.Val); 746 Changed = true; 747 break; 748 } 749 // Fall thru 750 751 default: 752 // Only add if it isn't already in the list. 753 if (SeenOps.insert(Op.Val)) 754 Ops.push_back(Op); 755 else 756 Changed = true; 757 break; 758 } 759 } 760 } 761 762 SDOperand Result; 763 764 // If we've change things around then replace token factor. 765 if (Changed) { 766 if (Ops.size() == 0) { 767 // The entry token is the only possible outcome. 768 Result = DAG.getEntryNode(); 769 } else { 770 // New and improved token factor. 771 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 772 } 773 774 // Don't add users to work list. 775 return CombineTo(N, Result, false); 776 } 777 778 return Result; 779} 780 781static 782SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 783 MVT::ValueType VT = N0.getValueType(); 784 SDOperand N00 = N0.getOperand(0); 785 SDOperand N01 = N0.getOperand(1); 786 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 787 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 788 isa<ConstantSDNode>(N00.getOperand(1))) { 789 N0 = DAG.getNode(ISD::ADD, VT, 790 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 791 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 792 return DAG.getNode(ISD::ADD, VT, N0, N1); 793 } 794 return SDOperand(); 795} 796 797static 798SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 799 SelectionDAG &DAG) { 800 MVT::ValueType VT = N->getValueType(0); 801 unsigned Opc = N->getOpcode(); 802 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 803 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 804 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 805 ISD::CondCode CC = ISD::SETCC_INVALID; 806 if (isSlctCC) 807 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 808 else { 809 SDOperand CCOp = Slct.getOperand(0); 810 if (CCOp.getOpcode() == ISD::SETCC) 811 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 812 } 813 814 bool DoXform = false; 815 bool InvCC = false; 816 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 817 "Bad input!"); 818 if (LHS.getOpcode() == ISD::Constant && 819 cast<ConstantSDNode>(LHS)->isNullValue()) 820 DoXform = true; 821 else if (CC != ISD::SETCC_INVALID && 822 RHS.getOpcode() == ISD::Constant && 823 cast<ConstantSDNode>(RHS)->isNullValue()) { 824 std::swap(LHS, RHS); 825 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType() 826 : Slct.getOperand(0).getOperand(0).getValueType()); 827 CC = ISD::getSetCCInverse(CC, isInt); 828 DoXform = true; 829 InvCC = true; 830 } 831 832 if (DoXform) { 833 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 834 if (isSlctCC) 835 return DAG.getSelectCC(OtherOp, Result, 836 Slct.getOperand(0), Slct.getOperand(1), CC); 837 SDOperand CCOp = Slct.getOperand(0); 838 if (InvCC) 839 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 840 CCOp.getOperand(1), CC); 841 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 842 } 843 return SDOperand(); 844} 845 846SDOperand DAGCombiner::visitADD(SDNode *N) { 847 SDOperand N0 = N->getOperand(0); 848 SDOperand N1 = N->getOperand(1); 849 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 850 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 851 MVT::ValueType VT = N0.getValueType(); 852 853 // fold vector ops 854 if (MVT::isVector(VT)) { 855 SDOperand FoldedVOp = SimplifyVBinOp(N); 856 if (FoldedVOp.Val) return FoldedVOp; 857 } 858 859 // fold (add x, undef) -> undef 860 if (N0.getOpcode() == ISD::UNDEF) 861 return N0; 862 if (N1.getOpcode() == ISD::UNDEF) 863 return N1; 864 // fold (add c1, c2) -> c1+c2 865 if (N0C && N1C) 866 return DAG.getNode(ISD::ADD, VT, N0, N1); 867 // canonicalize constant to RHS 868 if (N0C && !N1C) 869 return DAG.getNode(ISD::ADD, VT, N1, N0); 870 // fold (add x, 0) -> x 871 if (N1C && N1C->isNullValue()) 872 return N0; 873 // fold ((c1-A)+c2) -> (c1+c2)-A 874 if (N1C && N0.getOpcode() == ISD::SUB) 875 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 876 return DAG.getNode(ISD::SUB, VT, 877 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 878 N0.getOperand(1)); 879 // reassociate add 880 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 881 if (RADD.Val != 0) 882 return RADD; 883 // fold ((0-A) + B) -> B-A 884 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 885 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 886 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 887 // fold (A + (0-B)) -> A-B 888 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 889 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 890 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 891 // fold (A+(B-A)) -> B 892 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 893 return N1.getOperand(0); 894 895 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 896 return SDOperand(N, 0); 897 898 // fold (a+b) -> (a|b) iff a and b share no bits. 899 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 900 uint64_t LHSZero, LHSOne; 901 uint64_t RHSZero, RHSOne; 902 uint64_t Mask = MVT::getIntVTBitMask(VT); 903 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 904 if (LHSZero) { 905 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 906 907 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 908 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 909 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 910 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 911 return DAG.getNode(ISD::OR, VT, N0, N1); 912 } 913 } 914 915 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 916 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 917 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 918 if (Result.Val) return Result; 919 } 920 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 921 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 922 if (Result.Val) return Result; 923 } 924 925 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 926 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 927 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 928 if (Result.Val) return Result; 929 } 930 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 931 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 932 if (Result.Val) return Result; 933 } 934 935 return SDOperand(); 936} 937 938SDOperand DAGCombiner::visitADDC(SDNode *N) { 939 SDOperand N0 = N->getOperand(0); 940 SDOperand N1 = N->getOperand(1); 941 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 942 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 943 MVT::ValueType VT = N0.getValueType(); 944 945 // If the flag result is dead, turn this into an ADD. 946 if (N->hasNUsesOfValue(0, 1)) 947 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 948 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 949 950 // canonicalize constant to RHS. 951 if (N0C && !N1C) { 952 SDOperand Ops[] = { N1, N0 }; 953 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 954 } 955 956 // fold (addc x, 0) -> x + no carry out 957 if (N1C && N1C->isNullValue()) 958 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 959 960 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 961 uint64_t LHSZero, LHSOne; 962 uint64_t RHSZero, RHSOne; 963 uint64_t Mask = MVT::getIntVTBitMask(VT); 964 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 965 if (LHSZero) { 966 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 967 968 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 969 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 970 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 971 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 972 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 973 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 974 } 975 976 return SDOperand(); 977} 978 979SDOperand DAGCombiner::visitADDE(SDNode *N) { 980 SDOperand N0 = N->getOperand(0); 981 SDOperand N1 = N->getOperand(1); 982 SDOperand CarryIn = N->getOperand(2); 983 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 984 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 985 //MVT::ValueType VT = N0.getValueType(); 986 987 // canonicalize constant to RHS 988 if (N0C && !N1C) { 989 SDOperand Ops[] = { N1, N0, CarryIn }; 990 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 991 } 992 993 // fold (adde x, y, false) -> (addc x, y) 994 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 995 SDOperand Ops[] = { N1, N0 }; 996 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 997 } 998 999 return SDOperand(); 1000} 1001 1002 1003 1004SDOperand DAGCombiner::visitSUB(SDNode *N) { 1005 SDOperand N0 = N->getOperand(0); 1006 SDOperand N1 = N->getOperand(1); 1007 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1008 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1009 MVT::ValueType VT = N0.getValueType(); 1010 1011 // fold vector ops 1012 if (MVT::isVector(VT)) { 1013 SDOperand FoldedVOp = SimplifyVBinOp(N); 1014 if (FoldedVOp.Val) return FoldedVOp; 1015 } 1016 1017 // fold (sub x, x) -> 0 1018 if (N0 == N1) 1019 return DAG.getConstant(0, N->getValueType(0)); 1020 // fold (sub c1, c2) -> c1-c2 1021 if (N0C && N1C) 1022 return DAG.getNode(ISD::SUB, VT, N0, N1); 1023 // fold (sub x, c) -> (add x, -c) 1024 if (N1C) 1025 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1026 // fold (A+B)-A -> B 1027 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1028 return N0.getOperand(1); 1029 // fold (A+B)-B -> A 1030 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1031 return N0.getOperand(0); 1032 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1033 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1034 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1035 if (Result.Val) return Result; 1036 } 1037 // If either operand of a sub is undef, the result is undef 1038 if (N0.getOpcode() == ISD::UNDEF) 1039 return N0; 1040 if (N1.getOpcode() == ISD::UNDEF) 1041 return N1; 1042 1043 return SDOperand(); 1044} 1045 1046SDOperand DAGCombiner::visitMUL(SDNode *N) { 1047 SDOperand N0 = N->getOperand(0); 1048 SDOperand N1 = N->getOperand(1); 1049 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1050 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1051 MVT::ValueType VT = N0.getValueType(); 1052 1053 // fold vector ops 1054 if (MVT::isVector(VT)) { 1055 SDOperand FoldedVOp = SimplifyVBinOp(N); 1056 if (FoldedVOp.Val) return FoldedVOp; 1057 } 1058 1059 // fold (mul x, undef) -> 0 1060 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1061 return DAG.getConstant(0, VT); 1062 // fold (mul c1, c2) -> c1*c2 1063 if (N0C && N1C) 1064 return DAG.getNode(ISD::MUL, VT, N0, N1); 1065 // canonicalize constant to RHS 1066 if (N0C && !N1C) 1067 return DAG.getNode(ISD::MUL, VT, N1, N0); 1068 // fold (mul x, 0) -> 0 1069 if (N1C && N1C->isNullValue()) 1070 return N1; 1071 // fold (mul x, -1) -> 0-x 1072 if (N1C && N1C->isAllOnesValue()) 1073 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1074 // fold (mul x, (1 << c)) -> x << c 1075 if (N1C && isPowerOf2_64(N1C->getValue())) 1076 return DAG.getNode(ISD::SHL, VT, N0, 1077 DAG.getConstant(Log2_64(N1C->getValue()), 1078 TLI.getShiftAmountTy())); 1079 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1080 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1081 // FIXME: If the input is something that is easily negated (e.g. a 1082 // single-use add), we should put the negate there. 1083 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1084 DAG.getNode(ISD::SHL, VT, N0, 1085 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1086 TLI.getShiftAmountTy()))); 1087 } 1088 1089 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1090 if (N1C && N0.getOpcode() == ISD::SHL && 1091 isa<ConstantSDNode>(N0.getOperand(1))) { 1092 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1093 AddToWorkList(C3.Val); 1094 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1095 } 1096 1097 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1098 // use. 1099 { 1100 SDOperand Sh(0,0), Y(0,0); 1101 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1102 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1103 N0.Val->hasOneUse()) { 1104 Sh = N0; Y = N1; 1105 } else if (N1.getOpcode() == ISD::SHL && 1106 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1107 Sh = N1; Y = N0; 1108 } 1109 if (Sh.Val) { 1110 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1111 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1112 } 1113 } 1114 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1115 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1116 isa<ConstantSDNode>(N0.getOperand(1))) { 1117 return DAG.getNode(ISD::ADD, VT, 1118 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1119 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1120 } 1121 1122 // reassociate mul 1123 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1124 if (RMUL.Val != 0) 1125 return RMUL; 1126 1127 return SDOperand(); 1128} 1129 1130SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1131 SDOperand N0 = N->getOperand(0); 1132 SDOperand N1 = N->getOperand(1); 1133 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1134 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1135 MVT::ValueType VT = N->getValueType(0); 1136 1137 // fold vector ops 1138 if (MVT::isVector(VT)) { 1139 SDOperand FoldedVOp = SimplifyVBinOp(N); 1140 if (FoldedVOp.Val) return FoldedVOp; 1141 } 1142 1143 // fold (sdiv c1, c2) -> c1/c2 1144 if (N0C && N1C && !N1C->isNullValue()) 1145 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1146 // fold (sdiv X, 1) -> X 1147 if (N1C && N1C->getSignExtended() == 1LL) 1148 return N0; 1149 // fold (sdiv X, -1) -> 0-X 1150 if (N1C && N1C->isAllOnesValue()) 1151 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1152 // If we know the sign bits of both operands are zero, strength reduce to a 1153 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1154 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1155 if (DAG.MaskedValueIsZero(N1, SignBit) && 1156 DAG.MaskedValueIsZero(N0, SignBit)) 1157 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1158 // fold (sdiv X, pow2) -> simple ops after legalize 1159 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1160 (isPowerOf2_64(N1C->getSignExtended()) || 1161 isPowerOf2_64(-N1C->getSignExtended()))) { 1162 // If dividing by powers of two is cheap, then don't perform the following 1163 // fold. 1164 if (TLI.isPow2DivCheap()) 1165 return SDOperand(); 1166 int64_t pow2 = N1C->getSignExtended(); 1167 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1168 unsigned lg2 = Log2_64(abs2); 1169 // Splat the sign bit into the register 1170 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1171 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1172 TLI.getShiftAmountTy())); 1173 AddToWorkList(SGN.Val); 1174 // Add (N0 < 0) ? abs2 - 1 : 0; 1175 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1176 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1177 TLI.getShiftAmountTy())); 1178 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1179 AddToWorkList(SRL.Val); 1180 AddToWorkList(ADD.Val); // Divide by pow2 1181 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1182 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1183 // If we're dividing by a positive value, we're done. Otherwise, we must 1184 // negate the result. 1185 if (pow2 > 0) 1186 return SRA; 1187 AddToWorkList(SRA.Val); 1188 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1189 } 1190 // if integer divide is expensive and we satisfy the requirements, emit an 1191 // alternate sequence. 1192 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1193 !TLI.isIntDivCheap()) { 1194 SDOperand Op = BuildSDIV(N); 1195 if (Op.Val) return Op; 1196 } 1197 1198 // undef / X -> 0 1199 if (N0.getOpcode() == ISD::UNDEF) 1200 return DAG.getConstant(0, VT); 1201 // X / undef -> undef 1202 if (N1.getOpcode() == ISD::UNDEF) 1203 return N1; 1204 1205 return SDOperand(); 1206} 1207 1208SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1209 SDOperand N0 = N->getOperand(0); 1210 SDOperand N1 = N->getOperand(1); 1211 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1212 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1213 MVT::ValueType VT = N->getValueType(0); 1214 1215 // fold vector ops 1216 if (MVT::isVector(VT)) { 1217 SDOperand FoldedVOp = SimplifyVBinOp(N); 1218 if (FoldedVOp.Val) return FoldedVOp; 1219 } 1220 1221 // fold (udiv c1, c2) -> c1/c2 1222 if (N0C && N1C && !N1C->isNullValue()) 1223 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1224 // fold (udiv x, (1 << c)) -> x >>u c 1225 if (N1C && isPowerOf2_64(N1C->getValue())) 1226 return DAG.getNode(ISD::SRL, VT, N0, 1227 DAG.getConstant(Log2_64(N1C->getValue()), 1228 TLI.getShiftAmountTy())); 1229 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1230 if (N1.getOpcode() == ISD::SHL) { 1231 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1232 if (isPowerOf2_64(SHC->getValue())) { 1233 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1234 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1235 DAG.getConstant(Log2_64(SHC->getValue()), 1236 ADDVT)); 1237 AddToWorkList(Add.Val); 1238 return DAG.getNode(ISD::SRL, VT, N0, Add); 1239 } 1240 } 1241 } 1242 // fold (udiv x, c) -> alternate 1243 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1244 SDOperand Op = BuildUDIV(N); 1245 if (Op.Val) return Op; 1246 } 1247 1248 // undef / X -> 0 1249 if (N0.getOpcode() == ISD::UNDEF) 1250 return DAG.getConstant(0, VT); 1251 // X / undef -> undef 1252 if (N1.getOpcode() == ISD::UNDEF) 1253 return N1; 1254 1255 return SDOperand(); 1256} 1257 1258SDOperand DAGCombiner::visitSREM(SDNode *N) { 1259 SDOperand N0 = N->getOperand(0); 1260 SDOperand N1 = N->getOperand(1); 1261 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1262 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1263 MVT::ValueType VT = N->getValueType(0); 1264 1265 // fold (srem c1, c2) -> c1%c2 1266 if (N0C && N1C && !N1C->isNullValue()) 1267 return DAG.getNode(ISD::SREM, VT, N0, N1); 1268 // If we know the sign bits of both operands are zero, strength reduce to a 1269 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1270 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1271 if (DAG.MaskedValueIsZero(N1, SignBit) && 1272 DAG.MaskedValueIsZero(N0, SignBit)) 1273 return DAG.getNode(ISD::UREM, VT, N0, N1); 1274 1275 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1276 // the remainder operation. 1277 if (N1C && !N1C->isNullValue()) { 1278 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1279 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1280 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1281 AddToWorkList(Div.Val); 1282 AddToWorkList(Mul.Val); 1283 return Sub; 1284 } 1285 1286 // undef % X -> 0 1287 if (N0.getOpcode() == ISD::UNDEF) 1288 return DAG.getConstant(0, VT); 1289 // X % undef -> undef 1290 if (N1.getOpcode() == ISD::UNDEF) 1291 return N1; 1292 1293 return SDOperand(); 1294} 1295 1296SDOperand DAGCombiner::visitUREM(SDNode *N) { 1297 SDOperand N0 = N->getOperand(0); 1298 SDOperand N1 = N->getOperand(1); 1299 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1300 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1301 MVT::ValueType VT = N->getValueType(0); 1302 1303 // fold (urem c1, c2) -> c1%c2 1304 if (N0C && N1C && !N1C->isNullValue()) 1305 return DAG.getNode(ISD::UREM, VT, N0, N1); 1306 // fold (urem x, pow2) -> (and x, pow2-1) 1307 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1308 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1309 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1310 if (N1.getOpcode() == ISD::SHL) { 1311 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1312 if (isPowerOf2_64(SHC->getValue())) { 1313 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1314 AddToWorkList(Add.Val); 1315 return DAG.getNode(ISD::AND, VT, N0, Add); 1316 } 1317 } 1318 } 1319 1320 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1321 // the remainder operation. 1322 if (N1C && !N1C->isNullValue()) { 1323 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1324 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1325 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1326 AddToWorkList(Div.Val); 1327 AddToWorkList(Mul.Val); 1328 return Sub; 1329 } 1330 1331 // undef % X -> 0 1332 if (N0.getOpcode() == ISD::UNDEF) 1333 return DAG.getConstant(0, VT); 1334 // X % undef -> undef 1335 if (N1.getOpcode() == ISD::UNDEF) 1336 return N1; 1337 1338 return SDOperand(); 1339} 1340 1341SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1342 SDOperand N0 = N->getOperand(0); 1343 SDOperand N1 = N->getOperand(1); 1344 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1345 MVT::ValueType VT = N->getValueType(0); 1346 1347 // fold (mulhs x, 0) -> 0 1348 if (N1C && N1C->isNullValue()) 1349 return N1; 1350 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1351 if (N1C && N1C->getValue() == 1) 1352 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1353 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1354 TLI.getShiftAmountTy())); 1355 // fold (mulhs x, undef) -> 0 1356 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1357 return DAG.getConstant(0, VT); 1358 1359 return SDOperand(); 1360} 1361 1362SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1363 SDOperand N0 = N->getOperand(0); 1364 SDOperand N1 = N->getOperand(1); 1365 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1366 MVT::ValueType VT = N->getValueType(0); 1367 1368 // fold (mulhu x, 0) -> 0 1369 if (N1C && N1C->isNullValue()) 1370 return N1; 1371 // fold (mulhu x, 1) -> 0 1372 if (N1C && N1C->getValue() == 1) 1373 return DAG.getConstant(0, N0.getValueType()); 1374 // fold (mulhu x, undef) -> 0 1375 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1376 return DAG.getConstant(0, VT); 1377 1378 return SDOperand(); 1379} 1380 1381/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1382/// two operands of the same opcode, try to simplify it. 1383SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1384 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1385 MVT::ValueType VT = N0.getValueType(); 1386 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1387 1388 // For each of OP in AND/OR/XOR: 1389 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1390 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1391 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1392 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1393 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1394 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1395 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1396 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1397 N0.getOperand(0).getValueType(), 1398 N0.getOperand(0), N1.getOperand(0)); 1399 AddToWorkList(ORNode.Val); 1400 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1401 } 1402 1403 // For each of OP in SHL/SRL/SRA/AND... 1404 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1405 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1406 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1407 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1408 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1409 N0.getOperand(1) == N1.getOperand(1)) { 1410 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1411 N0.getOperand(0).getValueType(), 1412 N0.getOperand(0), N1.getOperand(0)); 1413 AddToWorkList(ORNode.Val); 1414 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1415 } 1416 1417 return SDOperand(); 1418} 1419 1420SDOperand DAGCombiner::visitAND(SDNode *N) { 1421 SDOperand N0 = N->getOperand(0); 1422 SDOperand N1 = N->getOperand(1); 1423 SDOperand LL, LR, RL, RR, CC0, CC1; 1424 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1425 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1426 MVT::ValueType VT = N1.getValueType(); 1427 1428 // fold vector ops 1429 if (MVT::isVector(VT)) { 1430 SDOperand FoldedVOp = SimplifyVBinOp(N); 1431 if (FoldedVOp.Val) return FoldedVOp; 1432 } 1433 1434 // fold (and x, undef) -> 0 1435 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1436 return DAG.getConstant(0, VT); 1437 // fold (and c1, c2) -> c1&c2 1438 if (N0C && N1C) 1439 return DAG.getNode(ISD::AND, VT, N0, N1); 1440 // canonicalize constant to RHS 1441 if (N0C && !N1C) 1442 return DAG.getNode(ISD::AND, VT, N1, N0); 1443 // fold (and x, -1) -> x 1444 if (N1C && N1C->isAllOnesValue()) 1445 return N0; 1446 // if (and x, c) is known to be zero, return 0 1447 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1448 return DAG.getConstant(0, VT); 1449 // reassociate and 1450 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1451 if (RAND.Val != 0) 1452 return RAND; 1453 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1454 if (N1C && N0.getOpcode() == ISD::OR) 1455 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1456 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1457 return N1; 1458 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1459 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1460 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1461 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1462 ~N1C->getValue() & InMask)) { 1463 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1464 N0.getOperand(0)); 1465 1466 // Replace uses of the AND with uses of the Zero extend node. 1467 CombineTo(N, Zext); 1468 1469 // We actually want to replace all uses of the any_extend with the 1470 // zero_extend, to avoid duplicating things. This will later cause this 1471 // AND to be folded. 1472 CombineTo(N0.Val, Zext); 1473 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1474 } 1475 } 1476 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1477 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1478 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1479 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1480 1481 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1482 MVT::isInteger(LL.getValueType())) { 1483 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1484 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1485 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1486 AddToWorkList(ORNode.Val); 1487 return DAG.getSetCC(VT, ORNode, LR, Op1); 1488 } 1489 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1490 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1491 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1492 AddToWorkList(ANDNode.Val); 1493 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1494 } 1495 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1496 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1497 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1498 AddToWorkList(ORNode.Val); 1499 return DAG.getSetCC(VT, ORNode, LR, Op1); 1500 } 1501 } 1502 // canonicalize equivalent to ll == rl 1503 if (LL == RR && LR == RL) { 1504 Op1 = ISD::getSetCCSwappedOperands(Op1); 1505 std::swap(RL, RR); 1506 } 1507 if (LL == RL && LR == RR) { 1508 bool isInteger = MVT::isInteger(LL.getValueType()); 1509 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1510 if (Result != ISD::SETCC_INVALID) 1511 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1512 } 1513 } 1514 1515 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1516 if (N0.getOpcode() == N1.getOpcode()) { 1517 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1518 if (Tmp.Val) return Tmp; 1519 } 1520 1521 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1522 // fold (and (sra)) -> (and (srl)) when possible. 1523 if (!MVT::isVector(VT) && 1524 SimplifyDemandedBits(SDOperand(N, 0))) 1525 return SDOperand(N, 0); 1526 // fold (zext_inreg (extload x)) -> (zextload x) 1527 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1528 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1529 MVT::ValueType EVT = LN0->getLoadedVT(); 1530 // If we zero all the possible extended bits, then we can turn this into 1531 // a zextload if we are running before legalize or the operation is legal. 1532 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1533 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1534 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1535 LN0->getBasePtr(), LN0->getSrcValue(), 1536 LN0->getSrcValueOffset(), EVT, 1537 LN0->isVolatile(), 1538 LN0->getAlignment()); 1539 AddToWorkList(N); 1540 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1541 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1542 } 1543 } 1544 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1545 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1546 N0.hasOneUse()) { 1547 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1548 MVT::ValueType EVT = LN0->getLoadedVT(); 1549 // If we zero all the possible extended bits, then we can turn this into 1550 // a zextload if we are running before legalize or the operation is legal. 1551 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1552 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1553 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1554 LN0->getBasePtr(), LN0->getSrcValue(), 1555 LN0->getSrcValueOffset(), EVT, 1556 LN0->isVolatile(), 1557 LN0->getAlignment()); 1558 AddToWorkList(N); 1559 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1560 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1561 } 1562 } 1563 1564 // fold (and (load x), 255) -> (zextload x, i8) 1565 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1566 if (N1C && N0.getOpcode() == ISD::LOAD) { 1567 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1568 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1569 LN0->getAddressingMode() == ISD::UNINDEXED && 1570 N0.hasOneUse()) { 1571 MVT::ValueType EVT, LoadedVT; 1572 if (N1C->getValue() == 255) 1573 EVT = MVT::i8; 1574 else if (N1C->getValue() == 65535) 1575 EVT = MVT::i16; 1576 else if (N1C->getValue() == ~0U) 1577 EVT = MVT::i32; 1578 else 1579 EVT = MVT::Other; 1580 1581 LoadedVT = LN0->getLoadedVT(); 1582 if (EVT != MVT::Other && LoadedVT > EVT && 1583 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1584 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1585 // For big endian targets, we need to add an offset to the pointer to 1586 // load the correct bytes. For little endian systems, we merely need to 1587 // read fewer bytes from the same pointer. 1588 unsigned PtrOff = 1589 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1590 SDOperand NewPtr = LN0->getBasePtr(); 1591 if (!TLI.isLittleEndian()) 1592 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1593 DAG.getConstant(PtrOff, PtrType)); 1594 AddToWorkList(NewPtr.Val); 1595 SDOperand Load = 1596 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1597 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1598 LN0->isVolatile(), LN0->getAlignment()); 1599 AddToWorkList(N); 1600 CombineTo(N0.Val, Load, Load.getValue(1)); 1601 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1602 } 1603 } 1604 } 1605 1606 return SDOperand(); 1607} 1608 1609SDOperand DAGCombiner::visitOR(SDNode *N) { 1610 SDOperand N0 = N->getOperand(0); 1611 SDOperand N1 = N->getOperand(1); 1612 SDOperand LL, LR, RL, RR, CC0, CC1; 1613 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1614 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1615 MVT::ValueType VT = N1.getValueType(); 1616 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1617 1618 // fold vector ops 1619 if (MVT::isVector(VT)) { 1620 SDOperand FoldedVOp = SimplifyVBinOp(N); 1621 if (FoldedVOp.Val) return FoldedVOp; 1622 } 1623 1624 // fold (or x, undef) -> -1 1625 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1626 return DAG.getConstant(~0ULL, VT); 1627 // fold (or c1, c2) -> c1|c2 1628 if (N0C && N1C) 1629 return DAG.getNode(ISD::OR, VT, N0, N1); 1630 // canonicalize constant to RHS 1631 if (N0C && !N1C) 1632 return DAG.getNode(ISD::OR, VT, N1, N0); 1633 // fold (or x, 0) -> x 1634 if (N1C && N1C->isNullValue()) 1635 return N0; 1636 // fold (or x, -1) -> -1 1637 if (N1C && N1C->isAllOnesValue()) 1638 return N1; 1639 // fold (or x, c) -> c iff (x & ~c) == 0 1640 if (N1C && 1641 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1642 return N1; 1643 // reassociate or 1644 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1645 if (ROR.Val != 0) 1646 return ROR; 1647 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1648 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1649 isa<ConstantSDNode>(N0.getOperand(1))) { 1650 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1651 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1652 N1), 1653 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1654 } 1655 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1656 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1657 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1658 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1659 1660 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1661 MVT::isInteger(LL.getValueType())) { 1662 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1663 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1664 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1665 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1666 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1667 AddToWorkList(ORNode.Val); 1668 return DAG.getSetCC(VT, ORNode, LR, Op1); 1669 } 1670 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1671 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1672 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1673 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1674 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1675 AddToWorkList(ANDNode.Val); 1676 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1677 } 1678 } 1679 // canonicalize equivalent to ll == rl 1680 if (LL == RR && LR == RL) { 1681 Op1 = ISD::getSetCCSwappedOperands(Op1); 1682 std::swap(RL, RR); 1683 } 1684 if (LL == RL && LR == RR) { 1685 bool isInteger = MVT::isInteger(LL.getValueType()); 1686 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1687 if (Result != ISD::SETCC_INVALID) 1688 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1689 } 1690 } 1691 1692 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1693 if (N0.getOpcode() == N1.getOpcode()) { 1694 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1695 if (Tmp.Val) return Tmp; 1696 } 1697 1698 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1699 if (N0.getOpcode() == ISD::AND && 1700 N1.getOpcode() == ISD::AND && 1701 N0.getOperand(1).getOpcode() == ISD::Constant && 1702 N1.getOperand(1).getOpcode() == ISD::Constant && 1703 // Don't increase # computations. 1704 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1705 // We can only do this xform if we know that bits from X that are set in C2 1706 // but not in C1 are already zero. Likewise for Y. 1707 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1708 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1709 1710 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1711 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1712 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1713 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1714 } 1715 } 1716 1717 1718 // See if this is some rotate idiom. 1719 if (SDNode *Rot = MatchRotate(N0, N1)) 1720 return SDOperand(Rot, 0); 1721 1722 return SDOperand(); 1723} 1724 1725 1726/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1727static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1728 if (Op.getOpcode() == ISD::AND) { 1729 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1730 Mask = Op.getOperand(1); 1731 Op = Op.getOperand(0); 1732 } else { 1733 return false; 1734 } 1735 } 1736 1737 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1738 Shift = Op; 1739 return true; 1740 } 1741 return false; 1742} 1743 1744 1745// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1746// idioms for rotate, and if the target supports rotation instructions, generate 1747// a rot[lr]. 1748SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1749 // Must be a legal type. Expanded an promoted things won't work with rotates. 1750 MVT::ValueType VT = LHS.getValueType(); 1751 if (!TLI.isTypeLegal(VT)) return 0; 1752 1753 // The target must have at least one rotate flavor. 1754 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1755 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1756 if (!HasROTL && !HasROTR) return 0; 1757 1758 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1759 SDOperand LHSShift; // The shift. 1760 SDOperand LHSMask; // AND value if any. 1761 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1762 return 0; // Not part of a rotate. 1763 1764 SDOperand RHSShift; // The shift. 1765 SDOperand RHSMask; // AND value if any. 1766 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1767 return 0; // Not part of a rotate. 1768 1769 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1770 return 0; // Not shifting the same value. 1771 1772 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1773 return 0; // Shifts must disagree. 1774 1775 // Canonicalize shl to left side in a shl/srl pair. 1776 if (RHSShift.getOpcode() == ISD::SHL) { 1777 std::swap(LHS, RHS); 1778 std::swap(LHSShift, RHSShift); 1779 std::swap(LHSMask , RHSMask ); 1780 } 1781 1782 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1783 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1784 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1785 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1786 1787 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1788 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1789 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1790 RHSShiftAmt.getOpcode() == ISD::Constant) { 1791 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1792 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1793 if ((LShVal + RShVal) != OpSizeInBits) 1794 return 0; 1795 1796 SDOperand Rot; 1797 if (HasROTL) 1798 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1799 else 1800 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1801 1802 // If there is an AND of either shifted operand, apply it to the result. 1803 if (LHSMask.Val || RHSMask.Val) { 1804 uint64_t Mask = MVT::getIntVTBitMask(VT); 1805 1806 if (LHSMask.Val) { 1807 uint64_t RHSBits = (1ULL << LShVal)-1; 1808 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1809 } 1810 if (RHSMask.Val) { 1811 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1812 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1813 } 1814 1815 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1816 } 1817 1818 return Rot.Val; 1819 } 1820 1821 // If there is a mask here, and we have a variable shift, we can't be sure 1822 // that we're masking out the right stuff. 1823 if (LHSMask.Val || RHSMask.Val) 1824 return 0; 1825 1826 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1827 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1828 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1829 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1830 if (ConstantSDNode *SUBC = 1831 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1832 if (SUBC->getValue() == OpSizeInBits) 1833 if (HasROTL) 1834 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1835 else 1836 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1837 } 1838 } 1839 1840 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1841 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1842 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1843 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1844 if (ConstantSDNode *SUBC = 1845 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1846 if (SUBC->getValue() == OpSizeInBits) 1847 if (HasROTL) 1848 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1849 else 1850 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1851 } 1852 } 1853 1854 // Look for sign/zext/any-extended cases: 1855 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1856 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1857 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1858 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1859 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1860 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1861 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1862 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1863 if (RExtOp0.getOpcode() == ISD::SUB && 1864 RExtOp0.getOperand(1) == LExtOp0) { 1865 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1866 // (rotr x, y) 1867 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1868 // (rotl x, (sub 32, y)) 1869 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1870 if (SUBC->getValue() == OpSizeInBits) { 1871 if (HasROTL) 1872 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1873 else 1874 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1875 } 1876 } 1877 } else if (LExtOp0.getOpcode() == ISD::SUB && 1878 RExtOp0 == LExtOp0.getOperand(1)) { 1879 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1880 // (rotl x, y) 1881 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1882 // (rotr x, (sub 32, y)) 1883 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 1884 if (SUBC->getValue() == OpSizeInBits) { 1885 if (HasROTL) 1886 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 1887 else 1888 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1889 } 1890 } 1891 } 1892 } 1893 1894 return 0; 1895} 1896 1897 1898SDOperand DAGCombiner::visitXOR(SDNode *N) { 1899 SDOperand N0 = N->getOperand(0); 1900 SDOperand N1 = N->getOperand(1); 1901 SDOperand LHS, RHS, CC; 1902 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1903 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1904 MVT::ValueType VT = N0.getValueType(); 1905 1906 // fold vector ops 1907 if (MVT::isVector(VT)) { 1908 SDOperand FoldedVOp = SimplifyVBinOp(N); 1909 if (FoldedVOp.Val) return FoldedVOp; 1910 } 1911 1912 // fold (xor x, undef) -> undef 1913 if (N0.getOpcode() == ISD::UNDEF) 1914 return N0; 1915 if (N1.getOpcode() == ISD::UNDEF) 1916 return N1; 1917 // fold (xor c1, c2) -> c1^c2 1918 if (N0C && N1C) 1919 return DAG.getNode(ISD::XOR, VT, N0, N1); 1920 // canonicalize constant to RHS 1921 if (N0C && !N1C) 1922 return DAG.getNode(ISD::XOR, VT, N1, N0); 1923 // fold (xor x, 0) -> x 1924 if (N1C && N1C->isNullValue()) 1925 return N0; 1926 // reassociate xor 1927 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1928 if (RXOR.Val != 0) 1929 return RXOR; 1930 // fold !(x cc y) -> (x !cc y) 1931 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1932 bool isInt = MVT::isInteger(LHS.getValueType()); 1933 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1934 isInt); 1935 if (N0.getOpcode() == ISD::SETCC) 1936 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1937 if (N0.getOpcode() == ISD::SELECT_CC) 1938 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1939 assert(0 && "Unhandled SetCC Equivalent!"); 1940 abort(); 1941 } 1942 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1943 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 1944 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1945 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1946 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1947 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1948 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1949 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1950 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1951 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1952 } 1953 } 1954 // fold !(x or y) -> (!x and !y) iff x or y are constants 1955 if (N1C && N1C->isAllOnesValue() && 1956 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1957 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1958 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1959 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1960 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1961 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1962 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1963 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1964 } 1965 } 1966 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1967 if (N1C && N0.getOpcode() == ISD::XOR) { 1968 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1969 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1970 if (N00C) 1971 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1972 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1973 if (N01C) 1974 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1975 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1976 } 1977 // fold (xor x, x) -> 0 1978 if (N0 == N1) { 1979 if (!MVT::isVector(VT)) { 1980 return DAG.getConstant(0, VT); 1981 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1982 // Produce a vector of zeros. 1983 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 1984 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1985 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1986 } 1987 } 1988 1989 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1990 if (N0.getOpcode() == N1.getOpcode()) { 1991 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1992 if (Tmp.Val) return Tmp; 1993 } 1994 1995 // Simplify the expression using non-local knowledge. 1996 if (!MVT::isVector(VT) && 1997 SimplifyDemandedBits(SDOperand(N, 0))) 1998 return SDOperand(N, 0); 1999 2000 return SDOperand(); 2001} 2002 2003SDOperand DAGCombiner::visitSHL(SDNode *N) { 2004 SDOperand N0 = N->getOperand(0); 2005 SDOperand N1 = N->getOperand(1); 2006 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2007 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2008 MVT::ValueType VT = N0.getValueType(); 2009 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2010 2011 // fold (shl c1, c2) -> c1<<c2 2012 if (N0C && N1C) 2013 return DAG.getNode(ISD::SHL, VT, N0, N1); 2014 // fold (shl 0, x) -> 0 2015 if (N0C && N0C->isNullValue()) 2016 return N0; 2017 // fold (shl x, c >= size(x)) -> undef 2018 if (N1C && N1C->getValue() >= OpSizeInBits) 2019 return DAG.getNode(ISD::UNDEF, VT); 2020 // fold (shl x, 0) -> x 2021 if (N1C && N1C->isNullValue()) 2022 return N0; 2023 // if (shl x, c) is known to be zero, return 0 2024 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2025 return DAG.getConstant(0, VT); 2026 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2027 return SDOperand(N, 0); 2028 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2029 if (N1C && N0.getOpcode() == ISD::SHL && 2030 N0.getOperand(1).getOpcode() == ISD::Constant) { 2031 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2032 uint64_t c2 = N1C->getValue(); 2033 if (c1 + c2 > OpSizeInBits) 2034 return DAG.getConstant(0, VT); 2035 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2036 DAG.getConstant(c1 + c2, N1.getValueType())); 2037 } 2038 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2039 // (srl (and x, -1 << c1), c1-c2) 2040 if (N1C && N0.getOpcode() == ISD::SRL && 2041 N0.getOperand(1).getOpcode() == ISD::Constant) { 2042 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2043 uint64_t c2 = N1C->getValue(); 2044 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2045 DAG.getConstant(~0ULL << c1, VT)); 2046 if (c2 > c1) 2047 return DAG.getNode(ISD::SHL, VT, Mask, 2048 DAG.getConstant(c2-c1, N1.getValueType())); 2049 else 2050 return DAG.getNode(ISD::SRL, VT, Mask, 2051 DAG.getConstant(c1-c2, N1.getValueType())); 2052 } 2053 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2054 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2055 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2056 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2057 return SDOperand(); 2058} 2059 2060SDOperand DAGCombiner::visitSRA(SDNode *N) { 2061 SDOperand N0 = N->getOperand(0); 2062 SDOperand N1 = N->getOperand(1); 2063 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2064 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2065 MVT::ValueType VT = N0.getValueType(); 2066 2067 // fold (sra c1, c2) -> c1>>c2 2068 if (N0C && N1C) 2069 return DAG.getNode(ISD::SRA, VT, N0, N1); 2070 // fold (sra 0, x) -> 0 2071 if (N0C && N0C->isNullValue()) 2072 return N0; 2073 // fold (sra -1, x) -> -1 2074 if (N0C && N0C->isAllOnesValue()) 2075 return N0; 2076 // fold (sra x, c >= size(x)) -> undef 2077 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2078 return DAG.getNode(ISD::UNDEF, VT); 2079 // fold (sra x, 0) -> x 2080 if (N1C && N1C->isNullValue()) 2081 return N0; 2082 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2083 // sext_inreg. 2084 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2085 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2086 MVT::ValueType EVT; 2087 switch (LowBits) { 2088 default: EVT = MVT::Other; break; 2089 case 1: EVT = MVT::i1; break; 2090 case 8: EVT = MVT::i8; break; 2091 case 16: EVT = MVT::i16; break; 2092 case 32: EVT = MVT::i32; break; 2093 } 2094 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2095 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2096 DAG.getValueType(EVT)); 2097 } 2098 2099 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2100 if (N1C && N0.getOpcode() == ISD::SRA) { 2101 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2102 unsigned Sum = N1C->getValue() + C1->getValue(); 2103 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2104 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2105 DAG.getConstant(Sum, N1C->getValueType(0))); 2106 } 2107 } 2108 2109 // Simplify, based on bits shifted out of the LHS. 2110 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2111 return SDOperand(N, 0); 2112 2113 2114 // If the sign bit is known to be zero, switch this to a SRL. 2115 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2116 return DAG.getNode(ISD::SRL, VT, N0, N1); 2117 return SDOperand(); 2118} 2119 2120SDOperand DAGCombiner::visitSRL(SDNode *N) { 2121 SDOperand N0 = N->getOperand(0); 2122 SDOperand N1 = N->getOperand(1); 2123 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2124 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2125 MVT::ValueType VT = N0.getValueType(); 2126 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2127 2128 // fold (srl c1, c2) -> c1 >>u c2 2129 if (N0C && N1C) 2130 return DAG.getNode(ISD::SRL, VT, N0, N1); 2131 // fold (srl 0, x) -> 0 2132 if (N0C && N0C->isNullValue()) 2133 return N0; 2134 // fold (srl x, c >= size(x)) -> undef 2135 if (N1C && N1C->getValue() >= OpSizeInBits) 2136 return DAG.getNode(ISD::UNDEF, VT); 2137 // fold (srl x, 0) -> x 2138 if (N1C && N1C->isNullValue()) 2139 return N0; 2140 // if (srl x, c) is known to be zero, return 0 2141 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2142 return DAG.getConstant(0, VT); 2143 2144 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2145 if (N1C && N0.getOpcode() == ISD::SRL && 2146 N0.getOperand(1).getOpcode() == ISD::Constant) { 2147 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2148 uint64_t c2 = N1C->getValue(); 2149 if (c1 + c2 > OpSizeInBits) 2150 return DAG.getConstant(0, VT); 2151 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2152 DAG.getConstant(c1 + c2, N1.getValueType())); 2153 } 2154 2155 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2156 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2157 // Shifting in all undef bits? 2158 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2159 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2160 return DAG.getNode(ISD::UNDEF, VT); 2161 2162 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2163 AddToWorkList(SmallShift.Val); 2164 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2165 } 2166 2167 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2168 // bit, which is unmodified by sra. 2169 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2170 if (N0.getOpcode() == ISD::SRA) 2171 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2172 } 2173 2174 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2175 if (N1C && N0.getOpcode() == ISD::CTLZ && 2176 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2177 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2178 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2179 2180 // If any of the input bits are KnownOne, then the input couldn't be all 2181 // zeros, thus the result of the srl will always be zero. 2182 if (KnownOne) return DAG.getConstant(0, VT); 2183 2184 // If all of the bits input the to ctlz node are known to be zero, then 2185 // the result of the ctlz is "32" and the result of the shift is one. 2186 uint64_t UnknownBits = ~KnownZero & Mask; 2187 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2188 2189 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2190 if ((UnknownBits & (UnknownBits-1)) == 0) { 2191 // Okay, we know that only that the single bit specified by UnknownBits 2192 // could be set on input to the CTLZ node. If this bit is set, the SRL 2193 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2194 // to an SRL,XOR pair, which is likely to simplify more. 2195 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2196 SDOperand Op = N0.getOperand(0); 2197 if (ShAmt) { 2198 Op = DAG.getNode(ISD::SRL, VT, Op, 2199 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2200 AddToWorkList(Op.Val); 2201 } 2202 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2203 } 2204 } 2205 2206 // fold operands of srl based on knowledge that the low bits are not 2207 // demanded. 2208 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2209 return SDOperand(N, 0); 2210 2211 return SDOperand(); 2212} 2213 2214SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2215 SDOperand N0 = N->getOperand(0); 2216 MVT::ValueType VT = N->getValueType(0); 2217 2218 // fold (ctlz c1) -> c2 2219 if (isa<ConstantSDNode>(N0)) 2220 return DAG.getNode(ISD::CTLZ, VT, N0); 2221 return SDOperand(); 2222} 2223 2224SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2225 SDOperand N0 = N->getOperand(0); 2226 MVT::ValueType VT = N->getValueType(0); 2227 2228 // fold (cttz c1) -> c2 2229 if (isa<ConstantSDNode>(N0)) 2230 return DAG.getNode(ISD::CTTZ, VT, N0); 2231 return SDOperand(); 2232} 2233 2234SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2235 SDOperand N0 = N->getOperand(0); 2236 MVT::ValueType VT = N->getValueType(0); 2237 2238 // fold (ctpop c1) -> c2 2239 if (isa<ConstantSDNode>(N0)) 2240 return DAG.getNode(ISD::CTPOP, VT, N0); 2241 return SDOperand(); 2242} 2243 2244SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2245 SDOperand N0 = N->getOperand(0); 2246 SDOperand N1 = N->getOperand(1); 2247 SDOperand N2 = N->getOperand(2); 2248 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2249 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2250 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2251 MVT::ValueType VT = N->getValueType(0); 2252 2253 // fold select C, X, X -> X 2254 if (N1 == N2) 2255 return N1; 2256 // fold select true, X, Y -> X 2257 if (N0C && !N0C->isNullValue()) 2258 return N1; 2259 // fold select false, X, Y -> Y 2260 if (N0C && N0C->isNullValue()) 2261 return N2; 2262 // fold select C, 1, X -> C | X 2263 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2264 return DAG.getNode(ISD::OR, VT, N0, N2); 2265 // fold select C, 0, X -> ~C & X 2266 // FIXME: this should check for C type == X type, not i1? 2267 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 2268 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2269 AddToWorkList(XORNode.Val); 2270 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2271 } 2272 // fold select C, X, 1 -> ~C | X 2273 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 2274 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2275 AddToWorkList(XORNode.Val); 2276 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2277 } 2278 // fold select C, X, 0 -> C & X 2279 // FIXME: this should check for C type == X type, not i1? 2280 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2281 return DAG.getNode(ISD::AND, VT, N0, N1); 2282 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2283 if (MVT::i1 == VT && N0 == N1) 2284 return DAG.getNode(ISD::OR, VT, N0, N2); 2285 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2286 if (MVT::i1 == VT && N0 == N2) 2287 return DAG.getNode(ISD::AND, VT, N0, N1); 2288 2289 // If we can fold this based on the true/false value, do so. 2290 if (SimplifySelectOps(N, N1, N2)) 2291 return SDOperand(N, 0); // Don't revisit N. 2292 2293 // fold selects based on a setcc into other things, such as min/max/abs 2294 if (N0.getOpcode() == ISD::SETCC) 2295 // FIXME: 2296 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2297 // having to say they don't support SELECT_CC on every type the DAG knows 2298 // about, since there is no way to mark an opcode illegal at all value types 2299 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2300 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2301 N1, N2, N0.getOperand(2)); 2302 else 2303 return SimplifySelect(N0, N1, N2); 2304 return SDOperand(); 2305} 2306 2307SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2308 SDOperand N0 = N->getOperand(0); 2309 SDOperand N1 = N->getOperand(1); 2310 SDOperand N2 = N->getOperand(2); 2311 SDOperand N3 = N->getOperand(3); 2312 SDOperand N4 = N->getOperand(4); 2313 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2314 2315 // fold select_cc lhs, rhs, x, x, cc -> x 2316 if (N2 == N3) 2317 return N2; 2318 2319 // Determine if the condition we're dealing with is constant 2320 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2321 if (SCC.Val) AddToWorkList(SCC.Val); 2322 2323 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2324 if (SCCC->getValue()) 2325 return N2; // cond always true -> true val 2326 else 2327 return N3; // cond always false -> false val 2328 } 2329 2330 // Fold to a simpler select_cc 2331 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2332 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2333 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2334 SCC.getOperand(2)); 2335 2336 // If we can fold this based on the true/false value, do so. 2337 if (SimplifySelectOps(N, N2, N3)) 2338 return SDOperand(N, 0); // Don't revisit N. 2339 2340 // fold select_cc into other things, such as min/max/abs 2341 return SimplifySelectCC(N0, N1, N2, N3, CC); 2342} 2343 2344SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2345 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2346 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2347} 2348 2349SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2350 SDOperand N0 = N->getOperand(0); 2351 MVT::ValueType VT = N->getValueType(0); 2352 2353 // fold (sext c1) -> c1 2354 if (isa<ConstantSDNode>(N0)) 2355 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2356 2357 // fold (sext (sext x)) -> (sext x) 2358 // fold (sext (aext x)) -> (sext x) 2359 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2360 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2361 2362 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2363 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2364 if (N0.getOpcode() == ISD::TRUNCATE) { 2365 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2366 if (NarrowLoad.Val) { 2367 if (NarrowLoad.Val != N0.Val) 2368 CombineTo(N0.Val, NarrowLoad); 2369 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2370 } 2371 } 2372 2373 // See if the value being truncated is already sign extended. If so, just 2374 // eliminate the trunc/sext pair. 2375 if (N0.getOpcode() == ISD::TRUNCATE) { 2376 SDOperand Op = N0.getOperand(0); 2377 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2378 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2379 unsigned DestBits = MVT::getSizeInBits(VT); 2380 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2381 2382 if (OpBits == DestBits) { 2383 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2384 // bits, it is already ready. 2385 if (NumSignBits > DestBits-MidBits) 2386 return Op; 2387 } else if (OpBits < DestBits) { 2388 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2389 // bits, just sext from i32. 2390 if (NumSignBits > OpBits-MidBits) 2391 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2392 } else { 2393 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2394 // bits, just truncate to i32. 2395 if (NumSignBits > OpBits-MidBits) 2396 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2397 } 2398 2399 // fold (sext (truncate x)) -> (sextinreg x). 2400 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2401 N0.getValueType())) { 2402 if (Op.getValueType() < VT) 2403 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2404 else if (Op.getValueType() > VT) 2405 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2406 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2407 DAG.getValueType(N0.getValueType())); 2408 } 2409 } 2410 2411 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2412 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2413 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2414 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2415 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2416 LN0->getBasePtr(), LN0->getSrcValue(), 2417 LN0->getSrcValueOffset(), 2418 N0.getValueType(), 2419 LN0->isVolatile(), 2420 LN0->getAlignment()); 2421 CombineTo(N, ExtLoad); 2422 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2423 ExtLoad.getValue(1)); 2424 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2425 } 2426 2427 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2428 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2429 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2430 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2431 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2432 MVT::ValueType EVT = LN0->getLoadedVT(); 2433 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2434 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2435 LN0->getBasePtr(), LN0->getSrcValue(), 2436 LN0->getSrcValueOffset(), EVT, 2437 LN0->isVolatile(), 2438 LN0->getAlignment()); 2439 CombineTo(N, ExtLoad); 2440 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2441 ExtLoad.getValue(1)); 2442 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2443 } 2444 } 2445 2446 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2447 if (N0.getOpcode() == ISD::SETCC) { 2448 SDOperand SCC = 2449 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2450 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2451 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2452 if (SCC.Val) return SCC; 2453 } 2454 2455 return SDOperand(); 2456} 2457 2458SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2459 SDOperand N0 = N->getOperand(0); 2460 MVT::ValueType VT = N->getValueType(0); 2461 2462 // fold (zext c1) -> c1 2463 if (isa<ConstantSDNode>(N0)) 2464 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2465 // fold (zext (zext x)) -> (zext x) 2466 // fold (zext (aext x)) -> (zext x) 2467 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2468 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2469 2470 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2471 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2472 if (N0.getOpcode() == ISD::TRUNCATE) { 2473 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2474 if (NarrowLoad.Val) { 2475 if (NarrowLoad.Val != N0.Val) 2476 CombineTo(N0.Val, NarrowLoad); 2477 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2478 } 2479 } 2480 2481 // fold (zext (truncate x)) -> (and x, mask) 2482 if (N0.getOpcode() == ISD::TRUNCATE && 2483 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2484 SDOperand Op = N0.getOperand(0); 2485 if (Op.getValueType() < VT) { 2486 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2487 } else if (Op.getValueType() > VT) { 2488 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2489 } 2490 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2491 } 2492 2493 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2494 if (N0.getOpcode() == ISD::AND && 2495 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2496 N0.getOperand(1).getOpcode() == ISD::Constant) { 2497 SDOperand X = N0.getOperand(0).getOperand(0); 2498 if (X.getValueType() < VT) { 2499 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2500 } else if (X.getValueType() > VT) { 2501 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2502 } 2503 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2504 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2505 } 2506 2507 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2508 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2509 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2510 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2511 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2512 LN0->getBasePtr(), LN0->getSrcValue(), 2513 LN0->getSrcValueOffset(), 2514 N0.getValueType(), 2515 LN0->isVolatile(), 2516 LN0->getAlignment()); 2517 CombineTo(N, ExtLoad); 2518 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2519 ExtLoad.getValue(1)); 2520 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2521 } 2522 2523 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2524 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2525 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2526 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2527 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2528 MVT::ValueType EVT = LN0->getLoadedVT(); 2529 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2530 LN0->getBasePtr(), LN0->getSrcValue(), 2531 LN0->getSrcValueOffset(), EVT, 2532 LN0->isVolatile(), 2533 LN0->getAlignment()); 2534 CombineTo(N, ExtLoad); 2535 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2536 ExtLoad.getValue(1)); 2537 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2538 } 2539 2540 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2541 if (N0.getOpcode() == ISD::SETCC) { 2542 SDOperand SCC = 2543 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2544 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2545 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2546 if (SCC.Val) return SCC; 2547 } 2548 2549 return SDOperand(); 2550} 2551 2552SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2553 SDOperand N0 = N->getOperand(0); 2554 MVT::ValueType VT = N->getValueType(0); 2555 2556 // fold (aext c1) -> c1 2557 if (isa<ConstantSDNode>(N0)) 2558 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2559 // fold (aext (aext x)) -> (aext x) 2560 // fold (aext (zext x)) -> (zext x) 2561 // fold (aext (sext x)) -> (sext x) 2562 if (N0.getOpcode() == ISD::ANY_EXTEND || 2563 N0.getOpcode() == ISD::ZERO_EXTEND || 2564 N0.getOpcode() == ISD::SIGN_EXTEND) 2565 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2566 2567 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2568 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2569 if (N0.getOpcode() == ISD::TRUNCATE) { 2570 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2571 if (NarrowLoad.Val) { 2572 if (NarrowLoad.Val != N0.Val) 2573 CombineTo(N0.Val, NarrowLoad); 2574 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2575 } 2576 } 2577 2578 // fold (aext (truncate x)) 2579 if (N0.getOpcode() == ISD::TRUNCATE) { 2580 SDOperand TruncOp = N0.getOperand(0); 2581 if (TruncOp.getValueType() == VT) 2582 return TruncOp; // x iff x size == zext size. 2583 if (TruncOp.getValueType() > VT) 2584 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2585 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2586 } 2587 2588 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2589 if (N0.getOpcode() == ISD::AND && 2590 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2591 N0.getOperand(1).getOpcode() == ISD::Constant) { 2592 SDOperand X = N0.getOperand(0).getOperand(0); 2593 if (X.getValueType() < VT) { 2594 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2595 } else if (X.getValueType() > VT) { 2596 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2597 } 2598 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2599 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2600 } 2601 2602 // fold (aext (load x)) -> (aext (truncate (extload x))) 2603 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2604 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2605 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2606 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2607 LN0->getBasePtr(), LN0->getSrcValue(), 2608 LN0->getSrcValueOffset(), 2609 N0.getValueType(), 2610 LN0->isVolatile(), 2611 LN0->getAlignment()); 2612 CombineTo(N, ExtLoad); 2613 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2614 ExtLoad.getValue(1)); 2615 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2616 } 2617 2618 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2619 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2620 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2621 if (N0.getOpcode() == ISD::LOAD && 2622 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2623 N0.hasOneUse()) { 2624 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2625 MVT::ValueType EVT = LN0->getLoadedVT(); 2626 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2627 LN0->getChain(), LN0->getBasePtr(), 2628 LN0->getSrcValue(), 2629 LN0->getSrcValueOffset(), EVT, 2630 LN0->isVolatile(), 2631 LN0->getAlignment()); 2632 CombineTo(N, ExtLoad); 2633 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2634 ExtLoad.getValue(1)); 2635 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2636 } 2637 2638 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2639 if (N0.getOpcode() == ISD::SETCC) { 2640 SDOperand SCC = 2641 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2642 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2643 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2644 if (SCC.Val) 2645 return SCC; 2646 } 2647 2648 return SDOperand(); 2649} 2650 2651/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2652/// bits and then truncated to a narrower type and where N is a multiple 2653/// of number of bits of the narrower type, transform it to a narrower load 2654/// from address + N / num of bits of new type. If the result is to be 2655/// extended, also fold the extension to form a extending load. 2656SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2657 unsigned Opc = N->getOpcode(); 2658 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2659 SDOperand N0 = N->getOperand(0); 2660 MVT::ValueType VT = N->getValueType(0); 2661 MVT::ValueType EVT = N->getValueType(0); 2662 2663 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2664 // extended to VT. 2665 if (Opc == ISD::SIGN_EXTEND_INREG) { 2666 ExtType = ISD::SEXTLOAD; 2667 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2668 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2669 return SDOperand(); 2670 } 2671 2672 unsigned EVTBits = MVT::getSizeInBits(EVT); 2673 unsigned ShAmt = 0; 2674 bool CombineSRL = false; 2675 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2676 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2677 ShAmt = N01->getValue(); 2678 // Is the shift amount a multiple of size of VT? 2679 if ((ShAmt & (EVTBits-1)) == 0) { 2680 N0 = N0.getOperand(0); 2681 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2682 return SDOperand(); 2683 CombineSRL = true; 2684 } 2685 } 2686 } 2687 2688 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2689 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2690 // zero extended form: by shrinking the load, we lose track of the fact 2691 // that it is already zero extended. 2692 // FIXME: This should be reevaluated. 2693 VT != MVT::i1) { 2694 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 2695 "Cannot truncate to larger type!"); 2696 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2697 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2698 // For big endian targets, we need to adjust the offset to the pointer to 2699 // load the correct bytes. 2700 if (!TLI.isLittleEndian()) 2701 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; 2702 uint64_t PtrOff = ShAmt / 8; 2703 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2704 DAG.getConstant(PtrOff, PtrType)); 2705 AddToWorkList(NewPtr.Val); 2706 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 2707 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 2708 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2709 LN0->isVolatile(), LN0->getAlignment()) 2710 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 2711 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 2712 LN0->isVolatile(), LN0->getAlignment()); 2713 AddToWorkList(N); 2714 if (CombineSRL) { 2715 std::vector<SDNode*> NowDead; 2716 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead); 2717 CombineTo(N->getOperand(0).Val, Load); 2718 } else 2719 CombineTo(N0.Val, Load, Load.getValue(1)); 2720 if (ShAmt) { 2721 if (Opc == ISD::SIGN_EXTEND_INREG) 2722 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 2723 else 2724 return DAG.getNode(Opc, VT, Load); 2725 } 2726 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2727 } 2728 2729 return SDOperand(); 2730} 2731 2732 2733SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2734 SDOperand N0 = N->getOperand(0); 2735 SDOperand N1 = N->getOperand(1); 2736 MVT::ValueType VT = N->getValueType(0); 2737 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2738 unsigned EVTBits = MVT::getSizeInBits(EVT); 2739 2740 // fold (sext_in_reg c1) -> c1 2741 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2742 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2743 2744 // If the input is already sign extended, just drop the extension. 2745 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2746 return N0; 2747 2748 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2749 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2750 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2751 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2752 } 2753 2754 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 2755 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2756 return DAG.getZeroExtendInReg(N0, EVT); 2757 2758 // fold operands of sext_in_reg based on knowledge that the top bits are not 2759 // demanded. 2760 if (SimplifyDemandedBits(SDOperand(N, 0))) 2761 return SDOperand(N, 0); 2762 2763 // fold (sext_in_reg (load x)) -> (smaller sextload x) 2764 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 2765 SDOperand NarrowLoad = ReduceLoadWidth(N); 2766 if (NarrowLoad.Val) 2767 return NarrowLoad; 2768 2769 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2770 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2771 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2772 if (N0.getOpcode() == ISD::SRL) { 2773 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2774 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2775 // We can turn this into an SRA iff the input to the SRL is already sign 2776 // extended enough. 2777 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 2778 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2779 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2780 } 2781 } 2782 2783 // fold (sext_inreg (extload x)) -> (sextload x) 2784 if (ISD::isEXTLoad(N0.Val) && 2785 ISD::isUNINDEXEDLoad(N0.Val) && 2786 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2787 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2788 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2789 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2790 LN0->getBasePtr(), LN0->getSrcValue(), 2791 LN0->getSrcValueOffset(), EVT, 2792 LN0->isVolatile(), 2793 LN0->getAlignment()); 2794 CombineTo(N, ExtLoad); 2795 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2796 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2797 } 2798 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2799 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2800 N0.hasOneUse() && 2801 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2802 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2803 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2804 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2805 LN0->getBasePtr(), LN0->getSrcValue(), 2806 LN0->getSrcValueOffset(), EVT, 2807 LN0->isVolatile(), 2808 LN0->getAlignment()); 2809 CombineTo(N, ExtLoad); 2810 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2811 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2812 } 2813 return SDOperand(); 2814} 2815 2816SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2817 SDOperand N0 = N->getOperand(0); 2818 MVT::ValueType VT = N->getValueType(0); 2819 2820 // noop truncate 2821 if (N0.getValueType() == N->getValueType(0)) 2822 return N0; 2823 // fold (truncate c1) -> c1 2824 if (isa<ConstantSDNode>(N0)) 2825 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2826 // fold (truncate (truncate x)) -> (truncate x) 2827 if (N0.getOpcode() == ISD::TRUNCATE) 2828 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2829 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2830 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2831 N0.getOpcode() == ISD::ANY_EXTEND) { 2832 if (N0.getOperand(0).getValueType() < VT) 2833 // if the source is smaller than the dest, we still need an extend 2834 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2835 else if (N0.getOperand(0).getValueType() > VT) 2836 // if the source is larger than the dest, than we just need the truncate 2837 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2838 else 2839 // if the source and dest are the same type, we can drop both the extend 2840 // and the truncate 2841 return N0.getOperand(0); 2842 } 2843 2844 // fold (truncate (load x)) -> (smaller load x) 2845 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 2846 return ReduceLoadWidth(N); 2847} 2848 2849SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2850 SDOperand N0 = N->getOperand(0); 2851 MVT::ValueType VT = N->getValueType(0); 2852 2853 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 2854 // Only do this before legalize, since afterward the target may be depending 2855 // on the bitconvert. 2856 // First check to see if this is all constant. 2857 if (!AfterLegalize && 2858 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 2859 MVT::isVector(VT)) { 2860 bool isSimple = true; 2861 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 2862 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2863 N0.getOperand(i).getOpcode() != ISD::Constant && 2864 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2865 isSimple = false; 2866 break; 2867 } 2868 2869 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 2870 assert(!MVT::isVector(DestEltVT) && 2871 "Element type of vector ValueType must not be vector!"); 2872 if (isSimple) { 2873 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 2874 } 2875 } 2876 2877 // If the input is a constant, let getNode() fold it. 2878 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2879 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2880 if (Res.Val != N) return Res; 2881 } 2882 2883 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2884 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2885 2886 // fold (conv (load x)) -> (load (conv*)x) 2887 // If the resultant load doesn't need a higher alignment than the original! 2888 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2889 ISD::isUNINDEXEDLoad(N0.Val) && 2890 TLI.isOperationLegal(ISD::LOAD, VT)) { 2891 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2892 unsigned Align = TLI.getTargetMachine().getTargetData()-> 2893 getABITypeAlignment(MVT::getTypeForValueType(VT)); 2894 unsigned OrigAlign = LN0->getAlignment(); 2895 if (Align <= OrigAlign) { 2896 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 2897 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2898 LN0->isVolatile(), Align); 2899 AddToWorkList(N); 2900 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2901 Load.getValue(1)); 2902 return Load; 2903 } 2904 } 2905 2906 return SDOperand(); 2907} 2908 2909/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 2910/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2911/// destination element value type. 2912SDOperand DAGCombiner:: 2913ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2914 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2915 2916 // If this is already the right type, we're done. 2917 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2918 2919 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2920 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2921 2922 // If this is a conversion of N elements of one type to N elements of another 2923 // type, convert each element. This handles FP<->INT cases. 2924 if (SrcBitSize == DstBitSize) { 2925 SmallVector<SDOperand, 8> Ops; 2926 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 2927 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2928 AddToWorkList(Ops.back().Val); 2929 } 2930 MVT::ValueType VT = 2931 MVT::getVectorType(DstEltVT, 2932 MVT::getVectorNumElements(BV->getValueType(0))); 2933 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2934 } 2935 2936 // Otherwise, we're growing or shrinking the elements. To avoid having to 2937 // handle annoying details of growing/shrinking FP values, we convert them to 2938 // int first. 2939 if (MVT::isFloatingPoint(SrcEltVT)) { 2940 // Convert the input float vector to a int vector where the elements are the 2941 // same sizes. 2942 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2943 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2944 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 2945 SrcEltVT = IntVT; 2946 } 2947 2948 // Now we know the input is an integer vector. If the output is a FP type, 2949 // convert to integer first, then to FP of the right size. 2950 if (MVT::isFloatingPoint(DstEltVT)) { 2951 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2952 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2953 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 2954 2955 // Next, convert to FP elements of the same size. 2956 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 2957 } 2958 2959 // Okay, we know the src/dst types are both integers of differing types. 2960 // Handling growing first. 2961 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2962 if (SrcBitSize < DstBitSize) { 2963 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2964 2965 SmallVector<SDOperand, 8> Ops; 2966 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 2967 i += NumInputsPerOutput) { 2968 bool isLE = TLI.isLittleEndian(); 2969 uint64_t NewBits = 0; 2970 bool EltIsUndef = true; 2971 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2972 // Shift the previously computed bits over. 2973 NewBits <<= SrcBitSize; 2974 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2975 if (Op.getOpcode() == ISD::UNDEF) continue; 2976 EltIsUndef = false; 2977 2978 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2979 } 2980 2981 if (EltIsUndef) 2982 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2983 else 2984 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2985 } 2986 2987 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 2988 Ops.size()); 2989 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2990 } 2991 2992 // Finally, this must be the case where we are shrinking elements: each input 2993 // turns into multiple outputs. 2994 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2995 SmallVector<SDOperand, 8> Ops; 2996 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 2997 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2998 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2999 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3000 continue; 3001 } 3002 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3003 3004 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3005 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3006 OpVal >>= DstBitSize; 3007 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3008 } 3009 3010 // For big endian targets, swap the order of the pieces of each element. 3011 if (!TLI.isLittleEndian()) 3012 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3013 } 3014 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3015 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3016} 3017 3018 3019 3020SDOperand DAGCombiner::visitFADD(SDNode *N) { 3021 SDOperand N0 = N->getOperand(0); 3022 SDOperand N1 = N->getOperand(1); 3023 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3024 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3025 MVT::ValueType VT = N->getValueType(0); 3026 3027 // fold vector ops 3028 if (MVT::isVector(VT)) { 3029 SDOperand FoldedVOp = SimplifyVBinOp(N); 3030 if (FoldedVOp.Val) return FoldedVOp; 3031 } 3032 3033 // fold (fadd c1, c2) -> c1+c2 3034 if (N0CFP && N1CFP) 3035 return DAG.getNode(ISD::FADD, VT, N0, N1); 3036 // canonicalize constant to RHS 3037 if (N0CFP && !N1CFP) 3038 return DAG.getNode(ISD::FADD, VT, N1, N0); 3039 // fold (A + (-B)) -> A-B 3040 if (isNegatibleForFree(N1) == 2) 3041 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3042 // fold ((-A) + B) -> B-A 3043 if (isNegatibleForFree(N0) == 2) 3044 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3045 3046 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3047 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3048 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3049 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3050 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3051 3052 return SDOperand(); 3053} 3054 3055SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3056 SDOperand N0 = N->getOperand(0); 3057 SDOperand N1 = N->getOperand(1); 3058 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3059 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3060 MVT::ValueType VT = N->getValueType(0); 3061 3062 // fold vector ops 3063 if (MVT::isVector(VT)) { 3064 SDOperand FoldedVOp = SimplifyVBinOp(N); 3065 if (FoldedVOp.Val) return FoldedVOp; 3066 } 3067 3068 // fold (fsub c1, c2) -> c1-c2 3069 if (N0CFP && N1CFP) 3070 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3071 // fold (0-B) -> -B 3072 if (UnsafeFPMath && N0CFP && N0CFP->getValue() == 0.0) { 3073 if (isNegatibleForFree(N1)) 3074 return GetNegatedExpression(N1, DAG); 3075 return DAG.getNode(ISD::FNEG, VT, N1); 3076 } 3077 // fold (A-(-B)) -> A+B 3078 if (isNegatibleForFree(N1)) 3079 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3080 3081 return SDOperand(); 3082} 3083 3084SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3085 SDOperand N0 = N->getOperand(0); 3086 SDOperand N1 = N->getOperand(1); 3087 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3088 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3089 MVT::ValueType VT = N->getValueType(0); 3090 3091 // fold vector ops 3092 if (MVT::isVector(VT)) { 3093 SDOperand FoldedVOp = SimplifyVBinOp(N); 3094 if (FoldedVOp.Val) return FoldedVOp; 3095 } 3096 3097 // fold (fmul c1, c2) -> c1*c2 3098 if (N0CFP && N1CFP) 3099 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3100 // canonicalize constant to RHS 3101 if (N0CFP && !N1CFP) 3102 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3103 // fold (fmul X, 2.0) -> (fadd X, X) 3104 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3105 return DAG.getNode(ISD::FADD, VT, N0, N0); 3106 // fold (fmul X, -1.0) -> (fneg X) 3107 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3108 return DAG.getNode(ISD::FNEG, VT, N0); 3109 3110 // -X * -Y -> X*Y 3111 if (char LHSNeg = isNegatibleForFree(N0)) { 3112 if (char RHSNeg = isNegatibleForFree(N1)) { 3113 // Both can be negated for free, check to see if at least one is cheaper 3114 // negated. 3115 if (LHSNeg == 2 || RHSNeg == 2) 3116 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3117 GetNegatedExpression(N1, DAG)); 3118 } 3119 } 3120 3121 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3122 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3123 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3124 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3125 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3126 3127 return SDOperand(); 3128} 3129 3130SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3131 SDOperand N0 = N->getOperand(0); 3132 SDOperand N1 = N->getOperand(1); 3133 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3134 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3135 MVT::ValueType VT = N->getValueType(0); 3136 3137 // fold vector ops 3138 if (MVT::isVector(VT)) { 3139 SDOperand FoldedVOp = SimplifyVBinOp(N); 3140 if (FoldedVOp.Val) return FoldedVOp; 3141 } 3142 3143 // fold (fdiv c1, c2) -> c1/c2 3144 if (N0CFP && N1CFP) 3145 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3146 3147 3148 // -X / -Y -> X*Y 3149 if (char LHSNeg = isNegatibleForFree(N0)) { 3150 if (char RHSNeg = isNegatibleForFree(N1)) { 3151 // Both can be negated for free, check to see if at least one is cheaper 3152 // negated. 3153 if (LHSNeg == 2 || RHSNeg == 2) 3154 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3155 GetNegatedExpression(N1, DAG)); 3156 } 3157 } 3158 3159 return SDOperand(); 3160} 3161 3162SDOperand DAGCombiner::visitFREM(SDNode *N) { 3163 SDOperand N0 = N->getOperand(0); 3164 SDOperand N1 = N->getOperand(1); 3165 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3166 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3167 MVT::ValueType VT = N->getValueType(0); 3168 3169 // fold (frem c1, c2) -> fmod(c1,c2) 3170 if (N0CFP && N1CFP) 3171 return DAG.getNode(ISD::FREM, VT, N0, N1); 3172 3173 return SDOperand(); 3174} 3175 3176SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3177 SDOperand N0 = N->getOperand(0); 3178 SDOperand N1 = N->getOperand(1); 3179 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3180 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3181 MVT::ValueType VT = N->getValueType(0); 3182 3183 if (N0CFP && N1CFP) // Constant fold 3184 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3185 3186 if (N1CFP) { 3187 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3188 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3189 union { 3190 double d; 3191 int64_t i; 3192 } u; 3193 u.d = N1CFP->getValue(); 3194 if (u.i >= 0) 3195 return DAG.getNode(ISD::FABS, VT, N0); 3196 else 3197 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3198 } 3199 3200 // copysign(fabs(x), y) -> copysign(x, y) 3201 // copysign(fneg(x), y) -> copysign(x, y) 3202 // copysign(copysign(x,z), y) -> copysign(x, y) 3203 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3204 N0.getOpcode() == ISD::FCOPYSIGN) 3205 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3206 3207 // copysign(x, abs(y)) -> abs(x) 3208 if (N1.getOpcode() == ISD::FABS) 3209 return DAG.getNode(ISD::FABS, VT, N0); 3210 3211 // copysign(x, copysign(y,z)) -> copysign(x, z) 3212 if (N1.getOpcode() == ISD::FCOPYSIGN) 3213 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3214 3215 // copysign(x, fp_extend(y)) -> copysign(x, y) 3216 // copysign(x, fp_round(y)) -> copysign(x, y) 3217 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3218 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3219 3220 return SDOperand(); 3221} 3222 3223 3224 3225SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3226 SDOperand N0 = N->getOperand(0); 3227 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3228 MVT::ValueType VT = N->getValueType(0); 3229 3230 // fold (sint_to_fp c1) -> c1fp 3231 if (N0C) 3232 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3233 return SDOperand(); 3234} 3235 3236SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3237 SDOperand N0 = N->getOperand(0); 3238 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3239 MVT::ValueType VT = N->getValueType(0); 3240 3241 // fold (uint_to_fp c1) -> c1fp 3242 if (N0C) 3243 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3244 return SDOperand(); 3245} 3246 3247SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3248 SDOperand N0 = N->getOperand(0); 3249 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3250 MVT::ValueType VT = N->getValueType(0); 3251 3252 // fold (fp_to_sint c1fp) -> c1 3253 if (N0CFP) 3254 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3255 return SDOperand(); 3256} 3257 3258SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3259 SDOperand N0 = N->getOperand(0); 3260 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3261 MVT::ValueType VT = N->getValueType(0); 3262 3263 // fold (fp_to_uint c1fp) -> c1 3264 if (N0CFP) 3265 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3266 return SDOperand(); 3267} 3268 3269SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3270 SDOperand N0 = N->getOperand(0); 3271 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3272 MVT::ValueType VT = N->getValueType(0); 3273 3274 // fold (fp_round c1fp) -> c1fp 3275 if (N0CFP) 3276 return DAG.getNode(ISD::FP_ROUND, VT, N0); 3277 3278 // fold (fp_round (fp_extend x)) -> x 3279 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3280 return N0.getOperand(0); 3281 3282 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3283 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3284 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 3285 AddToWorkList(Tmp.Val); 3286 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3287 } 3288 3289 return SDOperand(); 3290} 3291 3292SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3293 SDOperand N0 = N->getOperand(0); 3294 MVT::ValueType VT = N->getValueType(0); 3295 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3296 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3297 3298 // fold (fp_round_inreg c1fp) -> c1fp 3299 if (N0CFP) { 3300 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 3301 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3302 } 3303 return SDOperand(); 3304} 3305 3306SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3307 SDOperand N0 = N->getOperand(0); 3308 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3309 MVT::ValueType VT = N->getValueType(0); 3310 3311 // fold (fp_extend c1fp) -> c1fp 3312 if (N0CFP) 3313 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3314 3315 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 3316 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3317 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3318 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3319 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3320 LN0->getBasePtr(), LN0->getSrcValue(), 3321 LN0->getSrcValueOffset(), 3322 N0.getValueType(), 3323 LN0->isVolatile(), 3324 LN0->getAlignment()); 3325 CombineTo(N, ExtLoad); 3326 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 3327 ExtLoad.getValue(1)); 3328 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3329 } 3330 3331 3332 return SDOperand(); 3333} 3334 3335SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3336 SDOperand N0 = N->getOperand(0); 3337 3338 if (isNegatibleForFree(N0)) 3339 return GetNegatedExpression(N0, DAG); 3340 3341 return SDOperand(); 3342} 3343 3344SDOperand DAGCombiner::visitFABS(SDNode *N) { 3345 SDOperand N0 = N->getOperand(0); 3346 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3347 MVT::ValueType VT = N->getValueType(0); 3348 3349 // fold (fabs c1) -> fabs(c1) 3350 if (N0CFP) 3351 return DAG.getNode(ISD::FABS, VT, N0); 3352 // fold (fabs (fabs x)) -> (fabs x) 3353 if (N0.getOpcode() == ISD::FABS) 3354 return N->getOperand(0); 3355 // fold (fabs (fneg x)) -> (fabs x) 3356 // fold (fabs (fcopysign x, y)) -> (fabs x) 3357 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3358 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3359 3360 return SDOperand(); 3361} 3362 3363SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3364 SDOperand Chain = N->getOperand(0); 3365 SDOperand N1 = N->getOperand(1); 3366 SDOperand N2 = N->getOperand(2); 3367 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3368 3369 // never taken branch, fold to chain 3370 if (N1C && N1C->isNullValue()) 3371 return Chain; 3372 // unconditional branch 3373 if (N1C && N1C->getValue() == 1) 3374 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3375 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3376 // on the target. 3377 if (N1.getOpcode() == ISD::SETCC && 3378 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3379 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3380 N1.getOperand(0), N1.getOperand(1), N2); 3381 } 3382 return SDOperand(); 3383} 3384 3385// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3386// 3387SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3388 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3389 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3390 3391 // Use SimplifySetCC to simplify SETCC's. 3392 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3393 if (Simp.Val) AddToWorkList(Simp.Val); 3394 3395 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3396 3397 // fold br_cc true, dest -> br dest (unconditional branch) 3398 if (SCCC && SCCC->getValue()) 3399 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3400 N->getOperand(4)); 3401 // fold br_cc false, dest -> unconditional fall through 3402 if (SCCC && SCCC->isNullValue()) 3403 return N->getOperand(0); 3404 3405 // fold to a simpler setcc 3406 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3407 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3408 Simp.getOperand(2), Simp.getOperand(0), 3409 Simp.getOperand(1), N->getOperand(4)); 3410 return SDOperand(); 3411} 3412 3413 3414/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3415/// pre-indexed load / store when the base pointer is a add or subtract 3416/// and it has other uses besides the load / store. After the 3417/// transformation, the new indexed load / store has effectively folded 3418/// the add / subtract in and all of its other uses are redirected to the 3419/// new load / store. 3420bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3421 if (!AfterLegalize) 3422 return false; 3423 3424 bool isLoad = true; 3425 SDOperand Ptr; 3426 MVT::ValueType VT; 3427 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3428 if (LD->getAddressingMode() != ISD::UNINDEXED) 3429 return false; 3430 VT = LD->getLoadedVT(); 3431 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3432 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3433 return false; 3434 Ptr = LD->getBasePtr(); 3435 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3436 if (ST->getAddressingMode() != ISD::UNINDEXED) 3437 return false; 3438 VT = ST->getStoredVT(); 3439 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3440 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3441 return false; 3442 Ptr = ST->getBasePtr(); 3443 isLoad = false; 3444 } else 3445 return false; 3446 3447 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3448 // out. There is no reason to make this a preinc/predec. 3449 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3450 Ptr.Val->hasOneUse()) 3451 return false; 3452 3453 // Ask the target to do addressing mode selection. 3454 SDOperand BasePtr; 3455 SDOperand Offset; 3456 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3457 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3458 return false; 3459 // Don't create a indexed load / store with zero offset. 3460 if (isa<ConstantSDNode>(Offset) && 3461 cast<ConstantSDNode>(Offset)->getValue() == 0) 3462 return false; 3463 3464 // Try turning it into a pre-indexed load / store except when: 3465 // 1) The new base ptr is a frame index. 3466 // 2) If N is a store and the new base ptr is either the same as or is a 3467 // predecessor of the value being stored. 3468 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3469 // that would create a cycle. 3470 // 4) All uses are load / store ops that use it as old base ptr. 3471 3472 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3473 // (plus the implicit offset) to a register to preinc anyway. 3474 if (isa<FrameIndexSDNode>(BasePtr)) 3475 return false; 3476 3477 // Check #2. 3478 if (!isLoad) { 3479 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3480 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3481 return false; 3482 } 3483 3484 // Now check for #3 and #4. 3485 bool RealUse = false; 3486 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3487 E = Ptr.Val->use_end(); I != E; ++I) { 3488 SDNode *Use = *I; 3489 if (Use == N) 3490 continue; 3491 if (Use->isPredecessor(N)) 3492 return false; 3493 3494 if (!((Use->getOpcode() == ISD::LOAD && 3495 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3496 (Use->getOpcode() == ISD::STORE) && 3497 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3498 RealUse = true; 3499 } 3500 if (!RealUse) 3501 return false; 3502 3503 SDOperand Result; 3504 if (isLoad) 3505 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3506 else 3507 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3508 ++PreIndexedNodes; 3509 ++NodesCombined; 3510 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 3511 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3512 DOUT << '\n'; 3513 std::vector<SDNode*> NowDead; 3514 if (isLoad) { 3515 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3516 NowDead); 3517 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3518 NowDead); 3519 } else { 3520 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3521 NowDead); 3522 } 3523 3524 // Nodes can end up on the worklist more than once. Make sure we do 3525 // not process a node that has been replaced. 3526 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3527 removeFromWorkList(NowDead[i]); 3528 // Finally, since the node is now dead, remove it from the graph. 3529 DAG.DeleteNode(N); 3530 3531 // Replace the uses of Ptr with uses of the updated base value. 3532 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3533 NowDead); 3534 removeFromWorkList(Ptr.Val); 3535 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3536 removeFromWorkList(NowDead[i]); 3537 DAG.DeleteNode(Ptr.Val); 3538 3539 return true; 3540} 3541 3542/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3543/// add / sub of the base pointer node into a post-indexed load / store. 3544/// The transformation folded the add / subtract into the new indexed 3545/// load / store effectively and all of its uses are redirected to the 3546/// new load / store. 3547bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3548 if (!AfterLegalize) 3549 return false; 3550 3551 bool isLoad = true; 3552 SDOperand Ptr; 3553 MVT::ValueType VT; 3554 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3555 if (LD->getAddressingMode() != ISD::UNINDEXED) 3556 return false; 3557 VT = LD->getLoadedVT(); 3558 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3559 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3560 return false; 3561 Ptr = LD->getBasePtr(); 3562 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3563 if (ST->getAddressingMode() != ISD::UNINDEXED) 3564 return false; 3565 VT = ST->getStoredVT(); 3566 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3567 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3568 return false; 3569 Ptr = ST->getBasePtr(); 3570 isLoad = false; 3571 } else 3572 return false; 3573 3574 if (Ptr.Val->hasOneUse()) 3575 return false; 3576 3577 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3578 E = Ptr.Val->use_end(); I != E; ++I) { 3579 SDNode *Op = *I; 3580 if (Op == N || 3581 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3582 continue; 3583 3584 SDOperand BasePtr; 3585 SDOperand Offset; 3586 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3587 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3588 if (Ptr == Offset) 3589 std::swap(BasePtr, Offset); 3590 if (Ptr != BasePtr) 3591 continue; 3592 // Don't create a indexed load / store with zero offset. 3593 if (isa<ConstantSDNode>(Offset) && 3594 cast<ConstantSDNode>(Offset)->getValue() == 0) 3595 continue; 3596 3597 // Try turning it into a post-indexed load / store except when 3598 // 1) All uses are load / store ops that use it as base ptr. 3599 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3600 // nor a successor of N. Otherwise, if Op is folded that would 3601 // create a cycle. 3602 3603 // Check for #1. 3604 bool TryNext = false; 3605 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3606 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3607 SDNode *Use = *II; 3608 if (Use == Ptr.Val) 3609 continue; 3610 3611 // If all the uses are load / store addresses, then don't do the 3612 // transformation. 3613 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3614 bool RealUse = false; 3615 for (SDNode::use_iterator III = Use->use_begin(), 3616 EEE = Use->use_end(); III != EEE; ++III) { 3617 SDNode *UseUse = *III; 3618 if (!((UseUse->getOpcode() == ISD::LOAD && 3619 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3620 (UseUse->getOpcode() == ISD::STORE) && 3621 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3622 RealUse = true; 3623 } 3624 3625 if (!RealUse) { 3626 TryNext = true; 3627 break; 3628 } 3629 } 3630 } 3631 if (TryNext) 3632 continue; 3633 3634 // Check for #2 3635 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3636 SDOperand Result = isLoad 3637 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3638 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3639 ++PostIndexedNodes; 3640 ++NodesCombined; 3641 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 3642 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3643 DOUT << '\n'; 3644 std::vector<SDNode*> NowDead; 3645 if (isLoad) { 3646 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3647 NowDead); 3648 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3649 NowDead); 3650 } else { 3651 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3652 NowDead); 3653 } 3654 3655 // Nodes can end up on the worklist more than once. Make sure we do 3656 // not process a node that has been replaced. 3657 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3658 removeFromWorkList(NowDead[i]); 3659 // Finally, since the node is now dead, remove it from the graph. 3660 DAG.DeleteNode(N); 3661 3662 // Replace the uses of Use with uses of the updated base value. 3663 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3664 Result.getValue(isLoad ? 1 : 0), 3665 NowDead); 3666 removeFromWorkList(Op); 3667 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3668 removeFromWorkList(NowDead[i]); 3669 DAG.DeleteNode(Op); 3670 3671 return true; 3672 } 3673 } 3674 } 3675 return false; 3676} 3677 3678 3679SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3680 LoadSDNode *LD = cast<LoadSDNode>(N); 3681 SDOperand Chain = LD->getChain(); 3682 SDOperand Ptr = LD->getBasePtr(); 3683 3684 // If load is not volatile and there are no uses of the loaded value (and 3685 // the updated indexed value in case of indexed loads), change uses of the 3686 // chain value into uses of the chain input (i.e. delete the dead load). 3687 if (!LD->isVolatile()) { 3688 if (N->getValueType(1) == MVT::Other) { 3689 // Unindexed loads. 3690 if (N->hasNUsesOfValue(0, 0)) 3691 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3692 } else { 3693 // Indexed loads. 3694 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 3695 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 3696 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3697 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1)); 3698 SDOperand To[] = { Undef0, Undef1, Chain }; 3699 return CombineTo(N, To, 3); 3700 } 3701 } 3702 } 3703 3704 // If this load is directly stored, replace the load value with the stored 3705 // value. 3706 // TODO: Handle store large -> read small portion. 3707 // TODO: Handle TRUNCSTORE/LOADEXT 3708 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3709 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3710 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3711 if (PrevST->getBasePtr() == Ptr && 3712 PrevST->getValue().getValueType() == N->getValueType(0)) 3713 return CombineTo(N, Chain.getOperand(1), Chain); 3714 } 3715 } 3716 3717 if (CombinerAA) { 3718 // Walk up chain skipping non-aliasing memory nodes. 3719 SDOperand BetterChain = FindBetterChain(N, Chain); 3720 3721 // If there is a better chain. 3722 if (Chain != BetterChain) { 3723 SDOperand ReplLoad; 3724 3725 // Replace the chain to void dependency. 3726 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3727 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3728 LD->getSrcValue(), LD->getSrcValueOffset(), 3729 LD->isVolatile(), LD->getAlignment()); 3730 } else { 3731 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3732 LD->getValueType(0), 3733 BetterChain, Ptr, LD->getSrcValue(), 3734 LD->getSrcValueOffset(), 3735 LD->getLoadedVT(), 3736 LD->isVolatile(), 3737 LD->getAlignment()); 3738 } 3739 3740 // Create token factor to keep old chain connected. 3741 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3742 Chain, ReplLoad.getValue(1)); 3743 3744 // Replace uses with load result and token factor. Don't add users 3745 // to work list. 3746 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3747 } 3748 } 3749 3750 // Try transforming N to an indexed load. 3751 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3752 return SDOperand(N, 0); 3753 3754 return SDOperand(); 3755} 3756 3757SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3758 StoreSDNode *ST = cast<StoreSDNode>(N); 3759 SDOperand Chain = ST->getChain(); 3760 SDOperand Value = ST->getValue(); 3761 SDOperand Ptr = ST->getBasePtr(); 3762 3763 // If this is a store of a bit convert, store the input value if the 3764 // resultant store does not need a higher alignment than the original. 3765 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 3766 ST->getAddressingMode() == ISD::UNINDEXED) { 3767 unsigned Align = ST->getAlignment(); 3768 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 3769 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 3770 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 3771 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 3772 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3773 ST->getSrcValueOffset(), ST->isVolatile(), Align); 3774 } 3775 3776 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3777 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3778 if (Value.getOpcode() != ISD::TargetConstantFP) { 3779 SDOperand Tmp; 3780 switch (CFP->getValueType(0)) { 3781 default: assert(0 && "Unknown FP type"); 3782 case MVT::f32: 3783 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3784 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 3785 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3786 ST->getSrcValueOffset(), ST->isVolatile(), 3787 ST->getAlignment()); 3788 } 3789 break; 3790 case MVT::f64: 3791 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3792 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 3793 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3794 ST->getSrcValueOffset(), ST->isVolatile(), 3795 ST->getAlignment()); 3796 } else if (TLI.isTypeLegal(MVT::i32)) { 3797 // Many FP stores are not make apparent until after legalize, e.g. for 3798 // argument passing. Since this is so common, custom legalize the 3799 // 64-bit integer store into two 32-bit stores. 3800 uint64_t Val = DoubleToBits(CFP->getValue()); 3801 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3802 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3803 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3804 3805 int SVOffset = ST->getSrcValueOffset(); 3806 unsigned Alignment = ST->getAlignment(); 3807 bool isVolatile = ST->isVolatile(); 3808 3809 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3810 ST->getSrcValueOffset(), 3811 isVolatile, ST->getAlignment()); 3812 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3813 DAG.getConstant(4, Ptr.getValueType())); 3814 SVOffset += 4; 3815 if (Alignment > 4) 3816 Alignment = 4; 3817 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 3818 SVOffset, isVolatile, Alignment); 3819 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 3820 } 3821 break; 3822 } 3823 } 3824 } 3825 3826 if (CombinerAA) { 3827 // Walk up chain skipping non-aliasing memory nodes. 3828 SDOperand BetterChain = FindBetterChain(N, Chain); 3829 3830 // If there is a better chain. 3831 if (Chain != BetterChain) { 3832 // Replace the chain to avoid dependency. 3833 SDOperand ReplStore; 3834 if (ST->isTruncatingStore()) { 3835 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 3836 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(), 3837 ST->isVolatile(), ST->getAlignment()); 3838 } else { 3839 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 3840 ST->getSrcValue(), ST->getSrcValueOffset(), 3841 ST->isVolatile(), ST->getAlignment()); 3842 } 3843 3844 // Create token to keep both nodes around. 3845 SDOperand Token = 3846 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 3847 3848 // Don't add users to work list. 3849 return CombineTo(N, Token, false); 3850 } 3851 } 3852 3853 // Try transforming N to an indexed store. 3854 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3855 return SDOperand(N, 0); 3856 3857 return SDOperand(); 3858} 3859 3860SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 3861 SDOperand InVec = N->getOperand(0); 3862 SDOperand InVal = N->getOperand(1); 3863 SDOperand EltNo = N->getOperand(2); 3864 3865 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 3866 // vector with the inserted element. 3867 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3868 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3869 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3870 if (Elt < Ops.size()) 3871 Ops[Elt] = InVal; 3872 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 3873 &Ops[0], Ops.size()); 3874 } 3875 3876 return SDOperand(); 3877} 3878 3879SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 3880 unsigned NumInScalars = N->getNumOperands(); 3881 MVT::ValueType VT = N->getValueType(0); 3882 unsigned NumElts = MVT::getVectorNumElements(VT); 3883 MVT::ValueType EltType = MVT::getVectorElementType(VT); 3884 3885 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 3886 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 3887 // at most two distinct vectors, turn this into a shuffle node. 3888 SDOperand VecIn1, VecIn2; 3889 for (unsigned i = 0; i != NumInScalars; ++i) { 3890 // Ignore undef inputs. 3891 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3892 3893 // If this input is something other than a EXTRACT_VECTOR_ELT with a 3894 // constant index, bail out. 3895 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 3896 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 3897 VecIn1 = VecIn2 = SDOperand(0, 0); 3898 break; 3899 } 3900 3901 // If the input vector type disagrees with the result of the build_vector, 3902 // we can't make a shuffle. 3903 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 3904 if (ExtractedFromVec.getValueType() != VT) { 3905 VecIn1 = VecIn2 = SDOperand(0, 0); 3906 break; 3907 } 3908 3909 // Otherwise, remember this. We allow up to two distinct input vectors. 3910 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 3911 continue; 3912 3913 if (VecIn1.Val == 0) { 3914 VecIn1 = ExtractedFromVec; 3915 } else if (VecIn2.Val == 0) { 3916 VecIn2 = ExtractedFromVec; 3917 } else { 3918 // Too many inputs. 3919 VecIn1 = VecIn2 = SDOperand(0, 0); 3920 break; 3921 } 3922 } 3923 3924 // If everything is good, we can make a shuffle operation. 3925 if (VecIn1.Val) { 3926 SmallVector<SDOperand, 8> BuildVecIndices; 3927 for (unsigned i = 0; i != NumInScalars; ++i) { 3928 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 3929 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 3930 continue; 3931 } 3932 3933 SDOperand Extract = N->getOperand(i); 3934 3935 // If extracting from the first vector, just use the index directly. 3936 if (Extract.getOperand(0) == VecIn1) { 3937 BuildVecIndices.push_back(Extract.getOperand(1)); 3938 continue; 3939 } 3940 3941 // Otherwise, use InIdx + VecSize 3942 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 3943 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 3944 TLI.getPointerTy())); 3945 } 3946 3947 // Add count and size info. 3948 MVT::ValueType BuildVecVT = 3949 MVT::getVectorType(TLI.getPointerTy(), NumElts); 3950 3951 // Return the new VECTOR_SHUFFLE node. 3952 SDOperand Ops[5]; 3953 Ops[0] = VecIn1; 3954 if (VecIn2.Val) { 3955 Ops[1] = VecIn2; 3956 } else { 3957 // Use an undef build_vector as input for the second operand. 3958 std::vector<SDOperand> UnOps(NumInScalars, 3959 DAG.getNode(ISD::UNDEF, 3960 EltType)); 3961 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 3962 &UnOps[0], UnOps.size()); 3963 AddToWorkList(Ops[1].Val); 3964 } 3965 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 3966 &BuildVecIndices[0], BuildVecIndices.size()); 3967 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 3968 } 3969 3970 return SDOperand(); 3971} 3972 3973SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 3974 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 3975 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 3976 // inputs come from at most two distinct vectors, turn this into a shuffle 3977 // node. 3978 3979 // If we only have one input vector, we don't need to do any concatenation. 3980 if (N->getNumOperands() == 1) { 3981 return N->getOperand(0); 3982 } 3983 3984 return SDOperand(); 3985} 3986 3987SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 3988 SDOperand ShufMask = N->getOperand(2); 3989 unsigned NumElts = ShufMask.getNumOperands(); 3990 3991 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3992 bool isIdentity = true; 3993 for (unsigned i = 0; i != NumElts; ++i) { 3994 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3995 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3996 isIdentity = false; 3997 break; 3998 } 3999 } 4000 if (isIdentity) return N->getOperand(0); 4001 4002 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4003 isIdentity = true; 4004 for (unsigned i = 0; i != NumElts; ++i) { 4005 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4006 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4007 isIdentity = false; 4008 break; 4009 } 4010 } 4011 if (isIdentity) return N->getOperand(1); 4012 4013 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4014 // needed at all. 4015 bool isUnary = true; 4016 bool isSplat = true; 4017 int VecNum = -1; 4018 unsigned BaseIdx = 0; 4019 for (unsigned i = 0; i != NumElts; ++i) 4020 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4021 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4022 int V = (Idx < NumElts) ? 0 : 1; 4023 if (VecNum == -1) { 4024 VecNum = V; 4025 BaseIdx = Idx; 4026 } else { 4027 if (BaseIdx != Idx) 4028 isSplat = false; 4029 if (VecNum != V) { 4030 isUnary = false; 4031 break; 4032 } 4033 } 4034 } 4035 4036 SDOperand N0 = N->getOperand(0); 4037 SDOperand N1 = N->getOperand(1); 4038 // Normalize unary shuffle so the RHS is undef. 4039 if (isUnary && VecNum == 1) 4040 std::swap(N0, N1); 4041 4042 // If it is a splat, check if the argument vector is a build_vector with 4043 // all scalar elements the same. 4044 if (isSplat) { 4045 SDNode *V = N0.Val; 4046 4047 // If this is a bit convert that changes the element type of the vector but 4048 // not the number of vector elements, look through it. Be careful not to 4049 // look though conversions that change things like v4f32 to v2f64. 4050 if (V->getOpcode() == ISD::BIT_CONVERT) { 4051 SDOperand ConvInput = V->getOperand(0); 4052 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4053 V = ConvInput.Val; 4054 } 4055 4056 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4057 unsigned NumElems = V->getNumOperands(); 4058 if (NumElems > BaseIdx) { 4059 SDOperand Base; 4060 bool AllSame = true; 4061 for (unsigned i = 0; i != NumElems; ++i) { 4062 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4063 Base = V->getOperand(i); 4064 break; 4065 } 4066 } 4067 // Splat of <u, u, u, u>, return <u, u, u, u> 4068 if (!Base.Val) 4069 return N0; 4070 for (unsigned i = 0; i != NumElems; ++i) { 4071 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 4072 V->getOperand(i) != Base) { 4073 AllSame = false; 4074 break; 4075 } 4076 } 4077 // Splat of <x, x, x, x>, return <x, x, x, x> 4078 if (AllSame) 4079 return N0; 4080 } 4081 } 4082 } 4083 4084 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4085 // into an undef. 4086 if (isUnary || N0 == N1) { 4087 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4088 // first operand. 4089 SmallVector<SDOperand, 8> MappedOps; 4090 for (unsigned i = 0; i != NumElts; ++i) { 4091 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4092 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4093 MappedOps.push_back(ShufMask.getOperand(i)); 4094 } else { 4095 unsigned NewIdx = 4096 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4097 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4098 } 4099 } 4100 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4101 &MappedOps[0], MappedOps.size()); 4102 AddToWorkList(ShufMask.Val); 4103 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4104 N0, 4105 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4106 ShufMask); 4107 } 4108 4109 return SDOperand(); 4110} 4111 4112/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4113/// an AND to a vector_shuffle with the destination vector and a zero vector. 4114/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4115/// vector_shuffle V, Zero, <0, 4, 2, 4> 4116SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4117 SDOperand LHS = N->getOperand(0); 4118 SDOperand RHS = N->getOperand(1); 4119 if (N->getOpcode() == ISD::AND) { 4120 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4121 RHS = RHS.getOperand(0); 4122 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4123 std::vector<SDOperand> IdxOps; 4124 unsigned NumOps = RHS.getNumOperands(); 4125 unsigned NumElts = NumOps; 4126 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4127 for (unsigned i = 0; i != NumElts; ++i) { 4128 SDOperand Elt = RHS.getOperand(i); 4129 if (!isa<ConstantSDNode>(Elt)) 4130 return SDOperand(); 4131 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4132 IdxOps.push_back(DAG.getConstant(i, EVT)); 4133 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4134 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4135 else 4136 return SDOperand(); 4137 } 4138 4139 // Let's see if the target supports this vector_shuffle. 4140 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4141 return SDOperand(); 4142 4143 // Return the new VECTOR_SHUFFLE node. 4144 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4145 std::vector<SDOperand> Ops; 4146 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4147 Ops.push_back(LHS); 4148 AddToWorkList(LHS.Val); 4149 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4150 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4151 &ZeroOps[0], ZeroOps.size())); 4152 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4153 &IdxOps[0], IdxOps.size())); 4154 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4155 &Ops[0], Ops.size()); 4156 if (VT != LHS.getValueType()) { 4157 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4158 } 4159 return Result; 4160 } 4161 } 4162 return SDOperand(); 4163} 4164 4165/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4166SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4167 // After legalize, the target may be depending on adds and other 4168 // binary ops to provide legal ways to construct constants or other 4169 // things. Simplifying them may result in a loss of legality. 4170 if (AfterLegalize) return SDOperand(); 4171 4172 MVT::ValueType VT = N->getValueType(0); 4173 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4174 4175 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4176 SDOperand LHS = N->getOperand(0); 4177 SDOperand RHS = N->getOperand(1); 4178 SDOperand Shuffle = XformToShuffleWithZero(N); 4179 if (Shuffle.Val) return Shuffle; 4180 4181 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4182 // this operation. 4183 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4184 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4185 SmallVector<SDOperand, 8> Ops; 4186 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4187 SDOperand LHSOp = LHS.getOperand(i); 4188 SDOperand RHSOp = RHS.getOperand(i); 4189 // If these two elements can't be folded, bail out. 4190 if ((LHSOp.getOpcode() != ISD::UNDEF && 4191 LHSOp.getOpcode() != ISD::Constant && 4192 LHSOp.getOpcode() != ISD::ConstantFP) || 4193 (RHSOp.getOpcode() != ISD::UNDEF && 4194 RHSOp.getOpcode() != ISD::Constant && 4195 RHSOp.getOpcode() != ISD::ConstantFP)) 4196 break; 4197 // Can't fold divide by zero. 4198 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4199 N->getOpcode() == ISD::FDIV) { 4200 if ((RHSOp.getOpcode() == ISD::Constant && 4201 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4202 (RHSOp.getOpcode() == ISD::ConstantFP && 4203 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 4204 break; 4205 } 4206 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4207 AddToWorkList(Ops.back().Val); 4208 assert((Ops.back().getOpcode() == ISD::UNDEF || 4209 Ops.back().getOpcode() == ISD::Constant || 4210 Ops.back().getOpcode() == ISD::ConstantFP) && 4211 "Scalar binop didn't fold!"); 4212 } 4213 4214 if (Ops.size() == LHS.getNumOperands()) { 4215 MVT::ValueType VT = LHS.getValueType(); 4216 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4217 } 4218 } 4219 4220 return SDOperand(); 4221} 4222 4223SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4224 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4225 4226 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4227 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4228 // If we got a simplified select_cc node back from SimplifySelectCC, then 4229 // break it down into a new SETCC node, and a new SELECT node, and then return 4230 // the SELECT node, since we were called with a SELECT node. 4231 if (SCC.Val) { 4232 // Check to see if we got a select_cc back (to turn into setcc/select). 4233 // Otherwise, just return whatever node we got back, like fabs. 4234 if (SCC.getOpcode() == ISD::SELECT_CC) { 4235 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4236 SCC.getOperand(0), SCC.getOperand(1), 4237 SCC.getOperand(4)); 4238 AddToWorkList(SETCC.Val); 4239 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4240 SCC.getOperand(3), SETCC); 4241 } 4242 return SCC; 4243 } 4244 return SDOperand(); 4245} 4246 4247/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4248/// are the two values being selected between, see if we can simplify the 4249/// select. Callers of this should assume that TheSelect is deleted if this 4250/// returns true. As such, they should return the appropriate thing (e.g. the 4251/// node) back to the top-level of the DAG combiner loop to avoid it being 4252/// looked at. 4253/// 4254bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4255 SDOperand RHS) { 4256 4257 // If this is a select from two identical things, try to pull the operation 4258 // through the select. 4259 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4260 // If this is a load and the token chain is identical, replace the select 4261 // of two loads with a load through a select of the address to load from. 4262 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4263 // constants have been dropped into the constant pool. 4264 if (LHS.getOpcode() == ISD::LOAD && 4265 // Token chains must be identical. 4266 LHS.getOperand(0) == RHS.getOperand(0)) { 4267 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4268 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4269 4270 // If this is an EXTLOAD, the VT's must match. 4271 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4272 // FIXME: this conflates two src values, discarding one. This is not 4273 // the right thing to do, but nothing uses srcvalues now. When they do, 4274 // turn SrcValue into a list of locations. 4275 SDOperand Addr; 4276 if (TheSelect->getOpcode() == ISD::SELECT) { 4277 // Check that the condition doesn't reach either load. If so, folding 4278 // this will induce a cycle into the DAG. 4279 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4280 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4281 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4282 TheSelect->getOperand(0), LLD->getBasePtr(), 4283 RLD->getBasePtr()); 4284 } 4285 } else { 4286 // Check that the condition doesn't reach either load. If so, folding 4287 // this will induce a cycle into the DAG. 4288 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4289 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4290 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4291 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4292 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4293 TheSelect->getOperand(0), 4294 TheSelect->getOperand(1), 4295 LLD->getBasePtr(), RLD->getBasePtr(), 4296 TheSelect->getOperand(4)); 4297 } 4298 } 4299 4300 if (Addr.Val) { 4301 SDOperand Load; 4302 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4303 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4304 Addr,LLD->getSrcValue(), 4305 LLD->getSrcValueOffset(), 4306 LLD->isVolatile(), 4307 LLD->getAlignment()); 4308 else { 4309 Load = DAG.getExtLoad(LLD->getExtensionType(), 4310 TheSelect->getValueType(0), 4311 LLD->getChain(), Addr, LLD->getSrcValue(), 4312 LLD->getSrcValueOffset(), 4313 LLD->getLoadedVT(), 4314 LLD->isVolatile(), 4315 LLD->getAlignment()); 4316 } 4317 // Users of the select now use the result of the load. 4318 CombineTo(TheSelect, Load); 4319 4320 // Users of the old loads now use the new load's chain. We know the 4321 // old-load value is dead now. 4322 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4323 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4324 return true; 4325 } 4326 } 4327 } 4328 } 4329 4330 return false; 4331} 4332 4333SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4334 SDOperand N2, SDOperand N3, 4335 ISD::CondCode CC, bool NotExtCompare) { 4336 4337 MVT::ValueType VT = N2.getValueType(); 4338 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4339 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4340 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4341 4342 // Determine if the condition we're dealing with is constant 4343 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4344 if (SCC.Val) AddToWorkList(SCC.Val); 4345 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4346 4347 // fold select_cc true, x, y -> x 4348 if (SCCC && SCCC->getValue()) 4349 return N2; 4350 // fold select_cc false, x, y -> y 4351 if (SCCC && SCCC->getValue() == 0) 4352 return N3; 4353 4354 // Check to see if we can simplify the select into an fabs node 4355 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4356 // Allow either -0.0 or 0.0 4357 if (CFP->getValue() == 0.0) { 4358 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4359 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4360 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4361 N2 == N3.getOperand(0)) 4362 return DAG.getNode(ISD::FABS, VT, N0); 4363 4364 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4365 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4366 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4367 N2.getOperand(0) == N3) 4368 return DAG.getNode(ISD::FABS, VT, N3); 4369 } 4370 } 4371 4372 // Check to see if we can perform the "gzip trick", transforming 4373 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4374 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4375 MVT::isInteger(N0.getValueType()) && 4376 MVT::isInteger(N2.getValueType()) && 4377 (N1C->isNullValue() || // (a < 0) ? b : 0 4378 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4379 MVT::ValueType XType = N0.getValueType(); 4380 MVT::ValueType AType = N2.getValueType(); 4381 if (XType >= AType) { 4382 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4383 // single-bit constant. 4384 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4385 unsigned ShCtV = Log2_64(N2C->getValue()); 4386 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4387 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4388 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4389 AddToWorkList(Shift.Val); 4390 if (XType > AType) { 4391 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4392 AddToWorkList(Shift.Val); 4393 } 4394 return DAG.getNode(ISD::AND, AType, Shift, N2); 4395 } 4396 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4397 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4398 TLI.getShiftAmountTy())); 4399 AddToWorkList(Shift.Val); 4400 if (XType > AType) { 4401 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4402 AddToWorkList(Shift.Val); 4403 } 4404 return DAG.getNode(ISD::AND, AType, Shift, N2); 4405 } 4406 } 4407 4408 // fold select C, 16, 0 -> shl C, 4 4409 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4410 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4411 4412 // If the caller doesn't want us to simplify this into a zext of a compare, 4413 // don't do it. 4414 if (NotExtCompare && N2C->getValue() == 1) 4415 return SDOperand(); 4416 4417 // Get a SetCC of the condition 4418 // FIXME: Should probably make sure that setcc is legal if we ever have a 4419 // target where it isn't. 4420 SDOperand Temp, SCC; 4421 // cast from setcc result type to select result type 4422 if (AfterLegalize) { 4423 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4424 if (N2.getValueType() < SCC.getValueType()) 4425 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4426 else 4427 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4428 } else { 4429 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4430 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4431 } 4432 AddToWorkList(SCC.Val); 4433 AddToWorkList(Temp.Val); 4434 4435 if (N2C->getValue() == 1) 4436 return Temp; 4437 // shl setcc result by log2 n2c 4438 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4439 DAG.getConstant(Log2_64(N2C->getValue()), 4440 TLI.getShiftAmountTy())); 4441 } 4442 4443 // Check to see if this is the equivalent of setcc 4444 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4445 // otherwise, go ahead with the folds. 4446 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4447 MVT::ValueType XType = N0.getValueType(); 4448 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4449 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4450 if (Res.getValueType() != VT) 4451 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4452 return Res; 4453 } 4454 4455 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4456 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4457 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4458 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4459 return DAG.getNode(ISD::SRL, XType, Ctlz, 4460 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4461 TLI.getShiftAmountTy())); 4462 } 4463 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4464 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4465 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4466 N0); 4467 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4468 DAG.getConstant(~0ULL, XType)); 4469 return DAG.getNode(ISD::SRL, XType, 4470 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4471 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4472 TLI.getShiftAmountTy())); 4473 } 4474 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4475 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4476 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4477 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4478 TLI.getShiftAmountTy())); 4479 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4480 } 4481 } 4482 4483 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4484 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4485 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4486 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4487 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4488 MVT::ValueType XType = N0.getValueType(); 4489 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4490 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4491 TLI.getShiftAmountTy())); 4492 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4493 AddToWorkList(Shift.Val); 4494 AddToWorkList(Add.Val); 4495 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4496 } 4497 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4498 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4499 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4500 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4501 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4502 MVT::ValueType XType = N0.getValueType(); 4503 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4504 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4505 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4506 TLI.getShiftAmountTy())); 4507 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4508 AddToWorkList(Shift.Val); 4509 AddToWorkList(Add.Val); 4510 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4511 } 4512 } 4513 } 4514 4515 return SDOperand(); 4516} 4517 4518/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4519SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4520 SDOperand N1, ISD::CondCode Cond, 4521 bool foldBooleans) { 4522 TargetLowering::DAGCombinerInfo 4523 DagCombineInfo(DAG, !AfterLegalize, false, this); 4524 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4525} 4526 4527/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4528/// return a DAG expression to select that will generate the same value by 4529/// multiplying by a magic number. See: 4530/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4531SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4532 std::vector<SDNode*> Built; 4533 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4534 4535 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4536 ii != ee; ++ii) 4537 AddToWorkList(*ii); 4538 return S; 4539} 4540 4541/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4542/// return a DAG expression to select that will generate the same value by 4543/// multiplying by a magic number. See: 4544/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4545SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4546 std::vector<SDNode*> Built; 4547 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4548 4549 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4550 ii != ee; ++ii) 4551 AddToWorkList(*ii); 4552 return S; 4553} 4554 4555/// FindBaseOffset - Return true if base is known not to alias with anything 4556/// but itself. Provides base object and offset as results. 4557static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4558 // Assume it is a primitive operation. 4559 Base = Ptr; Offset = 0; 4560 4561 // If it's an adding a simple constant then integrate the offset. 4562 if (Base.getOpcode() == ISD::ADD) { 4563 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4564 Base = Base.getOperand(0); 4565 Offset += C->getValue(); 4566 } 4567 } 4568 4569 // If it's any of the following then it can't alias with anything but itself. 4570 return isa<FrameIndexSDNode>(Base) || 4571 isa<ConstantPoolSDNode>(Base) || 4572 isa<GlobalAddressSDNode>(Base); 4573} 4574 4575/// isAlias - Return true if there is any possibility that the two addresses 4576/// overlap. 4577bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4578 const Value *SrcValue1, int SrcValueOffset1, 4579 SDOperand Ptr2, int64_t Size2, 4580 const Value *SrcValue2, int SrcValueOffset2) 4581{ 4582 // If they are the same then they must be aliases. 4583 if (Ptr1 == Ptr2) return true; 4584 4585 // Gather base node and offset information. 4586 SDOperand Base1, Base2; 4587 int64_t Offset1, Offset2; 4588 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4589 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4590 4591 // If they have a same base address then... 4592 if (Base1 == Base2) { 4593 // Check to see if the addresses overlap. 4594 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4595 } 4596 4597 // If we know both bases then they can't alias. 4598 if (KnownBase1 && KnownBase2) return false; 4599 4600 if (CombinerGlobalAA) { 4601 // Use alias analysis information. 4602 int Overlap1 = Size1 + SrcValueOffset1 + Offset1; 4603 int Overlap2 = Size2 + SrcValueOffset2 + Offset2; 4604 AliasAnalysis::AliasResult AAResult = 4605 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4606 if (AAResult == AliasAnalysis::NoAlias) 4607 return false; 4608 } 4609 4610 // Otherwise we have to assume they alias. 4611 return true; 4612} 4613 4614/// FindAliasInfo - Extracts the relevant alias information from the memory 4615/// node. Returns true if the operand was a load. 4616bool DAGCombiner::FindAliasInfo(SDNode *N, 4617 SDOperand &Ptr, int64_t &Size, 4618 const Value *&SrcValue, int &SrcValueOffset) { 4619 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4620 Ptr = LD->getBasePtr(); 4621 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4622 SrcValue = LD->getSrcValue(); 4623 SrcValueOffset = LD->getSrcValueOffset(); 4624 return true; 4625 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4626 Ptr = ST->getBasePtr(); 4627 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4628 SrcValue = ST->getSrcValue(); 4629 SrcValueOffset = ST->getSrcValueOffset(); 4630 } else { 4631 assert(0 && "FindAliasInfo expected a memory operand"); 4632 } 4633 4634 return false; 4635} 4636 4637/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4638/// looking for aliasing nodes and adding them to the Aliases vector. 4639void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4640 SmallVector<SDOperand, 8> &Aliases) { 4641 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4642 std::set<SDNode *> Visited; // Visited node set. 4643 4644 // Get alias information for node. 4645 SDOperand Ptr; 4646 int64_t Size; 4647 const Value *SrcValue; 4648 int SrcValueOffset; 4649 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4650 4651 // Starting off. 4652 Chains.push_back(OriginalChain); 4653 4654 // Look at each chain and determine if it is an alias. If so, add it to the 4655 // aliases list. If not, then continue up the chain looking for the next 4656 // candidate. 4657 while (!Chains.empty()) { 4658 SDOperand Chain = Chains.back(); 4659 Chains.pop_back(); 4660 4661 // Don't bother if we've been before. 4662 if (Visited.find(Chain.Val) != Visited.end()) continue; 4663 Visited.insert(Chain.Val); 4664 4665 switch (Chain.getOpcode()) { 4666 case ISD::EntryToken: 4667 // Entry token is ideal chain operand, but handled in FindBetterChain. 4668 break; 4669 4670 case ISD::LOAD: 4671 case ISD::STORE: { 4672 // Get alias information for Chain. 4673 SDOperand OpPtr; 4674 int64_t OpSize; 4675 const Value *OpSrcValue; 4676 int OpSrcValueOffset; 4677 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4678 OpSrcValue, OpSrcValueOffset); 4679 4680 // If chain is alias then stop here. 4681 if (!(IsLoad && IsOpLoad) && 4682 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4683 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4684 Aliases.push_back(Chain); 4685 } else { 4686 // Look further up the chain. 4687 Chains.push_back(Chain.getOperand(0)); 4688 // Clean up old chain. 4689 AddToWorkList(Chain.Val); 4690 } 4691 break; 4692 } 4693 4694 case ISD::TokenFactor: 4695 // We have to check each of the operands of the token factor, so we queue 4696 // then up. Adding the operands to the queue (stack) in reverse order 4697 // maintains the original order and increases the likelihood that getNode 4698 // will find a matching token factor (CSE.) 4699 for (unsigned n = Chain.getNumOperands(); n;) 4700 Chains.push_back(Chain.getOperand(--n)); 4701 // Eliminate the token factor if we can. 4702 AddToWorkList(Chain.Val); 4703 break; 4704 4705 default: 4706 // For all other instructions we will just have to take what we can get. 4707 Aliases.push_back(Chain); 4708 break; 4709 } 4710 } 4711} 4712 4713/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4714/// for a better chain (aliasing node.) 4715SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4716 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4717 4718 // Accumulate all the aliases to this node. 4719 GatherAllAliases(N, OldChain, Aliases); 4720 4721 if (Aliases.size() == 0) { 4722 // If no operands then chain to entry token. 4723 return DAG.getEntryNode(); 4724 } else if (Aliases.size() == 1) { 4725 // If a single operand then chain to it. We don't need to revisit it. 4726 return Aliases[0]; 4727 } 4728 4729 // Construct a custom tailored token factor. 4730 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4731 &Aliases[0], Aliases.size()); 4732 4733 // Make sure the old chain gets cleaned up. 4734 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4735 4736 return NewChain; 4737} 4738 4739// SelectionDAG::Combine - This is the entry point for the file. 4740// 4741void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4742 if (!RunningAfterLegalize && ViewDAGCombine1) 4743 viewGraph(); 4744 if (RunningAfterLegalize && ViewDAGCombine2) 4745 viewGraph(); 4746 /// run - This is the main entry point to this class. 4747 /// 4748 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 4749} 4750