DAGCombiner.cpp revision 1982ef20c44d85386a239a1b24eb2bb72cea29ec
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include "llvm/Target/TargetOptions.h" 39#include "llvm/Support/Compiler.h" 40#include "llvm/Support/CommandLine.h" 41#include <algorithm> 42using namespace llvm; 43 44STATISTIC(NodesCombined , "Number of dag nodes combined"); 45STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 46STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 47 48namespace { 49#ifndef NDEBUG 50 static cl::opt<bool> 51 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 52 cl::desc("Pop up a window to show dags before the first " 53 "dag combine pass")); 54 static cl::opt<bool> 55 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 56 cl::desc("Pop up a window to show dags before the second " 57 "dag combine pass")); 58#else 59 static const bool ViewDAGCombine1 = false; 60 static const bool ViewDAGCombine2 = false; 61#endif 62 63 static cl::opt<bool> 64 CombinerAA("combiner-alias-analysis", cl::Hidden, 65 cl::desc("Turn on alias analysis during testing")); 66 67 static cl::opt<bool> 68 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 69 cl::desc("Include global information in alias analysis")); 70 71//------------------------------ DAGCombiner ---------------------------------// 72 73 class VISIBILITY_HIDDEN DAGCombiner { 74 SelectionDAG &DAG; 75 TargetLowering &TLI; 76 bool AfterLegalize; 77 78 // Worklist of all of the nodes that need to be simplified. 79 std::vector<SDNode*> WorkList; 80 81 // AA - Used for DAG load/store alias analysis. 82 AliasAnalysis &AA; 83 84 /// AddUsersToWorkList - When an instruction is simplified, add all users of 85 /// the instruction to the work lists because they might get more simplified 86 /// now. 87 /// 88 void AddUsersToWorkList(SDNode *N) { 89 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 90 UI != UE; ++UI) 91 AddToWorkList(*UI); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 public: 102 /// AddToWorkList - Add to the work list making sure it's instance is at the 103 /// the back (next to be processed.) 104 void AddToWorkList(SDNode *N) { 105 removeFromWorkList(N); 106 WorkList.push_back(N); 107 } 108 109 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 110 bool AddTo = true) { 111 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 112 ++NodesCombined; 113 DOUT << "\nReplacing.1 "; DEBUG(N->dump()); 114 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 115 DOUT << " and " << NumTo-1 << " other values\n"; 116 std::vector<SDNode*> NowDead; 117 DAG.ReplaceAllUsesWith(N, To, &NowDead); 118 119 if (AddTo) { 120 // Push the new nodes and any users onto the worklist 121 for (unsigned i = 0, e = NumTo; i != e; ++i) { 122 AddToWorkList(To[i].Val); 123 AddUsersToWorkList(To[i].Val); 124 } 125 } 126 127 // Nodes can be reintroduced into the worklist. Make sure we do not 128 // process a node that has been replaced. 129 removeFromWorkList(N); 130 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 131 removeFromWorkList(NowDead[i]); 132 133 // Finally, since the node is now dead, remove it from the graph. 134 DAG.DeleteNode(N); 135 return SDOperand(N, 0); 136 } 137 138 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 139 return CombineTo(N, &Res, 1, AddTo); 140 } 141 142 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 143 bool AddTo = true) { 144 SDOperand To[] = { Res0, Res1 }; 145 return CombineTo(N, To, 2, AddTo); 146 } 147 private: 148 149 /// SimplifyDemandedBits - Check the specified integer node value to see if 150 /// it can be simplified or if things it uses can be simplified by bit 151 /// propagation. If so, return true. 152 bool SimplifyDemandedBits(SDOperand Op) { 153 TargetLowering::TargetLoweringOpt TLO(DAG); 154 uint64_t KnownZero, KnownOne; 155 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 156 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 157 return false; 158 159 // Revisit the node. 160 AddToWorkList(Op.Val); 161 162 // Replace the old value with the new one. 163 ++NodesCombined; 164 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump()); 165 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 166 DOUT << '\n'; 167 168 std::vector<SDNode*> NowDead; 169 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 170 171 // Push the new node and any (possibly new) users onto the worklist. 172 AddToWorkList(TLO.New.Val); 173 AddUsersToWorkList(TLO.New.Val); 174 175 // Nodes can end up on the worklist more than once. Make sure we do 176 // not process a node that has been replaced. 177 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 178 removeFromWorkList(NowDead[i]); 179 180 // Finally, if the node is now dead, remove it from the graph. The node 181 // may not be dead if the replacement process recursively simplified to 182 // something else needing this node. 183 if (TLO.Old.Val->use_empty()) { 184 removeFromWorkList(TLO.Old.Val); 185 DAG.DeleteNode(TLO.Old.Val); 186 } 187 return true; 188 } 189 190 bool CombineToPreIndexedLoadStore(SDNode *N); 191 bool CombineToPostIndexedLoadStore(SDNode *N); 192 193 194 /// visit - call the node-specific routine that knows how to fold each 195 /// particular type of node. 196 SDOperand visit(SDNode *N); 197 198 // Visitation implementation - Implement dag node combining for different 199 // node types. The semantics are as follows: 200 // Return Value: 201 // SDOperand.Val == 0 - No change was made 202 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 203 // otherwise - N should be replaced by the returned Operand. 204 // 205 SDOperand visitTokenFactor(SDNode *N); 206 SDOperand visitADD(SDNode *N); 207 SDOperand visitSUB(SDNode *N); 208 SDOperand visitADDC(SDNode *N); 209 SDOperand visitADDE(SDNode *N); 210 SDOperand visitMUL(SDNode *N); 211 SDOperand visitSDIV(SDNode *N); 212 SDOperand visitUDIV(SDNode *N); 213 SDOperand visitSREM(SDNode *N); 214 SDOperand visitUREM(SDNode *N); 215 SDOperand visitMULHU(SDNode *N); 216 SDOperand visitMULHS(SDNode *N); 217 SDOperand visitAND(SDNode *N); 218 SDOperand visitOR(SDNode *N); 219 SDOperand visitXOR(SDNode *N); 220 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 221 SDOperand visitSHL(SDNode *N); 222 SDOperand visitSRA(SDNode *N); 223 SDOperand visitSRL(SDNode *N); 224 SDOperand visitCTLZ(SDNode *N); 225 SDOperand visitCTTZ(SDNode *N); 226 SDOperand visitCTPOP(SDNode *N); 227 SDOperand visitSELECT(SDNode *N); 228 SDOperand visitSELECT_CC(SDNode *N); 229 SDOperand visitSETCC(SDNode *N); 230 SDOperand visitSIGN_EXTEND(SDNode *N); 231 SDOperand visitZERO_EXTEND(SDNode *N); 232 SDOperand visitANY_EXTEND(SDNode *N); 233 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 234 SDOperand visitTRUNCATE(SDNode *N); 235 SDOperand visitBIT_CONVERT(SDNode *N); 236 SDOperand visitVBIT_CONVERT(SDNode *N); 237 SDOperand visitFADD(SDNode *N); 238 SDOperand visitFSUB(SDNode *N); 239 SDOperand visitFMUL(SDNode *N); 240 SDOperand visitFDIV(SDNode *N); 241 SDOperand visitFREM(SDNode *N); 242 SDOperand visitFCOPYSIGN(SDNode *N); 243 SDOperand visitSINT_TO_FP(SDNode *N); 244 SDOperand visitUINT_TO_FP(SDNode *N); 245 SDOperand visitFP_TO_SINT(SDNode *N); 246 SDOperand visitFP_TO_UINT(SDNode *N); 247 SDOperand visitFP_ROUND(SDNode *N); 248 SDOperand visitFP_ROUND_INREG(SDNode *N); 249 SDOperand visitFP_EXTEND(SDNode *N); 250 SDOperand visitFNEG(SDNode *N); 251 SDOperand visitFABS(SDNode *N); 252 SDOperand visitBRCOND(SDNode *N); 253 SDOperand visitBR_CC(SDNode *N); 254 SDOperand visitLOAD(SDNode *N); 255 SDOperand visitSTORE(SDNode *N); 256 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 257 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 258 SDOperand visitVBUILD_VECTOR(SDNode *N); 259 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 260 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 261 262 SDOperand XformToShuffleWithZero(SDNode *N); 263 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 264 265 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 266 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 267 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 268 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 269 SDOperand N3, ISD::CondCode CC); 270 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 271 ISD::CondCode Cond, bool foldBooleans = true); 272 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 273 SDOperand BuildSDIV(SDNode *N); 274 SDOperand BuildUDIV(SDNode *N); 275 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 276 SDOperand ReduceLoadWidth(SDNode *N); 277 278 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 279 /// looking for aliasing nodes and adding them to the Aliases vector. 280 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 281 SmallVector<SDOperand, 8> &Aliases); 282 283 /// isAlias - Return true if there is any possibility that the two addresses 284 /// overlap. 285 bool isAlias(SDOperand Ptr1, int64_t Size1, 286 const Value *SrcValue1, int SrcValueOffset1, 287 SDOperand Ptr2, int64_t Size2, 288 const Value *SrcValue2, int SrcValueOffset2); 289 290 /// FindAliasInfo - Extracts the relevant alias information from the memory 291 /// node. Returns true if the operand was a load. 292 bool FindAliasInfo(SDNode *N, 293 SDOperand &Ptr, int64_t &Size, 294 const Value *&SrcValue, int &SrcValueOffset); 295 296 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 297 /// looking for a better chain (aliasing node.) 298 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 299 300public: 301 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 302 : DAG(D), 303 TLI(D.getTargetLoweringInfo()), 304 AfterLegalize(false), 305 AA(A) {} 306 307 /// Run - runs the dag combiner on all nodes in the work list 308 void Run(bool RunningAfterLegalize); 309 }; 310} 311 312//===----------------------------------------------------------------------===// 313// TargetLowering::DAGCombinerInfo implementation 314//===----------------------------------------------------------------------===// 315 316void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 317 ((DAGCombiner*)DC)->AddToWorkList(N); 318} 319 320SDOperand TargetLowering::DAGCombinerInfo:: 321CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 322 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 323} 324 325SDOperand TargetLowering::DAGCombinerInfo:: 326CombineTo(SDNode *N, SDOperand Res) { 327 return ((DAGCombiner*)DC)->CombineTo(N, Res); 328} 329 330 331SDOperand TargetLowering::DAGCombinerInfo:: 332CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 333 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 334} 335 336 337 338 339//===----------------------------------------------------------------------===// 340 341 342// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 343// that selects between the values 1 and 0, making it equivalent to a setcc. 344// Also, set the incoming LHS, RHS, and CC references to the appropriate 345// nodes based on the type of node we are checking. This simplifies life a 346// bit for the callers. 347static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 348 SDOperand &CC) { 349 if (N.getOpcode() == ISD::SETCC) { 350 LHS = N.getOperand(0); 351 RHS = N.getOperand(1); 352 CC = N.getOperand(2); 353 return true; 354 } 355 if (N.getOpcode() == ISD::SELECT_CC && 356 N.getOperand(2).getOpcode() == ISD::Constant && 357 N.getOperand(3).getOpcode() == ISD::Constant && 358 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 359 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 360 LHS = N.getOperand(0); 361 RHS = N.getOperand(1); 362 CC = N.getOperand(4); 363 return true; 364 } 365 return false; 366} 367 368// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 369// one use. If this is true, it allows the users to invert the operation for 370// free when it is profitable to do so. 371static bool isOneUseSetCC(SDOperand N) { 372 SDOperand N0, N1, N2; 373 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 374 return true; 375 return false; 376} 377 378SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 379 MVT::ValueType VT = N0.getValueType(); 380 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 381 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 382 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 383 if (isa<ConstantSDNode>(N1)) { 384 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 385 AddToWorkList(OpNode.Val); 386 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 387 } else if (N0.hasOneUse()) { 388 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 389 AddToWorkList(OpNode.Val); 390 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 391 } 392 } 393 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 394 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 395 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 396 if (isa<ConstantSDNode>(N0)) { 397 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 398 AddToWorkList(OpNode.Val); 399 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 400 } else if (N1.hasOneUse()) { 401 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 402 AddToWorkList(OpNode.Val); 403 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 404 } 405 } 406 return SDOperand(); 407} 408 409void DAGCombiner::Run(bool RunningAfterLegalize) { 410 // set the instance variable, so that the various visit routines may use it. 411 AfterLegalize = RunningAfterLegalize; 412 413 // Add all the dag nodes to the worklist. 414 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 415 E = DAG.allnodes_end(); I != E; ++I) 416 WorkList.push_back(I); 417 418 // Create a dummy node (which is not added to allnodes), that adds a reference 419 // to the root node, preventing it from being deleted, and tracking any 420 // changes of the root. 421 HandleSDNode Dummy(DAG.getRoot()); 422 423 // The root of the dag may dangle to deleted nodes until the dag combiner is 424 // done. Set it to null to avoid confusion. 425 DAG.setRoot(SDOperand()); 426 427 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 428 TargetLowering::DAGCombinerInfo 429 DagCombineInfo(DAG, !RunningAfterLegalize, false, this); 430 431 // while the worklist isn't empty, inspect the node on the end of it and 432 // try and combine it. 433 while (!WorkList.empty()) { 434 SDNode *N = WorkList.back(); 435 WorkList.pop_back(); 436 437 // If N has no uses, it is dead. Make sure to revisit all N's operands once 438 // N is deleted from the DAG, since they too may now be dead or may have a 439 // reduced number of uses, allowing other xforms. 440 if (N->use_empty() && N != &Dummy) { 441 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 442 AddToWorkList(N->getOperand(i).Val); 443 444 DAG.DeleteNode(N); 445 continue; 446 } 447 448 SDOperand RV = visit(N); 449 450 // If nothing happened, try a target-specific DAG combine. 451 if (RV.Val == 0) { 452 assert(N->getOpcode() != ISD::DELETED_NODE && 453 "Node was deleted but visit returned NULL!"); 454 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 455 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 456 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 457 } 458 459 if (RV.Val) { 460 ++NodesCombined; 461 // If we get back the same node we passed in, rather than a new node or 462 // zero, we know that the node must have defined multiple values and 463 // CombineTo was used. Since CombineTo takes care of the worklist 464 // mechanics for us, we have no work to do in this case. 465 if (RV.Val != N) { 466 assert(N->getOpcode() != ISD::DELETED_NODE && 467 RV.Val->getOpcode() != ISD::DELETED_NODE && 468 "Node was deleted but visit returned new node!"); 469 470 DOUT << "\nReplacing.3 "; DEBUG(N->dump()); 471 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 472 DOUT << '\n'; 473 std::vector<SDNode*> NowDead; 474 if (N->getNumValues() == RV.Val->getNumValues()) 475 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 476 else { 477 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 478 SDOperand OpV = RV; 479 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 480 } 481 482 // Push the new node and any users onto the worklist 483 AddToWorkList(RV.Val); 484 AddUsersToWorkList(RV.Val); 485 486 // Nodes can be reintroduced into the worklist. Make sure we do not 487 // process a node that has been replaced. 488 removeFromWorkList(N); 489 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 490 removeFromWorkList(NowDead[i]); 491 492 // Finally, since the node is now dead, remove it from the graph. 493 DAG.DeleteNode(N); 494 } 495 } 496 } 497 498 // If the root changed (e.g. it was a dead load, update the root). 499 DAG.setRoot(Dummy.getValue()); 500} 501 502SDOperand DAGCombiner::visit(SDNode *N) { 503 switch(N->getOpcode()) { 504 default: break; 505 case ISD::TokenFactor: return visitTokenFactor(N); 506 case ISD::ADD: return visitADD(N); 507 case ISD::SUB: return visitSUB(N); 508 case ISD::ADDC: return visitADDC(N); 509 case ISD::ADDE: return visitADDE(N); 510 case ISD::MUL: return visitMUL(N); 511 case ISD::SDIV: return visitSDIV(N); 512 case ISD::UDIV: return visitUDIV(N); 513 case ISD::SREM: return visitSREM(N); 514 case ISD::UREM: return visitUREM(N); 515 case ISD::MULHU: return visitMULHU(N); 516 case ISD::MULHS: return visitMULHS(N); 517 case ISD::AND: return visitAND(N); 518 case ISD::OR: return visitOR(N); 519 case ISD::XOR: return visitXOR(N); 520 case ISD::SHL: return visitSHL(N); 521 case ISD::SRA: return visitSRA(N); 522 case ISD::SRL: return visitSRL(N); 523 case ISD::CTLZ: return visitCTLZ(N); 524 case ISD::CTTZ: return visitCTTZ(N); 525 case ISD::CTPOP: return visitCTPOP(N); 526 case ISD::SELECT: return visitSELECT(N); 527 case ISD::SELECT_CC: return visitSELECT_CC(N); 528 case ISD::SETCC: return visitSETCC(N); 529 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 530 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 531 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 532 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 533 case ISD::TRUNCATE: return visitTRUNCATE(N); 534 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 535 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 536 case ISD::FADD: return visitFADD(N); 537 case ISD::FSUB: return visitFSUB(N); 538 case ISD::FMUL: return visitFMUL(N); 539 case ISD::FDIV: return visitFDIV(N); 540 case ISD::FREM: return visitFREM(N); 541 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 542 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 543 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 544 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 545 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 546 case ISD::FP_ROUND: return visitFP_ROUND(N); 547 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 548 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 549 case ISD::FNEG: return visitFNEG(N); 550 case ISD::FABS: return visitFABS(N); 551 case ISD::BRCOND: return visitBRCOND(N); 552 case ISD::BR_CC: return visitBR_CC(N); 553 case ISD::LOAD: return visitLOAD(N); 554 case ISD::STORE: return visitSTORE(N); 555 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 556 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 557 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 558 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 559 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 560 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 561 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 562 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 563 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 564 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 565 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 566 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 567 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 568 } 569 return SDOperand(); 570} 571 572/// getInputChainForNode - Given a node, return its input chain if it has one, 573/// otherwise return a null sd operand. 574static SDOperand getInputChainForNode(SDNode *N) { 575 if (unsigned NumOps = N->getNumOperands()) { 576 if (N->getOperand(0).getValueType() == MVT::Other) 577 return N->getOperand(0); 578 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 579 return N->getOperand(NumOps-1); 580 for (unsigned i = 1; i < NumOps-1; ++i) 581 if (N->getOperand(i).getValueType() == MVT::Other) 582 return N->getOperand(i); 583 } 584 return SDOperand(0, 0); 585} 586 587SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 588 // If N has two operands, where one has an input chain equal to the other, 589 // the 'other' chain is redundant. 590 if (N->getNumOperands() == 2) { 591 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 592 return N->getOperand(0); 593 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 594 return N->getOperand(1); 595 } 596 597 598 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 599 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 600 bool Changed = false; // If we should replace this token factor. 601 602 // Start out with this token factor. 603 TFs.push_back(N); 604 605 // Iterate through token factors. The TFs grows when new token factors are 606 // encountered. 607 for (unsigned i = 0; i < TFs.size(); ++i) { 608 SDNode *TF = TFs[i]; 609 610 // Check each of the operands. 611 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 612 SDOperand Op = TF->getOperand(i); 613 614 switch (Op.getOpcode()) { 615 case ISD::EntryToken: 616 // Entry tokens don't need to be added to the list. They are 617 // rededundant. 618 Changed = true; 619 break; 620 621 case ISD::TokenFactor: 622 if ((CombinerAA || Op.hasOneUse()) && 623 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 624 // Queue up for processing. 625 TFs.push_back(Op.Val); 626 // Clean up in case the token factor is removed. 627 AddToWorkList(Op.Val); 628 Changed = true; 629 break; 630 } 631 // Fall thru 632 633 default: 634 // Only add if not there prior. 635 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end()) 636 Ops.push_back(Op); 637 break; 638 } 639 } 640 } 641 642 SDOperand Result; 643 644 // If we've change things around then replace token factor. 645 if (Changed) { 646 if (Ops.size() == 0) { 647 // The entry token is the only possible outcome. 648 Result = DAG.getEntryNode(); 649 } else { 650 // New and improved token factor. 651 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 652 } 653 654 // Don't add users to work list. 655 return CombineTo(N, Result, false); 656 } 657 658 return Result; 659} 660 661static 662SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 663 MVT::ValueType VT = N0.getValueType(); 664 SDOperand N00 = N0.getOperand(0); 665 SDOperand N01 = N0.getOperand(1); 666 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 667 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 668 isa<ConstantSDNode>(N00.getOperand(1))) { 669 N0 = DAG.getNode(ISD::ADD, VT, 670 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 671 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 672 return DAG.getNode(ISD::ADD, VT, N0, N1); 673 } 674 return SDOperand(); 675} 676 677SDOperand DAGCombiner::visitADD(SDNode *N) { 678 SDOperand N0 = N->getOperand(0); 679 SDOperand N1 = N->getOperand(1); 680 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 681 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 682 MVT::ValueType VT = N0.getValueType(); 683 684 // fold (add c1, c2) -> c1+c2 685 if (N0C && N1C) 686 return DAG.getNode(ISD::ADD, VT, N0, N1); 687 // canonicalize constant to RHS 688 if (N0C && !N1C) 689 return DAG.getNode(ISD::ADD, VT, N1, N0); 690 // fold (add x, 0) -> x 691 if (N1C && N1C->isNullValue()) 692 return N0; 693 // fold ((c1-A)+c2) -> (c1+c2)-A 694 if (N1C && N0.getOpcode() == ISD::SUB) 695 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 696 return DAG.getNode(ISD::SUB, VT, 697 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 698 N0.getOperand(1)); 699 // reassociate add 700 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 701 if (RADD.Val != 0) 702 return RADD; 703 // fold ((0-A) + B) -> B-A 704 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 705 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 706 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 707 // fold (A + (0-B)) -> A-B 708 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 709 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 710 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 711 // fold (A+(B-A)) -> B 712 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 713 return N1.getOperand(0); 714 715 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 716 return SDOperand(N, 0); 717 718 // fold (a+b) -> (a|b) iff a and b share no bits. 719 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 720 uint64_t LHSZero, LHSOne; 721 uint64_t RHSZero, RHSOne; 722 uint64_t Mask = MVT::getIntVTBitMask(VT); 723 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 724 if (LHSZero) { 725 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 726 727 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 728 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 729 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 730 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 731 return DAG.getNode(ISD::OR, VT, N0, N1); 732 } 733 } 734 735 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 736 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 737 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 738 if (Result.Val) return Result; 739 } 740 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 741 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 742 if (Result.Val) return Result; 743 } 744 745 return SDOperand(); 746} 747 748SDOperand DAGCombiner::visitADDC(SDNode *N) { 749 SDOperand N0 = N->getOperand(0); 750 SDOperand N1 = N->getOperand(1); 751 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 752 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 753 MVT::ValueType VT = N0.getValueType(); 754 755 // If the flag result is dead, turn this into an ADD. 756 if (N->hasNUsesOfValue(0, 1)) 757 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 758 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 759 760 // canonicalize constant to RHS. 761 if (N0C && !N1C) { 762 SDOperand Ops[] = { N1, N0 }; 763 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 764 } 765 766 // fold (addc x, 0) -> x + no carry out 767 if (N1C && N1C->isNullValue()) 768 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 769 770 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 771 uint64_t LHSZero, LHSOne; 772 uint64_t RHSZero, RHSOne; 773 uint64_t Mask = MVT::getIntVTBitMask(VT); 774 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 775 if (LHSZero) { 776 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 777 778 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 779 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 780 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 781 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 782 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 783 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 784 } 785 786 return SDOperand(); 787} 788 789SDOperand DAGCombiner::visitADDE(SDNode *N) { 790 SDOperand N0 = N->getOperand(0); 791 SDOperand N1 = N->getOperand(1); 792 SDOperand CarryIn = N->getOperand(2); 793 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 794 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 795 //MVT::ValueType VT = N0.getValueType(); 796 797 // canonicalize constant to RHS 798 if (N0C && !N1C) { 799 SDOperand Ops[] = { N1, N0, CarryIn }; 800 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 801 } 802 803 // fold (adde x, y, false) -> (addc x, y) 804 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 805 SDOperand Ops[] = { N1, N0 }; 806 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 807 } 808 809 return SDOperand(); 810} 811 812 813 814SDOperand DAGCombiner::visitSUB(SDNode *N) { 815 SDOperand N0 = N->getOperand(0); 816 SDOperand N1 = N->getOperand(1); 817 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 818 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 819 MVT::ValueType VT = N0.getValueType(); 820 821 // fold (sub x, x) -> 0 822 if (N0 == N1) 823 return DAG.getConstant(0, N->getValueType(0)); 824 // fold (sub c1, c2) -> c1-c2 825 if (N0C && N1C) 826 return DAG.getNode(ISD::SUB, VT, N0, N1); 827 // fold (sub x, c) -> (add x, -c) 828 if (N1C) 829 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 830 // fold (A+B)-A -> B 831 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 832 return N0.getOperand(1); 833 // fold (A+B)-B -> A 834 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 835 return N0.getOperand(0); 836 return SDOperand(); 837} 838 839SDOperand DAGCombiner::visitMUL(SDNode *N) { 840 SDOperand N0 = N->getOperand(0); 841 SDOperand N1 = N->getOperand(1); 842 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 843 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 844 MVT::ValueType VT = N0.getValueType(); 845 846 // fold (mul c1, c2) -> c1*c2 847 if (N0C && N1C) 848 return DAG.getNode(ISD::MUL, VT, N0, N1); 849 // canonicalize constant to RHS 850 if (N0C && !N1C) 851 return DAG.getNode(ISD::MUL, VT, N1, N0); 852 // fold (mul x, 0) -> 0 853 if (N1C && N1C->isNullValue()) 854 return N1; 855 // fold (mul x, -1) -> 0-x 856 if (N1C && N1C->isAllOnesValue()) 857 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 858 // fold (mul x, (1 << c)) -> x << c 859 if (N1C && isPowerOf2_64(N1C->getValue())) 860 return DAG.getNode(ISD::SHL, VT, N0, 861 DAG.getConstant(Log2_64(N1C->getValue()), 862 TLI.getShiftAmountTy())); 863 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 864 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 865 // FIXME: If the input is something that is easily negated (e.g. a 866 // single-use add), we should put the negate there. 867 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 868 DAG.getNode(ISD::SHL, VT, N0, 869 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 870 TLI.getShiftAmountTy()))); 871 } 872 873 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 874 if (N1C && N0.getOpcode() == ISD::SHL && 875 isa<ConstantSDNode>(N0.getOperand(1))) { 876 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 877 AddToWorkList(C3.Val); 878 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 879 } 880 881 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 882 // use. 883 { 884 SDOperand Sh(0,0), Y(0,0); 885 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 886 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 887 N0.Val->hasOneUse()) { 888 Sh = N0; Y = N1; 889 } else if (N1.getOpcode() == ISD::SHL && 890 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 891 Sh = N1; Y = N0; 892 } 893 if (Sh.Val) { 894 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 895 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 896 } 897 } 898 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 899 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 900 isa<ConstantSDNode>(N0.getOperand(1))) { 901 return DAG.getNode(ISD::ADD, VT, 902 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 903 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 904 } 905 906 // reassociate mul 907 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 908 if (RMUL.Val != 0) 909 return RMUL; 910 return SDOperand(); 911} 912 913SDOperand DAGCombiner::visitSDIV(SDNode *N) { 914 SDOperand N0 = N->getOperand(0); 915 SDOperand N1 = N->getOperand(1); 916 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 917 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 918 MVT::ValueType VT = N->getValueType(0); 919 920 // fold (sdiv c1, c2) -> c1/c2 921 if (N0C && N1C && !N1C->isNullValue()) 922 return DAG.getNode(ISD::SDIV, VT, N0, N1); 923 // fold (sdiv X, 1) -> X 924 if (N1C && N1C->getSignExtended() == 1LL) 925 return N0; 926 // fold (sdiv X, -1) -> 0-X 927 if (N1C && N1C->isAllOnesValue()) 928 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 929 // If we know the sign bits of both operands are zero, strength reduce to a 930 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 931 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 932 if (TLI.MaskedValueIsZero(N1, SignBit) && 933 TLI.MaskedValueIsZero(N0, SignBit)) 934 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 935 // fold (sdiv X, pow2) -> simple ops after legalize 936 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 937 (isPowerOf2_64(N1C->getSignExtended()) || 938 isPowerOf2_64(-N1C->getSignExtended()))) { 939 // If dividing by powers of two is cheap, then don't perform the following 940 // fold. 941 if (TLI.isPow2DivCheap()) 942 return SDOperand(); 943 int64_t pow2 = N1C->getSignExtended(); 944 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 945 unsigned lg2 = Log2_64(abs2); 946 // Splat the sign bit into the register 947 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 948 DAG.getConstant(MVT::getSizeInBits(VT)-1, 949 TLI.getShiftAmountTy())); 950 AddToWorkList(SGN.Val); 951 // Add (N0 < 0) ? abs2 - 1 : 0; 952 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 953 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 954 TLI.getShiftAmountTy())); 955 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 956 AddToWorkList(SRL.Val); 957 AddToWorkList(ADD.Val); // Divide by pow2 958 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 959 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 960 // If we're dividing by a positive value, we're done. Otherwise, we must 961 // negate the result. 962 if (pow2 > 0) 963 return SRA; 964 AddToWorkList(SRA.Val); 965 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 966 } 967 // if integer divide is expensive and we satisfy the requirements, emit an 968 // alternate sequence. 969 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 970 !TLI.isIntDivCheap()) { 971 SDOperand Op = BuildSDIV(N); 972 if (Op.Val) return Op; 973 } 974 return SDOperand(); 975} 976 977SDOperand DAGCombiner::visitUDIV(SDNode *N) { 978 SDOperand N0 = N->getOperand(0); 979 SDOperand N1 = N->getOperand(1); 980 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 981 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 982 MVT::ValueType VT = N->getValueType(0); 983 984 // fold (udiv c1, c2) -> c1/c2 985 if (N0C && N1C && !N1C->isNullValue()) 986 return DAG.getNode(ISD::UDIV, VT, N0, N1); 987 // fold (udiv x, (1 << c)) -> x >>u c 988 if (N1C && isPowerOf2_64(N1C->getValue())) 989 return DAG.getNode(ISD::SRL, VT, N0, 990 DAG.getConstant(Log2_64(N1C->getValue()), 991 TLI.getShiftAmountTy())); 992 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 993 if (N1.getOpcode() == ISD::SHL) { 994 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 995 if (isPowerOf2_64(SHC->getValue())) { 996 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 997 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 998 DAG.getConstant(Log2_64(SHC->getValue()), 999 ADDVT)); 1000 AddToWorkList(Add.Val); 1001 return DAG.getNode(ISD::SRL, VT, N0, Add); 1002 } 1003 } 1004 } 1005 // fold (udiv x, c) -> alternate 1006 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1007 SDOperand Op = BuildUDIV(N); 1008 if (Op.Val) return Op; 1009 } 1010 return SDOperand(); 1011} 1012 1013SDOperand DAGCombiner::visitSREM(SDNode *N) { 1014 SDOperand N0 = N->getOperand(0); 1015 SDOperand N1 = N->getOperand(1); 1016 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1017 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1018 MVT::ValueType VT = N->getValueType(0); 1019 1020 // fold (srem c1, c2) -> c1%c2 1021 if (N0C && N1C && !N1C->isNullValue()) 1022 return DAG.getNode(ISD::SREM, VT, N0, N1); 1023 // If we know the sign bits of both operands are zero, strength reduce to a 1024 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1025 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1026 if (TLI.MaskedValueIsZero(N1, SignBit) && 1027 TLI.MaskedValueIsZero(N0, SignBit)) 1028 return DAG.getNode(ISD::UREM, VT, N0, N1); 1029 1030 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1031 // the remainder operation. 1032 if (N1C && !N1C->isNullValue()) { 1033 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1034 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1035 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1036 AddToWorkList(Div.Val); 1037 AddToWorkList(Mul.Val); 1038 return Sub; 1039 } 1040 1041 return SDOperand(); 1042} 1043 1044SDOperand DAGCombiner::visitUREM(SDNode *N) { 1045 SDOperand N0 = N->getOperand(0); 1046 SDOperand N1 = N->getOperand(1); 1047 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1048 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1049 MVT::ValueType VT = N->getValueType(0); 1050 1051 // fold (urem c1, c2) -> c1%c2 1052 if (N0C && N1C && !N1C->isNullValue()) 1053 return DAG.getNode(ISD::UREM, VT, N0, N1); 1054 // fold (urem x, pow2) -> (and x, pow2-1) 1055 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1056 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1057 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1058 if (N1.getOpcode() == ISD::SHL) { 1059 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1060 if (isPowerOf2_64(SHC->getValue())) { 1061 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1062 AddToWorkList(Add.Val); 1063 return DAG.getNode(ISD::AND, VT, N0, Add); 1064 } 1065 } 1066 } 1067 1068 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1069 // the remainder operation. 1070 if (N1C && !N1C->isNullValue()) { 1071 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1072 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1073 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1074 AddToWorkList(Div.Val); 1075 AddToWorkList(Mul.Val); 1076 return Sub; 1077 } 1078 1079 return SDOperand(); 1080} 1081 1082SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1083 SDOperand N0 = N->getOperand(0); 1084 SDOperand N1 = N->getOperand(1); 1085 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1086 1087 // fold (mulhs x, 0) -> 0 1088 if (N1C && N1C->isNullValue()) 1089 return N1; 1090 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1091 if (N1C && N1C->getValue() == 1) 1092 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1093 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1094 TLI.getShiftAmountTy())); 1095 return SDOperand(); 1096} 1097 1098SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1099 SDOperand N0 = N->getOperand(0); 1100 SDOperand N1 = N->getOperand(1); 1101 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1102 1103 // fold (mulhu x, 0) -> 0 1104 if (N1C && N1C->isNullValue()) 1105 return N1; 1106 // fold (mulhu x, 1) -> 0 1107 if (N1C && N1C->getValue() == 1) 1108 return DAG.getConstant(0, N0.getValueType()); 1109 return SDOperand(); 1110} 1111 1112/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1113/// two operands of the same opcode, try to simplify it. 1114SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1115 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1116 MVT::ValueType VT = N0.getValueType(); 1117 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1118 1119 // For each of OP in AND/OR/XOR: 1120 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1121 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1122 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1123 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1124 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1125 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1126 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1127 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1128 N0.getOperand(0).getValueType(), 1129 N0.getOperand(0), N1.getOperand(0)); 1130 AddToWorkList(ORNode.Val); 1131 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1132 } 1133 1134 // For each of OP in SHL/SRL/SRA/AND... 1135 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1136 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1137 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1138 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1139 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1140 N0.getOperand(1) == N1.getOperand(1)) { 1141 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1142 N0.getOperand(0).getValueType(), 1143 N0.getOperand(0), N1.getOperand(0)); 1144 AddToWorkList(ORNode.Val); 1145 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1146 } 1147 1148 return SDOperand(); 1149} 1150 1151SDOperand DAGCombiner::visitAND(SDNode *N) { 1152 SDOperand N0 = N->getOperand(0); 1153 SDOperand N1 = N->getOperand(1); 1154 SDOperand LL, LR, RL, RR, CC0, CC1; 1155 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1156 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1157 MVT::ValueType VT = N1.getValueType(); 1158 1159 // fold (and c1, c2) -> c1&c2 1160 if (N0C && N1C) 1161 return DAG.getNode(ISD::AND, VT, N0, N1); 1162 // canonicalize constant to RHS 1163 if (N0C && !N1C) 1164 return DAG.getNode(ISD::AND, VT, N1, N0); 1165 // fold (and x, -1) -> x 1166 if (N1C && N1C->isAllOnesValue()) 1167 return N0; 1168 // if (and x, c) is known to be zero, return 0 1169 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1170 return DAG.getConstant(0, VT); 1171 // reassociate and 1172 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1173 if (RAND.Val != 0) 1174 return RAND; 1175 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1176 if (N1C && N0.getOpcode() == ISD::OR) 1177 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1178 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1179 return N1; 1180 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1181 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1182 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1183 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1184 ~N1C->getValue() & InMask)) { 1185 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1186 N0.getOperand(0)); 1187 1188 // Replace uses of the AND with uses of the Zero extend node. 1189 CombineTo(N, Zext); 1190 1191 // We actually want to replace all uses of the any_extend with the 1192 // zero_extend, to avoid duplicating things. This will later cause this 1193 // AND to be folded. 1194 CombineTo(N0.Val, Zext); 1195 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1196 } 1197 } 1198 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1199 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1200 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1201 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1202 1203 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1204 MVT::isInteger(LL.getValueType())) { 1205 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1206 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1207 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1208 AddToWorkList(ORNode.Val); 1209 return DAG.getSetCC(VT, ORNode, LR, Op1); 1210 } 1211 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1212 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1213 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1214 AddToWorkList(ANDNode.Val); 1215 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1216 } 1217 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1218 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1219 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1220 AddToWorkList(ORNode.Val); 1221 return DAG.getSetCC(VT, ORNode, LR, Op1); 1222 } 1223 } 1224 // canonicalize equivalent to ll == rl 1225 if (LL == RR && LR == RL) { 1226 Op1 = ISD::getSetCCSwappedOperands(Op1); 1227 std::swap(RL, RR); 1228 } 1229 if (LL == RL && LR == RR) { 1230 bool isInteger = MVT::isInteger(LL.getValueType()); 1231 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1232 if (Result != ISD::SETCC_INVALID) 1233 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1234 } 1235 } 1236 1237 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1238 if (N0.getOpcode() == N1.getOpcode()) { 1239 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1240 if (Tmp.Val) return Tmp; 1241 } 1242 1243 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1244 // fold (and (sra)) -> (and (srl)) when possible. 1245 if (!MVT::isVector(VT) && 1246 SimplifyDemandedBits(SDOperand(N, 0))) 1247 return SDOperand(N, 0); 1248 // fold (zext_inreg (extload x)) -> (zextload x) 1249 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1250 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1251 MVT::ValueType EVT = LN0->getLoadedVT(); 1252 // If we zero all the possible extended bits, then we can turn this into 1253 // a zextload if we are running before legalize or the operation is legal. 1254 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1255 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1256 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1257 LN0->getBasePtr(), LN0->getSrcValue(), 1258 LN0->getSrcValueOffset(), EVT); 1259 AddToWorkList(N); 1260 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1261 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1262 } 1263 } 1264 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1265 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1266 N0.hasOneUse()) { 1267 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1268 MVT::ValueType EVT = LN0->getLoadedVT(); 1269 // If we zero all the possible extended bits, then we can turn this into 1270 // a zextload if we are running before legalize or the operation is legal. 1271 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1272 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1273 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1274 LN0->getBasePtr(), LN0->getSrcValue(), 1275 LN0->getSrcValueOffset(), EVT); 1276 AddToWorkList(N); 1277 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1278 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1279 } 1280 } 1281 1282 // fold (and (load x), 255) -> (zextload x, i8) 1283 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1284 if (N1C && N0.getOpcode() == ISD::LOAD) { 1285 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1286 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1287 LN0->getAddressingMode() == ISD::UNINDEXED && 1288 N0.hasOneUse()) { 1289 MVT::ValueType EVT, LoadedVT; 1290 if (N1C->getValue() == 255) 1291 EVT = MVT::i8; 1292 else if (N1C->getValue() == 65535) 1293 EVT = MVT::i16; 1294 else if (N1C->getValue() == ~0U) 1295 EVT = MVT::i32; 1296 else 1297 EVT = MVT::Other; 1298 1299 LoadedVT = LN0->getLoadedVT(); 1300 if (EVT != MVT::Other && LoadedVT > EVT && 1301 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1302 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1303 // For big endian targets, we need to add an offset to the pointer to 1304 // load the correct bytes. For little endian systems, we merely need to 1305 // read fewer bytes from the same pointer. 1306 unsigned PtrOff = 1307 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1308 SDOperand NewPtr = LN0->getBasePtr(); 1309 if (!TLI.isLittleEndian()) 1310 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1311 DAG.getConstant(PtrOff, PtrType)); 1312 AddToWorkList(NewPtr.Val); 1313 SDOperand Load = 1314 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1315 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT); 1316 AddToWorkList(N); 1317 CombineTo(N0.Val, Load, Load.getValue(1)); 1318 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1319 } 1320 } 1321 } 1322 1323 return SDOperand(); 1324} 1325 1326SDOperand DAGCombiner::visitOR(SDNode *N) { 1327 SDOperand N0 = N->getOperand(0); 1328 SDOperand N1 = N->getOperand(1); 1329 SDOperand LL, LR, RL, RR, CC0, CC1; 1330 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1331 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1332 MVT::ValueType VT = N1.getValueType(); 1333 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1334 1335 // fold (or c1, c2) -> c1|c2 1336 if (N0C && N1C) 1337 return DAG.getNode(ISD::OR, VT, N0, N1); 1338 // canonicalize constant to RHS 1339 if (N0C && !N1C) 1340 return DAG.getNode(ISD::OR, VT, N1, N0); 1341 // fold (or x, 0) -> x 1342 if (N1C && N1C->isNullValue()) 1343 return N0; 1344 // fold (or x, -1) -> -1 1345 if (N1C && N1C->isAllOnesValue()) 1346 return N1; 1347 // fold (or x, c) -> c iff (x & ~c) == 0 1348 if (N1C && 1349 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1350 return N1; 1351 // reassociate or 1352 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1353 if (ROR.Val != 0) 1354 return ROR; 1355 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1356 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1357 isa<ConstantSDNode>(N0.getOperand(1))) { 1358 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1359 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1360 N1), 1361 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1362 } 1363 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1364 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1365 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1366 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1367 1368 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1369 MVT::isInteger(LL.getValueType())) { 1370 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1371 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1372 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1373 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1374 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1375 AddToWorkList(ORNode.Val); 1376 return DAG.getSetCC(VT, ORNode, LR, Op1); 1377 } 1378 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1379 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1380 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1381 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1382 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1383 AddToWorkList(ANDNode.Val); 1384 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1385 } 1386 } 1387 // canonicalize equivalent to ll == rl 1388 if (LL == RR && LR == RL) { 1389 Op1 = ISD::getSetCCSwappedOperands(Op1); 1390 std::swap(RL, RR); 1391 } 1392 if (LL == RL && LR == RR) { 1393 bool isInteger = MVT::isInteger(LL.getValueType()); 1394 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1395 if (Result != ISD::SETCC_INVALID) 1396 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1397 } 1398 } 1399 1400 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1401 if (N0.getOpcode() == N1.getOpcode()) { 1402 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1403 if (Tmp.Val) return Tmp; 1404 } 1405 1406 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1407 if (N0.getOpcode() == ISD::AND && 1408 N1.getOpcode() == ISD::AND && 1409 N0.getOperand(1).getOpcode() == ISD::Constant && 1410 N1.getOperand(1).getOpcode() == ISD::Constant && 1411 // Don't increase # computations. 1412 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1413 // We can only do this xform if we know that bits from X that are set in C2 1414 // but not in C1 are already zero. Likewise for Y. 1415 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1416 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1417 1418 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1419 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1420 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1421 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1422 } 1423 } 1424 1425 1426 // See if this is some rotate idiom. 1427 if (SDNode *Rot = MatchRotate(N0, N1)) 1428 return SDOperand(Rot, 0); 1429 1430 return SDOperand(); 1431} 1432 1433 1434/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1435static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1436 if (Op.getOpcode() == ISD::AND) { 1437 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1438 Mask = Op.getOperand(1); 1439 Op = Op.getOperand(0); 1440 } else { 1441 return false; 1442 } 1443 } 1444 1445 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1446 Shift = Op; 1447 return true; 1448 } 1449 return false; 1450} 1451 1452 1453// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1454// idioms for rotate, and if the target supports rotation instructions, generate 1455// a rot[lr]. 1456SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1457 // Must be a legal type. Expanded an promoted things won't work with rotates. 1458 MVT::ValueType VT = LHS.getValueType(); 1459 if (!TLI.isTypeLegal(VT)) return 0; 1460 1461 // The target must have at least one rotate flavor. 1462 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1463 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1464 if (!HasROTL && !HasROTR) return 0; 1465 1466 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1467 SDOperand LHSShift; // The shift. 1468 SDOperand LHSMask; // AND value if any. 1469 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1470 return 0; // Not part of a rotate. 1471 1472 SDOperand RHSShift; // The shift. 1473 SDOperand RHSMask; // AND value if any. 1474 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1475 return 0; // Not part of a rotate. 1476 1477 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1478 return 0; // Not shifting the same value. 1479 1480 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1481 return 0; // Shifts must disagree. 1482 1483 // Canonicalize shl to left side in a shl/srl pair. 1484 if (RHSShift.getOpcode() == ISD::SHL) { 1485 std::swap(LHS, RHS); 1486 std::swap(LHSShift, RHSShift); 1487 std::swap(LHSMask , RHSMask ); 1488 } 1489 1490 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1491 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1492 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1493 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1494 1495 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1496 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1497 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1498 RHSShiftAmt.getOpcode() == ISD::Constant) { 1499 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1500 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1501 if ((LShVal + RShVal) != OpSizeInBits) 1502 return 0; 1503 1504 SDOperand Rot; 1505 if (HasROTL) 1506 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1507 else 1508 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1509 1510 // If there is an AND of either shifted operand, apply it to the result. 1511 if (LHSMask.Val || RHSMask.Val) { 1512 uint64_t Mask = MVT::getIntVTBitMask(VT); 1513 1514 if (LHSMask.Val) { 1515 uint64_t RHSBits = (1ULL << LShVal)-1; 1516 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1517 } 1518 if (RHSMask.Val) { 1519 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1520 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1521 } 1522 1523 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1524 } 1525 1526 return Rot.Val; 1527 } 1528 1529 // If there is a mask here, and we have a variable shift, we can't be sure 1530 // that we're masking out the right stuff. 1531 if (LHSMask.Val || RHSMask.Val) 1532 return 0; 1533 1534 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1535 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1536 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1537 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1538 if (ConstantSDNode *SUBC = 1539 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1540 if (SUBC->getValue() == OpSizeInBits) 1541 if (HasROTL) 1542 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1543 else 1544 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1545 } 1546 } 1547 1548 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1549 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1550 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1551 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1552 if (ConstantSDNode *SUBC = 1553 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1554 if (SUBC->getValue() == OpSizeInBits) 1555 if (HasROTL) 1556 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1557 else 1558 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1559 } 1560 } 1561 1562 // Look for sign/zext/any-extended cases: 1563 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1564 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1565 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1566 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1567 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1568 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1569 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1570 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1571 if (RExtOp0.getOpcode() == ISD::SUB && 1572 RExtOp0.getOperand(1) == LExtOp0) { 1573 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1574 // (rotr x, y) 1575 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1576 // (rotl x, (sub 32, y)) 1577 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1578 if (SUBC->getValue() == OpSizeInBits) { 1579 if (HasROTL) 1580 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1581 else 1582 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1583 } 1584 } 1585 } else if (LExtOp0.getOpcode() == ISD::SUB && 1586 RExtOp0 == LExtOp0.getOperand(1)) { 1587 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1588 // (rotl x, y) 1589 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1590 // (rotr x, (sub 32, y)) 1591 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 1592 if (SUBC->getValue() == OpSizeInBits) { 1593 if (HasROTL) 1594 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 1595 else 1596 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1597 } 1598 } 1599 } 1600 } 1601 1602 return 0; 1603} 1604 1605 1606SDOperand DAGCombiner::visitXOR(SDNode *N) { 1607 SDOperand N0 = N->getOperand(0); 1608 SDOperand N1 = N->getOperand(1); 1609 SDOperand LHS, RHS, CC; 1610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1612 MVT::ValueType VT = N0.getValueType(); 1613 1614 // fold (xor c1, c2) -> c1^c2 1615 if (N0C && N1C) 1616 return DAG.getNode(ISD::XOR, VT, N0, N1); 1617 // canonicalize constant to RHS 1618 if (N0C && !N1C) 1619 return DAG.getNode(ISD::XOR, VT, N1, N0); 1620 // fold (xor x, 0) -> x 1621 if (N1C && N1C->isNullValue()) 1622 return N0; 1623 // reassociate xor 1624 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1625 if (RXOR.Val != 0) 1626 return RXOR; 1627 // fold !(x cc y) -> (x !cc y) 1628 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1629 bool isInt = MVT::isInteger(LHS.getValueType()); 1630 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1631 isInt); 1632 if (N0.getOpcode() == ISD::SETCC) 1633 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1634 if (N0.getOpcode() == ISD::SELECT_CC) 1635 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1636 assert(0 && "Unhandled SetCC Equivalent!"); 1637 abort(); 1638 } 1639 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1640 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 1641 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1642 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1643 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1644 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1645 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1646 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1647 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1648 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1649 } 1650 } 1651 // fold !(x or y) -> (!x and !y) iff x or y are constants 1652 if (N1C && N1C->isAllOnesValue() && 1653 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1654 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1655 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1656 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1657 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1658 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1659 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1660 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1661 } 1662 } 1663 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1664 if (N1C && N0.getOpcode() == ISD::XOR) { 1665 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1666 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1667 if (N00C) 1668 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1669 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1670 if (N01C) 1671 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1672 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1673 } 1674 // fold (xor x, x) -> 0 1675 if (N0 == N1) { 1676 if (!MVT::isVector(VT)) { 1677 return DAG.getConstant(0, VT); 1678 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1679 // Produce a vector of zeros. 1680 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1681 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1682 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1683 } 1684 } 1685 1686 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1687 if (N0.getOpcode() == N1.getOpcode()) { 1688 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1689 if (Tmp.Val) return Tmp; 1690 } 1691 1692 // Simplify the expression using non-local knowledge. 1693 if (!MVT::isVector(VT) && 1694 SimplifyDemandedBits(SDOperand(N, 0))) 1695 return SDOperand(N, 0); 1696 1697 return SDOperand(); 1698} 1699 1700SDOperand DAGCombiner::visitSHL(SDNode *N) { 1701 SDOperand N0 = N->getOperand(0); 1702 SDOperand N1 = N->getOperand(1); 1703 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1704 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1705 MVT::ValueType VT = N0.getValueType(); 1706 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1707 1708 // fold (shl c1, c2) -> c1<<c2 1709 if (N0C && N1C) 1710 return DAG.getNode(ISD::SHL, VT, N0, N1); 1711 // fold (shl 0, x) -> 0 1712 if (N0C && N0C->isNullValue()) 1713 return N0; 1714 // fold (shl x, c >= size(x)) -> undef 1715 if (N1C && N1C->getValue() >= OpSizeInBits) 1716 return DAG.getNode(ISD::UNDEF, VT); 1717 // fold (shl x, 0) -> x 1718 if (N1C && N1C->isNullValue()) 1719 return N0; 1720 // if (shl x, c) is known to be zero, return 0 1721 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1722 return DAG.getConstant(0, VT); 1723 if (SimplifyDemandedBits(SDOperand(N, 0))) 1724 return SDOperand(N, 0); 1725 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1726 if (N1C && N0.getOpcode() == ISD::SHL && 1727 N0.getOperand(1).getOpcode() == ISD::Constant) { 1728 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1729 uint64_t c2 = N1C->getValue(); 1730 if (c1 + c2 > OpSizeInBits) 1731 return DAG.getConstant(0, VT); 1732 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1733 DAG.getConstant(c1 + c2, N1.getValueType())); 1734 } 1735 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1736 // (srl (and x, -1 << c1), c1-c2) 1737 if (N1C && N0.getOpcode() == ISD::SRL && 1738 N0.getOperand(1).getOpcode() == ISD::Constant) { 1739 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1740 uint64_t c2 = N1C->getValue(); 1741 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1742 DAG.getConstant(~0ULL << c1, VT)); 1743 if (c2 > c1) 1744 return DAG.getNode(ISD::SHL, VT, Mask, 1745 DAG.getConstant(c2-c1, N1.getValueType())); 1746 else 1747 return DAG.getNode(ISD::SRL, VT, Mask, 1748 DAG.getConstant(c1-c2, N1.getValueType())); 1749 } 1750 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1751 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1752 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1753 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1754 return SDOperand(); 1755} 1756 1757SDOperand DAGCombiner::visitSRA(SDNode *N) { 1758 SDOperand N0 = N->getOperand(0); 1759 SDOperand N1 = N->getOperand(1); 1760 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1761 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1762 MVT::ValueType VT = N0.getValueType(); 1763 1764 // fold (sra c1, c2) -> c1>>c2 1765 if (N0C && N1C) 1766 return DAG.getNode(ISD::SRA, VT, N0, N1); 1767 // fold (sra 0, x) -> 0 1768 if (N0C && N0C->isNullValue()) 1769 return N0; 1770 // fold (sra -1, x) -> -1 1771 if (N0C && N0C->isAllOnesValue()) 1772 return N0; 1773 // fold (sra x, c >= size(x)) -> undef 1774 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1775 return DAG.getNode(ISD::UNDEF, VT); 1776 // fold (sra x, 0) -> x 1777 if (N1C && N1C->isNullValue()) 1778 return N0; 1779 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1780 // sext_inreg. 1781 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1782 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1783 MVT::ValueType EVT; 1784 switch (LowBits) { 1785 default: EVT = MVT::Other; break; 1786 case 1: EVT = MVT::i1; break; 1787 case 8: EVT = MVT::i8; break; 1788 case 16: EVT = MVT::i16; break; 1789 case 32: EVT = MVT::i32; break; 1790 } 1791 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1792 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1793 DAG.getValueType(EVT)); 1794 } 1795 1796 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1797 if (N1C && N0.getOpcode() == ISD::SRA) { 1798 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1799 unsigned Sum = N1C->getValue() + C1->getValue(); 1800 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1801 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1802 DAG.getConstant(Sum, N1C->getValueType(0))); 1803 } 1804 } 1805 1806 // Simplify, based on bits shifted out of the LHS. 1807 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1808 return SDOperand(N, 0); 1809 1810 1811 // If the sign bit is known to be zero, switch this to a SRL. 1812 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1813 return DAG.getNode(ISD::SRL, VT, N0, N1); 1814 return SDOperand(); 1815} 1816 1817SDOperand DAGCombiner::visitSRL(SDNode *N) { 1818 SDOperand N0 = N->getOperand(0); 1819 SDOperand N1 = N->getOperand(1); 1820 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1821 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1822 MVT::ValueType VT = N0.getValueType(); 1823 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1824 1825 // fold (srl c1, c2) -> c1 >>u c2 1826 if (N0C && N1C) 1827 return DAG.getNode(ISD::SRL, VT, N0, N1); 1828 // fold (srl 0, x) -> 0 1829 if (N0C && N0C->isNullValue()) 1830 return N0; 1831 // fold (srl x, c >= size(x)) -> undef 1832 if (N1C && N1C->getValue() >= OpSizeInBits) 1833 return DAG.getNode(ISD::UNDEF, VT); 1834 // fold (srl x, 0) -> x 1835 if (N1C && N1C->isNullValue()) 1836 return N0; 1837 // if (srl x, c) is known to be zero, return 0 1838 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1839 return DAG.getConstant(0, VT); 1840 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1841 if (N1C && N0.getOpcode() == ISD::SRL && 1842 N0.getOperand(1).getOpcode() == ISD::Constant) { 1843 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1844 uint64_t c2 = N1C->getValue(); 1845 if (c1 + c2 > OpSizeInBits) 1846 return DAG.getConstant(0, VT); 1847 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1848 DAG.getConstant(c1 + c2, N1.getValueType())); 1849 } 1850 1851 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1852 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1853 // Shifting in all undef bits? 1854 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1855 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1856 return DAG.getNode(ISD::UNDEF, VT); 1857 1858 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1859 AddToWorkList(SmallShift.Val); 1860 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1861 } 1862 1863 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 1864 // bit, which is unmodified by sra. 1865 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 1866 if (N0.getOpcode() == ISD::SRA) 1867 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 1868 } 1869 1870 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1871 if (N1C && N0.getOpcode() == ISD::CTLZ && 1872 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1873 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1874 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1875 1876 // If any of the input bits are KnownOne, then the input couldn't be all 1877 // zeros, thus the result of the srl will always be zero. 1878 if (KnownOne) return DAG.getConstant(0, VT); 1879 1880 // If all of the bits input the to ctlz node are known to be zero, then 1881 // the result of the ctlz is "32" and the result of the shift is one. 1882 uint64_t UnknownBits = ~KnownZero & Mask; 1883 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1884 1885 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1886 if ((UnknownBits & (UnknownBits-1)) == 0) { 1887 // Okay, we know that only that the single bit specified by UnknownBits 1888 // could be set on input to the CTLZ node. If this bit is set, the SRL 1889 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1890 // to an SRL,XOR pair, which is likely to simplify more. 1891 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1892 SDOperand Op = N0.getOperand(0); 1893 if (ShAmt) { 1894 Op = DAG.getNode(ISD::SRL, VT, Op, 1895 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1896 AddToWorkList(Op.Val); 1897 } 1898 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1899 } 1900 } 1901 1902 return SDOperand(); 1903} 1904 1905SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1906 SDOperand N0 = N->getOperand(0); 1907 MVT::ValueType VT = N->getValueType(0); 1908 1909 // fold (ctlz c1) -> c2 1910 if (isa<ConstantSDNode>(N0)) 1911 return DAG.getNode(ISD::CTLZ, VT, N0); 1912 return SDOperand(); 1913} 1914 1915SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1916 SDOperand N0 = N->getOperand(0); 1917 MVT::ValueType VT = N->getValueType(0); 1918 1919 // fold (cttz c1) -> c2 1920 if (isa<ConstantSDNode>(N0)) 1921 return DAG.getNode(ISD::CTTZ, VT, N0); 1922 return SDOperand(); 1923} 1924 1925SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1926 SDOperand N0 = N->getOperand(0); 1927 MVT::ValueType VT = N->getValueType(0); 1928 1929 // fold (ctpop c1) -> c2 1930 if (isa<ConstantSDNode>(N0)) 1931 return DAG.getNode(ISD::CTPOP, VT, N0); 1932 return SDOperand(); 1933} 1934 1935SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1936 SDOperand N0 = N->getOperand(0); 1937 SDOperand N1 = N->getOperand(1); 1938 SDOperand N2 = N->getOperand(2); 1939 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1941 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1942 MVT::ValueType VT = N->getValueType(0); 1943 1944 // fold select C, X, X -> X 1945 if (N1 == N2) 1946 return N1; 1947 // fold select true, X, Y -> X 1948 if (N0C && !N0C->isNullValue()) 1949 return N1; 1950 // fold select false, X, Y -> Y 1951 if (N0C && N0C->isNullValue()) 1952 return N2; 1953 // fold select C, 1, X -> C | X 1954 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1955 return DAG.getNode(ISD::OR, VT, N0, N2); 1956 // fold select C, 0, X -> ~C & X 1957 // FIXME: this should check for C type == X type, not i1? 1958 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1959 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1960 AddToWorkList(XORNode.Val); 1961 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1962 } 1963 // fold select C, X, 1 -> ~C | X 1964 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1965 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1966 AddToWorkList(XORNode.Val); 1967 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1968 } 1969 // fold select C, X, 0 -> C & X 1970 // FIXME: this should check for C type == X type, not i1? 1971 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1972 return DAG.getNode(ISD::AND, VT, N0, N1); 1973 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1974 if (MVT::i1 == VT && N0 == N1) 1975 return DAG.getNode(ISD::OR, VT, N0, N2); 1976 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1977 if (MVT::i1 == VT && N0 == N2) 1978 return DAG.getNode(ISD::AND, VT, N0, N1); 1979 1980 // If we can fold this based on the true/false value, do so. 1981 if (SimplifySelectOps(N, N1, N2)) 1982 return SDOperand(N, 0); // Don't revisit N. 1983 1984 // fold selects based on a setcc into other things, such as min/max/abs 1985 if (N0.getOpcode() == ISD::SETCC) 1986 // FIXME: 1987 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1988 // having to say they don't support SELECT_CC on every type the DAG knows 1989 // about, since there is no way to mark an opcode illegal at all value types 1990 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1991 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1992 N1, N2, N0.getOperand(2)); 1993 else 1994 return SimplifySelect(N0, N1, N2); 1995 return SDOperand(); 1996} 1997 1998SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1999 SDOperand N0 = N->getOperand(0); 2000 SDOperand N1 = N->getOperand(1); 2001 SDOperand N2 = N->getOperand(2); 2002 SDOperand N3 = N->getOperand(3); 2003 SDOperand N4 = N->getOperand(4); 2004 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2005 2006 // fold select_cc lhs, rhs, x, x, cc -> x 2007 if (N2 == N3) 2008 return N2; 2009 2010 // Determine if the condition we're dealing with is constant 2011 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2012 if (SCC.Val) AddToWorkList(SCC.Val); 2013 2014 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2015 if (SCCC->getValue()) 2016 return N2; // cond always true -> true val 2017 else 2018 return N3; // cond always false -> false val 2019 } 2020 2021 // Fold to a simpler select_cc 2022 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2023 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2024 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2025 SCC.getOperand(2)); 2026 2027 // If we can fold this based on the true/false value, do so. 2028 if (SimplifySelectOps(N, N2, N3)) 2029 return SDOperand(N, 0); // Don't revisit N. 2030 2031 // fold select_cc into other things, such as min/max/abs 2032 return SimplifySelectCC(N0, N1, N2, N3, CC); 2033} 2034 2035SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2036 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2037 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2038} 2039 2040SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2041 SDOperand N0 = N->getOperand(0); 2042 MVT::ValueType VT = N->getValueType(0); 2043 2044 // fold (sext c1) -> c1 2045 if (isa<ConstantSDNode>(N0)) 2046 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2047 2048 // fold (sext (sext x)) -> (sext x) 2049 // fold (sext (aext x)) -> (sext x) 2050 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2051 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2052 2053 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2054 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2055 if (N0.getOpcode() == ISD::TRUNCATE) { 2056 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2057 if (NarrowLoad.Val) { 2058 if (NarrowLoad.Val != N0.Val) 2059 CombineTo(N0.Val, NarrowLoad); 2060 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2061 } 2062 } 2063 2064 // See if the value being truncated is already sign extended. If so, just 2065 // eliminate the trunc/sext pair. 2066 if (N0.getOpcode() == ISD::TRUNCATE) { 2067 SDOperand Op = N0.getOperand(0); 2068 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2069 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2070 unsigned DestBits = MVT::getSizeInBits(VT); 2071 unsigned NumSignBits = TLI.ComputeNumSignBits(Op); 2072 2073 if (OpBits == DestBits) { 2074 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2075 // bits, it is already ready. 2076 if (NumSignBits > DestBits-MidBits) 2077 return Op; 2078 } else if (OpBits < DestBits) { 2079 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2080 // bits, just sext from i32. 2081 if (NumSignBits > OpBits-MidBits) 2082 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2083 } else { 2084 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2085 // bits, just truncate to i32. 2086 if (NumSignBits > OpBits-MidBits) 2087 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2088 } 2089 2090 // fold (sext (truncate x)) -> (sextinreg x). 2091 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2092 N0.getValueType())) { 2093 if (Op.getValueType() < VT) 2094 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2095 else if (Op.getValueType() > VT) 2096 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2097 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2098 DAG.getValueType(N0.getValueType())); 2099 } 2100 } 2101 2102 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2103 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2104 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2105 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2106 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2107 LN0->getBasePtr(), LN0->getSrcValue(), 2108 LN0->getSrcValueOffset(), 2109 N0.getValueType()); 2110 CombineTo(N, ExtLoad); 2111 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2112 ExtLoad.getValue(1)); 2113 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2114 } 2115 2116 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2117 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2118 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2119 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2120 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2121 MVT::ValueType EVT = LN0->getLoadedVT(); 2122 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2123 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2124 LN0->getBasePtr(), LN0->getSrcValue(), 2125 LN0->getSrcValueOffset(), EVT); 2126 CombineTo(N, ExtLoad); 2127 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2128 ExtLoad.getValue(1)); 2129 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2130 } 2131 } 2132 2133 return SDOperand(); 2134} 2135 2136SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2137 SDOperand N0 = N->getOperand(0); 2138 MVT::ValueType VT = N->getValueType(0); 2139 2140 // fold (zext c1) -> c1 2141 if (isa<ConstantSDNode>(N0)) 2142 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2143 // fold (zext (zext x)) -> (zext x) 2144 // fold (zext (aext x)) -> (zext x) 2145 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2146 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2147 2148 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2149 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2150 if (N0.getOpcode() == ISD::TRUNCATE) { 2151 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2152 if (NarrowLoad.Val) { 2153 if (NarrowLoad.Val != N0.Val) 2154 CombineTo(N0.Val, NarrowLoad); 2155 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2156 } 2157 } 2158 2159 // fold (zext (truncate x)) -> (and x, mask) 2160 if (N0.getOpcode() == ISD::TRUNCATE && 2161 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2162 SDOperand Op = N0.getOperand(0); 2163 if (Op.getValueType() < VT) { 2164 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2165 } else if (Op.getValueType() > VT) { 2166 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2167 } 2168 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2169 } 2170 2171 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2172 if (N0.getOpcode() == ISD::AND && 2173 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2174 N0.getOperand(1).getOpcode() == ISD::Constant) { 2175 SDOperand X = N0.getOperand(0).getOperand(0); 2176 if (X.getValueType() < VT) { 2177 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2178 } else if (X.getValueType() > VT) { 2179 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2180 } 2181 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2182 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2183 } 2184 2185 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2186 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2187 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2188 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2189 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2190 LN0->getBasePtr(), LN0->getSrcValue(), 2191 LN0->getSrcValueOffset(), 2192 N0.getValueType()); 2193 CombineTo(N, ExtLoad); 2194 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2195 ExtLoad.getValue(1)); 2196 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2197 } 2198 2199 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2200 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2201 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2202 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2203 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2204 MVT::ValueType EVT = LN0->getLoadedVT(); 2205 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2206 LN0->getBasePtr(), LN0->getSrcValue(), 2207 LN0->getSrcValueOffset(), EVT); 2208 CombineTo(N, ExtLoad); 2209 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2210 ExtLoad.getValue(1)); 2211 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2212 } 2213 return SDOperand(); 2214} 2215 2216SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2217 SDOperand N0 = N->getOperand(0); 2218 MVT::ValueType VT = N->getValueType(0); 2219 2220 // fold (aext c1) -> c1 2221 if (isa<ConstantSDNode>(N0)) 2222 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2223 // fold (aext (aext x)) -> (aext x) 2224 // fold (aext (zext x)) -> (zext x) 2225 // fold (aext (sext x)) -> (sext x) 2226 if (N0.getOpcode() == ISD::ANY_EXTEND || 2227 N0.getOpcode() == ISD::ZERO_EXTEND || 2228 N0.getOpcode() == ISD::SIGN_EXTEND) 2229 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2230 2231 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2232 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2233 if (N0.getOpcode() == ISD::TRUNCATE) { 2234 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2235 if (NarrowLoad.Val) { 2236 if (NarrowLoad.Val != N0.Val) 2237 CombineTo(N0.Val, NarrowLoad); 2238 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2239 } 2240 } 2241 2242 // fold (aext (truncate x)) 2243 if (N0.getOpcode() == ISD::TRUNCATE) { 2244 SDOperand TruncOp = N0.getOperand(0); 2245 if (TruncOp.getValueType() == VT) 2246 return TruncOp; // x iff x size == zext size. 2247 if (TruncOp.getValueType() > VT) 2248 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2249 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2250 } 2251 2252 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2253 if (N0.getOpcode() == ISD::AND && 2254 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2255 N0.getOperand(1).getOpcode() == ISD::Constant) { 2256 SDOperand X = N0.getOperand(0).getOperand(0); 2257 if (X.getValueType() < VT) { 2258 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2259 } else if (X.getValueType() > VT) { 2260 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2261 } 2262 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2263 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2264 } 2265 2266 // fold (aext (load x)) -> (aext (truncate (extload x))) 2267 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2268 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2269 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2270 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2271 LN0->getBasePtr(), LN0->getSrcValue(), 2272 LN0->getSrcValueOffset(), 2273 N0.getValueType()); 2274 CombineTo(N, ExtLoad); 2275 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2276 ExtLoad.getValue(1)); 2277 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2278 } 2279 2280 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2281 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2282 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2283 if (N0.getOpcode() == ISD::LOAD && 2284 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2285 N0.hasOneUse()) { 2286 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2287 MVT::ValueType EVT = LN0->getLoadedVT(); 2288 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2289 LN0->getChain(), LN0->getBasePtr(), 2290 LN0->getSrcValue(), 2291 LN0->getSrcValueOffset(), EVT); 2292 CombineTo(N, ExtLoad); 2293 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2294 ExtLoad.getValue(1)); 2295 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2296 } 2297 return SDOperand(); 2298} 2299 2300/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2301/// bits and then truncated to a narrower type and where N is a multiple 2302/// of number of bits of the narrower type, transform it to a narrower load 2303/// from address + N / num of bits of new type. If the result is to be 2304/// extended, also fold the extension to form a extending load. 2305SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2306 unsigned Opc = N->getOpcode(); 2307 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2308 SDOperand N0 = N->getOperand(0); 2309 MVT::ValueType VT = N->getValueType(0); 2310 MVT::ValueType EVT = N->getValueType(0); 2311 2312 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2313 // extended to VT. 2314 if (Opc == ISD::SIGN_EXTEND_INREG) { 2315 ExtType = ISD::SEXTLOAD; 2316 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2317 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2318 return SDOperand(); 2319 } 2320 2321 unsigned EVTBits = MVT::getSizeInBits(EVT); 2322 unsigned ShAmt = 0; 2323 bool CombineSRL = false; 2324 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2325 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2326 ShAmt = N01->getValue(); 2327 // Is the shift amount a multiple of size of VT? 2328 if ((ShAmt & (EVTBits-1)) == 0) { 2329 N0 = N0.getOperand(0); 2330 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2331 return SDOperand(); 2332 CombineSRL = true; 2333 } 2334 } 2335 } 2336 2337 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2338 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2339 // zero extended form: by shrinking the load, we lose track of the fact 2340 // that it is already zero extended. 2341 // FIXME: This should be reevaluated. 2342 VT != MVT::i1) { 2343 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 2344 "Cannot truncate to larger type!"); 2345 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2346 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2347 // For big endian targets, we need to adjust the offset to the pointer to 2348 // load the correct bytes. 2349 if (!TLI.isLittleEndian()) 2350 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; 2351 uint64_t PtrOff = ShAmt / 8; 2352 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2353 DAG.getConstant(PtrOff, PtrType)); 2354 AddToWorkList(NewPtr.Val); 2355 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 2356 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 2357 LN0->getSrcValue(), LN0->getSrcValueOffset()) 2358 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 2359 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT); 2360 AddToWorkList(N); 2361 if (CombineSRL) { 2362 std::vector<SDNode*> NowDead; 2363 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead); 2364 CombineTo(N->getOperand(0).Val, Load); 2365 } else 2366 CombineTo(N0.Val, Load, Load.getValue(1)); 2367 if (ShAmt) { 2368 if (Opc == ISD::SIGN_EXTEND_INREG) 2369 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 2370 else 2371 return DAG.getNode(Opc, VT, Load); 2372 } 2373 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2374 } 2375 2376 return SDOperand(); 2377} 2378 2379 2380SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2381 SDOperand N0 = N->getOperand(0); 2382 SDOperand N1 = N->getOperand(1); 2383 MVT::ValueType VT = N->getValueType(0); 2384 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2385 unsigned EVTBits = MVT::getSizeInBits(EVT); 2386 2387 // fold (sext_in_reg c1) -> c1 2388 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2389 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2390 2391 // If the input is already sign extended, just drop the extension. 2392 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2393 return N0; 2394 2395 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2396 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2397 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2398 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2399 } 2400 2401 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 2402 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2403 return DAG.getZeroExtendInReg(N0, EVT); 2404 2405 // fold (sext_in_reg (load x)) -> (smaller sextload x) 2406 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 2407 SDOperand NarrowLoad = ReduceLoadWidth(N); 2408 if (NarrowLoad.Val) 2409 return NarrowLoad; 2410 2411 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2412 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2413 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2414 if (N0.getOpcode() == ISD::SRL) { 2415 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2416 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2417 // We can turn this into an SRA iff the input to the SRL is already sign 2418 // extended enough. 2419 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 2420 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2421 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2422 } 2423 } 2424 2425 // fold (sext_inreg (extload x)) -> (sextload x) 2426 if (ISD::isEXTLoad(N0.Val) && 2427 ISD::isUNINDEXEDLoad(N0.Val) && 2428 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2429 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2430 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2431 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2432 LN0->getBasePtr(), LN0->getSrcValue(), 2433 LN0->getSrcValueOffset(), EVT); 2434 CombineTo(N, ExtLoad); 2435 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2436 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2437 } 2438 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2439 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2440 N0.hasOneUse() && 2441 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2442 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2443 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2444 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2445 LN0->getBasePtr(), LN0->getSrcValue(), 2446 LN0->getSrcValueOffset(), EVT); 2447 CombineTo(N, ExtLoad); 2448 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2449 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2450 } 2451 return SDOperand(); 2452} 2453 2454SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2455 SDOperand N0 = N->getOperand(0); 2456 MVT::ValueType VT = N->getValueType(0); 2457 2458 // noop truncate 2459 if (N0.getValueType() == N->getValueType(0)) 2460 return N0; 2461 // fold (truncate c1) -> c1 2462 if (isa<ConstantSDNode>(N0)) 2463 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2464 // fold (truncate (truncate x)) -> (truncate x) 2465 if (N0.getOpcode() == ISD::TRUNCATE) 2466 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2467 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2468 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2469 N0.getOpcode() == ISD::ANY_EXTEND) { 2470 if (N0.getOperand(0).getValueType() < VT) 2471 // if the source is smaller than the dest, we still need an extend 2472 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2473 else if (N0.getOperand(0).getValueType() > VT) 2474 // if the source is larger than the dest, than we just need the truncate 2475 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2476 else 2477 // if the source and dest are the same type, we can drop both the extend 2478 // and the truncate 2479 return N0.getOperand(0); 2480 } 2481 2482 // fold (truncate (load x)) -> (smaller load x) 2483 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 2484 return ReduceLoadWidth(N); 2485} 2486 2487SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2488 SDOperand N0 = N->getOperand(0); 2489 MVT::ValueType VT = N->getValueType(0); 2490 2491 // If the input is a constant, let getNode() fold it. 2492 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2493 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2494 if (Res.Val != N) return Res; 2495 } 2496 2497 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2498 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2499 2500 // fold (conv (load x)) -> (load (conv*)x) 2501 // FIXME: These xforms need to know that the resultant load doesn't need a 2502 // higher alignment than the original! 2503 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) { 2504 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2505 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 2506 LN0->getSrcValue(), LN0->getSrcValueOffset()); 2507 AddToWorkList(N); 2508 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2509 Load.getValue(1)); 2510 return Load; 2511 } 2512 2513 return SDOperand(); 2514} 2515 2516SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2517 SDOperand N0 = N->getOperand(0); 2518 MVT::ValueType VT = N->getValueType(0); 2519 2520 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2521 // First check to see if this is all constant. 2522 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2523 VT == MVT::Vector) { 2524 bool isSimple = true; 2525 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2526 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2527 N0.getOperand(i).getOpcode() != ISD::Constant && 2528 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2529 isSimple = false; 2530 break; 2531 } 2532 2533 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2534 if (isSimple && !MVT::isVector(DestEltVT)) { 2535 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2536 } 2537 } 2538 2539 return SDOperand(); 2540} 2541 2542/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2543/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2544/// destination element value type. 2545SDOperand DAGCombiner:: 2546ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2547 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2548 2549 // If this is already the right type, we're done. 2550 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2551 2552 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2553 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2554 2555 // If this is a conversion of N elements of one type to N elements of another 2556 // type, convert each element. This handles FP<->INT cases. 2557 if (SrcBitSize == DstBitSize) { 2558 SmallVector<SDOperand, 8> Ops; 2559 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2560 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2561 AddToWorkList(Ops.back().Val); 2562 } 2563 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2564 Ops.push_back(DAG.getValueType(DstEltVT)); 2565 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2566 } 2567 2568 // Otherwise, we're growing or shrinking the elements. To avoid having to 2569 // handle annoying details of growing/shrinking FP values, we convert them to 2570 // int first. 2571 if (MVT::isFloatingPoint(SrcEltVT)) { 2572 // Convert the input float vector to a int vector where the elements are the 2573 // same sizes. 2574 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2575 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2576 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2577 SrcEltVT = IntVT; 2578 } 2579 2580 // Now we know the input is an integer vector. If the output is a FP type, 2581 // convert to integer first, then to FP of the right size. 2582 if (MVT::isFloatingPoint(DstEltVT)) { 2583 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2584 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2585 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2586 2587 // Next, convert to FP elements of the same size. 2588 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2589 } 2590 2591 // Okay, we know the src/dst types are both integers of differing types. 2592 // Handling growing first. 2593 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2594 if (SrcBitSize < DstBitSize) { 2595 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2596 2597 SmallVector<SDOperand, 8> Ops; 2598 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2599 i += NumInputsPerOutput) { 2600 bool isLE = TLI.isLittleEndian(); 2601 uint64_t NewBits = 0; 2602 bool EltIsUndef = true; 2603 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2604 // Shift the previously computed bits over. 2605 NewBits <<= SrcBitSize; 2606 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2607 if (Op.getOpcode() == ISD::UNDEF) continue; 2608 EltIsUndef = false; 2609 2610 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2611 } 2612 2613 if (EltIsUndef) 2614 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2615 else 2616 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2617 } 2618 2619 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2620 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2621 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2622 } 2623 2624 // Finally, this must be the case where we are shrinking elements: each input 2625 // turns into multiple outputs. 2626 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2627 SmallVector<SDOperand, 8> Ops; 2628 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2629 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2630 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2631 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2632 continue; 2633 } 2634 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2635 2636 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2637 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2638 OpVal >>= DstBitSize; 2639 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2640 } 2641 2642 // For big endian targets, swap the order of the pieces of each element. 2643 if (!TLI.isLittleEndian()) 2644 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2645 } 2646 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2647 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2648 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2649} 2650 2651 2652 2653SDOperand DAGCombiner::visitFADD(SDNode *N) { 2654 SDOperand N0 = N->getOperand(0); 2655 SDOperand N1 = N->getOperand(1); 2656 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2657 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2658 MVT::ValueType VT = N->getValueType(0); 2659 2660 // fold (fadd c1, c2) -> c1+c2 2661 if (N0CFP && N1CFP) 2662 return DAG.getNode(ISD::FADD, VT, N0, N1); 2663 // canonicalize constant to RHS 2664 if (N0CFP && !N1CFP) 2665 return DAG.getNode(ISD::FADD, VT, N1, N0); 2666 // fold (A + (-B)) -> A-B 2667 if (N1.getOpcode() == ISD::FNEG) 2668 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2669 // fold ((-A) + B) -> B-A 2670 if (N0.getOpcode() == ISD::FNEG) 2671 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2672 2673 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 2674 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 2675 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2676 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 2677 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 2678 2679 return SDOperand(); 2680} 2681 2682SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2683 SDOperand N0 = N->getOperand(0); 2684 SDOperand N1 = N->getOperand(1); 2685 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2686 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2687 MVT::ValueType VT = N->getValueType(0); 2688 2689 // fold (fsub c1, c2) -> c1-c2 2690 if (N0CFP && N1CFP) 2691 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2692 // fold (A-(-B)) -> A+B 2693 if (N1.getOpcode() == ISD::FNEG) 2694 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2695 return SDOperand(); 2696} 2697 2698SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2699 SDOperand N0 = N->getOperand(0); 2700 SDOperand N1 = N->getOperand(1); 2701 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2702 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2703 MVT::ValueType VT = N->getValueType(0); 2704 2705 // fold (fmul c1, c2) -> c1*c2 2706 if (N0CFP && N1CFP) 2707 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2708 // canonicalize constant to RHS 2709 if (N0CFP && !N1CFP) 2710 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2711 // fold (fmul X, 2.0) -> (fadd X, X) 2712 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2713 return DAG.getNode(ISD::FADD, VT, N0, N0); 2714 2715 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 2716 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 2717 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2718 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 2719 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 2720 2721 return SDOperand(); 2722} 2723 2724SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2725 SDOperand N0 = N->getOperand(0); 2726 SDOperand N1 = N->getOperand(1); 2727 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2728 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2729 MVT::ValueType VT = N->getValueType(0); 2730 2731 // fold (fdiv c1, c2) -> c1/c2 2732 if (N0CFP && N1CFP) 2733 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2734 return SDOperand(); 2735} 2736 2737SDOperand DAGCombiner::visitFREM(SDNode *N) { 2738 SDOperand N0 = N->getOperand(0); 2739 SDOperand N1 = N->getOperand(1); 2740 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2741 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2742 MVT::ValueType VT = N->getValueType(0); 2743 2744 // fold (frem c1, c2) -> fmod(c1,c2) 2745 if (N0CFP && N1CFP) 2746 return DAG.getNode(ISD::FREM, VT, N0, N1); 2747 return SDOperand(); 2748} 2749 2750SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2751 SDOperand N0 = N->getOperand(0); 2752 SDOperand N1 = N->getOperand(1); 2753 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2754 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2755 MVT::ValueType VT = N->getValueType(0); 2756 2757 if (N0CFP && N1CFP) // Constant fold 2758 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2759 2760 if (N1CFP) { 2761 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2762 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2763 union { 2764 double d; 2765 int64_t i; 2766 } u; 2767 u.d = N1CFP->getValue(); 2768 if (u.i >= 0) 2769 return DAG.getNode(ISD::FABS, VT, N0); 2770 else 2771 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2772 } 2773 2774 // copysign(fabs(x), y) -> copysign(x, y) 2775 // copysign(fneg(x), y) -> copysign(x, y) 2776 // copysign(copysign(x,z), y) -> copysign(x, y) 2777 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2778 N0.getOpcode() == ISD::FCOPYSIGN) 2779 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2780 2781 // copysign(x, abs(y)) -> abs(x) 2782 if (N1.getOpcode() == ISD::FABS) 2783 return DAG.getNode(ISD::FABS, VT, N0); 2784 2785 // copysign(x, copysign(y,z)) -> copysign(x, z) 2786 if (N1.getOpcode() == ISD::FCOPYSIGN) 2787 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2788 2789 // copysign(x, fp_extend(y)) -> copysign(x, y) 2790 // copysign(x, fp_round(y)) -> copysign(x, y) 2791 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2792 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2793 2794 return SDOperand(); 2795} 2796 2797 2798 2799SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2800 SDOperand N0 = N->getOperand(0); 2801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2802 MVT::ValueType VT = N->getValueType(0); 2803 2804 // fold (sint_to_fp c1) -> c1fp 2805 if (N0C) 2806 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2807 return SDOperand(); 2808} 2809 2810SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2811 SDOperand N0 = N->getOperand(0); 2812 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2813 MVT::ValueType VT = N->getValueType(0); 2814 2815 // fold (uint_to_fp c1) -> c1fp 2816 if (N0C) 2817 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2818 return SDOperand(); 2819} 2820 2821SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2822 SDOperand N0 = N->getOperand(0); 2823 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2824 MVT::ValueType VT = N->getValueType(0); 2825 2826 // fold (fp_to_sint c1fp) -> c1 2827 if (N0CFP) 2828 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2829 return SDOperand(); 2830} 2831 2832SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2833 SDOperand N0 = N->getOperand(0); 2834 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2835 MVT::ValueType VT = N->getValueType(0); 2836 2837 // fold (fp_to_uint c1fp) -> c1 2838 if (N0CFP) 2839 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2840 return SDOperand(); 2841} 2842 2843SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2844 SDOperand N0 = N->getOperand(0); 2845 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2846 MVT::ValueType VT = N->getValueType(0); 2847 2848 // fold (fp_round c1fp) -> c1fp 2849 if (N0CFP) 2850 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2851 2852 // fold (fp_round (fp_extend x)) -> x 2853 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2854 return N0.getOperand(0); 2855 2856 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2857 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2858 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2859 AddToWorkList(Tmp.Val); 2860 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2861 } 2862 2863 return SDOperand(); 2864} 2865 2866SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2867 SDOperand N0 = N->getOperand(0); 2868 MVT::ValueType VT = N->getValueType(0); 2869 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2870 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2871 2872 // fold (fp_round_inreg c1fp) -> c1fp 2873 if (N0CFP) { 2874 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2875 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2876 } 2877 return SDOperand(); 2878} 2879 2880SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2881 SDOperand N0 = N->getOperand(0); 2882 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2883 MVT::ValueType VT = N->getValueType(0); 2884 2885 // fold (fp_extend c1fp) -> c1fp 2886 if (N0CFP) 2887 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2888 2889 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2890 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2891 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2892 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2893 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2894 LN0->getBasePtr(), LN0->getSrcValue(), 2895 LN0->getSrcValueOffset(), 2896 N0.getValueType()); 2897 CombineTo(N, ExtLoad); 2898 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2899 ExtLoad.getValue(1)); 2900 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2901 } 2902 2903 2904 return SDOperand(); 2905} 2906 2907SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2908 SDOperand N0 = N->getOperand(0); 2909 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2910 MVT::ValueType VT = N->getValueType(0); 2911 2912 // fold (fneg c1) -> -c1 2913 if (N0CFP) 2914 return DAG.getNode(ISD::FNEG, VT, N0); 2915 // fold (fneg (sub x, y)) -> (sub y, x) 2916 if (N0.getOpcode() == ISD::SUB) 2917 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2918 // fold (fneg (fneg x)) -> x 2919 if (N0.getOpcode() == ISD::FNEG) 2920 return N0.getOperand(0); 2921 return SDOperand(); 2922} 2923 2924SDOperand DAGCombiner::visitFABS(SDNode *N) { 2925 SDOperand N0 = N->getOperand(0); 2926 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2927 MVT::ValueType VT = N->getValueType(0); 2928 2929 // fold (fabs c1) -> fabs(c1) 2930 if (N0CFP) 2931 return DAG.getNode(ISD::FABS, VT, N0); 2932 // fold (fabs (fabs x)) -> (fabs x) 2933 if (N0.getOpcode() == ISD::FABS) 2934 return N->getOperand(0); 2935 // fold (fabs (fneg x)) -> (fabs x) 2936 // fold (fabs (fcopysign x, y)) -> (fabs x) 2937 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2938 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2939 2940 return SDOperand(); 2941} 2942 2943SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2944 SDOperand Chain = N->getOperand(0); 2945 SDOperand N1 = N->getOperand(1); 2946 SDOperand N2 = N->getOperand(2); 2947 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2948 2949 // never taken branch, fold to chain 2950 if (N1C && N1C->isNullValue()) 2951 return Chain; 2952 // unconditional branch 2953 if (N1C && N1C->getValue() == 1) 2954 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2955 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2956 // on the target. 2957 if (N1.getOpcode() == ISD::SETCC && 2958 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2959 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2960 N1.getOperand(0), N1.getOperand(1), N2); 2961 } 2962 return SDOperand(); 2963} 2964 2965// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2966// 2967SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2968 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2969 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2970 2971 // Use SimplifySetCC to simplify SETCC's. 2972 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2973 if (Simp.Val) AddToWorkList(Simp.Val); 2974 2975 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2976 2977 // fold br_cc true, dest -> br dest (unconditional branch) 2978 if (SCCC && SCCC->getValue()) 2979 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2980 N->getOperand(4)); 2981 // fold br_cc false, dest -> unconditional fall through 2982 if (SCCC && SCCC->isNullValue()) 2983 return N->getOperand(0); 2984 2985 // fold to a simpler setcc 2986 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2987 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2988 Simp.getOperand(2), Simp.getOperand(0), 2989 Simp.getOperand(1), N->getOperand(4)); 2990 return SDOperand(); 2991} 2992 2993 2994/// CombineToPreIndexedLoadStore - Try turning a load / store and a 2995/// pre-indexed load / store when the base pointer is a add or subtract 2996/// and it has other uses besides the load / store. After the 2997/// transformation, the new indexed load / store has effectively folded 2998/// the add / subtract in and all of its other uses are redirected to the 2999/// new load / store. 3000bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3001 if (!AfterLegalize) 3002 return false; 3003 3004 bool isLoad = true; 3005 SDOperand Ptr; 3006 MVT::ValueType VT; 3007 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3008 if (LD->getAddressingMode() != ISD::UNINDEXED) 3009 return false; 3010 VT = LD->getLoadedVT(); 3011 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3012 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3013 return false; 3014 Ptr = LD->getBasePtr(); 3015 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3016 if (ST->getAddressingMode() != ISD::UNINDEXED) 3017 return false; 3018 VT = ST->getStoredVT(); 3019 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3020 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3021 return false; 3022 Ptr = ST->getBasePtr(); 3023 isLoad = false; 3024 } else 3025 return false; 3026 3027 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3028 // out. There is no reason to make this a preinc/predec. 3029 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3030 Ptr.Val->hasOneUse()) 3031 return false; 3032 3033 // Ask the target to do addressing mode selection. 3034 SDOperand BasePtr; 3035 SDOperand Offset; 3036 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3037 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3038 return false; 3039 3040 // Try turning it into a pre-indexed load / store except when: 3041 // 1) The base is a frame index. 3042 // 2) If N is a store and the ptr is either the same as or is a 3043 // predecessor of the value being stored. 3044 // 3) Another use of base ptr is a predecessor of N. If ptr is folded 3045 // that would create a cycle. 3046 // 4) All uses are load / store ops that use it as base ptr. 3047 3048 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3049 // (plus the implicit offset) to a register to preinc anyway. 3050 if (isa<FrameIndexSDNode>(BasePtr)) 3051 return false; 3052 3053 // Check #2. 3054 if (!isLoad) { 3055 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3056 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val)) 3057 return false; 3058 } 3059 3060 // Now check for #2 and #3. 3061 bool RealUse = false; 3062 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3063 E = Ptr.Val->use_end(); I != E; ++I) { 3064 SDNode *Use = *I; 3065 if (Use == N) 3066 continue; 3067 if (Use->isPredecessor(N)) 3068 return false; 3069 3070 if (!((Use->getOpcode() == ISD::LOAD && 3071 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3072 (Use->getOpcode() == ISD::STORE) && 3073 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3074 RealUse = true; 3075 } 3076 if (!RealUse) 3077 return false; 3078 3079 SDOperand Result; 3080 if (isLoad) 3081 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3082 else 3083 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3084 ++PreIndexedNodes; 3085 ++NodesCombined; 3086 DOUT << "\nReplacing.4 "; DEBUG(N->dump()); 3087 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3088 DOUT << '\n'; 3089 std::vector<SDNode*> NowDead; 3090 if (isLoad) { 3091 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3092 NowDead); 3093 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3094 NowDead); 3095 } else { 3096 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3097 NowDead); 3098 } 3099 3100 // Nodes can end up on the worklist more than once. Make sure we do 3101 // not process a node that has been replaced. 3102 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3103 removeFromWorkList(NowDead[i]); 3104 // Finally, since the node is now dead, remove it from the graph. 3105 DAG.DeleteNode(N); 3106 3107 // Replace the uses of Ptr with uses of the updated base value. 3108 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3109 NowDead); 3110 removeFromWorkList(Ptr.Val); 3111 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3112 removeFromWorkList(NowDead[i]); 3113 DAG.DeleteNode(Ptr.Val); 3114 3115 return true; 3116} 3117 3118/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3119/// add / sub of the base pointer node into a post-indexed load / store. 3120/// The transformation folded the add / subtract into the new indexed 3121/// load / store effectively and all of its uses are redirected to the 3122/// new load / store. 3123bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3124 if (!AfterLegalize) 3125 return false; 3126 3127 bool isLoad = true; 3128 SDOperand Ptr; 3129 MVT::ValueType VT; 3130 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3131 if (LD->getAddressingMode() != ISD::UNINDEXED) 3132 return false; 3133 VT = LD->getLoadedVT(); 3134 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3135 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3136 return false; 3137 Ptr = LD->getBasePtr(); 3138 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3139 if (ST->getAddressingMode() != ISD::UNINDEXED) 3140 return false; 3141 VT = ST->getStoredVT(); 3142 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3143 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3144 return false; 3145 Ptr = ST->getBasePtr(); 3146 isLoad = false; 3147 } else 3148 return false; 3149 3150 if (Ptr.Val->hasOneUse()) 3151 return false; 3152 3153 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3154 E = Ptr.Val->use_end(); I != E; ++I) { 3155 SDNode *Op = *I; 3156 if (Op == N || 3157 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3158 continue; 3159 3160 SDOperand BasePtr; 3161 SDOperand Offset; 3162 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3163 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3164 if (Ptr == Offset) 3165 std::swap(BasePtr, Offset); 3166 if (Ptr != BasePtr) 3167 continue; 3168 3169 // Try turning it into a post-indexed load / store except when 3170 // 1) All uses are load / store ops that use it as base ptr. 3171 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3172 // nor a successor of N. Otherwise, if Op is folded that would 3173 // create a cycle. 3174 3175 // Check for #1. 3176 bool TryNext = false; 3177 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3178 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3179 SDNode *Use = *II; 3180 if (Use == Ptr.Val) 3181 continue; 3182 3183 // If all the uses are load / store addresses, then don't do the 3184 // transformation. 3185 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3186 bool RealUse = false; 3187 for (SDNode::use_iterator III = Use->use_begin(), 3188 EEE = Use->use_end(); III != EEE; ++III) { 3189 SDNode *UseUse = *III; 3190 if (!((UseUse->getOpcode() == ISD::LOAD && 3191 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3192 (UseUse->getOpcode() == ISD::STORE) && 3193 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3194 RealUse = true; 3195 } 3196 3197 if (!RealUse) { 3198 TryNext = true; 3199 break; 3200 } 3201 } 3202 } 3203 if (TryNext) 3204 continue; 3205 3206 // Check for #2 3207 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3208 SDOperand Result = isLoad 3209 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3210 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3211 ++PostIndexedNodes; 3212 ++NodesCombined; 3213 DOUT << "\nReplacing.5 "; DEBUG(N->dump()); 3214 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3215 DOUT << '\n'; 3216 std::vector<SDNode*> NowDead; 3217 if (isLoad) { 3218 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3219 NowDead); 3220 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3221 NowDead); 3222 } else { 3223 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3224 NowDead); 3225 } 3226 3227 // Nodes can end up on the worklist more than once. Make sure we do 3228 // not process a node that has been replaced. 3229 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3230 removeFromWorkList(NowDead[i]); 3231 // Finally, since the node is now dead, remove it from the graph. 3232 DAG.DeleteNode(N); 3233 3234 // Replace the uses of Use with uses of the updated base value. 3235 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3236 Result.getValue(isLoad ? 1 : 0), 3237 NowDead); 3238 removeFromWorkList(Op); 3239 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3240 removeFromWorkList(NowDead[i]); 3241 DAG.DeleteNode(Op); 3242 3243 return true; 3244 } 3245 } 3246 } 3247 return false; 3248} 3249 3250 3251SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3252 LoadSDNode *LD = cast<LoadSDNode>(N); 3253 SDOperand Chain = LD->getChain(); 3254 SDOperand Ptr = LD->getBasePtr(); 3255 3256 // If there are no uses of the loaded value, change uses of the chain value 3257 // into uses of the chain input (i.e. delete the dead load). 3258 if (N->hasNUsesOfValue(0, 0)) 3259 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3260 3261 // If this load is directly stored, replace the load value with the stored 3262 // value. 3263 // TODO: Handle store large -> read small portion. 3264 // TODO: Handle TRUNCSTORE/LOADEXT 3265 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3266 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3267 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3268 if (PrevST->getBasePtr() == Ptr && 3269 PrevST->getValue().getValueType() == N->getValueType(0)) 3270 return CombineTo(N, Chain.getOperand(1), Chain); 3271 } 3272 } 3273 3274 if (CombinerAA) { 3275 // Walk up chain skipping non-aliasing memory nodes. 3276 SDOperand BetterChain = FindBetterChain(N, Chain); 3277 3278 // If there is a better chain. 3279 if (Chain != BetterChain) { 3280 SDOperand ReplLoad; 3281 3282 // Replace the chain to void dependency. 3283 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3284 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3285 LD->getSrcValue(), LD->getSrcValueOffset()); 3286 } else { 3287 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3288 LD->getValueType(0), 3289 BetterChain, Ptr, LD->getSrcValue(), 3290 LD->getSrcValueOffset(), 3291 LD->getLoadedVT()); 3292 } 3293 3294 // Create token factor to keep old chain connected. 3295 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3296 Chain, ReplLoad.getValue(1)); 3297 3298 // Replace uses with load result and token factor. Don't add users 3299 // to work list. 3300 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3301 } 3302 } 3303 3304 // Try transforming N to an indexed load. 3305 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3306 return SDOperand(N, 0); 3307 3308 return SDOperand(); 3309} 3310 3311SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3312 StoreSDNode *ST = cast<StoreSDNode>(N); 3313 SDOperand Chain = ST->getChain(); 3314 SDOperand Value = ST->getValue(); 3315 SDOperand Ptr = ST->getBasePtr(); 3316 3317 // If this is a store of a bit convert, store the input value. 3318 // FIXME: This needs to know that the resultant store does not need a 3319 // higher alignment than the original. 3320 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) { 3321 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3322 ST->getSrcValueOffset()); 3323 } 3324 3325 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3326 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3327 if (Value.getOpcode() != ISD::TargetConstantFP) { 3328 SDOperand Tmp; 3329 switch (CFP->getValueType(0)) { 3330 default: assert(0 && "Unknown FP type"); 3331 case MVT::f32: 3332 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3333 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 3334 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3335 ST->getSrcValueOffset()); 3336 } 3337 break; 3338 case MVT::f64: 3339 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3340 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 3341 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3342 ST->getSrcValueOffset()); 3343 } else if (TLI.isTypeLegal(MVT::i32)) { 3344 // Many FP stores are not make apparent until after legalize, e.g. for 3345 // argument passing. Since this is so common, custom legalize the 3346 // 64-bit integer store into two 32-bit stores. 3347 uint64_t Val = DoubleToBits(CFP->getValue()); 3348 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3349 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3350 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3351 3352 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3353 ST->getSrcValueOffset()); 3354 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3355 DAG.getConstant(4, Ptr.getValueType())); 3356 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 3357 ST->getSrcValueOffset()+4); 3358 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 3359 } 3360 break; 3361 } 3362 } 3363 } 3364 3365 if (CombinerAA) { 3366 // Walk up chain skipping non-aliasing memory nodes. 3367 SDOperand BetterChain = FindBetterChain(N, Chain); 3368 3369 // If there is a better chain. 3370 if (Chain != BetterChain) { 3371 // Replace the chain to avoid dependency. 3372 SDOperand ReplStore; 3373 if (ST->isTruncatingStore()) { 3374 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 3375 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT()); 3376 } else { 3377 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 3378 ST->getSrcValue(), ST->getSrcValueOffset()); 3379 } 3380 3381 // Create token to keep both nodes around. 3382 SDOperand Token = 3383 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 3384 3385 // Don't add users to work list. 3386 return CombineTo(N, Token, false); 3387 } 3388 } 3389 3390 // Try transforming N to an indexed store. 3391 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3392 return SDOperand(N, 0); 3393 3394 return SDOperand(); 3395} 3396 3397SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 3398 SDOperand InVec = N->getOperand(0); 3399 SDOperand InVal = N->getOperand(1); 3400 SDOperand EltNo = N->getOperand(2); 3401 3402 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 3403 // vector with the inserted element. 3404 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3405 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3406 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3407 if (Elt < Ops.size()) 3408 Ops[Elt] = InVal; 3409 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 3410 &Ops[0], Ops.size()); 3411 } 3412 3413 return SDOperand(); 3414} 3415 3416SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 3417 SDOperand InVec = N->getOperand(0); 3418 SDOperand InVal = N->getOperand(1); 3419 SDOperand EltNo = N->getOperand(2); 3420 SDOperand NumElts = N->getOperand(3); 3421 SDOperand EltType = N->getOperand(4); 3422 3423 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 3424 // vector with the inserted element. 3425 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3426 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3427 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3428 if (Elt < Ops.size()-2) 3429 Ops[Elt] = InVal; 3430 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), 3431 &Ops[0], Ops.size()); 3432 } 3433 3434 return SDOperand(); 3435} 3436 3437SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 3438 unsigned NumInScalars = N->getNumOperands()-2; 3439 SDOperand NumElts = N->getOperand(NumInScalars); 3440 SDOperand EltType = N->getOperand(NumInScalars+1); 3441 3442 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 3443 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 3444 // two distinct vectors, turn this into a shuffle node. 3445 SDOperand VecIn1, VecIn2; 3446 for (unsigned i = 0; i != NumInScalars; ++i) { 3447 // Ignore undef inputs. 3448 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3449 3450 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 3451 // constant index, bail out. 3452 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 3453 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 3454 VecIn1 = VecIn2 = SDOperand(0, 0); 3455 break; 3456 } 3457 3458 // If the input vector type disagrees with the result of the vbuild_vector, 3459 // we can't make a shuffle. 3460 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 3461 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 3462 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 3463 VecIn1 = VecIn2 = SDOperand(0, 0); 3464 break; 3465 } 3466 3467 // Otherwise, remember this. We allow up to two distinct input vectors. 3468 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 3469 continue; 3470 3471 if (VecIn1.Val == 0) { 3472 VecIn1 = ExtractedFromVec; 3473 } else if (VecIn2.Val == 0) { 3474 VecIn2 = ExtractedFromVec; 3475 } else { 3476 // Too many inputs. 3477 VecIn1 = VecIn2 = SDOperand(0, 0); 3478 break; 3479 } 3480 } 3481 3482 // If everything is good, we can make a shuffle operation. 3483 if (VecIn1.Val) { 3484 SmallVector<SDOperand, 8> BuildVecIndices; 3485 for (unsigned i = 0; i != NumInScalars; ++i) { 3486 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 3487 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 3488 continue; 3489 } 3490 3491 SDOperand Extract = N->getOperand(i); 3492 3493 // If extracting from the first vector, just use the index directly. 3494 if (Extract.getOperand(0) == VecIn1) { 3495 BuildVecIndices.push_back(Extract.getOperand(1)); 3496 continue; 3497 } 3498 3499 // Otherwise, use InIdx + VecSize 3500 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 3501 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 3502 TLI.getPointerTy())); 3503 } 3504 3505 // Add count and size info. 3506 BuildVecIndices.push_back(NumElts); 3507 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy())); 3508 3509 // Return the new VVECTOR_SHUFFLE node. 3510 SDOperand Ops[5]; 3511 Ops[0] = VecIn1; 3512 if (VecIn2.Val) { 3513 Ops[1] = VecIn2; 3514 } else { 3515 // Use an undef vbuild_vector as input for the second operand. 3516 std::vector<SDOperand> UnOps(NumInScalars, 3517 DAG.getNode(ISD::UNDEF, 3518 cast<VTSDNode>(EltType)->getVT())); 3519 UnOps.push_back(NumElts); 3520 UnOps.push_back(EltType); 3521 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3522 &UnOps[0], UnOps.size()); 3523 AddToWorkList(Ops[1].Val); 3524 } 3525 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3526 &BuildVecIndices[0], BuildVecIndices.size()); 3527 Ops[3] = NumElts; 3528 Ops[4] = EltType; 3529 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5); 3530 } 3531 3532 return SDOperand(); 3533} 3534 3535SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 3536 SDOperand ShufMask = N->getOperand(2); 3537 unsigned NumElts = ShufMask.getNumOperands(); 3538 3539 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3540 bool isIdentity = true; 3541 for (unsigned i = 0; i != NumElts; ++i) { 3542 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3543 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3544 isIdentity = false; 3545 break; 3546 } 3547 } 3548 if (isIdentity) return N->getOperand(0); 3549 3550 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3551 isIdentity = true; 3552 for (unsigned i = 0; i != NumElts; ++i) { 3553 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3554 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3555 isIdentity = false; 3556 break; 3557 } 3558 } 3559 if (isIdentity) return N->getOperand(1); 3560 3561 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3562 // needed at all. 3563 bool isUnary = true; 3564 bool isSplat = true; 3565 int VecNum = -1; 3566 unsigned BaseIdx = 0; 3567 for (unsigned i = 0; i != NumElts; ++i) 3568 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3569 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3570 int V = (Idx < NumElts) ? 0 : 1; 3571 if (VecNum == -1) { 3572 VecNum = V; 3573 BaseIdx = Idx; 3574 } else { 3575 if (BaseIdx != Idx) 3576 isSplat = false; 3577 if (VecNum != V) { 3578 isUnary = false; 3579 break; 3580 } 3581 } 3582 } 3583 3584 SDOperand N0 = N->getOperand(0); 3585 SDOperand N1 = N->getOperand(1); 3586 // Normalize unary shuffle so the RHS is undef. 3587 if (isUnary && VecNum == 1) 3588 std::swap(N0, N1); 3589 3590 // If it is a splat, check if the argument vector is a build_vector with 3591 // all scalar elements the same. 3592 if (isSplat) { 3593 SDNode *V = N0.Val; 3594 if (V->getOpcode() == ISD::BIT_CONVERT) 3595 V = V->getOperand(0).Val; 3596 if (V->getOpcode() == ISD::BUILD_VECTOR) { 3597 unsigned NumElems = V->getNumOperands()-2; 3598 if (NumElems > BaseIdx) { 3599 SDOperand Base; 3600 bool AllSame = true; 3601 for (unsigned i = 0; i != NumElems; ++i) { 3602 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3603 Base = V->getOperand(i); 3604 break; 3605 } 3606 } 3607 // Splat of <u, u, u, u>, return <u, u, u, u> 3608 if (!Base.Val) 3609 return N0; 3610 for (unsigned i = 0; i != NumElems; ++i) { 3611 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3612 V->getOperand(i) != Base) { 3613 AllSame = false; 3614 break; 3615 } 3616 } 3617 // Splat of <x, x, x, x>, return <x, x, x, x> 3618 if (AllSame) 3619 return N0; 3620 } 3621 } 3622 } 3623 3624 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3625 // into an undef. 3626 if (isUnary || N0 == N1) { 3627 if (N0.getOpcode() == ISD::UNDEF) 3628 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3629 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3630 // first operand. 3631 SmallVector<SDOperand, 8> MappedOps; 3632 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 3633 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3634 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3635 MappedOps.push_back(ShufMask.getOperand(i)); 3636 } else { 3637 unsigned NewIdx = 3638 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3639 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3640 } 3641 } 3642 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 3643 &MappedOps[0], MappedOps.size()); 3644 AddToWorkList(ShufMask.Val); 3645 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 3646 N0, 3647 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 3648 ShufMask); 3649 } 3650 3651 return SDOperand(); 3652} 3653 3654SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 3655 SDOperand ShufMask = N->getOperand(2); 3656 unsigned NumElts = ShufMask.getNumOperands()-2; 3657 3658 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3659 bool isIdentity = true; 3660 for (unsigned i = 0; i != NumElts; ++i) { 3661 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3662 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3663 isIdentity = false; 3664 break; 3665 } 3666 } 3667 if (isIdentity) return N->getOperand(0); 3668 3669 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3670 isIdentity = true; 3671 for (unsigned i = 0; i != NumElts; ++i) { 3672 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3673 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3674 isIdentity = false; 3675 break; 3676 } 3677 } 3678 if (isIdentity) return N->getOperand(1); 3679 3680 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3681 // needed at all. 3682 bool isUnary = true; 3683 bool isSplat = true; 3684 int VecNum = -1; 3685 unsigned BaseIdx = 0; 3686 for (unsigned i = 0; i != NumElts; ++i) 3687 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3688 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3689 int V = (Idx < NumElts) ? 0 : 1; 3690 if (VecNum == -1) { 3691 VecNum = V; 3692 BaseIdx = Idx; 3693 } else { 3694 if (BaseIdx != Idx) 3695 isSplat = false; 3696 if (VecNum != V) { 3697 isUnary = false; 3698 break; 3699 } 3700 } 3701 } 3702 3703 SDOperand N0 = N->getOperand(0); 3704 SDOperand N1 = N->getOperand(1); 3705 // Normalize unary shuffle so the RHS is undef. 3706 if (isUnary && VecNum == 1) 3707 std::swap(N0, N1); 3708 3709 // If it is a splat, check if the argument vector is a build_vector with 3710 // all scalar elements the same. 3711 if (isSplat) { 3712 SDNode *V = N0.Val; 3713 3714 // If this is a vbit convert that changes the element type of the vector but 3715 // not the number of vector elements, look through it. Be careful not to 3716 // look though conversions that change things like v4f32 to v2f64. 3717 if (V->getOpcode() == ISD::VBIT_CONVERT) { 3718 SDOperand ConvInput = V->getOperand(0); 3719 if (ConvInput.getValueType() == MVT::Vector && 3720 NumElts == 3721 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2)) 3722 V = ConvInput.Val; 3723 } 3724 3725 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 3726 unsigned NumElems = V->getNumOperands()-2; 3727 if (NumElems > BaseIdx) { 3728 SDOperand Base; 3729 bool AllSame = true; 3730 for (unsigned i = 0; i != NumElems; ++i) { 3731 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3732 Base = V->getOperand(i); 3733 break; 3734 } 3735 } 3736 // Splat of <u, u, u, u>, return <u, u, u, u> 3737 if (!Base.Val) 3738 return N0; 3739 for (unsigned i = 0; i != NumElems; ++i) { 3740 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3741 V->getOperand(i) != Base) { 3742 AllSame = false; 3743 break; 3744 } 3745 } 3746 // Splat of <x, x, x, x>, return <x, x, x, x> 3747 if (AllSame) 3748 return N0; 3749 } 3750 } 3751 } 3752 3753 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3754 // into an undef. 3755 if (isUnary || N0 == N1) { 3756 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3757 // first operand. 3758 SmallVector<SDOperand, 8> MappedOps; 3759 for (unsigned i = 0; i != NumElts; ++i) { 3760 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3761 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3762 MappedOps.push_back(ShufMask.getOperand(i)); 3763 } else { 3764 unsigned NewIdx = 3765 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3766 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3767 } 3768 } 3769 // Add the type/#elts values. 3770 MappedOps.push_back(ShufMask.getOperand(NumElts)); 3771 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 3772 3773 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 3774 &MappedOps[0], MappedOps.size()); 3775 AddToWorkList(ShufMask.Val); 3776 3777 // Build the undef vector. 3778 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 3779 for (unsigned i = 0; i != NumElts; ++i) 3780 MappedOps[i] = UDVal; 3781 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 3782 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 3783 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3784 &MappedOps[0], MappedOps.size()); 3785 3786 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3787 N0, UDVal, ShufMask, 3788 MappedOps[NumElts], MappedOps[NumElts+1]); 3789 } 3790 3791 return SDOperand(); 3792} 3793 3794/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 3795/// a VAND to a vector_shuffle with the destination vector and a zero vector. 3796/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 3797/// vector_shuffle V, Zero, <0, 4, 2, 4> 3798SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 3799 SDOperand LHS = N->getOperand(0); 3800 SDOperand RHS = N->getOperand(1); 3801 if (N->getOpcode() == ISD::VAND) { 3802 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 3803 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 3804 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 3805 RHS = RHS.getOperand(0); 3806 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3807 std::vector<SDOperand> IdxOps; 3808 unsigned NumOps = RHS.getNumOperands(); 3809 unsigned NumElts = NumOps-2; 3810 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 3811 for (unsigned i = 0; i != NumElts; ++i) { 3812 SDOperand Elt = RHS.getOperand(i); 3813 if (!isa<ConstantSDNode>(Elt)) 3814 return SDOperand(); 3815 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 3816 IdxOps.push_back(DAG.getConstant(i, EVT)); 3817 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 3818 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 3819 else 3820 return SDOperand(); 3821 } 3822 3823 // Let's see if the target supports this vector_shuffle. 3824 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 3825 return SDOperand(); 3826 3827 // Return the new VVECTOR_SHUFFLE node. 3828 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 3829 SDOperand EVTNode = DAG.getValueType(EVT); 3830 std::vector<SDOperand> Ops; 3831 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, 3832 EVTNode); 3833 Ops.push_back(LHS); 3834 AddToWorkList(LHS.Val); 3835 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 3836 ZeroOps.push_back(NumEltsNode); 3837 ZeroOps.push_back(EVTNode); 3838 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3839 &ZeroOps[0], ZeroOps.size())); 3840 IdxOps.push_back(NumEltsNode); 3841 IdxOps.push_back(EVTNode); 3842 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3843 &IdxOps[0], IdxOps.size())); 3844 Ops.push_back(NumEltsNode); 3845 Ops.push_back(EVTNode); 3846 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3847 &Ops[0], Ops.size()); 3848 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 3849 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 3850 DstVecSize, DstVecEVT); 3851 } 3852 return Result; 3853 } 3854 } 3855 return SDOperand(); 3856} 3857 3858/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 3859/// the scalar operation of the vop if it is operating on an integer vector 3860/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 3861SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 3862 ISD::NodeType FPOp) { 3863 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 3864 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 3865 SDOperand LHS = N->getOperand(0); 3866 SDOperand RHS = N->getOperand(1); 3867 SDOperand Shuffle = XformToShuffleWithZero(N); 3868 if (Shuffle.Val) return Shuffle; 3869 3870 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 3871 // this operation. 3872 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 3873 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3874 SmallVector<SDOperand, 8> Ops; 3875 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 3876 SDOperand LHSOp = LHS.getOperand(i); 3877 SDOperand RHSOp = RHS.getOperand(i); 3878 // If these two elements can't be folded, bail out. 3879 if ((LHSOp.getOpcode() != ISD::UNDEF && 3880 LHSOp.getOpcode() != ISD::Constant && 3881 LHSOp.getOpcode() != ISD::ConstantFP) || 3882 (RHSOp.getOpcode() != ISD::UNDEF && 3883 RHSOp.getOpcode() != ISD::Constant && 3884 RHSOp.getOpcode() != ISD::ConstantFP)) 3885 break; 3886 // Can't fold divide by zero. 3887 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 3888 if ((RHSOp.getOpcode() == ISD::Constant && 3889 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 3890 (RHSOp.getOpcode() == ISD::ConstantFP && 3891 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 3892 break; 3893 } 3894 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 3895 AddToWorkList(Ops.back().Val); 3896 assert((Ops.back().getOpcode() == ISD::UNDEF || 3897 Ops.back().getOpcode() == ISD::Constant || 3898 Ops.back().getOpcode() == ISD::ConstantFP) && 3899 "Scalar binop didn't fold!"); 3900 } 3901 3902 if (Ops.size() == LHS.getNumOperands()-2) { 3903 Ops.push_back(*(LHS.Val->op_end()-2)); 3904 Ops.push_back(*(LHS.Val->op_end()-1)); 3905 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 3906 } 3907 } 3908 3909 return SDOperand(); 3910} 3911 3912SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 3913 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 3914 3915 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 3916 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3917 // If we got a simplified select_cc node back from SimplifySelectCC, then 3918 // break it down into a new SETCC node, and a new SELECT node, and then return 3919 // the SELECT node, since we were called with a SELECT node. 3920 if (SCC.Val) { 3921 // Check to see if we got a select_cc back (to turn into setcc/select). 3922 // Otherwise, just return whatever node we got back, like fabs. 3923 if (SCC.getOpcode() == ISD::SELECT_CC) { 3924 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 3925 SCC.getOperand(0), SCC.getOperand(1), 3926 SCC.getOperand(4)); 3927 AddToWorkList(SETCC.Val); 3928 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 3929 SCC.getOperand(3), SETCC); 3930 } 3931 return SCC; 3932 } 3933 return SDOperand(); 3934} 3935 3936/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 3937/// are the two values being selected between, see if we can simplify the 3938/// select. Callers of this should assume that TheSelect is deleted if this 3939/// returns true. As such, they should return the appropriate thing (e.g. the 3940/// node) back to the top-level of the DAG combiner loop to avoid it being 3941/// looked at. 3942/// 3943bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 3944 SDOperand RHS) { 3945 3946 // If this is a select from two identical things, try to pull the operation 3947 // through the select. 3948 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 3949 // If this is a load and the token chain is identical, replace the select 3950 // of two loads with a load through a select of the address to load from. 3951 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 3952 // constants have been dropped into the constant pool. 3953 if (LHS.getOpcode() == ISD::LOAD && 3954 // Token chains must be identical. 3955 LHS.getOperand(0) == RHS.getOperand(0)) { 3956 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 3957 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 3958 3959 // If this is an EXTLOAD, the VT's must match. 3960 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 3961 // FIXME: this conflates two src values, discarding one. This is not 3962 // the right thing to do, but nothing uses srcvalues now. When they do, 3963 // turn SrcValue into a list of locations. 3964 SDOperand Addr; 3965 if (TheSelect->getOpcode() == ISD::SELECT) { 3966 // Check that the condition doesn't reach either load. If so, folding 3967 // this will induce a cycle into the DAG. 3968 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 3969 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 3970 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 3971 TheSelect->getOperand(0), LLD->getBasePtr(), 3972 RLD->getBasePtr()); 3973 } 3974 } else { 3975 // Check that the condition doesn't reach either load. If so, folding 3976 // this will induce a cycle into the DAG. 3977 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 3978 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 3979 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 3980 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 3981 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 3982 TheSelect->getOperand(0), 3983 TheSelect->getOperand(1), 3984 LLD->getBasePtr(), RLD->getBasePtr(), 3985 TheSelect->getOperand(4)); 3986 } 3987 } 3988 3989 if (Addr.Val) { 3990 SDOperand Load; 3991 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 3992 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 3993 Addr,LLD->getSrcValue(), 3994 LLD->getSrcValueOffset()); 3995 else { 3996 Load = DAG.getExtLoad(LLD->getExtensionType(), 3997 TheSelect->getValueType(0), 3998 LLD->getChain(), Addr, LLD->getSrcValue(), 3999 LLD->getSrcValueOffset(), 4000 LLD->getLoadedVT()); 4001 } 4002 // Users of the select now use the result of the load. 4003 CombineTo(TheSelect, Load); 4004 4005 // Users of the old loads now use the new load's chain. We know the 4006 // old-load value is dead now. 4007 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4008 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4009 return true; 4010 } 4011 } 4012 } 4013 } 4014 4015 return false; 4016} 4017 4018SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4019 SDOperand N2, SDOperand N3, 4020 ISD::CondCode CC) { 4021 4022 MVT::ValueType VT = N2.getValueType(); 4023 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4024 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4025 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4026 4027 // Determine if the condition we're dealing with is constant 4028 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4029 if (SCC.Val) AddToWorkList(SCC.Val); 4030 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4031 4032 // fold select_cc true, x, y -> x 4033 if (SCCC && SCCC->getValue()) 4034 return N2; 4035 // fold select_cc false, x, y -> y 4036 if (SCCC && SCCC->getValue() == 0) 4037 return N3; 4038 4039 // Check to see if we can simplify the select into an fabs node 4040 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4041 // Allow either -0.0 or 0.0 4042 if (CFP->getValue() == 0.0) { 4043 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4044 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4045 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4046 N2 == N3.getOperand(0)) 4047 return DAG.getNode(ISD::FABS, VT, N0); 4048 4049 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4050 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4051 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4052 N2.getOperand(0) == N3) 4053 return DAG.getNode(ISD::FABS, VT, N3); 4054 } 4055 } 4056 4057 // Check to see if we can perform the "gzip trick", transforming 4058 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4059 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4060 MVT::isInteger(N0.getValueType()) && 4061 MVT::isInteger(N2.getValueType()) && 4062 (N1C->isNullValue() || // (a < 0) ? b : 0 4063 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4064 MVT::ValueType XType = N0.getValueType(); 4065 MVT::ValueType AType = N2.getValueType(); 4066 if (XType >= AType) { 4067 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4068 // single-bit constant. 4069 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4070 unsigned ShCtV = Log2_64(N2C->getValue()); 4071 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4072 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4073 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4074 AddToWorkList(Shift.Val); 4075 if (XType > AType) { 4076 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4077 AddToWorkList(Shift.Val); 4078 } 4079 return DAG.getNode(ISD::AND, AType, Shift, N2); 4080 } 4081 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4082 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4083 TLI.getShiftAmountTy())); 4084 AddToWorkList(Shift.Val); 4085 if (XType > AType) { 4086 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4087 AddToWorkList(Shift.Val); 4088 } 4089 return DAG.getNode(ISD::AND, AType, Shift, N2); 4090 } 4091 } 4092 4093 // fold select C, 16, 0 -> shl C, 4 4094 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4095 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4096 // Get a SetCC of the condition 4097 // FIXME: Should probably make sure that setcc is legal if we ever have a 4098 // target where it isn't. 4099 SDOperand Temp, SCC; 4100 // cast from setcc result type to select result type 4101 if (AfterLegalize) { 4102 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4103 if (N2.getValueType() < SCC.getValueType()) 4104 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4105 else 4106 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4107 } else { 4108 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4109 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4110 } 4111 AddToWorkList(SCC.Val); 4112 AddToWorkList(Temp.Val); 4113 // shl setcc result by log2 n2c 4114 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4115 DAG.getConstant(Log2_64(N2C->getValue()), 4116 TLI.getShiftAmountTy())); 4117 } 4118 4119 // Check to see if this is the equivalent of setcc 4120 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4121 // otherwise, go ahead with the folds. 4122 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4123 MVT::ValueType XType = N0.getValueType(); 4124 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4125 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4126 if (Res.getValueType() != VT) 4127 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4128 return Res; 4129 } 4130 4131 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4132 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4133 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4134 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4135 return DAG.getNode(ISD::SRL, XType, Ctlz, 4136 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4137 TLI.getShiftAmountTy())); 4138 } 4139 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4140 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4141 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4142 N0); 4143 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4144 DAG.getConstant(~0ULL, XType)); 4145 return DAG.getNode(ISD::SRL, XType, 4146 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4147 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4148 TLI.getShiftAmountTy())); 4149 } 4150 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4151 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4152 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4153 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4154 TLI.getShiftAmountTy())); 4155 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4156 } 4157 } 4158 4159 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4160 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4161 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4162 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4163 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4164 MVT::ValueType XType = N0.getValueType(); 4165 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4166 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4167 TLI.getShiftAmountTy())); 4168 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4169 AddToWorkList(Shift.Val); 4170 AddToWorkList(Add.Val); 4171 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4172 } 4173 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4174 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4175 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4176 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4177 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4178 MVT::ValueType XType = N0.getValueType(); 4179 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4180 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4181 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4182 TLI.getShiftAmountTy())); 4183 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4184 AddToWorkList(Shift.Val); 4185 AddToWorkList(Add.Val); 4186 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4187 } 4188 } 4189 } 4190 4191 return SDOperand(); 4192} 4193 4194/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4195SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4196 SDOperand N1, ISD::CondCode Cond, 4197 bool foldBooleans) { 4198 TargetLowering::DAGCombinerInfo 4199 DagCombineInfo(DAG, !AfterLegalize, false, this); 4200 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4201} 4202 4203/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4204/// return a DAG expression to select that will generate the same value by 4205/// multiplying by a magic number. See: 4206/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4207SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4208 std::vector<SDNode*> Built; 4209 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4210 4211 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4212 ii != ee; ++ii) 4213 AddToWorkList(*ii); 4214 return S; 4215} 4216 4217/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4218/// return a DAG expression to select that will generate the same value by 4219/// multiplying by a magic number. See: 4220/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4221SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4222 std::vector<SDNode*> Built; 4223 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4224 4225 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4226 ii != ee; ++ii) 4227 AddToWorkList(*ii); 4228 return S; 4229} 4230 4231/// FindBaseOffset - Return true if base is known not to alias with anything 4232/// but itself. Provides base object and offset as results. 4233static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4234 // Assume it is a primitive operation. 4235 Base = Ptr; Offset = 0; 4236 4237 // If it's an adding a simple constant then integrate the offset. 4238 if (Base.getOpcode() == ISD::ADD) { 4239 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4240 Base = Base.getOperand(0); 4241 Offset += C->getValue(); 4242 } 4243 } 4244 4245 // If it's any of the following then it can't alias with anything but itself. 4246 return isa<FrameIndexSDNode>(Base) || 4247 isa<ConstantPoolSDNode>(Base) || 4248 isa<GlobalAddressSDNode>(Base); 4249} 4250 4251/// isAlias - Return true if there is any possibility that the two addresses 4252/// overlap. 4253bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4254 const Value *SrcValue1, int SrcValueOffset1, 4255 SDOperand Ptr2, int64_t Size2, 4256 const Value *SrcValue2, int SrcValueOffset2) 4257{ 4258 // If they are the same then they must be aliases. 4259 if (Ptr1 == Ptr2) return true; 4260 4261 // Gather base node and offset information. 4262 SDOperand Base1, Base2; 4263 int64_t Offset1, Offset2; 4264 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4265 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4266 4267 // If they have a same base address then... 4268 if (Base1 == Base2) { 4269 // Check to see if the addresses overlap. 4270 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4271 } 4272 4273 // If we know both bases then they can't alias. 4274 if (KnownBase1 && KnownBase2) return false; 4275 4276 if (CombinerGlobalAA) { 4277 // Use alias analysis information. 4278 int Overlap1 = Size1 + SrcValueOffset1 + Offset1; 4279 int Overlap2 = Size2 + SrcValueOffset2 + Offset2; 4280 AliasAnalysis::AliasResult AAResult = 4281 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4282 if (AAResult == AliasAnalysis::NoAlias) 4283 return false; 4284 } 4285 4286 // Otherwise we have to assume they alias. 4287 return true; 4288} 4289 4290/// FindAliasInfo - Extracts the relevant alias information from the memory 4291/// node. Returns true if the operand was a load. 4292bool DAGCombiner::FindAliasInfo(SDNode *N, 4293 SDOperand &Ptr, int64_t &Size, 4294 const Value *&SrcValue, int &SrcValueOffset) { 4295 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4296 Ptr = LD->getBasePtr(); 4297 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4298 SrcValue = LD->getSrcValue(); 4299 SrcValueOffset = LD->getSrcValueOffset(); 4300 return true; 4301 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4302 Ptr = ST->getBasePtr(); 4303 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4304 SrcValue = ST->getSrcValue(); 4305 SrcValueOffset = ST->getSrcValueOffset(); 4306 } else { 4307 assert(0 && "FindAliasInfo expected a memory operand"); 4308 } 4309 4310 return false; 4311} 4312 4313/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4314/// looking for aliasing nodes and adding them to the Aliases vector. 4315void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4316 SmallVector<SDOperand, 8> &Aliases) { 4317 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4318 std::set<SDNode *> Visited; // Visited node set. 4319 4320 // Get alias information for node. 4321 SDOperand Ptr; 4322 int64_t Size; 4323 const Value *SrcValue; 4324 int SrcValueOffset; 4325 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4326 4327 // Starting off. 4328 Chains.push_back(OriginalChain); 4329 4330 // Look at each chain and determine if it is an alias. If so, add it to the 4331 // aliases list. If not, then continue up the chain looking for the next 4332 // candidate. 4333 while (!Chains.empty()) { 4334 SDOperand Chain = Chains.back(); 4335 Chains.pop_back(); 4336 4337 // Don't bother if we've been before. 4338 if (Visited.find(Chain.Val) != Visited.end()) continue; 4339 Visited.insert(Chain.Val); 4340 4341 switch (Chain.getOpcode()) { 4342 case ISD::EntryToken: 4343 // Entry token is ideal chain operand, but handled in FindBetterChain. 4344 break; 4345 4346 case ISD::LOAD: 4347 case ISD::STORE: { 4348 // Get alias information for Chain. 4349 SDOperand OpPtr; 4350 int64_t OpSize; 4351 const Value *OpSrcValue; 4352 int OpSrcValueOffset; 4353 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4354 OpSrcValue, OpSrcValueOffset); 4355 4356 // If chain is alias then stop here. 4357 if (!(IsLoad && IsOpLoad) && 4358 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4359 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4360 Aliases.push_back(Chain); 4361 } else { 4362 // Look further up the chain. 4363 Chains.push_back(Chain.getOperand(0)); 4364 // Clean up old chain. 4365 AddToWorkList(Chain.Val); 4366 } 4367 break; 4368 } 4369 4370 case ISD::TokenFactor: 4371 // We have to check each of the operands of the token factor, so we queue 4372 // then up. Adding the operands to the queue (stack) in reverse order 4373 // maintains the original order and increases the likelihood that getNode 4374 // will find a matching token factor (CSE.) 4375 for (unsigned n = Chain.getNumOperands(); n;) 4376 Chains.push_back(Chain.getOperand(--n)); 4377 // Eliminate the token factor if we can. 4378 AddToWorkList(Chain.Val); 4379 break; 4380 4381 default: 4382 // For all other instructions we will just have to take what we can get. 4383 Aliases.push_back(Chain); 4384 break; 4385 } 4386 } 4387} 4388 4389/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4390/// for a better chain (aliasing node.) 4391SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4392 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4393 4394 // Accumulate all the aliases to this node. 4395 GatherAllAliases(N, OldChain, Aliases); 4396 4397 if (Aliases.size() == 0) { 4398 // If no operands then chain to entry token. 4399 return DAG.getEntryNode(); 4400 } else if (Aliases.size() == 1) { 4401 // If a single operand then chain to it. We don't need to revisit it. 4402 return Aliases[0]; 4403 } 4404 4405 // Construct a custom tailored token factor. 4406 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4407 &Aliases[0], Aliases.size()); 4408 4409 // Make sure the old chain gets cleaned up. 4410 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4411 4412 return NewChain; 4413} 4414 4415// SelectionDAG::Combine - This is the entry point for the file. 4416// 4417void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4418 if (!RunningAfterLegalize && ViewDAGCombine1) 4419 viewGraph(); 4420 if (RunningAfterLegalize && ViewDAGCombine2) 4421 viewGraph(); 4422 /// run - This is the main entry point to this class. 4423 /// 4424 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 4425} 4426