DAGCombiner.cpp revision 1c49fda408ae5ba90fdaf1b274edd1119aea58b7
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/SmallPtrSet.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/Analysis/AliasAnalysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/DataLayout.h" 27#include "llvm/DerivedTypes.h" 28#include "llvm/LLVMContext.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/ErrorHandling.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetLowering.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetOptions.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue SimplifyVUnaryOp(SDNode *N); 198 SDValue visitSHL(SDNode *N); 199 SDValue visitSRA(SDNode *N); 200 SDValue visitSRL(SDNode *N); 201 SDValue visitCTLZ(SDNode *N); 202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 203 SDValue visitCTTZ(SDNode *N); 204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 205 SDValue visitCTPOP(SDNode *N); 206 SDValue visitSELECT(SDNode *N); 207 SDValue visitSELECT_CC(SDNode *N); 208 SDValue visitSETCC(SDNode *N); 209 SDValue visitSIGN_EXTEND(SDNode *N); 210 SDValue visitZERO_EXTEND(SDNode *N); 211 SDValue visitANY_EXTEND(SDNode *N); 212 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 213 SDValue visitTRUNCATE(SDNode *N); 214 SDValue visitBITCAST(SDNode *N); 215 SDValue visitBUILD_PAIR(SDNode *N); 216 SDValue visitFADD(SDNode *N); 217 SDValue visitFSUB(SDNode *N); 218 SDValue visitFMUL(SDNode *N); 219 SDValue visitFMA(SDNode *N); 220 SDValue visitFDIV(SDNode *N); 221 SDValue visitFREM(SDNode *N); 222 SDValue visitFCOPYSIGN(SDNode *N); 223 SDValue visitSINT_TO_FP(SDNode *N); 224 SDValue visitUINT_TO_FP(SDNode *N); 225 SDValue visitFP_TO_SINT(SDNode *N); 226 SDValue visitFP_TO_UINT(SDNode *N); 227 SDValue visitFP_ROUND(SDNode *N); 228 SDValue visitFP_ROUND_INREG(SDNode *N); 229 SDValue visitFP_EXTEND(SDNode *N); 230 SDValue visitFNEG(SDNode *N); 231 SDValue visitFABS(SDNode *N); 232 SDValue visitFCEIL(SDNode *N); 233 SDValue visitFTRUNC(SDNode *N); 234 SDValue visitFFLOOR(SDNode *N); 235 SDValue visitBRCOND(SDNode *N); 236 SDValue visitBR_CC(SDNode *N); 237 SDValue visitLOAD(SDNode *N); 238 SDValue visitSTORE(SDNode *N); 239 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 241 SDValue visitBUILD_VECTOR(SDNode *N); 242 SDValue visitCONCAT_VECTORS(SDNode *N); 243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 244 SDValue visitVECTOR_SHUFFLE(SDNode *N); 245 SDValue visitMEMBARRIER(SDNode *N); 246 247 SDValue XformToShuffleWithZero(SDNode *N); 248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 249 250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 251 252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 256 SDValue N3, ISD::CondCode CC, 257 bool NotExtCompare = false); 258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 259 DebugLoc DL, bool foldBooleans = true); 260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 261 unsigned HiOp); 262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 264 SDValue BuildSDIV(SDNode *N); 265 SDValue BuildUDIV(SDNode *N); 266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 267 bool DemandHighBits = true); 268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 270 SDValue ReduceLoadWidth(SDNode *N); 271 SDValue ReduceLoadOpStoreWidth(SDNode *N); 272 SDValue TransformFPLoadStorePair(SDNode *N); 273 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N); 274 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N); 275 276 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 277 278 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 279 /// looking for aliasing nodes and adding them to the Aliases vector. 280 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 281 SmallVector<SDValue, 8> &Aliases); 282 283 /// isAlias - Return true if there is any possibility that the two addresses 284 /// overlap. 285 bool isAlias(SDValue Ptr1, int64_t Size1, 286 const Value *SrcValue1, int SrcValueOffset1, 287 unsigned SrcValueAlign1, 288 const MDNode *TBAAInfo1, 289 SDValue Ptr2, int64_t Size2, 290 const Value *SrcValue2, int SrcValueOffset2, 291 unsigned SrcValueAlign2, 292 const MDNode *TBAAInfo2) const; 293 294 /// isAlias - Return true if there is any possibility that the two addresses 295 /// overlap. 296 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1); 297 298 /// FindAliasInfo - Extracts the relevant alias information from the memory 299 /// node. Returns true if the operand was a load. 300 bool FindAliasInfo(SDNode *N, 301 SDValue &Ptr, int64_t &Size, 302 const Value *&SrcValue, int &SrcValueOffset, 303 unsigned &SrcValueAlignment, 304 const MDNode *&TBAAInfo) const; 305 306 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 307 /// looking for a better chain (aliasing node.) 308 SDValue FindBetterChain(SDNode *N, SDValue Chain); 309 310 /// Merge consecutive store operations into a wide store. 311 /// This optimization uses wide integers or vectors when possible. 312 /// \return True if some memory operations were changed. 313 bool MergeConsecutiveStores(StoreSDNode *N); 314 315 public: 316 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 317 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 318 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 319 320 /// Run - runs the dag combiner on all nodes in the work list 321 void Run(CombineLevel AtLevel); 322 323 SelectionDAG &getDAG() const { return DAG; } 324 325 /// getShiftAmountTy - Returns a type large enough to hold any valid 326 /// shift amount - before type legalization these can be huge. 327 EVT getShiftAmountTy(EVT LHSTy) { 328 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 329 } 330 331 /// isTypeLegal - This method returns true if we are running before type 332 /// legalization or if the specified VT is legal. 333 bool isTypeLegal(const EVT &VT) { 334 if (!LegalTypes) return true; 335 return TLI.isTypeLegal(VT); 336 } 337 }; 338} 339 340 341namespace { 342/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 343/// nodes from the worklist. 344class WorkListRemover : public SelectionDAG::DAGUpdateListener { 345 DAGCombiner &DC; 346public: 347 explicit WorkListRemover(DAGCombiner &dc) 348 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 349 350 virtual void NodeDeleted(SDNode *N, SDNode *E) { 351 DC.removeFromWorkList(N); 352 } 353}; 354} 355 356//===----------------------------------------------------------------------===// 357// TargetLowering::DAGCombinerInfo implementation 358//===----------------------------------------------------------------------===// 359 360void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 361 ((DAGCombiner*)DC)->AddToWorkList(N); 362} 363 364void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 365 ((DAGCombiner*)DC)->removeFromWorkList(N); 366} 367 368SDValue TargetLowering::DAGCombinerInfo:: 369CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 370 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 371} 372 373SDValue TargetLowering::DAGCombinerInfo:: 374CombineTo(SDNode *N, SDValue Res, bool AddTo) { 375 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 376} 377 378 379SDValue TargetLowering::DAGCombinerInfo:: 380CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 381 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 382} 383 384void TargetLowering::DAGCombinerInfo:: 385CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 386 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 387} 388 389//===----------------------------------------------------------------------===// 390// Helper Functions 391//===----------------------------------------------------------------------===// 392 393/// isNegatibleForFree - Return 1 if we can compute the negated form of the 394/// specified expression for the same cost as the expression itself, or 2 if we 395/// can compute the negated form more cheaply than the expression itself. 396static char isNegatibleForFree(SDValue Op, bool LegalOperations, 397 const TargetLowering &TLI, 398 const TargetOptions *Options, 399 unsigned Depth = 0) { 400 // fneg is removable even if it has multiple uses. 401 if (Op.getOpcode() == ISD::FNEG) return 2; 402 403 // Don't allow anything with multiple uses. 404 if (!Op.hasOneUse()) return 0; 405 406 // Don't recurse exponentially. 407 if (Depth > 6) return 0; 408 409 switch (Op.getOpcode()) { 410 default: return false; 411 case ISD::ConstantFP: 412 // Don't invert constant FP values after legalize. The negated constant 413 // isn't necessarily legal. 414 return LegalOperations ? 0 : 1; 415 case ISD::FADD: 416 // FIXME: determine better conditions for this xform. 417 if (!Options->UnsafeFPMath) return 0; 418 419 // After operation legalization, it might not be legal to create new FSUBs. 420 if (LegalOperations && 421 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 422 return 0; 423 424 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 425 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 426 Options, Depth + 1)) 427 return V; 428 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 429 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 430 Depth + 1); 431 case ISD::FSUB: 432 // We can't turn -(A-B) into B-A when we honor signed zeros. 433 if (!Options->UnsafeFPMath) return 0; 434 435 // fold (fneg (fsub A, B)) -> (fsub B, A) 436 return 1; 437 438 case ISD::FMUL: 439 case ISD::FDIV: 440 if (Options->HonorSignDependentRoundingFPMath()) return 0; 441 442 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 443 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 444 Options, Depth + 1)) 445 return V; 446 447 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 448 Depth + 1); 449 450 case ISD::FP_EXTEND: 451 case ISD::FP_ROUND: 452 case ISD::FSIN: 453 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 454 Depth + 1); 455 } 456} 457 458/// GetNegatedExpression - If isNegatibleForFree returns true, this function 459/// returns the newly negated expression. 460static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 461 bool LegalOperations, unsigned Depth = 0) { 462 // fneg is removable even if it has multiple uses. 463 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 464 465 // Don't allow anything with multiple uses. 466 assert(Op.hasOneUse() && "Unknown reuse!"); 467 468 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 469 switch (Op.getOpcode()) { 470 default: llvm_unreachable("Unknown code"); 471 case ISD::ConstantFP: { 472 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 473 V.changeSign(); 474 return DAG.getConstantFP(V, Op.getValueType()); 475 } 476 case ISD::FADD: 477 // FIXME: determine better conditions for this xform. 478 assert(DAG.getTarget().Options.UnsafeFPMath); 479 480 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 481 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 482 DAG.getTargetLoweringInfo(), 483 &DAG.getTarget().Options, Depth+1)) 484 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 485 GetNegatedExpression(Op.getOperand(0), DAG, 486 LegalOperations, Depth+1), 487 Op.getOperand(1)); 488 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 489 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 490 GetNegatedExpression(Op.getOperand(1), DAG, 491 LegalOperations, Depth+1), 492 Op.getOperand(0)); 493 case ISD::FSUB: 494 // We can't turn -(A-B) into B-A when we honor signed zeros. 495 assert(DAG.getTarget().Options.UnsafeFPMath); 496 497 // fold (fneg (fsub 0, B)) -> B 498 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 499 if (N0CFP->getValueAPF().isZero()) 500 return Op.getOperand(1); 501 502 // fold (fneg (fsub A, B)) -> (fsub B, A) 503 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 504 Op.getOperand(1), Op.getOperand(0)); 505 506 case ISD::FMUL: 507 case ISD::FDIV: 508 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 509 510 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 511 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 512 DAG.getTargetLoweringInfo(), 513 &DAG.getTarget().Options, Depth+1)) 514 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 515 GetNegatedExpression(Op.getOperand(0), DAG, 516 LegalOperations, Depth+1), 517 Op.getOperand(1)); 518 519 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 520 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 521 Op.getOperand(0), 522 GetNegatedExpression(Op.getOperand(1), DAG, 523 LegalOperations, Depth+1)); 524 525 case ISD::FP_EXTEND: 526 case ISD::FSIN: 527 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 528 GetNegatedExpression(Op.getOperand(0), DAG, 529 LegalOperations, Depth+1)); 530 case ISD::FP_ROUND: 531 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 532 GetNegatedExpression(Op.getOperand(0), DAG, 533 LegalOperations, Depth+1), 534 Op.getOperand(1)); 535 } 536} 537 538 539// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 540// that selects between the values 1 and 0, making it equivalent to a setcc. 541// Also, set the incoming LHS, RHS, and CC references to the appropriate 542// nodes based on the type of node we are checking. This simplifies life a 543// bit for the callers. 544static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 545 SDValue &CC) { 546 if (N.getOpcode() == ISD::SETCC) { 547 LHS = N.getOperand(0); 548 RHS = N.getOperand(1); 549 CC = N.getOperand(2); 550 return true; 551 } 552 if (N.getOpcode() == ISD::SELECT_CC && 553 N.getOperand(2).getOpcode() == ISD::Constant && 554 N.getOperand(3).getOpcode() == ISD::Constant && 555 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 556 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 557 LHS = N.getOperand(0); 558 RHS = N.getOperand(1); 559 CC = N.getOperand(4); 560 return true; 561 } 562 return false; 563} 564 565// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 566// one use. If this is true, it allows the users to invert the operation for 567// free when it is profitable to do so. 568static bool isOneUseSetCC(SDValue N) { 569 SDValue N0, N1, N2; 570 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 571 return true; 572 return false; 573} 574 575SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 576 SDValue N0, SDValue N1) { 577 EVT VT = N0.getValueType(); 578 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 579 if (isa<ConstantSDNode>(N1)) { 580 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 581 SDValue OpNode = 582 DAG.FoldConstantArithmetic(Opc, VT, 583 cast<ConstantSDNode>(N0.getOperand(1)), 584 cast<ConstantSDNode>(N1)); 585 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 586 } 587 if (N0.hasOneUse()) { 588 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 589 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 590 N0.getOperand(0), N1); 591 AddToWorkList(OpNode.getNode()); 592 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 593 } 594 } 595 596 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 597 if (isa<ConstantSDNode>(N0)) { 598 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 599 SDValue OpNode = 600 DAG.FoldConstantArithmetic(Opc, VT, 601 cast<ConstantSDNode>(N1.getOperand(1)), 602 cast<ConstantSDNode>(N0)); 603 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 604 } 605 if (N1.hasOneUse()) { 606 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 607 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 608 N1.getOperand(0), N0); 609 AddToWorkList(OpNode.getNode()); 610 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 611 } 612 } 613 614 return SDValue(); 615} 616 617SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 618 bool AddTo) { 619 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 620 ++NodesCombined; 621 DEBUG(dbgs() << "\nReplacing.1 "; 622 N->dump(&DAG); 623 dbgs() << "\nWith: "; 624 To[0].getNode()->dump(&DAG); 625 dbgs() << " and " << NumTo-1 << " other values\n"; 626 for (unsigned i = 0, e = NumTo; i != e; ++i) 627 assert((!To[i].getNode() || 628 N->getValueType(i) == To[i].getValueType()) && 629 "Cannot combine value to value of different type!")); 630 WorkListRemover DeadNodes(*this); 631 DAG.ReplaceAllUsesWith(N, To); 632 if (AddTo) { 633 // Push the new nodes and any users onto the worklist 634 for (unsigned i = 0, e = NumTo; i != e; ++i) { 635 if (To[i].getNode()) { 636 AddToWorkList(To[i].getNode()); 637 AddUsersToWorkList(To[i].getNode()); 638 } 639 } 640 } 641 642 // Finally, if the node is now dead, remove it from the graph. The node 643 // may not be dead if the replacement process recursively simplified to 644 // something else needing this node. 645 if (N->use_empty()) { 646 // Nodes can be reintroduced into the worklist. Make sure we do not 647 // process a node that has been replaced. 648 removeFromWorkList(N); 649 650 // Finally, since the node is now dead, remove it from the graph. 651 DAG.DeleteNode(N); 652 } 653 return SDValue(N, 0); 654} 655 656void DAGCombiner:: 657CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 658 // Replace all uses. If any nodes become isomorphic to other nodes and 659 // are deleted, make sure to remove them from our worklist. 660 WorkListRemover DeadNodes(*this); 661 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 662 663 // Push the new node and any (possibly new) users onto the worklist. 664 AddToWorkList(TLO.New.getNode()); 665 AddUsersToWorkList(TLO.New.getNode()); 666 667 // Finally, if the node is now dead, remove it from the graph. The node 668 // may not be dead if the replacement process recursively simplified to 669 // something else needing this node. 670 if (TLO.Old.getNode()->use_empty()) { 671 removeFromWorkList(TLO.Old.getNode()); 672 673 // If the operands of this node are only used by the node, they will now 674 // be dead. Make sure to visit them first to delete dead nodes early. 675 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 676 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 677 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 678 679 DAG.DeleteNode(TLO.Old.getNode()); 680 } 681} 682 683/// SimplifyDemandedBits - Check the specified integer node value to see if 684/// it can be simplified or if things it uses can be simplified by bit 685/// propagation. If so, return true. 686bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 687 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 688 APInt KnownZero, KnownOne; 689 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 690 return false; 691 692 // Revisit the node. 693 AddToWorkList(Op.getNode()); 694 695 // Replace the old value with the new one. 696 ++NodesCombined; 697 DEBUG(dbgs() << "\nReplacing.2 "; 698 TLO.Old.getNode()->dump(&DAG); 699 dbgs() << "\nWith: "; 700 TLO.New.getNode()->dump(&DAG); 701 dbgs() << '\n'); 702 703 CommitTargetLoweringOpt(TLO); 704 return true; 705} 706 707void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 708 DebugLoc dl = Load->getDebugLoc(); 709 EVT VT = Load->getValueType(0); 710 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 711 712 DEBUG(dbgs() << "\nReplacing.9 "; 713 Load->dump(&DAG); 714 dbgs() << "\nWith: "; 715 Trunc.getNode()->dump(&DAG); 716 dbgs() << '\n'); 717 WorkListRemover DeadNodes(*this); 718 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 719 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 720 removeFromWorkList(Load); 721 DAG.DeleteNode(Load); 722 AddToWorkList(Trunc.getNode()); 723} 724 725SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 726 Replace = false; 727 DebugLoc dl = Op.getDebugLoc(); 728 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 729 EVT MemVT = LD->getMemoryVT(); 730 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 731 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 732 : ISD::EXTLOAD) 733 : LD->getExtensionType(); 734 Replace = true; 735 return DAG.getExtLoad(ExtType, dl, PVT, 736 LD->getChain(), LD->getBasePtr(), 737 LD->getPointerInfo(), 738 MemVT, LD->isVolatile(), 739 LD->isNonTemporal(), LD->getAlignment()); 740 } 741 742 unsigned Opc = Op.getOpcode(); 743 switch (Opc) { 744 default: break; 745 case ISD::AssertSext: 746 return DAG.getNode(ISD::AssertSext, dl, PVT, 747 SExtPromoteOperand(Op.getOperand(0), PVT), 748 Op.getOperand(1)); 749 case ISD::AssertZext: 750 return DAG.getNode(ISD::AssertZext, dl, PVT, 751 ZExtPromoteOperand(Op.getOperand(0), PVT), 752 Op.getOperand(1)); 753 case ISD::Constant: { 754 unsigned ExtOpc = 755 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 756 return DAG.getNode(ExtOpc, dl, PVT, Op); 757 } 758 } 759 760 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 761 return SDValue(); 762 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 763} 764 765SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 766 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 767 return SDValue(); 768 EVT OldVT = Op.getValueType(); 769 DebugLoc dl = Op.getDebugLoc(); 770 bool Replace = false; 771 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 772 if (NewOp.getNode() == 0) 773 return SDValue(); 774 AddToWorkList(NewOp.getNode()); 775 776 if (Replace) 777 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 778 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 779 DAG.getValueType(OldVT)); 780} 781 782SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 783 EVT OldVT = Op.getValueType(); 784 DebugLoc dl = Op.getDebugLoc(); 785 bool Replace = false; 786 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 787 if (NewOp.getNode() == 0) 788 return SDValue(); 789 AddToWorkList(NewOp.getNode()); 790 791 if (Replace) 792 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 793 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 794} 795 796/// PromoteIntBinOp - Promote the specified integer binary operation if the 797/// target indicates it is beneficial. e.g. On x86, it's usually better to 798/// promote i16 operations to i32 since i16 instructions are longer. 799SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 800 if (!LegalOperations) 801 return SDValue(); 802 803 EVT VT = Op.getValueType(); 804 if (VT.isVector() || !VT.isInteger()) 805 return SDValue(); 806 807 // If operation type is 'undesirable', e.g. i16 on x86, consider 808 // promoting it. 809 unsigned Opc = Op.getOpcode(); 810 if (TLI.isTypeDesirableForOp(Opc, VT)) 811 return SDValue(); 812 813 EVT PVT = VT; 814 // Consult target whether it is a good idea to promote this operation and 815 // what's the right type to promote it to. 816 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 817 assert(PVT != VT && "Don't know what type to promote to!"); 818 819 bool Replace0 = false; 820 SDValue N0 = Op.getOperand(0); 821 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 822 if (NN0.getNode() == 0) 823 return SDValue(); 824 825 bool Replace1 = false; 826 SDValue N1 = Op.getOperand(1); 827 SDValue NN1; 828 if (N0 == N1) 829 NN1 = NN0; 830 else { 831 NN1 = PromoteOperand(N1, PVT, Replace1); 832 if (NN1.getNode() == 0) 833 return SDValue(); 834 } 835 836 AddToWorkList(NN0.getNode()); 837 if (NN1.getNode()) 838 AddToWorkList(NN1.getNode()); 839 840 if (Replace0) 841 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 842 if (Replace1) 843 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 844 845 DEBUG(dbgs() << "\nPromoting "; 846 Op.getNode()->dump(&DAG)); 847 DebugLoc dl = Op.getDebugLoc(); 848 return DAG.getNode(ISD::TRUNCATE, dl, VT, 849 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 850 } 851 return SDValue(); 852} 853 854/// PromoteIntShiftOp - Promote the specified integer shift operation if the 855/// target indicates it is beneficial. e.g. On x86, it's usually better to 856/// promote i16 operations to i32 since i16 instructions are longer. 857SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 858 if (!LegalOperations) 859 return SDValue(); 860 861 EVT VT = Op.getValueType(); 862 if (VT.isVector() || !VT.isInteger()) 863 return SDValue(); 864 865 // If operation type is 'undesirable', e.g. i16 on x86, consider 866 // promoting it. 867 unsigned Opc = Op.getOpcode(); 868 if (TLI.isTypeDesirableForOp(Opc, VT)) 869 return SDValue(); 870 871 EVT PVT = VT; 872 // Consult target whether it is a good idea to promote this operation and 873 // what's the right type to promote it to. 874 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 875 assert(PVT != VT && "Don't know what type to promote to!"); 876 877 bool Replace = false; 878 SDValue N0 = Op.getOperand(0); 879 if (Opc == ISD::SRA) 880 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 881 else if (Opc == ISD::SRL) 882 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 883 else 884 N0 = PromoteOperand(N0, PVT, Replace); 885 if (N0.getNode() == 0) 886 return SDValue(); 887 888 AddToWorkList(N0.getNode()); 889 if (Replace) 890 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 891 892 DEBUG(dbgs() << "\nPromoting "; 893 Op.getNode()->dump(&DAG)); 894 DebugLoc dl = Op.getDebugLoc(); 895 return DAG.getNode(ISD::TRUNCATE, dl, VT, 896 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 897 } 898 return SDValue(); 899} 900 901SDValue DAGCombiner::PromoteExtend(SDValue Op) { 902 if (!LegalOperations) 903 return SDValue(); 904 905 EVT VT = Op.getValueType(); 906 if (VT.isVector() || !VT.isInteger()) 907 return SDValue(); 908 909 // If operation type is 'undesirable', e.g. i16 on x86, consider 910 // promoting it. 911 unsigned Opc = Op.getOpcode(); 912 if (TLI.isTypeDesirableForOp(Opc, VT)) 913 return SDValue(); 914 915 EVT PVT = VT; 916 // Consult target whether it is a good idea to promote this operation and 917 // what's the right type to promote it to. 918 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 919 assert(PVT != VT && "Don't know what type to promote to!"); 920 // fold (aext (aext x)) -> (aext x) 921 // fold (aext (zext x)) -> (zext x) 922 // fold (aext (sext x)) -> (sext x) 923 DEBUG(dbgs() << "\nPromoting "; 924 Op.getNode()->dump(&DAG)); 925 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 926 } 927 return SDValue(); 928} 929 930bool DAGCombiner::PromoteLoad(SDValue Op) { 931 if (!LegalOperations) 932 return false; 933 934 EVT VT = Op.getValueType(); 935 if (VT.isVector() || !VT.isInteger()) 936 return false; 937 938 // If operation type is 'undesirable', e.g. i16 on x86, consider 939 // promoting it. 940 unsigned Opc = Op.getOpcode(); 941 if (TLI.isTypeDesirableForOp(Opc, VT)) 942 return false; 943 944 EVT PVT = VT; 945 // Consult target whether it is a good idea to promote this operation and 946 // what's the right type to promote it to. 947 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 948 assert(PVT != VT && "Don't know what type to promote to!"); 949 950 DebugLoc dl = Op.getDebugLoc(); 951 SDNode *N = Op.getNode(); 952 LoadSDNode *LD = cast<LoadSDNode>(N); 953 EVT MemVT = LD->getMemoryVT(); 954 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 955 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 956 : ISD::EXTLOAD) 957 : LD->getExtensionType(); 958 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 959 LD->getChain(), LD->getBasePtr(), 960 LD->getPointerInfo(), 961 MemVT, LD->isVolatile(), 962 LD->isNonTemporal(), LD->getAlignment()); 963 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 964 965 DEBUG(dbgs() << "\nPromoting "; 966 N->dump(&DAG); 967 dbgs() << "\nTo: "; 968 Result.getNode()->dump(&DAG); 969 dbgs() << '\n'); 970 WorkListRemover DeadNodes(*this); 971 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 973 removeFromWorkList(N); 974 DAG.DeleteNode(N); 975 AddToWorkList(Result.getNode()); 976 return true; 977 } 978 return false; 979} 980 981 982//===----------------------------------------------------------------------===// 983// Main DAG Combiner implementation 984//===----------------------------------------------------------------------===// 985 986void DAGCombiner::Run(CombineLevel AtLevel) { 987 // set the instance variables, so that the various visit routines may use it. 988 Level = AtLevel; 989 LegalOperations = Level >= AfterLegalizeVectorOps; 990 LegalTypes = Level >= AfterLegalizeTypes; 991 992 // Add all the dag nodes to the worklist. 993 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 994 E = DAG.allnodes_end(); I != E; ++I) 995 AddToWorkList(I); 996 997 // Create a dummy node (which is not added to allnodes), that adds a reference 998 // to the root node, preventing it from being deleted, and tracking any 999 // changes of the root. 1000 HandleSDNode Dummy(DAG.getRoot()); 1001 1002 // The root of the dag may dangle to deleted nodes until the dag combiner is 1003 // done. Set it to null to avoid confusion. 1004 DAG.setRoot(SDValue()); 1005 1006 // while the worklist isn't empty, find a node and 1007 // try and combine it. 1008 while (!WorkListContents.empty()) { 1009 SDNode *N; 1010 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1011 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1012 // worklist *should* contain, and check the node we want to visit is should 1013 // actually be visited. 1014 do { 1015 N = WorkListOrder.pop_back_val(); 1016 } while (!WorkListContents.erase(N)); 1017 1018 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1019 // N is deleted from the DAG, since they too may now be dead or may have a 1020 // reduced number of uses, allowing other xforms. 1021 if (N->use_empty() && N != &Dummy) { 1022 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1023 AddToWorkList(N->getOperand(i).getNode()); 1024 1025 DAG.DeleteNode(N); 1026 continue; 1027 } 1028 1029 SDValue RV = combine(N); 1030 1031 if (RV.getNode() == 0) 1032 continue; 1033 1034 ++NodesCombined; 1035 1036 // If we get back the same node we passed in, rather than a new node or 1037 // zero, we know that the node must have defined multiple values and 1038 // CombineTo was used. Since CombineTo takes care of the worklist 1039 // mechanics for us, we have no work to do in this case. 1040 if (RV.getNode() == N) 1041 continue; 1042 1043 assert(N->getOpcode() != ISD::DELETED_NODE && 1044 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1045 "Node was deleted but visit returned new node!"); 1046 1047 DEBUG(dbgs() << "\nReplacing.3 "; 1048 N->dump(&DAG); 1049 dbgs() << "\nWith: "; 1050 RV.getNode()->dump(&DAG); 1051 dbgs() << '\n'); 1052 1053 // Transfer debug value. 1054 DAG.TransferDbgValues(SDValue(N, 0), RV); 1055 WorkListRemover DeadNodes(*this); 1056 if (N->getNumValues() == RV.getNode()->getNumValues()) 1057 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1058 else { 1059 assert(N->getValueType(0) == RV.getValueType() && 1060 N->getNumValues() == 1 && "Type mismatch"); 1061 SDValue OpV = RV; 1062 DAG.ReplaceAllUsesWith(N, &OpV); 1063 } 1064 1065 // Push the new node and any users onto the worklist 1066 AddToWorkList(RV.getNode()); 1067 AddUsersToWorkList(RV.getNode()); 1068 1069 // Add any uses of the old node to the worklist in case this node is the 1070 // last one that uses them. They may become dead after this node is 1071 // deleted. 1072 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1073 AddToWorkList(N->getOperand(i).getNode()); 1074 1075 // Finally, if the node is now dead, remove it from the graph. The node 1076 // may not be dead if the replacement process recursively simplified to 1077 // something else needing this node. 1078 if (N->use_empty()) { 1079 // Nodes can be reintroduced into the worklist. Make sure we do not 1080 // process a node that has been replaced. 1081 removeFromWorkList(N); 1082 1083 // Finally, since the node is now dead, remove it from the graph. 1084 DAG.DeleteNode(N); 1085 } 1086 } 1087 1088 // If the root changed (e.g. it was a dead load, update the root). 1089 DAG.setRoot(Dummy.getValue()); 1090 DAG.RemoveDeadNodes(); 1091} 1092 1093SDValue DAGCombiner::visit(SDNode *N) { 1094 switch (N->getOpcode()) { 1095 default: break; 1096 case ISD::TokenFactor: return visitTokenFactor(N); 1097 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1098 case ISD::ADD: return visitADD(N); 1099 case ISD::SUB: return visitSUB(N); 1100 case ISD::ADDC: return visitADDC(N); 1101 case ISD::SUBC: return visitSUBC(N); 1102 case ISD::ADDE: return visitADDE(N); 1103 case ISD::SUBE: return visitSUBE(N); 1104 case ISD::MUL: return visitMUL(N); 1105 case ISD::SDIV: return visitSDIV(N); 1106 case ISD::UDIV: return visitUDIV(N); 1107 case ISD::SREM: return visitSREM(N); 1108 case ISD::UREM: return visitUREM(N); 1109 case ISD::MULHU: return visitMULHU(N); 1110 case ISD::MULHS: return visitMULHS(N); 1111 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1112 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1113 case ISD::SMULO: return visitSMULO(N); 1114 case ISD::UMULO: return visitUMULO(N); 1115 case ISD::SDIVREM: return visitSDIVREM(N); 1116 case ISD::UDIVREM: return visitUDIVREM(N); 1117 case ISD::AND: return visitAND(N); 1118 case ISD::OR: return visitOR(N); 1119 case ISD::XOR: return visitXOR(N); 1120 case ISD::SHL: return visitSHL(N); 1121 case ISD::SRA: return visitSRA(N); 1122 case ISD::SRL: return visitSRL(N); 1123 case ISD::CTLZ: return visitCTLZ(N); 1124 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1125 case ISD::CTTZ: return visitCTTZ(N); 1126 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1127 case ISD::CTPOP: return visitCTPOP(N); 1128 case ISD::SELECT: return visitSELECT(N); 1129 case ISD::SELECT_CC: return visitSELECT_CC(N); 1130 case ISD::SETCC: return visitSETCC(N); 1131 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1132 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1133 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1134 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1135 case ISD::TRUNCATE: return visitTRUNCATE(N); 1136 case ISD::BITCAST: return visitBITCAST(N); 1137 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1138 case ISD::FADD: return visitFADD(N); 1139 case ISD::FSUB: return visitFSUB(N); 1140 case ISD::FMUL: return visitFMUL(N); 1141 case ISD::FMA: return visitFMA(N); 1142 case ISD::FDIV: return visitFDIV(N); 1143 case ISD::FREM: return visitFREM(N); 1144 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1145 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1146 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1147 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1148 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1149 case ISD::FP_ROUND: return visitFP_ROUND(N); 1150 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1151 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1152 case ISD::FNEG: return visitFNEG(N); 1153 case ISD::FABS: return visitFABS(N); 1154 case ISD::FFLOOR: return visitFFLOOR(N); 1155 case ISD::FCEIL: return visitFCEIL(N); 1156 case ISD::FTRUNC: return visitFTRUNC(N); 1157 case ISD::BRCOND: return visitBRCOND(N); 1158 case ISD::BR_CC: return visitBR_CC(N); 1159 case ISD::LOAD: return visitLOAD(N); 1160 case ISD::STORE: return visitSTORE(N); 1161 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1162 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1163 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1164 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1165 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1166 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1167 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1168 } 1169 return SDValue(); 1170} 1171 1172SDValue DAGCombiner::combine(SDNode *N) { 1173 SDValue RV = visit(N); 1174 1175 // If nothing happened, try a target-specific DAG combine. 1176 if (RV.getNode() == 0) { 1177 assert(N->getOpcode() != ISD::DELETED_NODE && 1178 "Node was deleted but visit returned NULL!"); 1179 1180 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1181 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1182 1183 // Expose the DAG combiner to the target combiner impls. 1184 TargetLowering::DAGCombinerInfo 1185 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1186 1187 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1188 } 1189 } 1190 1191 // If nothing happened still, try promoting the operation. 1192 if (RV.getNode() == 0) { 1193 switch (N->getOpcode()) { 1194 default: break; 1195 case ISD::ADD: 1196 case ISD::SUB: 1197 case ISD::MUL: 1198 case ISD::AND: 1199 case ISD::OR: 1200 case ISD::XOR: 1201 RV = PromoteIntBinOp(SDValue(N, 0)); 1202 break; 1203 case ISD::SHL: 1204 case ISD::SRA: 1205 case ISD::SRL: 1206 RV = PromoteIntShiftOp(SDValue(N, 0)); 1207 break; 1208 case ISD::SIGN_EXTEND: 1209 case ISD::ZERO_EXTEND: 1210 case ISD::ANY_EXTEND: 1211 RV = PromoteExtend(SDValue(N, 0)); 1212 break; 1213 case ISD::LOAD: 1214 if (PromoteLoad(SDValue(N, 0))) 1215 RV = SDValue(N, 0); 1216 break; 1217 } 1218 } 1219 1220 // If N is a commutative binary node, try commuting it to enable more 1221 // sdisel CSE. 1222 if (RV.getNode() == 0 && 1223 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1224 N->getNumValues() == 1) { 1225 SDValue N0 = N->getOperand(0); 1226 SDValue N1 = N->getOperand(1); 1227 1228 // Constant operands are canonicalized to RHS. 1229 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1230 SDValue Ops[] = { N1, N0 }; 1231 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1232 Ops, 2); 1233 if (CSENode) 1234 return SDValue(CSENode, 0); 1235 } 1236 } 1237 1238 return RV; 1239} 1240 1241/// getInputChainForNode - Given a node, return its input chain if it has one, 1242/// otherwise return a null sd operand. 1243static SDValue getInputChainForNode(SDNode *N) { 1244 if (unsigned NumOps = N->getNumOperands()) { 1245 if (N->getOperand(0).getValueType() == MVT::Other) 1246 return N->getOperand(0); 1247 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1248 return N->getOperand(NumOps-1); 1249 for (unsigned i = 1; i < NumOps-1; ++i) 1250 if (N->getOperand(i).getValueType() == MVT::Other) 1251 return N->getOperand(i); 1252 } 1253 return SDValue(); 1254} 1255 1256SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1257 // If N has two operands, where one has an input chain equal to the other, 1258 // the 'other' chain is redundant. 1259 if (N->getNumOperands() == 2) { 1260 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1261 return N->getOperand(0); 1262 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1263 return N->getOperand(1); 1264 } 1265 1266 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1267 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1268 SmallPtrSet<SDNode*, 16> SeenOps; 1269 bool Changed = false; // If we should replace this token factor. 1270 1271 // Start out with this token factor. 1272 TFs.push_back(N); 1273 1274 // Iterate through token factors. The TFs grows when new token factors are 1275 // encountered. 1276 for (unsigned i = 0; i < TFs.size(); ++i) { 1277 SDNode *TF = TFs[i]; 1278 1279 // Check each of the operands. 1280 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1281 SDValue Op = TF->getOperand(i); 1282 1283 switch (Op.getOpcode()) { 1284 case ISD::EntryToken: 1285 // Entry tokens don't need to be added to the list. They are 1286 // rededundant. 1287 Changed = true; 1288 break; 1289 1290 case ISD::TokenFactor: 1291 if (Op.hasOneUse() && 1292 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1293 // Queue up for processing. 1294 TFs.push_back(Op.getNode()); 1295 // Clean up in case the token factor is removed. 1296 AddToWorkList(Op.getNode()); 1297 Changed = true; 1298 break; 1299 } 1300 // Fall thru 1301 1302 default: 1303 // Only add if it isn't already in the list. 1304 if (SeenOps.insert(Op.getNode())) 1305 Ops.push_back(Op); 1306 else 1307 Changed = true; 1308 break; 1309 } 1310 } 1311 } 1312 1313 SDValue Result; 1314 1315 // If we've change things around then replace token factor. 1316 if (Changed) { 1317 if (Ops.empty()) { 1318 // The entry token is the only possible outcome. 1319 Result = DAG.getEntryNode(); 1320 } else { 1321 // New and improved token factor. 1322 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1323 MVT::Other, &Ops[0], Ops.size()); 1324 } 1325 1326 // Don't add users to work list. 1327 return CombineTo(N, Result, false); 1328 } 1329 1330 return Result; 1331} 1332 1333/// MERGE_VALUES can always be eliminated. 1334SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1335 WorkListRemover DeadNodes(*this); 1336 // Replacing results may cause a different MERGE_VALUES to suddenly 1337 // be CSE'd with N, and carry its uses with it. Iterate until no 1338 // uses remain, to ensure that the node can be safely deleted. 1339 // First add the users of this node to the work list so that they 1340 // can be tried again once they have new operands. 1341 AddUsersToWorkList(N); 1342 do { 1343 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1344 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1345 } while (!N->use_empty()); 1346 removeFromWorkList(N); 1347 DAG.DeleteNode(N); 1348 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1349} 1350 1351static 1352SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1353 SelectionDAG &DAG) { 1354 EVT VT = N0.getValueType(); 1355 SDValue N00 = N0.getOperand(0); 1356 SDValue N01 = N0.getOperand(1); 1357 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1358 1359 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1360 isa<ConstantSDNode>(N00.getOperand(1))) { 1361 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1362 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1363 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1364 N00.getOperand(0), N01), 1365 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1366 N00.getOperand(1), N01)); 1367 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1368 } 1369 1370 return SDValue(); 1371} 1372 1373SDValue DAGCombiner::visitADD(SDNode *N) { 1374 SDValue N0 = N->getOperand(0); 1375 SDValue N1 = N->getOperand(1); 1376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1378 EVT VT = N0.getValueType(); 1379 1380 // fold vector ops 1381 if (VT.isVector()) { 1382 SDValue FoldedVOp = SimplifyVBinOp(N); 1383 if (FoldedVOp.getNode()) return FoldedVOp; 1384 1385 // fold (add x, 0) -> x, vector edition 1386 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1387 return N0; 1388 if (ISD::isBuildVectorAllZeros(N0.getNode())) 1389 return N1; 1390 } 1391 1392 // fold (add x, undef) -> undef 1393 if (N0.getOpcode() == ISD::UNDEF) 1394 return N0; 1395 if (N1.getOpcode() == ISD::UNDEF) 1396 return N1; 1397 // fold (add c1, c2) -> c1+c2 1398 if (N0C && N1C) 1399 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1400 // canonicalize constant to RHS 1401 if (N0C && !N1C) 1402 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1403 // fold (add x, 0) -> x 1404 if (N1C && N1C->isNullValue()) 1405 return N0; 1406 // fold (add Sym, c) -> Sym+c 1407 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1408 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1409 GA->getOpcode() == ISD::GlobalAddress) 1410 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1411 GA->getOffset() + 1412 (uint64_t)N1C->getSExtValue()); 1413 // fold ((c1-A)+c2) -> (c1+c2)-A 1414 if (N1C && N0.getOpcode() == ISD::SUB) 1415 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1416 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1417 DAG.getConstant(N1C->getAPIntValue()+ 1418 N0C->getAPIntValue(), VT), 1419 N0.getOperand(1)); 1420 // reassociate add 1421 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1422 if (RADD.getNode() != 0) 1423 return RADD; 1424 // fold ((0-A) + B) -> B-A 1425 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1426 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1427 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1428 // fold (A + (0-B)) -> A-B 1429 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1430 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1431 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1432 // fold (A+(B-A)) -> B 1433 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1434 return N1.getOperand(0); 1435 // fold ((B-A)+A) -> B 1436 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1437 return N0.getOperand(0); 1438 // fold (A+(B-(A+C))) to (B-C) 1439 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1440 N0 == N1.getOperand(1).getOperand(0)) 1441 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1442 N1.getOperand(1).getOperand(1)); 1443 // fold (A+(B-(C+A))) to (B-C) 1444 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1445 N0 == N1.getOperand(1).getOperand(1)) 1446 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1447 N1.getOperand(1).getOperand(0)); 1448 // fold (A+((B-A)+or-C)) to (B+or-C) 1449 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1450 N1.getOperand(0).getOpcode() == ISD::SUB && 1451 N0 == N1.getOperand(0).getOperand(1)) 1452 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1453 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1454 1455 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1456 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1457 SDValue N00 = N0.getOperand(0); 1458 SDValue N01 = N0.getOperand(1); 1459 SDValue N10 = N1.getOperand(0); 1460 SDValue N11 = N1.getOperand(1); 1461 1462 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1463 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1464 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1465 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1466 } 1467 1468 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1469 return SDValue(N, 0); 1470 1471 // fold (a+b) -> (a|b) iff a and b share no bits. 1472 if (VT.isInteger() && !VT.isVector()) { 1473 APInt LHSZero, LHSOne; 1474 APInt RHSZero, RHSOne; 1475 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1476 1477 if (LHSZero.getBoolValue()) { 1478 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1479 1480 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1481 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1482 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1483 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1484 } 1485 } 1486 1487 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1488 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1489 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1490 if (Result.getNode()) return Result; 1491 } 1492 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1493 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1494 if (Result.getNode()) return Result; 1495 } 1496 1497 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1498 if (N1.getOpcode() == ISD::SHL && 1499 N1.getOperand(0).getOpcode() == ISD::SUB) 1500 if (ConstantSDNode *C = 1501 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1502 if (C->getAPIntValue() == 0) 1503 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1504 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1505 N1.getOperand(0).getOperand(1), 1506 N1.getOperand(1))); 1507 if (N0.getOpcode() == ISD::SHL && 1508 N0.getOperand(0).getOpcode() == ISD::SUB) 1509 if (ConstantSDNode *C = 1510 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1511 if (C->getAPIntValue() == 0) 1512 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1513 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1514 N0.getOperand(0).getOperand(1), 1515 N0.getOperand(1))); 1516 1517 if (N1.getOpcode() == ISD::AND) { 1518 SDValue AndOp0 = N1.getOperand(0); 1519 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1520 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1521 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1522 1523 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1524 // and similar xforms where the inner op is either ~0 or 0. 1525 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1526 DebugLoc DL = N->getDebugLoc(); 1527 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1528 } 1529 } 1530 1531 // add (sext i1), X -> sub X, (zext i1) 1532 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1533 N0.getOperand(0).getValueType() == MVT::i1 && 1534 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1535 DebugLoc DL = N->getDebugLoc(); 1536 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1537 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1538 } 1539 1540 return SDValue(); 1541} 1542 1543SDValue DAGCombiner::visitADDC(SDNode *N) { 1544 SDValue N0 = N->getOperand(0); 1545 SDValue N1 = N->getOperand(1); 1546 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1547 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1548 EVT VT = N0.getValueType(); 1549 1550 // If the flag result is dead, turn this into an ADD. 1551 if (!N->hasAnyUseOfValue(1)) 1552 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1553 DAG.getNode(ISD::CARRY_FALSE, 1554 N->getDebugLoc(), MVT::Glue)); 1555 1556 // canonicalize constant to RHS. 1557 if (N0C && !N1C) 1558 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1559 1560 // fold (addc x, 0) -> x + no carry out 1561 if (N1C && N1C->isNullValue()) 1562 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1563 N->getDebugLoc(), MVT::Glue)); 1564 1565 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1566 APInt LHSZero, LHSOne; 1567 APInt RHSZero, RHSOne; 1568 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1569 1570 if (LHSZero.getBoolValue()) { 1571 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1572 1573 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1574 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1575 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1576 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1577 DAG.getNode(ISD::CARRY_FALSE, 1578 N->getDebugLoc(), MVT::Glue)); 1579 } 1580 1581 return SDValue(); 1582} 1583 1584SDValue DAGCombiner::visitADDE(SDNode *N) { 1585 SDValue N0 = N->getOperand(0); 1586 SDValue N1 = N->getOperand(1); 1587 SDValue CarryIn = N->getOperand(2); 1588 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1589 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1590 1591 // canonicalize constant to RHS 1592 if (N0C && !N1C) 1593 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1594 N1, N0, CarryIn); 1595 1596 // fold (adde x, y, false) -> (addc x, y) 1597 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1598 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1599 1600 return SDValue(); 1601} 1602 1603// Since it may not be valid to emit a fold to zero for vector initializers 1604// check if we can before folding. 1605static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1606 SelectionDAG &DAG, bool LegalOperations) { 1607 if (!VT.isVector()) { 1608 return DAG.getConstant(0, VT); 1609 } 1610 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1611 // Produce a vector of zeros. 1612 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1613 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1614 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1615 &Ops[0], Ops.size()); 1616 } 1617 return SDValue(); 1618} 1619 1620SDValue DAGCombiner::visitSUB(SDNode *N) { 1621 SDValue N0 = N->getOperand(0); 1622 SDValue N1 = N->getOperand(1); 1623 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1624 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1625 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1626 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1627 EVT VT = N0.getValueType(); 1628 1629 // fold vector ops 1630 if (VT.isVector()) { 1631 SDValue FoldedVOp = SimplifyVBinOp(N); 1632 if (FoldedVOp.getNode()) return FoldedVOp; 1633 1634 // fold (sub x, 0) -> x, vector edition 1635 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1636 return N0; 1637 } 1638 1639 // fold (sub x, x) -> 0 1640 // FIXME: Refactor this and xor and other similar operations together. 1641 if (N0 == N1) 1642 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1643 // fold (sub c1, c2) -> c1-c2 1644 if (N0C && N1C) 1645 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1646 // fold (sub x, c) -> (add x, -c) 1647 if (N1C) 1648 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1649 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1650 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1651 if (N0C && N0C->isAllOnesValue()) 1652 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1653 // fold A-(A-B) -> B 1654 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1655 return N1.getOperand(1); 1656 // fold (A+B)-A -> B 1657 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1658 return N0.getOperand(1); 1659 // fold (A+B)-B -> A 1660 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1661 return N0.getOperand(0); 1662 // fold C2-(A+C1) -> (C2-C1)-A 1663 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1664 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), 1665 VT); 1666 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1667 N1.getOperand(0)); 1668 } 1669 // fold ((A+(B+or-C))-B) -> A+or-C 1670 if (N0.getOpcode() == ISD::ADD && 1671 (N0.getOperand(1).getOpcode() == ISD::SUB || 1672 N0.getOperand(1).getOpcode() == ISD::ADD) && 1673 N0.getOperand(1).getOperand(0) == N1) 1674 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1675 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1676 // fold ((A+(C+B))-B) -> A+C 1677 if (N0.getOpcode() == ISD::ADD && 1678 N0.getOperand(1).getOpcode() == ISD::ADD && 1679 N0.getOperand(1).getOperand(1) == N1) 1680 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1681 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1682 // fold ((A-(B-C))-C) -> A-B 1683 if (N0.getOpcode() == ISD::SUB && 1684 N0.getOperand(1).getOpcode() == ISD::SUB && 1685 N0.getOperand(1).getOperand(1) == N1) 1686 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1687 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1688 1689 // If either operand of a sub is undef, the result is undef 1690 if (N0.getOpcode() == ISD::UNDEF) 1691 return N0; 1692 if (N1.getOpcode() == ISD::UNDEF) 1693 return N1; 1694 1695 // If the relocation model supports it, consider symbol offsets. 1696 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1697 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1698 // fold (sub Sym, c) -> Sym-c 1699 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1700 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1701 GA->getOffset() - 1702 (uint64_t)N1C->getSExtValue()); 1703 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1704 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1705 if (GA->getGlobal() == GB->getGlobal()) 1706 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1707 VT); 1708 } 1709 1710 return SDValue(); 1711} 1712 1713SDValue DAGCombiner::visitSUBC(SDNode *N) { 1714 SDValue N0 = N->getOperand(0); 1715 SDValue N1 = N->getOperand(1); 1716 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1717 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1718 EVT VT = N0.getValueType(); 1719 1720 // If the flag result is dead, turn this into an SUB. 1721 if (!N->hasAnyUseOfValue(1)) 1722 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1723 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1724 MVT::Glue)); 1725 1726 // fold (subc x, x) -> 0 + no borrow 1727 if (N0 == N1) 1728 return CombineTo(N, DAG.getConstant(0, VT), 1729 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1730 MVT::Glue)); 1731 1732 // fold (subc x, 0) -> x + no borrow 1733 if (N1C && N1C->isNullValue()) 1734 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1735 MVT::Glue)); 1736 1737 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1738 if (N0C && N0C->isAllOnesValue()) 1739 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1740 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1741 MVT::Glue)); 1742 1743 return SDValue(); 1744} 1745 1746SDValue DAGCombiner::visitSUBE(SDNode *N) { 1747 SDValue N0 = N->getOperand(0); 1748 SDValue N1 = N->getOperand(1); 1749 SDValue CarryIn = N->getOperand(2); 1750 1751 // fold (sube x, y, false) -> (subc x, y) 1752 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1753 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1754 1755 return SDValue(); 1756} 1757 1758SDValue DAGCombiner::visitMUL(SDNode *N) { 1759 SDValue N0 = N->getOperand(0); 1760 SDValue N1 = N->getOperand(1); 1761 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1762 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1763 EVT VT = N0.getValueType(); 1764 1765 // fold vector ops 1766 if (VT.isVector()) { 1767 SDValue FoldedVOp = SimplifyVBinOp(N); 1768 if (FoldedVOp.getNode()) return FoldedVOp; 1769 } 1770 1771 // fold (mul x, undef) -> 0 1772 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1773 return DAG.getConstant(0, VT); 1774 // fold (mul c1, c2) -> c1*c2 1775 if (N0C && N1C) 1776 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1777 // canonicalize constant to RHS 1778 if (N0C && !N1C) 1779 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1780 // fold (mul x, 0) -> 0 1781 if (N1C && N1C->isNullValue()) 1782 return N1; 1783 // fold (mul x, -1) -> 0-x 1784 if (N1C && N1C->isAllOnesValue()) 1785 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1786 DAG.getConstant(0, VT), N0); 1787 // fold (mul x, (1 << c)) -> x << c 1788 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1789 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1790 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1791 getShiftAmountTy(N0.getValueType()))); 1792 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1793 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1794 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1795 // FIXME: If the input is something that is easily negated (e.g. a 1796 // single-use add), we should put the negate there. 1797 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1798 DAG.getConstant(0, VT), 1799 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1800 DAG.getConstant(Log2Val, 1801 getShiftAmountTy(N0.getValueType())))); 1802 } 1803 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1804 if (N1C && N0.getOpcode() == ISD::SHL && 1805 isa<ConstantSDNode>(N0.getOperand(1))) { 1806 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1807 N1, N0.getOperand(1)); 1808 AddToWorkList(C3.getNode()); 1809 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1810 N0.getOperand(0), C3); 1811 } 1812 1813 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1814 // use. 1815 { 1816 SDValue Sh(0,0), Y(0,0); 1817 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1818 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1819 N0.getNode()->hasOneUse()) { 1820 Sh = N0; Y = N1; 1821 } else if (N1.getOpcode() == ISD::SHL && 1822 isa<ConstantSDNode>(N1.getOperand(1)) && 1823 N1.getNode()->hasOneUse()) { 1824 Sh = N1; Y = N0; 1825 } 1826 1827 if (Sh.getNode()) { 1828 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1829 Sh.getOperand(0), Y); 1830 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1831 Mul, Sh.getOperand(1)); 1832 } 1833 } 1834 1835 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1836 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1837 isa<ConstantSDNode>(N0.getOperand(1))) 1838 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1839 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1840 N0.getOperand(0), N1), 1841 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1842 N0.getOperand(1), N1)); 1843 1844 // reassociate mul 1845 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1846 if (RMUL.getNode() != 0) 1847 return RMUL; 1848 1849 return SDValue(); 1850} 1851 1852SDValue DAGCombiner::visitSDIV(SDNode *N) { 1853 SDValue N0 = N->getOperand(0); 1854 SDValue N1 = N->getOperand(1); 1855 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1856 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1857 EVT VT = N->getValueType(0); 1858 1859 // fold vector ops 1860 if (VT.isVector()) { 1861 SDValue FoldedVOp = SimplifyVBinOp(N); 1862 if (FoldedVOp.getNode()) return FoldedVOp; 1863 } 1864 1865 // fold (sdiv c1, c2) -> c1/c2 1866 if (N0C && N1C && !N1C->isNullValue()) 1867 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1868 // fold (sdiv X, 1) -> X 1869 if (N1C && N1C->getAPIntValue() == 1LL) 1870 return N0; 1871 // fold (sdiv X, -1) -> 0-X 1872 if (N1C && N1C->isAllOnesValue()) 1873 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1874 DAG.getConstant(0, VT), N0); 1875 // If we know the sign bits of both operands are zero, strength reduce to a 1876 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1877 if (!VT.isVector()) { 1878 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1879 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1880 N0, N1); 1881 } 1882 // fold (sdiv X, pow2) -> simple ops after legalize 1883 if (N1C && !N1C->isNullValue() && 1884 (N1C->getAPIntValue().isPowerOf2() || 1885 (-N1C->getAPIntValue()).isPowerOf2())) { 1886 // If dividing by powers of two is cheap, then don't perform the following 1887 // fold. 1888 if (TLI.isPow2DivCheap()) 1889 return SDValue(); 1890 1891 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1892 1893 // Splat the sign bit into the register 1894 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1895 DAG.getConstant(VT.getSizeInBits()-1, 1896 getShiftAmountTy(N0.getValueType()))); 1897 AddToWorkList(SGN.getNode()); 1898 1899 // Add (N0 < 0) ? abs2 - 1 : 0; 1900 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1901 DAG.getConstant(VT.getSizeInBits() - lg2, 1902 getShiftAmountTy(SGN.getValueType()))); 1903 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1904 AddToWorkList(SRL.getNode()); 1905 AddToWorkList(ADD.getNode()); // Divide by pow2 1906 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1907 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1908 1909 // If we're dividing by a positive value, we're done. Otherwise, we must 1910 // negate the result. 1911 if (N1C->getAPIntValue().isNonNegative()) 1912 return SRA; 1913 1914 AddToWorkList(SRA.getNode()); 1915 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1916 DAG.getConstant(0, VT), SRA); 1917 } 1918 1919 // if integer divide is expensive and we satisfy the requirements, emit an 1920 // alternate sequence. 1921 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1922 SDValue Op = BuildSDIV(N); 1923 if (Op.getNode()) return Op; 1924 } 1925 1926 // undef / X -> 0 1927 if (N0.getOpcode() == ISD::UNDEF) 1928 return DAG.getConstant(0, VT); 1929 // X / undef -> undef 1930 if (N1.getOpcode() == ISD::UNDEF) 1931 return N1; 1932 1933 return SDValue(); 1934} 1935 1936SDValue DAGCombiner::visitUDIV(SDNode *N) { 1937 SDValue N0 = N->getOperand(0); 1938 SDValue N1 = N->getOperand(1); 1939 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1941 EVT VT = N->getValueType(0); 1942 1943 // fold vector ops 1944 if (VT.isVector()) { 1945 SDValue FoldedVOp = SimplifyVBinOp(N); 1946 if (FoldedVOp.getNode()) return FoldedVOp; 1947 } 1948 1949 // fold (udiv c1, c2) -> c1/c2 1950 if (N0C && N1C && !N1C->isNullValue()) 1951 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1952 // fold (udiv x, (1 << c)) -> x >>u c 1953 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1954 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1955 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1956 getShiftAmountTy(N0.getValueType()))); 1957 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1958 if (N1.getOpcode() == ISD::SHL) { 1959 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1960 if (SHC->getAPIntValue().isPowerOf2()) { 1961 EVT ADDVT = N1.getOperand(1).getValueType(); 1962 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1963 N1.getOperand(1), 1964 DAG.getConstant(SHC->getAPIntValue() 1965 .logBase2(), 1966 ADDVT)); 1967 AddToWorkList(Add.getNode()); 1968 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1969 } 1970 } 1971 } 1972 // fold (udiv x, c) -> alternate 1973 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1974 SDValue Op = BuildUDIV(N); 1975 if (Op.getNode()) return Op; 1976 } 1977 1978 // undef / X -> 0 1979 if (N0.getOpcode() == ISD::UNDEF) 1980 return DAG.getConstant(0, VT); 1981 // X / undef -> undef 1982 if (N1.getOpcode() == ISD::UNDEF) 1983 return N1; 1984 1985 return SDValue(); 1986} 1987 1988SDValue DAGCombiner::visitSREM(SDNode *N) { 1989 SDValue N0 = N->getOperand(0); 1990 SDValue N1 = N->getOperand(1); 1991 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1992 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1993 EVT VT = N->getValueType(0); 1994 1995 // fold (srem c1, c2) -> c1%c2 1996 if (N0C && N1C && !N1C->isNullValue()) 1997 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1998 // If we know the sign bits of both operands are zero, strength reduce to a 1999 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 2000 if (!VT.isVector()) { 2001 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 2002 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 2003 } 2004 2005 // If X/C can be simplified by the division-by-constant logic, lower 2006 // X%C to the equivalent of X-X/C*C. 2007 if (N1C && !N1C->isNullValue()) { 2008 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 2009 AddToWorkList(Div.getNode()); 2010 SDValue OptimizedDiv = combine(Div.getNode()); 2011 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2012 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2013 OptimizedDiv, N1); 2014 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2015 AddToWorkList(Mul.getNode()); 2016 return Sub; 2017 } 2018 } 2019 2020 // undef % X -> 0 2021 if (N0.getOpcode() == ISD::UNDEF) 2022 return DAG.getConstant(0, VT); 2023 // X % undef -> undef 2024 if (N1.getOpcode() == ISD::UNDEF) 2025 return N1; 2026 2027 return SDValue(); 2028} 2029 2030SDValue DAGCombiner::visitUREM(SDNode *N) { 2031 SDValue N0 = N->getOperand(0); 2032 SDValue N1 = N->getOperand(1); 2033 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2034 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2035 EVT VT = N->getValueType(0); 2036 2037 // fold (urem c1, c2) -> c1%c2 2038 if (N0C && N1C && !N1C->isNullValue()) 2039 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2040 // fold (urem x, pow2) -> (and x, pow2-1) 2041 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2042 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2043 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2044 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2045 if (N1.getOpcode() == ISD::SHL) { 2046 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2047 if (SHC->getAPIntValue().isPowerOf2()) { 2048 SDValue Add = 2049 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2050 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2051 VT)); 2052 AddToWorkList(Add.getNode()); 2053 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2054 } 2055 } 2056 } 2057 2058 // If X/C can be simplified by the division-by-constant logic, lower 2059 // X%C to the equivalent of X-X/C*C. 2060 if (N1C && !N1C->isNullValue()) { 2061 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2062 AddToWorkList(Div.getNode()); 2063 SDValue OptimizedDiv = combine(Div.getNode()); 2064 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2065 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2066 OptimizedDiv, N1); 2067 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2068 AddToWorkList(Mul.getNode()); 2069 return Sub; 2070 } 2071 } 2072 2073 // undef % X -> 0 2074 if (N0.getOpcode() == ISD::UNDEF) 2075 return DAG.getConstant(0, VT); 2076 // X % undef -> undef 2077 if (N1.getOpcode() == ISD::UNDEF) 2078 return N1; 2079 2080 return SDValue(); 2081} 2082 2083SDValue DAGCombiner::visitMULHS(SDNode *N) { 2084 SDValue N0 = N->getOperand(0); 2085 SDValue N1 = N->getOperand(1); 2086 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2087 EVT VT = N->getValueType(0); 2088 DebugLoc DL = N->getDebugLoc(); 2089 2090 // fold (mulhs x, 0) -> 0 2091 if (N1C && N1C->isNullValue()) 2092 return N1; 2093 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2094 if (N1C && N1C->getAPIntValue() == 1) 2095 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2096 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2097 getShiftAmountTy(N0.getValueType()))); 2098 // fold (mulhs x, undef) -> 0 2099 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2100 return DAG.getConstant(0, VT); 2101 2102 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2103 // plus a shift. 2104 if (VT.isSimple() && !VT.isVector()) { 2105 MVT Simple = VT.getSimpleVT(); 2106 unsigned SimpleSize = Simple.getSizeInBits(); 2107 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2108 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2109 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2110 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2111 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2112 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2113 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2114 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2115 } 2116 } 2117 2118 return SDValue(); 2119} 2120 2121SDValue DAGCombiner::visitMULHU(SDNode *N) { 2122 SDValue N0 = N->getOperand(0); 2123 SDValue N1 = N->getOperand(1); 2124 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2125 EVT VT = N->getValueType(0); 2126 DebugLoc DL = N->getDebugLoc(); 2127 2128 // fold (mulhu x, 0) -> 0 2129 if (N1C && N1C->isNullValue()) 2130 return N1; 2131 // fold (mulhu x, 1) -> 0 2132 if (N1C && N1C->getAPIntValue() == 1) 2133 return DAG.getConstant(0, N0.getValueType()); 2134 // fold (mulhu x, undef) -> 0 2135 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2136 return DAG.getConstant(0, VT); 2137 2138 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2139 // plus a shift. 2140 if (VT.isSimple() && !VT.isVector()) { 2141 MVT Simple = VT.getSimpleVT(); 2142 unsigned SimpleSize = Simple.getSizeInBits(); 2143 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2144 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2145 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2146 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2147 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2148 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2149 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2150 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2151 } 2152 } 2153 2154 return SDValue(); 2155} 2156 2157/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2158/// compute two values. LoOp and HiOp give the opcodes for the two computations 2159/// that are being performed. Return true if a simplification was made. 2160/// 2161SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2162 unsigned HiOp) { 2163 // If the high half is not needed, just compute the low half. 2164 bool HiExists = N->hasAnyUseOfValue(1); 2165 if (!HiExists && 2166 (!LegalOperations || 2167 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2168 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2169 N->op_begin(), N->getNumOperands()); 2170 return CombineTo(N, Res, Res); 2171 } 2172 2173 // If the low half is not needed, just compute the high half. 2174 bool LoExists = N->hasAnyUseOfValue(0); 2175 if (!LoExists && 2176 (!LegalOperations || 2177 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2178 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2179 N->op_begin(), N->getNumOperands()); 2180 return CombineTo(N, Res, Res); 2181 } 2182 2183 // If both halves are used, return as it is. 2184 if (LoExists && HiExists) 2185 return SDValue(); 2186 2187 // If the two computed results can be simplified separately, separate them. 2188 if (LoExists) { 2189 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2190 N->op_begin(), N->getNumOperands()); 2191 AddToWorkList(Lo.getNode()); 2192 SDValue LoOpt = combine(Lo.getNode()); 2193 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2194 (!LegalOperations || 2195 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2196 return CombineTo(N, LoOpt, LoOpt); 2197 } 2198 2199 if (HiExists) { 2200 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2201 N->op_begin(), N->getNumOperands()); 2202 AddToWorkList(Hi.getNode()); 2203 SDValue HiOpt = combine(Hi.getNode()); 2204 if (HiOpt.getNode() && HiOpt != Hi && 2205 (!LegalOperations || 2206 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2207 return CombineTo(N, HiOpt, HiOpt); 2208 } 2209 2210 return SDValue(); 2211} 2212 2213SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2214 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2215 if (Res.getNode()) return Res; 2216 2217 EVT VT = N->getValueType(0); 2218 DebugLoc DL = N->getDebugLoc(); 2219 2220 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2221 // plus a shift. 2222 if (VT.isSimple() && !VT.isVector()) { 2223 MVT Simple = VT.getSimpleVT(); 2224 unsigned SimpleSize = Simple.getSizeInBits(); 2225 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2226 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2227 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2228 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2229 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2230 // Compute the high part as N1. 2231 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2232 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2233 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2234 // Compute the low part as N0. 2235 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2236 return CombineTo(N, Lo, Hi); 2237 } 2238 } 2239 2240 return SDValue(); 2241} 2242 2243SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2244 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2245 if (Res.getNode()) return Res; 2246 2247 EVT VT = N->getValueType(0); 2248 DebugLoc DL = N->getDebugLoc(); 2249 2250 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2251 // plus a shift. 2252 if (VT.isSimple() && !VT.isVector()) { 2253 MVT Simple = VT.getSimpleVT(); 2254 unsigned SimpleSize = Simple.getSizeInBits(); 2255 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2256 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2257 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2258 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2259 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2260 // Compute the high part as N1. 2261 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2262 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2263 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2264 // Compute the low part as N0. 2265 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2266 return CombineTo(N, Lo, Hi); 2267 } 2268 } 2269 2270 return SDValue(); 2271} 2272 2273SDValue DAGCombiner::visitSMULO(SDNode *N) { 2274 // (smulo x, 2) -> (saddo x, x) 2275 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2276 if (C2->getAPIntValue() == 2) 2277 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2278 N->getOperand(0), N->getOperand(0)); 2279 2280 return SDValue(); 2281} 2282 2283SDValue DAGCombiner::visitUMULO(SDNode *N) { 2284 // (umulo x, 2) -> (uaddo x, x) 2285 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2286 if (C2->getAPIntValue() == 2) 2287 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2288 N->getOperand(0), N->getOperand(0)); 2289 2290 return SDValue(); 2291} 2292 2293SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2294 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2295 if (Res.getNode()) return Res; 2296 2297 return SDValue(); 2298} 2299 2300SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2301 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2302 if (Res.getNode()) return Res; 2303 2304 return SDValue(); 2305} 2306 2307/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2308/// two operands of the same opcode, try to simplify it. 2309SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2310 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2311 EVT VT = N0.getValueType(); 2312 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2313 2314 // Bail early if none of these transforms apply. 2315 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2316 2317 // For each of OP in AND/OR/XOR: 2318 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2319 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2320 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2321 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2322 // 2323 // do not sink logical op inside of a vector extend, since it may combine 2324 // into a vsetcc. 2325 EVT Op0VT = N0.getOperand(0).getValueType(); 2326 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2327 N0.getOpcode() == ISD::SIGN_EXTEND || 2328 // Avoid infinite looping with PromoteIntBinOp. 2329 (N0.getOpcode() == ISD::ANY_EXTEND && 2330 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2331 (N0.getOpcode() == ISD::TRUNCATE && 2332 (!TLI.isZExtFree(VT, Op0VT) || 2333 !TLI.isTruncateFree(Op0VT, VT)) && 2334 TLI.isTypeLegal(Op0VT))) && 2335 !VT.isVector() && 2336 Op0VT == N1.getOperand(0).getValueType() && 2337 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2338 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2339 N0.getOperand(0).getValueType(), 2340 N0.getOperand(0), N1.getOperand(0)); 2341 AddToWorkList(ORNode.getNode()); 2342 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2343 } 2344 2345 // For each of OP in SHL/SRL/SRA/AND... 2346 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2347 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2348 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2349 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2350 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2351 N0.getOperand(1) == N1.getOperand(1)) { 2352 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2353 N0.getOperand(0).getValueType(), 2354 N0.getOperand(0), N1.getOperand(0)); 2355 AddToWorkList(ORNode.getNode()); 2356 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2357 ORNode, N0.getOperand(1)); 2358 } 2359 2360 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2361 // Only perform this optimization after type legalization and before 2362 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2363 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2364 // we don't want to undo this promotion. 2365 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2366 // on scalars. 2367 if ((N0.getOpcode() == ISD::BITCAST || 2368 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && 2369 Level == AfterLegalizeTypes) { 2370 SDValue In0 = N0.getOperand(0); 2371 SDValue In1 = N1.getOperand(0); 2372 EVT In0Ty = In0.getValueType(); 2373 EVT In1Ty = In1.getValueType(); 2374 DebugLoc DL = N->getDebugLoc(); 2375 // If both incoming values are integers, and the original types are the 2376 // same. 2377 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2378 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1); 2379 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op); 2380 AddToWorkList(Op.getNode()); 2381 return BC; 2382 } 2383 } 2384 2385 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2386 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2387 // If both shuffles use the same mask, and both shuffle within a single 2388 // vector, then it is worthwhile to move the swizzle after the operation. 2389 // The type-legalizer generates this pattern when loading illegal 2390 // vector types from memory. In many cases this allows additional shuffle 2391 // optimizations. 2392 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2393 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2394 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2395 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2396 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2397 2398 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2399 "Inputs to shuffles are not the same type"); 2400 2401 unsigned NumElts = VT.getVectorNumElements(); 2402 2403 // Check that both shuffles use the same mask. The masks are known to be of 2404 // the same length because the result vector type is the same. 2405 bool SameMask = true; 2406 for (unsigned i = 0; i != NumElts; ++i) { 2407 int Idx0 = SVN0->getMaskElt(i); 2408 int Idx1 = SVN1->getMaskElt(i); 2409 if (Idx0 != Idx1) { 2410 SameMask = false; 2411 break; 2412 } 2413 } 2414 2415 if (SameMask) { 2416 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2417 N0.getOperand(0), N1.getOperand(0)); 2418 AddToWorkList(Op.getNode()); 2419 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2420 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2421 } 2422 } 2423 2424 return SDValue(); 2425} 2426 2427SDValue DAGCombiner::visitAND(SDNode *N) { 2428 SDValue N0 = N->getOperand(0); 2429 SDValue N1 = N->getOperand(1); 2430 SDValue LL, LR, RL, RR, CC0, CC1; 2431 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2432 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2433 EVT VT = N1.getValueType(); 2434 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2435 2436 // fold vector ops 2437 if (VT.isVector()) { 2438 SDValue FoldedVOp = SimplifyVBinOp(N); 2439 if (FoldedVOp.getNode()) return FoldedVOp; 2440 2441 // fold (and x, 0) -> 0, vector edition 2442 if (ISD::isBuildVectorAllZeros(N0.getNode())) 2443 return N0; 2444 if (ISD::isBuildVectorAllZeros(N1.getNode())) 2445 return N1; 2446 2447 // fold (and x, -1) -> x, vector edition 2448 if (ISD::isBuildVectorAllOnes(N0.getNode())) 2449 return N1; 2450 if (ISD::isBuildVectorAllOnes(N1.getNode())) 2451 return N0; 2452 } 2453 2454 // fold (and x, undef) -> 0 2455 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2456 return DAG.getConstant(0, VT); 2457 // fold (and c1, c2) -> c1&c2 2458 if (N0C && N1C) 2459 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2460 // canonicalize constant to RHS 2461 if (N0C && !N1C) 2462 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2463 // fold (and x, -1) -> x 2464 if (N1C && N1C->isAllOnesValue()) 2465 return N0; 2466 // if (and x, c) is known to be zero, return 0 2467 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2468 APInt::getAllOnesValue(BitWidth))) 2469 return DAG.getConstant(0, VT); 2470 // reassociate and 2471 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2472 if (RAND.getNode() != 0) 2473 return RAND; 2474 // fold (and (or x, C), D) -> D if (C & D) == D 2475 if (N1C && N0.getOpcode() == ISD::OR) 2476 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2477 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2478 return N1; 2479 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2480 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2481 SDValue N0Op0 = N0.getOperand(0); 2482 APInt Mask = ~N1C->getAPIntValue(); 2483 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2484 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2485 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2486 N0.getValueType(), N0Op0); 2487 2488 // Replace uses of the AND with uses of the Zero extend node. 2489 CombineTo(N, Zext); 2490 2491 // We actually want to replace all uses of the any_extend with the 2492 // zero_extend, to avoid duplicating things. This will later cause this 2493 // AND to be folded. 2494 CombineTo(N0.getNode(), Zext); 2495 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2496 } 2497 } 2498 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2499 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2500 // already be zero by virtue of the width of the base type of the load. 2501 // 2502 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2503 // more cases. 2504 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2505 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2506 N0.getOpcode() == ISD::LOAD) { 2507 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2508 N0 : N0.getOperand(0) ); 2509 2510 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2511 // This can be a pure constant or a vector splat, in which case we treat the 2512 // vector as a scalar and use the splat value. 2513 APInt Constant = APInt::getNullValue(1); 2514 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2515 Constant = C->getAPIntValue(); 2516 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2517 APInt SplatValue, SplatUndef; 2518 unsigned SplatBitSize; 2519 bool HasAnyUndefs; 2520 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2521 SplatBitSize, HasAnyUndefs); 2522 if (IsSplat) { 2523 // Undef bits can contribute to a possible optimisation if set, so 2524 // set them. 2525 SplatValue |= SplatUndef; 2526 2527 // The splat value may be something like "0x00FFFFFF", which means 0 for 2528 // the first vector value and FF for the rest, repeating. We need a mask 2529 // that will apply equally to all members of the vector, so AND all the 2530 // lanes of the constant together. 2531 EVT VT = Vector->getValueType(0); 2532 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2533 2534 // If the splat value has been compressed to a bitlength lower 2535 // than the size of the vector lane, we need to re-expand it to 2536 // the lane size. 2537 if (BitWidth > SplatBitSize) 2538 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2539 SplatBitSize < BitWidth; 2540 SplatBitSize = SplatBitSize * 2) 2541 SplatValue |= SplatValue.shl(SplatBitSize); 2542 2543 Constant = APInt::getAllOnesValue(BitWidth); 2544 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2545 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2546 } 2547 } 2548 2549 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2550 // actually legal and isn't going to get expanded, else this is a false 2551 // optimisation. 2552 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2553 Load->getMemoryVT()); 2554 2555 // Resize the constant to the same size as the original memory access before 2556 // extension. If it is still the AllOnesValue then this AND is completely 2557 // unneeded. 2558 Constant = 2559 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2560 2561 bool B; 2562 switch (Load->getExtensionType()) { 2563 default: B = false; break; 2564 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2565 case ISD::ZEXTLOAD: 2566 case ISD::NON_EXTLOAD: B = true; break; 2567 } 2568 2569 if (B && Constant.isAllOnesValue()) { 2570 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2571 // preserve semantics once we get rid of the AND. 2572 SDValue NewLoad(Load, 0); 2573 if (Load->getExtensionType() == ISD::EXTLOAD) { 2574 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2575 Load->getValueType(0), Load->getDebugLoc(), 2576 Load->getChain(), Load->getBasePtr(), 2577 Load->getOffset(), Load->getMemoryVT(), 2578 Load->getMemOperand()); 2579 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2580 if (Load->getNumValues() == 3) { 2581 // PRE/POST_INC loads have 3 values. 2582 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2583 NewLoad.getValue(2) }; 2584 CombineTo(Load, To, 3, true); 2585 } else { 2586 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2587 } 2588 } 2589 2590 // Fold the AND away, taking care not to fold to the old load node if we 2591 // replaced it. 2592 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2593 2594 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2595 } 2596 } 2597 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2598 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2599 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2600 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2601 2602 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2603 LL.getValueType().isInteger()) { 2604 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2605 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2606 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2607 LR.getValueType(), LL, RL); 2608 AddToWorkList(ORNode.getNode()); 2609 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2610 } 2611 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2612 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2613 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2614 LR.getValueType(), LL, RL); 2615 AddToWorkList(ANDNode.getNode()); 2616 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2617 } 2618 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2619 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2620 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2621 LR.getValueType(), LL, RL); 2622 AddToWorkList(ORNode.getNode()); 2623 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2624 } 2625 } 2626 // canonicalize equivalent to ll == rl 2627 if (LL == RR && LR == RL) { 2628 Op1 = ISD::getSetCCSwappedOperands(Op1); 2629 std::swap(RL, RR); 2630 } 2631 if (LL == RL && LR == RR) { 2632 bool isInteger = LL.getValueType().isInteger(); 2633 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2634 if (Result != ISD::SETCC_INVALID && 2635 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2636 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2637 LL, LR, Result); 2638 } 2639 } 2640 2641 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2642 if (N0.getOpcode() == N1.getOpcode()) { 2643 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2644 if (Tmp.getNode()) return Tmp; 2645 } 2646 2647 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2648 // fold (and (sra)) -> (and (srl)) when possible. 2649 if (!VT.isVector() && 2650 SimplifyDemandedBits(SDValue(N, 0))) 2651 return SDValue(N, 0); 2652 2653 // fold (zext_inreg (extload x)) -> (zextload x) 2654 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2655 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2656 EVT MemVT = LN0->getMemoryVT(); 2657 // If we zero all the possible extended bits, then we can turn this into 2658 // a zextload if we are running before legalize or the operation is legal. 2659 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2660 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2661 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2662 ((!LegalOperations && !LN0->isVolatile()) || 2663 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2664 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2665 LN0->getChain(), LN0->getBasePtr(), 2666 LN0->getPointerInfo(), MemVT, 2667 LN0->isVolatile(), LN0->isNonTemporal(), 2668 LN0->getAlignment()); 2669 AddToWorkList(N); 2670 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2671 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2672 } 2673 } 2674 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2675 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2676 N0.hasOneUse()) { 2677 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2678 EVT MemVT = LN0->getMemoryVT(); 2679 // If we zero all the possible extended bits, then we can turn this into 2680 // a zextload if we are running before legalize or the operation is legal. 2681 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2682 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2683 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2684 ((!LegalOperations && !LN0->isVolatile()) || 2685 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2686 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2687 LN0->getChain(), 2688 LN0->getBasePtr(), LN0->getPointerInfo(), 2689 MemVT, 2690 LN0->isVolatile(), LN0->isNonTemporal(), 2691 LN0->getAlignment()); 2692 AddToWorkList(N); 2693 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2694 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2695 } 2696 } 2697 2698 // fold (and (load x), 255) -> (zextload x, i8) 2699 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2700 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2701 if (N1C && (N0.getOpcode() == ISD::LOAD || 2702 (N0.getOpcode() == ISD::ANY_EXTEND && 2703 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2704 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2705 LoadSDNode *LN0 = HasAnyExt 2706 ? cast<LoadSDNode>(N0.getOperand(0)) 2707 : cast<LoadSDNode>(N0); 2708 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2709 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2710 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2711 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2712 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2713 EVT LoadedVT = LN0->getMemoryVT(); 2714 2715 if (ExtVT == LoadedVT && 2716 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2717 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2718 2719 SDValue NewLoad = 2720 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2721 LN0->getChain(), LN0->getBasePtr(), 2722 LN0->getPointerInfo(), 2723 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2724 LN0->getAlignment()); 2725 AddToWorkList(N); 2726 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2727 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2728 } 2729 2730 // Do not change the width of a volatile load. 2731 // Do not generate loads of non-round integer types since these can 2732 // be expensive (and would be wrong if the type is not byte sized). 2733 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2734 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2735 EVT PtrType = LN0->getOperand(1).getValueType(); 2736 2737 unsigned Alignment = LN0->getAlignment(); 2738 SDValue NewPtr = LN0->getBasePtr(); 2739 2740 // For big endian targets, we need to add an offset to the pointer 2741 // to load the correct bytes. For little endian systems, we merely 2742 // need to read fewer bytes from the same pointer. 2743 if (TLI.isBigEndian()) { 2744 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2745 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2746 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2747 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2748 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2749 Alignment = MinAlign(Alignment, PtrOff); 2750 } 2751 2752 AddToWorkList(NewPtr.getNode()); 2753 2754 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2755 SDValue Load = 2756 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2757 LN0->getChain(), NewPtr, 2758 LN0->getPointerInfo(), 2759 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2760 Alignment); 2761 AddToWorkList(N); 2762 CombineTo(LN0, Load, Load.getValue(1)); 2763 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2764 } 2765 } 2766 } 2767 } 2768 2769 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2770 VT.getSizeInBits() <= 64) { 2771 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2772 APInt ADDC = ADDI->getAPIntValue(); 2773 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2774 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2775 // immediate for an add, but it is legal if its top c2 bits are set, 2776 // transform the ADD so the immediate doesn't need to be materialized 2777 // in a register. 2778 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2779 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2780 SRLI->getZExtValue()); 2781 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2782 ADDC |= Mask; 2783 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2784 SDValue NewAdd = 2785 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 2786 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2787 CombineTo(N0.getNode(), NewAdd); 2788 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2789 } 2790 } 2791 } 2792 } 2793 } 2794 } 2795 2796 return SDValue(); 2797} 2798 2799/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2800/// 2801SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2802 bool DemandHighBits) { 2803 if (!LegalOperations) 2804 return SDValue(); 2805 2806 EVT VT = N->getValueType(0); 2807 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2808 return SDValue(); 2809 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2810 return SDValue(); 2811 2812 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2813 bool LookPassAnd0 = false; 2814 bool LookPassAnd1 = false; 2815 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2816 std::swap(N0, N1); 2817 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2818 std::swap(N0, N1); 2819 if (N0.getOpcode() == ISD::AND) { 2820 if (!N0.getNode()->hasOneUse()) 2821 return SDValue(); 2822 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2823 if (!N01C || N01C->getZExtValue() != 0xFF00) 2824 return SDValue(); 2825 N0 = N0.getOperand(0); 2826 LookPassAnd0 = true; 2827 } 2828 2829 if (N1.getOpcode() == ISD::AND) { 2830 if (!N1.getNode()->hasOneUse()) 2831 return SDValue(); 2832 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2833 if (!N11C || N11C->getZExtValue() != 0xFF) 2834 return SDValue(); 2835 N1 = N1.getOperand(0); 2836 LookPassAnd1 = true; 2837 } 2838 2839 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2840 std::swap(N0, N1); 2841 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2842 return SDValue(); 2843 if (!N0.getNode()->hasOneUse() || 2844 !N1.getNode()->hasOneUse()) 2845 return SDValue(); 2846 2847 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2848 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2849 if (!N01C || !N11C) 2850 return SDValue(); 2851 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2852 return SDValue(); 2853 2854 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2855 SDValue N00 = N0->getOperand(0); 2856 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2857 if (!N00.getNode()->hasOneUse()) 2858 return SDValue(); 2859 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2860 if (!N001C || N001C->getZExtValue() != 0xFF) 2861 return SDValue(); 2862 N00 = N00.getOperand(0); 2863 LookPassAnd0 = true; 2864 } 2865 2866 SDValue N10 = N1->getOperand(0); 2867 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2868 if (!N10.getNode()->hasOneUse()) 2869 return SDValue(); 2870 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2871 if (!N101C || N101C->getZExtValue() != 0xFF00) 2872 return SDValue(); 2873 N10 = N10.getOperand(0); 2874 LookPassAnd1 = true; 2875 } 2876 2877 if (N00 != N10) 2878 return SDValue(); 2879 2880 // Make sure everything beyond the low halfword is zero since the SRL 16 2881 // will clear the top bits. 2882 unsigned OpSizeInBits = VT.getSizeInBits(); 2883 if (DemandHighBits && OpSizeInBits > 16 && 2884 (!LookPassAnd0 || !LookPassAnd1) && 2885 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2886 return SDValue(); 2887 2888 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2889 if (OpSizeInBits > 16) 2890 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2891 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2892 return Res; 2893} 2894 2895/// isBSwapHWordElement - Return true if the specified node is an element 2896/// that makes up a 32-bit packed halfword byteswap. i.e. 2897/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2898static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2899 if (!N.getNode()->hasOneUse()) 2900 return false; 2901 2902 unsigned Opc = N.getOpcode(); 2903 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2904 return false; 2905 2906 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2907 if (!N1C) 2908 return false; 2909 2910 unsigned Num; 2911 switch (N1C->getZExtValue()) { 2912 default: 2913 return false; 2914 case 0xFF: Num = 0; break; 2915 case 0xFF00: Num = 1; break; 2916 case 0xFF0000: Num = 2; break; 2917 case 0xFF000000: Num = 3; break; 2918 } 2919 2920 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2921 SDValue N0 = N.getOperand(0); 2922 if (Opc == ISD::AND) { 2923 if (Num == 0 || Num == 2) { 2924 // (x >> 8) & 0xff 2925 // (x >> 8) & 0xff0000 2926 if (N0.getOpcode() != ISD::SRL) 2927 return false; 2928 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2929 if (!C || C->getZExtValue() != 8) 2930 return false; 2931 } else { 2932 // (x << 8) & 0xff00 2933 // (x << 8) & 0xff000000 2934 if (N0.getOpcode() != ISD::SHL) 2935 return false; 2936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2937 if (!C || C->getZExtValue() != 8) 2938 return false; 2939 } 2940 } else if (Opc == ISD::SHL) { 2941 // (x & 0xff) << 8 2942 // (x & 0xff0000) << 8 2943 if (Num != 0 && Num != 2) 2944 return false; 2945 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2946 if (!C || C->getZExtValue() != 8) 2947 return false; 2948 } else { // Opc == ISD::SRL 2949 // (x & 0xff00) >> 8 2950 // (x & 0xff000000) >> 8 2951 if (Num != 1 && Num != 3) 2952 return false; 2953 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2954 if (!C || C->getZExtValue() != 8) 2955 return false; 2956 } 2957 2958 if (Parts[Num]) 2959 return false; 2960 2961 Parts[Num] = N0.getOperand(0).getNode(); 2962 return true; 2963} 2964 2965/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2966/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2967/// => (rotl (bswap x), 16) 2968SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2969 if (!LegalOperations) 2970 return SDValue(); 2971 2972 EVT VT = N->getValueType(0); 2973 if (VT != MVT::i32) 2974 return SDValue(); 2975 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2976 return SDValue(); 2977 2978 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2979 // Look for either 2980 // (or (or (and), (and)), (or (and), (and))) 2981 // (or (or (or (and), (and)), (and)), (and)) 2982 if (N0.getOpcode() != ISD::OR) 2983 return SDValue(); 2984 SDValue N00 = N0.getOperand(0); 2985 SDValue N01 = N0.getOperand(1); 2986 2987 if (N1.getOpcode() == ISD::OR) { 2988 // (or (or (and), (and)), (or (and), (and))) 2989 SDValue N000 = N00.getOperand(0); 2990 if (!isBSwapHWordElement(N000, Parts)) 2991 return SDValue(); 2992 2993 SDValue N001 = N00.getOperand(1); 2994 if (!isBSwapHWordElement(N001, Parts)) 2995 return SDValue(); 2996 SDValue N010 = N01.getOperand(0); 2997 if (!isBSwapHWordElement(N010, Parts)) 2998 return SDValue(); 2999 SDValue N011 = N01.getOperand(1); 3000 if (!isBSwapHWordElement(N011, Parts)) 3001 return SDValue(); 3002 } else { 3003 // (or (or (or (and), (and)), (and)), (and)) 3004 if (!isBSwapHWordElement(N1, Parts)) 3005 return SDValue(); 3006 if (!isBSwapHWordElement(N01, Parts)) 3007 return SDValue(); 3008 if (N00.getOpcode() != ISD::OR) 3009 return SDValue(); 3010 SDValue N000 = N00.getOperand(0); 3011 if (!isBSwapHWordElement(N000, Parts)) 3012 return SDValue(); 3013 SDValue N001 = N00.getOperand(1); 3014 if (!isBSwapHWordElement(N001, Parts)) 3015 return SDValue(); 3016 } 3017 3018 // Make sure the parts are all coming from the same node. 3019 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 3020 return SDValue(); 3021 3022 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 3023 SDValue(Parts[0],0)); 3024 3025 // Result of the bswap should be rotated by 16. If it's not legal, than 3026 // do (x << 16) | (x >> 16). 3027 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 3028 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3029 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 3030 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3031 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 3032 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 3033 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 3034 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 3035} 3036 3037SDValue DAGCombiner::visitOR(SDNode *N) { 3038 SDValue N0 = N->getOperand(0); 3039 SDValue N1 = N->getOperand(1); 3040 SDValue LL, LR, RL, RR, CC0, CC1; 3041 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3042 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3043 EVT VT = N1.getValueType(); 3044 3045 // fold vector ops 3046 if (VT.isVector()) { 3047 SDValue FoldedVOp = SimplifyVBinOp(N); 3048 if (FoldedVOp.getNode()) return FoldedVOp; 3049 3050 // fold (or x, 0) -> x, vector edition 3051 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3052 return N1; 3053 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3054 return N0; 3055 3056 // fold (or x, -1) -> -1, vector edition 3057 if (ISD::isBuildVectorAllOnes(N0.getNode())) 3058 return N0; 3059 if (ISD::isBuildVectorAllOnes(N1.getNode())) 3060 return N1; 3061 } 3062 3063 // fold (or x, undef) -> -1 3064 if (!LegalOperations && 3065 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3066 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3067 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3068 } 3069 // fold (or c1, c2) -> c1|c2 3070 if (N0C && N1C) 3071 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3072 // canonicalize constant to RHS 3073 if (N0C && !N1C) 3074 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 3075 // fold (or x, 0) -> x 3076 if (N1C && N1C->isNullValue()) 3077 return N0; 3078 // fold (or x, -1) -> -1 3079 if (N1C && N1C->isAllOnesValue()) 3080 return N1; 3081 // fold (or x, c) -> c iff (x & ~c) == 0 3082 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3083 return N1; 3084 3085 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3086 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3087 if (BSwap.getNode() != 0) 3088 return BSwap; 3089 BSwap = MatchBSwapHWordLow(N, N0, N1); 3090 if (BSwap.getNode() != 0) 3091 return BSwap; 3092 3093 // reassociate or 3094 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3095 if (ROR.getNode() != 0) 3096 return ROR; 3097 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3098 // iff (c1 & c2) == 0. 3099 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3100 isa<ConstantSDNode>(N0.getOperand(1))) { 3101 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3102 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3103 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3104 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3105 N0.getOperand(0), N1), 3106 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3107 } 3108 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3109 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3110 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3111 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3112 3113 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3114 LL.getValueType().isInteger()) { 3115 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3116 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3117 if (cast<ConstantSDNode>(LR)->isNullValue() && 3118 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3119 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3120 LR.getValueType(), LL, RL); 3121 AddToWorkList(ORNode.getNode()); 3122 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3123 } 3124 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3125 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3126 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3127 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3128 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3129 LR.getValueType(), LL, RL); 3130 AddToWorkList(ANDNode.getNode()); 3131 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3132 } 3133 } 3134 // canonicalize equivalent to ll == rl 3135 if (LL == RR && LR == RL) { 3136 Op1 = ISD::getSetCCSwappedOperands(Op1); 3137 std::swap(RL, RR); 3138 } 3139 if (LL == RL && LR == RR) { 3140 bool isInteger = LL.getValueType().isInteger(); 3141 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3142 if (Result != ISD::SETCC_INVALID && 3143 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3144 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3145 LL, LR, Result); 3146 } 3147 } 3148 3149 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3150 if (N0.getOpcode() == N1.getOpcode()) { 3151 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3152 if (Tmp.getNode()) return Tmp; 3153 } 3154 3155 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3156 if (N0.getOpcode() == ISD::AND && 3157 N1.getOpcode() == ISD::AND && 3158 N0.getOperand(1).getOpcode() == ISD::Constant && 3159 N1.getOperand(1).getOpcode() == ISD::Constant && 3160 // Don't increase # computations. 3161 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3162 // We can only do this xform if we know that bits from X that are set in C2 3163 // but not in C1 are already zero. Likewise for Y. 3164 const APInt &LHSMask = 3165 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3166 const APInt &RHSMask = 3167 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3168 3169 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3170 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3171 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3172 N0.getOperand(0), N1.getOperand(0)); 3173 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3174 DAG.getConstant(LHSMask | RHSMask, VT)); 3175 } 3176 } 3177 3178 // See if this is some rotate idiom. 3179 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3180 return SDValue(Rot, 0); 3181 3182 // Simplify the operands using demanded-bits information. 3183 if (!VT.isVector() && 3184 SimplifyDemandedBits(SDValue(N, 0))) 3185 return SDValue(N, 0); 3186 3187 return SDValue(); 3188} 3189 3190/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3191static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3192 if (Op.getOpcode() == ISD::AND) { 3193 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3194 Mask = Op.getOperand(1); 3195 Op = Op.getOperand(0); 3196 } else { 3197 return false; 3198 } 3199 } 3200 3201 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3202 Shift = Op; 3203 return true; 3204 } 3205 3206 return false; 3207} 3208 3209// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3210// idioms for rotate, and if the target supports rotation instructions, generate 3211// a rot[lr]. 3212SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3213 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3214 EVT VT = LHS.getValueType(); 3215 if (!TLI.isTypeLegal(VT)) return 0; 3216 3217 // The target must have at least one rotate flavor. 3218 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3219 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3220 if (!HasROTL && !HasROTR) return 0; 3221 3222 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3223 SDValue LHSShift; // The shift. 3224 SDValue LHSMask; // AND value if any. 3225 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3226 return 0; // Not part of a rotate. 3227 3228 SDValue RHSShift; // The shift. 3229 SDValue RHSMask; // AND value if any. 3230 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3231 return 0; // Not part of a rotate. 3232 3233 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3234 return 0; // Not shifting the same value. 3235 3236 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3237 return 0; // Shifts must disagree. 3238 3239 // Canonicalize shl to left side in a shl/srl pair. 3240 if (RHSShift.getOpcode() == ISD::SHL) { 3241 std::swap(LHS, RHS); 3242 std::swap(LHSShift, RHSShift); 3243 std::swap(LHSMask , RHSMask ); 3244 } 3245 3246 unsigned OpSizeInBits = VT.getSizeInBits(); 3247 SDValue LHSShiftArg = LHSShift.getOperand(0); 3248 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3249 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3250 3251 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3252 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3253 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3254 RHSShiftAmt.getOpcode() == ISD::Constant) { 3255 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3256 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3257 if ((LShVal + RShVal) != OpSizeInBits) 3258 return 0; 3259 3260 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3261 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt); 3262 3263 // If there is an AND of either shifted operand, apply it to the result. 3264 if (LHSMask.getNode() || RHSMask.getNode()) { 3265 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3266 3267 if (LHSMask.getNode()) { 3268 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3269 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3270 } 3271 if (RHSMask.getNode()) { 3272 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3273 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3274 } 3275 3276 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3277 } 3278 3279 return Rot.getNode(); 3280 } 3281 3282 // If there is a mask here, and we have a variable shift, we can't be sure 3283 // that we're masking out the right stuff. 3284 if (LHSMask.getNode() || RHSMask.getNode()) 3285 return 0; 3286 3287 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3288 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3289 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3290 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3291 if (ConstantSDNode *SUBC = 3292 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3293 if (SUBC->getAPIntValue() == OpSizeInBits) { 3294 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, 3295 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3296 } 3297 } 3298 } 3299 3300 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3301 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3302 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3303 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3304 if (ConstantSDNode *SUBC = 3305 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3306 if (SUBC->getAPIntValue() == OpSizeInBits) { 3307 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, 3308 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3309 } 3310 } 3311 } 3312 3313 // Look for sign/zext/any-extended or truncate cases: 3314 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3315 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3316 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3317 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3318 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3319 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3320 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3321 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3322 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3323 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3324 if (RExtOp0.getOpcode() == ISD::SUB && 3325 RExtOp0.getOperand(1) == LExtOp0) { 3326 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3327 // (rotl x, y) 3328 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3329 // (rotr x, (sub 32, y)) 3330 if (ConstantSDNode *SUBC = 3331 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3332 if (SUBC->getAPIntValue() == OpSizeInBits) { 3333 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3334 LHSShiftArg, 3335 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3336 } 3337 } 3338 } else if (LExtOp0.getOpcode() == ISD::SUB && 3339 RExtOp0 == LExtOp0.getOperand(1)) { 3340 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3341 // (rotr x, y) 3342 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3343 // (rotl x, (sub 32, y)) 3344 if (ConstantSDNode *SUBC = 3345 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3346 if (SUBC->getAPIntValue() == OpSizeInBits) { 3347 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3348 LHSShiftArg, 3349 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3350 } 3351 } 3352 } 3353 } 3354 3355 return 0; 3356} 3357 3358SDValue DAGCombiner::visitXOR(SDNode *N) { 3359 SDValue N0 = N->getOperand(0); 3360 SDValue N1 = N->getOperand(1); 3361 SDValue LHS, RHS, CC; 3362 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3364 EVT VT = N0.getValueType(); 3365 3366 // fold vector ops 3367 if (VT.isVector()) { 3368 SDValue FoldedVOp = SimplifyVBinOp(N); 3369 if (FoldedVOp.getNode()) return FoldedVOp; 3370 3371 // fold (xor x, 0) -> x, vector edition 3372 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3373 return N1; 3374 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3375 return N0; 3376 } 3377 3378 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3379 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3380 return DAG.getConstant(0, VT); 3381 // fold (xor x, undef) -> undef 3382 if (N0.getOpcode() == ISD::UNDEF) 3383 return N0; 3384 if (N1.getOpcode() == ISD::UNDEF) 3385 return N1; 3386 // fold (xor c1, c2) -> c1^c2 3387 if (N0C && N1C) 3388 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3389 // canonicalize constant to RHS 3390 if (N0C && !N1C) 3391 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3392 // fold (xor x, 0) -> x 3393 if (N1C && N1C->isNullValue()) 3394 return N0; 3395 // reassociate xor 3396 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3397 if (RXOR.getNode() != 0) 3398 return RXOR; 3399 3400 // fold !(x cc y) -> (x !cc y) 3401 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3402 bool isInt = LHS.getValueType().isInteger(); 3403 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3404 isInt); 3405 3406 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3407 switch (N0.getOpcode()) { 3408 default: 3409 llvm_unreachable("Unhandled SetCC Equivalent!"); 3410 case ISD::SETCC: 3411 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3412 case ISD::SELECT_CC: 3413 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3414 N0.getOperand(3), NotCC); 3415 } 3416 } 3417 } 3418 3419 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3420 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3421 N0.getNode()->hasOneUse() && 3422 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3423 SDValue V = N0.getOperand(0); 3424 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3425 DAG.getConstant(1, V.getValueType())); 3426 AddToWorkList(V.getNode()); 3427 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3428 } 3429 3430 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3431 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3432 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3433 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3434 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3435 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3436 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3437 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3438 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3439 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3440 } 3441 } 3442 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3443 if (N1C && N1C->isAllOnesValue() && 3444 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3445 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3446 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3447 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3448 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3449 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3450 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3451 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3452 } 3453 } 3454 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3455 if (N1C && N0.getOpcode() == ISD::XOR) { 3456 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3457 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3458 if (N00C) 3459 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3460 DAG.getConstant(N1C->getAPIntValue() ^ 3461 N00C->getAPIntValue(), VT)); 3462 if (N01C) 3463 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3464 DAG.getConstant(N1C->getAPIntValue() ^ 3465 N01C->getAPIntValue(), VT)); 3466 } 3467 // fold (xor x, x) -> 0 3468 if (N0 == N1) 3469 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3470 3471 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3472 if (N0.getOpcode() == N1.getOpcode()) { 3473 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3474 if (Tmp.getNode()) return Tmp; 3475 } 3476 3477 // Simplify the expression using non-local knowledge. 3478 if (!VT.isVector() && 3479 SimplifyDemandedBits(SDValue(N, 0))) 3480 return SDValue(N, 0); 3481 3482 return SDValue(); 3483} 3484 3485/// visitShiftByConstant - Handle transforms common to the three shifts, when 3486/// the shift amount is a constant. 3487SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3488 SDNode *LHS = N->getOperand(0).getNode(); 3489 if (!LHS->hasOneUse()) return SDValue(); 3490 3491 // We want to pull some binops through shifts, so that we have (and (shift)) 3492 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3493 // thing happens with address calculations, so it's important to canonicalize 3494 // it. 3495 bool HighBitSet = false; // Can we transform this if the high bit is set? 3496 3497 switch (LHS->getOpcode()) { 3498 default: return SDValue(); 3499 case ISD::OR: 3500 case ISD::XOR: 3501 HighBitSet = false; // We can only transform sra if the high bit is clear. 3502 break; 3503 case ISD::AND: 3504 HighBitSet = true; // We can only transform sra if the high bit is set. 3505 break; 3506 case ISD::ADD: 3507 if (N->getOpcode() != ISD::SHL) 3508 return SDValue(); // only shl(add) not sr[al](add). 3509 HighBitSet = false; // We can only transform sra if the high bit is clear. 3510 break; 3511 } 3512 3513 // We require the RHS of the binop to be a constant as well. 3514 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3515 if (!BinOpCst) return SDValue(); 3516 3517 // FIXME: disable this unless the input to the binop is a shift by a constant. 3518 // If it is not a shift, it pessimizes some common cases like: 3519 // 3520 // void foo(int *X, int i) { X[i & 1235] = 1; } 3521 // int bar(int *X, int i) { return X[i & 255]; } 3522 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3523 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3524 BinOpLHSVal->getOpcode() != ISD::SRA && 3525 BinOpLHSVal->getOpcode() != ISD::SRL) || 3526 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3527 return SDValue(); 3528 3529 EVT VT = N->getValueType(0); 3530 3531 // If this is a signed shift right, and the high bit is modified by the 3532 // logical operation, do not perform the transformation. The highBitSet 3533 // boolean indicates the value of the high bit of the constant which would 3534 // cause it to be modified for this operation. 3535 if (N->getOpcode() == ISD::SRA) { 3536 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3537 if (BinOpRHSSignSet != HighBitSet) 3538 return SDValue(); 3539 } 3540 3541 // Fold the constants, shifting the binop RHS by the shift amount. 3542 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3543 N->getValueType(0), 3544 LHS->getOperand(1), N->getOperand(1)); 3545 3546 // Create the new shift. 3547 SDValue NewShift = DAG.getNode(N->getOpcode(), 3548 LHS->getOperand(0).getDebugLoc(), 3549 VT, LHS->getOperand(0), N->getOperand(1)); 3550 3551 // Create the new binop. 3552 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3553} 3554 3555SDValue DAGCombiner::visitSHL(SDNode *N) { 3556 SDValue N0 = N->getOperand(0); 3557 SDValue N1 = N->getOperand(1); 3558 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3559 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3560 EVT VT = N0.getValueType(); 3561 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3562 3563 // fold (shl c1, c2) -> c1<<c2 3564 if (N0C && N1C) 3565 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3566 // fold (shl 0, x) -> 0 3567 if (N0C && N0C->isNullValue()) 3568 return N0; 3569 // fold (shl x, c >= size(x)) -> undef 3570 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3571 return DAG.getUNDEF(VT); 3572 // fold (shl x, 0) -> x 3573 if (N1C && N1C->isNullValue()) 3574 return N0; 3575 // fold (shl undef, x) -> 0 3576 if (N0.getOpcode() == ISD::UNDEF) 3577 return DAG.getConstant(0, VT); 3578 // if (shl x, c) is known to be zero, return 0 3579 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3580 APInt::getAllOnesValue(OpSizeInBits))) 3581 return DAG.getConstant(0, VT); 3582 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3583 if (N1.getOpcode() == ISD::TRUNCATE && 3584 N1.getOperand(0).getOpcode() == ISD::AND && 3585 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3586 SDValue N101 = N1.getOperand(0).getOperand(1); 3587 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3588 EVT TruncVT = N1.getValueType(); 3589 SDValue N100 = N1.getOperand(0).getOperand(0); 3590 APInt TruncC = N101C->getAPIntValue(); 3591 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3592 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3593 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3594 DAG.getNode(ISD::TRUNCATE, 3595 N->getDebugLoc(), 3596 TruncVT, N100), 3597 DAG.getConstant(TruncC, TruncVT))); 3598 } 3599 } 3600 3601 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3602 return SDValue(N, 0); 3603 3604 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3605 if (N1C && N0.getOpcode() == ISD::SHL && 3606 N0.getOperand(1).getOpcode() == ISD::Constant) { 3607 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3608 uint64_t c2 = N1C->getZExtValue(); 3609 if (c1 + c2 >= OpSizeInBits) 3610 return DAG.getConstant(0, VT); 3611 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3612 DAG.getConstant(c1 + c2, N1.getValueType())); 3613 } 3614 3615 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3616 // For this to be valid, the second form must not preserve any of the bits 3617 // that are shifted out by the inner shift in the first form. This means 3618 // the outer shift size must be >= the number of bits added by the ext. 3619 // As a corollary, we don't care what kind of ext it is. 3620 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3621 N0.getOpcode() == ISD::ANY_EXTEND || 3622 N0.getOpcode() == ISD::SIGN_EXTEND) && 3623 N0.getOperand(0).getOpcode() == ISD::SHL && 3624 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3625 uint64_t c1 = 3626 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3627 uint64_t c2 = N1C->getZExtValue(); 3628 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3629 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3630 if (c2 >= OpSizeInBits - InnerShiftSize) { 3631 if (c1 + c2 >= OpSizeInBits) 3632 return DAG.getConstant(0, VT); 3633 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3634 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3635 N0.getOperand(0)->getOperand(0)), 3636 DAG.getConstant(c1 + c2, N1.getValueType())); 3637 } 3638 } 3639 3640 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3641 // (and (srl x, (sub c1, c2), MASK) 3642 // Only fold this if the inner shift has no other uses -- if it does, folding 3643 // this will increase the total number of instructions. 3644 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3645 N0.getOperand(1).getOpcode() == ISD::Constant) { 3646 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3647 if (c1 < VT.getSizeInBits()) { 3648 uint64_t c2 = N1C->getZExtValue(); 3649 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3650 VT.getSizeInBits() - c1); 3651 SDValue Shift; 3652 if (c2 > c1) { 3653 Mask = Mask.shl(c2-c1); 3654 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3655 DAG.getConstant(c2-c1, N1.getValueType())); 3656 } else { 3657 Mask = Mask.lshr(c1-c2); 3658 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3659 DAG.getConstant(c1-c2, N1.getValueType())); 3660 } 3661 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3662 DAG.getConstant(Mask, VT)); 3663 } 3664 } 3665 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3666 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3667 SDValue HiBitsMask = 3668 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3669 VT.getSizeInBits() - 3670 N1C->getZExtValue()), 3671 VT); 3672 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3673 HiBitsMask); 3674 } 3675 3676 if (N1C) { 3677 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3678 if (NewSHL.getNode()) 3679 return NewSHL; 3680 } 3681 3682 return SDValue(); 3683} 3684 3685SDValue DAGCombiner::visitSRA(SDNode *N) { 3686 SDValue N0 = N->getOperand(0); 3687 SDValue N1 = N->getOperand(1); 3688 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3689 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3690 EVT VT = N0.getValueType(); 3691 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3692 3693 // fold (sra c1, c2) -> (sra c1, c2) 3694 if (N0C && N1C) 3695 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3696 // fold (sra 0, x) -> 0 3697 if (N0C && N0C->isNullValue()) 3698 return N0; 3699 // fold (sra -1, x) -> -1 3700 if (N0C && N0C->isAllOnesValue()) 3701 return N0; 3702 // fold (sra x, (setge c, size(x))) -> undef 3703 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3704 return DAG.getUNDEF(VT); 3705 // fold (sra x, 0) -> x 3706 if (N1C && N1C->isNullValue()) 3707 return N0; 3708 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3709 // sext_inreg. 3710 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3711 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3712 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3713 if (VT.isVector()) 3714 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3715 ExtVT, VT.getVectorNumElements()); 3716 if ((!LegalOperations || 3717 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3718 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3719 N0.getOperand(0), DAG.getValueType(ExtVT)); 3720 } 3721 3722 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3723 if (N1C && N0.getOpcode() == ISD::SRA) { 3724 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3725 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3726 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3727 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3728 DAG.getConstant(Sum, N1C->getValueType(0))); 3729 } 3730 } 3731 3732 // fold (sra (shl X, m), (sub result_size, n)) 3733 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3734 // result_size - n != m. 3735 // If truncate is free for the target sext(shl) is likely to result in better 3736 // code. 3737 if (N0.getOpcode() == ISD::SHL) { 3738 // Get the two constanst of the shifts, CN0 = m, CN = n. 3739 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3740 if (N01C && N1C) { 3741 // Determine what the truncate's result bitsize and type would be. 3742 EVT TruncVT = 3743 EVT::getIntegerVT(*DAG.getContext(), 3744 OpSizeInBits - N1C->getZExtValue()); 3745 // Determine the residual right-shift amount. 3746 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3747 3748 // If the shift is not a no-op (in which case this should be just a sign 3749 // extend already), the truncated to type is legal, sign_extend is legal 3750 // on that type, and the truncate to that type is both legal and free, 3751 // perform the transform. 3752 if ((ShiftAmt > 0) && 3753 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3754 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3755 TLI.isTruncateFree(VT, TruncVT)) { 3756 3757 SDValue Amt = DAG.getConstant(ShiftAmt, 3758 getShiftAmountTy(N0.getOperand(0).getValueType())); 3759 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3760 N0.getOperand(0), Amt); 3761 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3762 Shift); 3763 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3764 N->getValueType(0), Trunc); 3765 } 3766 } 3767 } 3768 3769 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3770 if (N1.getOpcode() == ISD::TRUNCATE && 3771 N1.getOperand(0).getOpcode() == ISD::AND && 3772 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3773 SDValue N101 = N1.getOperand(0).getOperand(1); 3774 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3775 EVT TruncVT = N1.getValueType(); 3776 SDValue N100 = N1.getOperand(0).getOperand(0); 3777 APInt TruncC = N101C->getAPIntValue(); 3778 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3779 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3780 DAG.getNode(ISD::AND, N->getDebugLoc(), 3781 TruncVT, 3782 DAG.getNode(ISD::TRUNCATE, 3783 N->getDebugLoc(), 3784 TruncVT, N100), 3785 DAG.getConstant(TruncC, TruncVT))); 3786 } 3787 } 3788 3789 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3790 // if c1 is equal to the number of bits the trunc removes 3791 if (N0.getOpcode() == ISD::TRUNCATE && 3792 (N0.getOperand(0).getOpcode() == ISD::SRL || 3793 N0.getOperand(0).getOpcode() == ISD::SRA) && 3794 N0.getOperand(0).hasOneUse() && 3795 N0.getOperand(0).getOperand(1).hasOneUse() && 3796 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3797 EVT LargeVT = N0.getOperand(0).getValueType(); 3798 ConstantSDNode *LargeShiftAmt = 3799 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3800 3801 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3802 LargeShiftAmt->getZExtValue()) { 3803 SDValue Amt = 3804 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3805 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3806 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3807 N0.getOperand(0).getOperand(0), Amt); 3808 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3809 } 3810 } 3811 3812 // Simplify, based on bits shifted out of the LHS. 3813 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3814 return SDValue(N, 0); 3815 3816 3817 // If the sign bit is known to be zero, switch this to a SRL. 3818 if (DAG.SignBitIsZero(N0)) 3819 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3820 3821 if (N1C) { 3822 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3823 if (NewSRA.getNode()) 3824 return NewSRA; 3825 } 3826 3827 return SDValue(); 3828} 3829 3830SDValue DAGCombiner::visitSRL(SDNode *N) { 3831 SDValue N0 = N->getOperand(0); 3832 SDValue N1 = N->getOperand(1); 3833 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3834 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3835 EVT VT = N0.getValueType(); 3836 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3837 3838 // fold (srl c1, c2) -> c1 >>u c2 3839 if (N0C && N1C) 3840 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3841 // fold (srl 0, x) -> 0 3842 if (N0C && N0C->isNullValue()) 3843 return N0; 3844 // fold (srl x, c >= size(x)) -> undef 3845 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3846 return DAG.getUNDEF(VT); 3847 // fold (srl x, 0) -> x 3848 if (N1C && N1C->isNullValue()) 3849 return N0; 3850 // if (srl x, c) is known to be zero, return 0 3851 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3852 APInt::getAllOnesValue(OpSizeInBits))) 3853 return DAG.getConstant(0, VT); 3854 3855 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3856 if (N1C && N0.getOpcode() == ISD::SRL && 3857 N0.getOperand(1).getOpcode() == ISD::Constant) { 3858 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3859 uint64_t c2 = N1C->getZExtValue(); 3860 if (c1 + c2 >= OpSizeInBits) 3861 return DAG.getConstant(0, VT); 3862 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3863 DAG.getConstant(c1 + c2, N1.getValueType())); 3864 } 3865 3866 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3867 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3868 N0.getOperand(0).getOpcode() == ISD::SRL && 3869 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3870 uint64_t c1 = 3871 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3872 uint64_t c2 = N1C->getZExtValue(); 3873 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3874 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3875 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3876 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3877 if (c1 + OpSizeInBits == InnerShiftSize) { 3878 if (c1 + c2 >= InnerShiftSize) 3879 return DAG.getConstant(0, VT); 3880 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3881 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3882 N0.getOperand(0)->getOperand(0), 3883 DAG.getConstant(c1 + c2, ShiftCountVT))); 3884 } 3885 } 3886 3887 // fold (srl (shl x, c), c) -> (and x, cst2) 3888 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3889 N0.getValueSizeInBits() <= 64) { 3890 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3891 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3892 DAG.getConstant(~0ULL >> ShAmt, VT)); 3893 } 3894 3895 3896 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3897 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3898 // Shifting in all undef bits? 3899 EVT SmallVT = N0.getOperand(0).getValueType(); 3900 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3901 return DAG.getUNDEF(VT); 3902 3903 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3904 uint64_t ShiftAmt = N1C->getZExtValue(); 3905 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3906 N0.getOperand(0), 3907 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3908 AddToWorkList(SmallShift.getNode()); 3909 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3910 } 3911 } 3912 3913 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3914 // bit, which is unmodified by sra. 3915 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3916 if (N0.getOpcode() == ISD::SRA) 3917 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3918 } 3919 3920 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3921 if (N1C && N0.getOpcode() == ISD::CTLZ && 3922 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3923 APInt KnownZero, KnownOne; 3924 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3925 3926 // If any of the input bits are KnownOne, then the input couldn't be all 3927 // zeros, thus the result of the srl will always be zero. 3928 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3929 3930 // If all of the bits input the to ctlz node are known to be zero, then 3931 // the result of the ctlz is "32" and the result of the shift is one. 3932 APInt UnknownBits = ~KnownZero; 3933 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3934 3935 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3936 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3937 // Okay, we know that only that the single bit specified by UnknownBits 3938 // could be set on input to the CTLZ node. If this bit is set, the SRL 3939 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3940 // to an SRL/XOR pair, which is likely to simplify more. 3941 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3942 SDValue Op = N0.getOperand(0); 3943 3944 if (ShAmt) { 3945 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3946 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3947 AddToWorkList(Op.getNode()); 3948 } 3949 3950 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3951 Op, DAG.getConstant(1, VT)); 3952 } 3953 } 3954 3955 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3956 if (N1.getOpcode() == ISD::TRUNCATE && 3957 N1.getOperand(0).getOpcode() == ISD::AND && 3958 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3959 SDValue N101 = N1.getOperand(0).getOperand(1); 3960 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3961 EVT TruncVT = N1.getValueType(); 3962 SDValue N100 = N1.getOperand(0).getOperand(0); 3963 APInt TruncC = N101C->getAPIntValue(); 3964 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3965 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3966 DAG.getNode(ISD::AND, N->getDebugLoc(), 3967 TruncVT, 3968 DAG.getNode(ISD::TRUNCATE, 3969 N->getDebugLoc(), 3970 TruncVT, N100), 3971 DAG.getConstant(TruncC, TruncVT))); 3972 } 3973 } 3974 3975 // fold operands of srl based on knowledge that the low bits are not 3976 // demanded. 3977 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3978 return SDValue(N, 0); 3979 3980 if (N1C) { 3981 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3982 if (NewSRL.getNode()) 3983 return NewSRL; 3984 } 3985 3986 // Attempt to convert a srl of a load into a narrower zero-extending load. 3987 SDValue NarrowLoad = ReduceLoadWidth(N); 3988 if (NarrowLoad.getNode()) 3989 return NarrowLoad; 3990 3991 // Here is a common situation. We want to optimize: 3992 // 3993 // %a = ... 3994 // %b = and i32 %a, 2 3995 // %c = srl i32 %b, 1 3996 // brcond i32 %c ... 3997 // 3998 // into 3999 // 4000 // %a = ... 4001 // %b = and %a, 2 4002 // %c = setcc eq %b, 0 4003 // brcond %c ... 4004 // 4005 // However when after the source operand of SRL is optimized into AND, the SRL 4006 // itself may not be optimized further. Look for it and add the BRCOND into 4007 // the worklist. 4008 if (N->hasOneUse()) { 4009 SDNode *Use = *N->use_begin(); 4010 if (Use->getOpcode() == ISD::BRCOND) 4011 AddToWorkList(Use); 4012 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 4013 // Also look pass the truncate. 4014 Use = *Use->use_begin(); 4015 if (Use->getOpcode() == ISD::BRCOND) 4016 AddToWorkList(Use); 4017 } 4018 } 4019 4020 return SDValue(); 4021} 4022 4023SDValue DAGCombiner::visitCTLZ(SDNode *N) { 4024 SDValue N0 = N->getOperand(0); 4025 EVT VT = N->getValueType(0); 4026 4027 // fold (ctlz c1) -> c2 4028 if (isa<ConstantSDNode>(N0)) 4029 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 4030 return SDValue(); 4031} 4032 4033SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 4034 SDValue N0 = N->getOperand(0); 4035 EVT VT = N->getValueType(0); 4036 4037 // fold (ctlz_zero_undef c1) -> c2 4038 if (isa<ConstantSDNode>(N0)) 4039 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4040 return SDValue(); 4041} 4042 4043SDValue DAGCombiner::visitCTTZ(SDNode *N) { 4044 SDValue N0 = N->getOperand(0); 4045 EVT VT = N->getValueType(0); 4046 4047 // fold (cttz c1) -> c2 4048 if (isa<ConstantSDNode>(N0)) 4049 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 4050 return SDValue(); 4051} 4052 4053SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4054 SDValue N0 = N->getOperand(0); 4055 EVT VT = N->getValueType(0); 4056 4057 // fold (cttz_zero_undef c1) -> c2 4058 if (isa<ConstantSDNode>(N0)) 4059 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4060 return SDValue(); 4061} 4062 4063SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4064 SDValue N0 = N->getOperand(0); 4065 EVT VT = N->getValueType(0); 4066 4067 // fold (ctpop c1) -> c2 4068 if (isa<ConstantSDNode>(N0)) 4069 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 4070 return SDValue(); 4071} 4072 4073SDValue DAGCombiner::visitSELECT(SDNode *N) { 4074 SDValue N0 = N->getOperand(0); 4075 SDValue N1 = N->getOperand(1); 4076 SDValue N2 = N->getOperand(2); 4077 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4078 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4079 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4080 EVT VT = N->getValueType(0); 4081 EVT VT0 = N0.getValueType(); 4082 4083 // fold (select C, X, X) -> X 4084 if (N1 == N2) 4085 return N1; 4086 // fold (select true, X, Y) -> X 4087 if (N0C && !N0C->isNullValue()) 4088 return N1; 4089 // fold (select false, X, Y) -> Y 4090 if (N0C && N0C->isNullValue()) 4091 return N2; 4092 // fold (select C, 1, X) -> (or C, X) 4093 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4094 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4095 // fold (select C, 0, 1) -> (xor C, 1) 4096 if (VT.isInteger() && 4097 (VT0 == MVT::i1 || 4098 (VT0.isInteger() && 4099 TLI.getBooleanContents(false) == 4100 TargetLowering::ZeroOrOneBooleanContent)) && 4101 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4102 SDValue XORNode; 4103 if (VT == VT0) 4104 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4105 N0, DAG.getConstant(1, VT0)); 4106 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4107 N0, DAG.getConstant(1, VT0)); 4108 AddToWorkList(XORNode.getNode()); 4109 if (VT.bitsGT(VT0)) 4110 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4111 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4112 } 4113 // fold (select C, 0, X) -> (and (not C), X) 4114 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4115 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4116 AddToWorkList(NOTNode.getNode()); 4117 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4118 } 4119 // fold (select C, X, 1) -> (or (not C), X) 4120 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4121 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4122 AddToWorkList(NOTNode.getNode()); 4123 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4124 } 4125 // fold (select C, X, 0) -> (and C, X) 4126 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4127 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4128 // fold (select X, X, Y) -> (or X, Y) 4129 // fold (select X, 1, Y) -> (or X, Y) 4130 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4131 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4132 // fold (select X, Y, X) -> (and X, Y) 4133 // fold (select X, Y, 0) -> (and X, Y) 4134 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4135 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4136 4137 // If we can fold this based on the true/false value, do so. 4138 if (SimplifySelectOps(N, N1, N2)) 4139 return SDValue(N, 0); // Don't revisit N. 4140 4141 // fold selects based on a setcc into other things, such as min/max/abs 4142 if (N0.getOpcode() == ISD::SETCC) { 4143 // FIXME: 4144 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4145 // having to say they don't support SELECT_CC on every type the DAG knows 4146 // about, since there is no way to mark an opcode illegal at all value types 4147 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4148 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4149 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4150 N0.getOperand(0), N0.getOperand(1), 4151 N1, N2, N0.getOperand(2)); 4152 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4153 } 4154 4155 return SDValue(); 4156} 4157 4158SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4159 SDValue N0 = N->getOperand(0); 4160 SDValue N1 = N->getOperand(1); 4161 SDValue N2 = N->getOperand(2); 4162 SDValue N3 = N->getOperand(3); 4163 SDValue N4 = N->getOperand(4); 4164 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4165 4166 // fold select_cc lhs, rhs, x, x, cc -> x 4167 if (N2 == N3) 4168 return N2; 4169 4170 // Determine if the condition we're dealing with is constant 4171 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4172 N0, N1, CC, N->getDebugLoc(), false); 4173 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4174 4175 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4176 if (!SCCC->isNullValue()) 4177 return N2; // cond always true -> true val 4178 else 4179 return N3; // cond always false -> false val 4180 } 4181 4182 // Fold to a simpler select_cc 4183 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4184 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4185 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4186 SCC.getOperand(2)); 4187 4188 // If we can fold this based on the true/false value, do so. 4189 if (SimplifySelectOps(N, N2, N3)) 4190 return SDValue(N, 0); // Don't revisit N. 4191 4192 // fold select_cc into other things, such as min/max/abs 4193 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4194} 4195 4196SDValue DAGCombiner::visitSETCC(SDNode *N) { 4197 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4198 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4199 N->getDebugLoc()); 4200} 4201 4202// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4203// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4204// transformation. Returns true if extension are possible and the above 4205// mentioned transformation is profitable. 4206static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4207 unsigned ExtOpc, 4208 SmallVector<SDNode*, 4> &ExtendNodes, 4209 const TargetLowering &TLI) { 4210 bool HasCopyToRegUses = false; 4211 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4212 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4213 UE = N0.getNode()->use_end(); 4214 UI != UE; ++UI) { 4215 SDNode *User = *UI; 4216 if (User == N) 4217 continue; 4218 if (UI.getUse().getResNo() != N0.getResNo()) 4219 continue; 4220 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4221 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4222 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4223 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4224 // Sign bits will be lost after a zext. 4225 return false; 4226 bool Add = false; 4227 for (unsigned i = 0; i != 2; ++i) { 4228 SDValue UseOp = User->getOperand(i); 4229 if (UseOp == N0) 4230 continue; 4231 if (!isa<ConstantSDNode>(UseOp)) 4232 return false; 4233 Add = true; 4234 } 4235 if (Add) 4236 ExtendNodes.push_back(User); 4237 continue; 4238 } 4239 // If truncates aren't free and there are users we can't 4240 // extend, it isn't worthwhile. 4241 if (!isTruncFree) 4242 return false; 4243 // Remember if this value is live-out. 4244 if (User->getOpcode() == ISD::CopyToReg) 4245 HasCopyToRegUses = true; 4246 } 4247 4248 if (HasCopyToRegUses) { 4249 bool BothLiveOut = false; 4250 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4251 UI != UE; ++UI) { 4252 SDUse &Use = UI.getUse(); 4253 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4254 BothLiveOut = true; 4255 break; 4256 } 4257 } 4258 if (BothLiveOut) 4259 // Both unextended and extended values are live out. There had better be 4260 // a good reason for the transformation. 4261 return ExtendNodes.size(); 4262 } 4263 return true; 4264} 4265 4266void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4267 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4268 ISD::NodeType ExtType) { 4269 // Extend SetCC uses if necessary. 4270 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4271 SDNode *SetCC = SetCCs[i]; 4272 SmallVector<SDValue, 4> Ops; 4273 4274 for (unsigned j = 0; j != 2; ++j) { 4275 SDValue SOp = SetCC->getOperand(j); 4276 if (SOp == Trunc) 4277 Ops.push_back(ExtLoad); 4278 else 4279 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4280 } 4281 4282 Ops.push_back(SetCC->getOperand(2)); 4283 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4284 &Ops[0], Ops.size())); 4285 } 4286} 4287 4288SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4289 SDValue N0 = N->getOperand(0); 4290 EVT VT = N->getValueType(0); 4291 4292 // fold (sext c1) -> c1 4293 if (isa<ConstantSDNode>(N0)) 4294 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4295 4296 // fold (sext (sext x)) -> (sext x) 4297 // fold (sext (aext x)) -> (sext x) 4298 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4299 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4300 N0.getOperand(0)); 4301 4302 if (N0.getOpcode() == ISD::TRUNCATE) { 4303 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4304 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4305 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4306 if (NarrowLoad.getNode()) { 4307 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4308 if (NarrowLoad.getNode() != N0.getNode()) { 4309 CombineTo(N0.getNode(), NarrowLoad); 4310 // CombineTo deleted the truncate, if needed, but not what's under it. 4311 AddToWorkList(oye); 4312 } 4313 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4314 } 4315 4316 // See if the value being truncated is already sign extended. If so, just 4317 // eliminate the trunc/sext pair. 4318 SDValue Op = N0.getOperand(0); 4319 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4320 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4321 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4322 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4323 4324 if (OpBits == DestBits) { 4325 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4326 // bits, it is already ready. 4327 if (NumSignBits > DestBits-MidBits) 4328 return Op; 4329 } else if (OpBits < DestBits) { 4330 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4331 // bits, just sext from i32. 4332 if (NumSignBits > OpBits-MidBits) 4333 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4334 } else { 4335 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4336 // bits, just truncate to i32. 4337 if (NumSignBits > OpBits-MidBits) 4338 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4339 } 4340 4341 // fold (sext (truncate x)) -> (sextinreg x). 4342 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4343 N0.getValueType())) { 4344 if (OpBits < DestBits) 4345 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4346 else if (OpBits > DestBits) 4347 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4348 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4349 DAG.getValueType(N0.getValueType())); 4350 } 4351 } 4352 4353 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4354 // None of the supported targets knows how to perform load and sign extend 4355 // on vectors in one instruction. We only perform this transformation on 4356 // scalars. 4357 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4358 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4359 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4360 bool DoXform = true; 4361 SmallVector<SDNode*, 4> SetCCs; 4362 if (!N0.hasOneUse()) 4363 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4364 if (DoXform) { 4365 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4366 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4367 LN0->getChain(), 4368 LN0->getBasePtr(), LN0->getPointerInfo(), 4369 N0.getValueType(), 4370 LN0->isVolatile(), LN0->isNonTemporal(), 4371 LN0->getAlignment()); 4372 CombineTo(N, ExtLoad); 4373 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4374 N0.getValueType(), ExtLoad); 4375 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4376 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4377 ISD::SIGN_EXTEND); 4378 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4379 } 4380 } 4381 4382 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4383 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4384 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4385 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4386 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4387 EVT MemVT = LN0->getMemoryVT(); 4388 if ((!LegalOperations && !LN0->isVolatile()) || 4389 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4390 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4391 LN0->getChain(), 4392 LN0->getBasePtr(), LN0->getPointerInfo(), 4393 MemVT, 4394 LN0->isVolatile(), LN0->isNonTemporal(), 4395 LN0->getAlignment()); 4396 CombineTo(N, ExtLoad); 4397 CombineTo(N0.getNode(), 4398 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4399 N0.getValueType(), ExtLoad), 4400 ExtLoad.getValue(1)); 4401 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4402 } 4403 } 4404 4405 // fold (sext (and/or/xor (load x), cst)) -> 4406 // (and/or/xor (sextload x), (sext cst)) 4407 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4408 N0.getOpcode() == ISD::XOR) && 4409 isa<LoadSDNode>(N0.getOperand(0)) && 4410 N0.getOperand(1).getOpcode() == ISD::Constant && 4411 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4412 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4413 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4414 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4415 bool DoXform = true; 4416 SmallVector<SDNode*, 4> SetCCs; 4417 if (!N0.hasOneUse()) 4418 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4419 SetCCs, TLI); 4420 if (DoXform) { 4421 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4422 LN0->getChain(), LN0->getBasePtr(), 4423 LN0->getPointerInfo(), 4424 LN0->getMemoryVT(), 4425 LN0->isVolatile(), 4426 LN0->isNonTemporal(), 4427 LN0->getAlignment()); 4428 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4429 Mask = Mask.sext(VT.getSizeInBits()); 4430 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4431 ExtLoad, DAG.getConstant(Mask, VT)); 4432 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4433 N0.getOperand(0).getDebugLoc(), 4434 N0.getOperand(0).getValueType(), ExtLoad); 4435 CombineTo(N, And); 4436 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4437 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4438 ISD::SIGN_EXTEND); 4439 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4440 } 4441 } 4442 } 4443 4444 if (N0.getOpcode() == ISD::SETCC) { 4445 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4446 // Only do this before legalize for now. 4447 if (VT.isVector() && !LegalOperations) { 4448 EVT N0VT = N0.getOperand(0).getValueType(); 4449 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4450 // of the same size as the compared operands. Only optimize sext(setcc()) 4451 // if this is the case. 4452 EVT SVT = TLI.getSetCCResultType(N0VT); 4453 4454 // We know that the # elements of the results is the same as the 4455 // # elements of the compare (and the # elements of the compare result 4456 // for that matter). Check to see that they are the same size. If so, 4457 // we know that the element size of the sext'd result matches the 4458 // element size of the compare operands. 4459 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4460 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4461 N0.getOperand(1), 4462 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4463 // If the desired elements are smaller or larger than the source 4464 // elements we can use a matching integer vector type and then 4465 // truncate/sign extend 4466 EVT MatchingElementType = 4467 EVT::getIntegerVT(*DAG.getContext(), 4468 N0VT.getScalarType().getSizeInBits()); 4469 EVT MatchingVectorType = 4470 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4471 N0VT.getVectorNumElements()); 4472 4473 if (SVT == MatchingVectorType) { 4474 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4475 N0.getOperand(0), N0.getOperand(1), 4476 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4477 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4478 } 4479 } 4480 4481 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4482 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4483 SDValue NegOne = 4484 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4485 SDValue SCC = 4486 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4487 NegOne, DAG.getConstant(0, VT), 4488 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4489 if (SCC.getNode()) return SCC; 4490 if (!LegalOperations || 4491 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4492 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4493 DAG.getSetCC(N->getDebugLoc(), 4494 TLI.getSetCCResultType(VT), 4495 N0.getOperand(0), N0.getOperand(1), 4496 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4497 NegOne, DAG.getConstant(0, VT)); 4498 } 4499 4500 // fold (sext x) -> (zext x) if the sign bit is known zero. 4501 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4502 DAG.SignBitIsZero(N0)) 4503 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4504 4505 return SDValue(); 4506} 4507 4508// isTruncateOf - If N is a truncate of some other value, return true, record 4509// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4510// This function computes KnownZero to avoid a duplicated call to 4511// ComputeMaskedBits in the caller. 4512static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4513 APInt &KnownZero) { 4514 APInt KnownOne; 4515 if (N->getOpcode() == ISD::TRUNCATE) { 4516 Op = N->getOperand(0); 4517 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4518 return true; 4519 } 4520 4521 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4522 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4523 return false; 4524 4525 SDValue Op0 = N->getOperand(0); 4526 SDValue Op1 = N->getOperand(1); 4527 assert(Op0.getValueType() == Op1.getValueType()); 4528 4529 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4530 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4531 if (COp0 && COp0->isNullValue()) 4532 Op = Op1; 4533 else if (COp1 && COp1->isNullValue()) 4534 Op = Op0; 4535 else 4536 return false; 4537 4538 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4539 4540 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4541 return false; 4542 4543 return true; 4544} 4545 4546SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4547 SDValue N0 = N->getOperand(0); 4548 EVT VT = N->getValueType(0); 4549 4550 // fold (zext c1) -> c1 4551 if (isa<ConstantSDNode>(N0)) 4552 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4553 // fold (zext (zext x)) -> (zext x) 4554 // fold (zext (aext x)) -> (zext x) 4555 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4556 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4557 N0.getOperand(0)); 4558 4559 // fold (zext (truncate x)) -> (zext x) or 4560 // (zext (truncate x)) -> (truncate x) 4561 // This is valid when the truncated bits of x are already zero. 4562 // FIXME: We should extend this to work for vectors too. 4563 SDValue Op; 4564 APInt KnownZero; 4565 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4566 APInt TruncatedBits = 4567 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4568 APInt(Op.getValueSizeInBits(), 0) : 4569 APInt::getBitsSet(Op.getValueSizeInBits(), 4570 N0.getValueSizeInBits(), 4571 std::min(Op.getValueSizeInBits(), 4572 VT.getSizeInBits())); 4573 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4574 if (VT.bitsGT(Op.getValueType())) 4575 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4576 if (VT.bitsLT(Op.getValueType())) 4577 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4578 4579 return Op; 4580 } 4581 } 4582 4583 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4584 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4585 if (N0.getOpcode() == ISD::TRUNCATE) { 4586 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4587 if (NarrowLoad.getNode()) { 4588 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4589 if (NarrowLoad.getNode() != N0.getNode()) { 4590 CombineTo(N0.getNode(), NarrowLoad); 4591 // CombineTo deleted the truncate, if needed, but not what's under it. 4592 AddToWorkList(oye); 4593 } 4594 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4595 } 4596 } 4597 4598 // fold (zext (truncate x)) -> (and x, mask) 4599 if (N0.getOpcode() == ISD::TRUNCATE && 4600 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4601 4602 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4603 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4604 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4605 if (NarrowLoad.getNode()) { 4606 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4607 if (NarrowLoad.getNode() != N0.getNode()) { 4608 CombineTo(N0.getNode(), NarrowLoad); 4609 // CombineTo deleted the truncate, if needed, but not what's under it. 4610 AddToWorkList(oye); 4611 } 4612 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4613 } 4614 4615 SDValue Op = N0.getOperand(0); 4616 if (Op.getValueType().bitsLT(VT)) { 4617 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4618 AddToWorkList(Op.getNode()); 4619 } else if (Op.getValueType().bitsGT(VT)) { 4620 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4621 AddToWorkList(Op.getNode()); 4622 } 4623 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4624 N0.getValueType().getScalarType()); 4625 } 4626 4627 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4628 // if either of the casts is not free. 4629 if (N0.getOpcode() == ISD::AND && 4630 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4631 N0.getOperand(1).getOpcode() == ISD::Constant && 4632 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4633 N0.getValueType()) || 4634 !TLI.isZExtFree(N0.getValueType(), VT))) { 4635 SDValue X = N0.getOperand(0).getOperand(0); 4636 if (X.getValueType().bitsLT(VT)) { 4637 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4638 } else if (X.getValueType().bitsGT(VT)) { 4639 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4640 } 4641 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4642 Mask = Mask.zext(VT.getSizeInBits()); 4643 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4644 X, DAG.getConstant(Mask, VT)); 4645 } 4646 4647 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4648 // None of the supported targets knows how to perform load and vector_zext 4649 // on vectors in one instruction. We only perform this transformation on 4650 // scalars. 4651 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4652 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4653 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4654 bool DoXform = true; 4655 SmallVector<SDNode*, 4> SetCCs; 4656 if (!N0.hasOneUse()) 4657 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4658 if (DoXform) { 4659 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4660 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4661 LN0->getChain(), 4662 LN0->getBasePtr(), LN0->getPointerInfo(), 4663 N0.getValueType(), 4664 LN0->isVolatile(), LN0->isNonTemporal(), 4665 LN0->getAlignment()); 4666 CombineTo(N, ExtLoad); 4667 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4668 N0.getValueType(), ExtLoad); 4669 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4670 4671 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4672 ISD::ZERO_EXTEND); 4673 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4674 } 4675 } 4676 4677 // fold (zext (and/or/xor (load x), cst)) -> 4678 // (and/or/xor (zextload x), (zext cst)) 4679 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4680 N0.getOpcode() == ISD::XOR) && 4681 isa<LoadSDNode>(N0.getOperand(0)) && 4682 N0.getOperand(1).getOpcode() == ISD::Constant && 4683 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4684 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4685 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4686 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4687 bool DoXform = true; 4688 SmallVector<SDNode*, 4> SetCCs; 4689 if (!N0.hasOneUse()) 4690 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4691 SetCCs, TLI); 4692 if (DoXform) { 4693 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4694 LN0->getChain(), LN0->getBasePtr(), 4695 LN0->getPointerInfo(), 4696 LN0->getMemoryVT(), 4697 LN0->isVolatile(), 4698 LN0->isNonTemporal(), 4699 LN0->getAlignment()); 4700 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4701 Mask = Mask.zext(VT.getSizeInBits()); 4702 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4703 ExtLoad, DAG.getConstant(Mask, VT)); 4704 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4705 N0.getOperand(0).getDebugLoc(), 4706 N0.getOperand(0).getValueType(), ExtLoad); 4707 CombineTo(N, And); 4708 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4709 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4710 ISD::ZERO_EXTEND); 4711 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4712 } 4713 } 4714 } 4715 4716 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4717 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4718 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4719 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4720 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4721 EVT MemVT = LN0->getMemoryVT(); 4722 if ((!LegalOperations && !LN0->isVolatile()) || 4723 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4724 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4725 LN0->getChain(), 4726 LN0->getBasePtr(), LN0->getPointerInfo(), 4727 MemVT, 4728 LN0->isVolatile(), LN0->isNonTemporal(), 4729 LN0->getAlignment()); 4730 CombineTo(N, ExtLoad); 4731 CombineTo(N0.getNode(), 4732 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4733 ExtLoad), 4734 ExtLoad.getValue(1)); 4735 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4736 } 4737 } 4738 4739 if (N0.getOpcode() == ISD::SETCC) { 4740 if (!LegalOperations && VT.isVector()) { 4741 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4742 // Only do this before legalize for now. 4743 EVT N0VT = N0.getOperand(0).getValueType(); 4744 EVT EltVT = VT.getVectorElementType(); 4745 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4746 DAG.getConstant(1, EltVT)); 4747 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4748 // We know that the # elements of the results is the same as the 4749 // # elements of the compare (and the # elements of the compare result 4750 // for that matter). Check to see that they are the same size. If so, 4751 // we know that the element size of the sext'd result matches the 4752 // element size of the compare operands. 4753 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4754 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4755 N0.getOperand(1), 4756 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4757 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4758 &OneOps[0], OneOps.size())); 4759 4760 // If the desired elements are smaller or larger than the source 4761 // elements we can use a matching integer vector type and then 4762 // truncate/sign extend 4763 EVT MatchingElementType = 4764 EVT::getIntegerVT(*DAG.getContext(), 4765 N0VT.getScalarType().getSizeInBits()); 4766 EVT MatchingVectorType = 4767 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4768 N0VT.getVectorNumElements()); 4769 SDValue VsetCC = 4770 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4771 N0.getOperand(1), 4772 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4773 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4774 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4775 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4776 &OneOps[0], OneOps.size())); 4777 } 4778 4779 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4780 SDValue SCC = 4781 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4782 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4783 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4784 if (SCC.getNode()) return SCC; 4785 } 4786 4787 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4788 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4789 isa<ConstantSDNode>(N0.getOperand(1)) && 4790 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4791 N0.hasOneUse()) { 4792 SDValue ShAmt = N0.getOperand(1); 4793 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4794 if (N0.getOpcode() == ISD::SHL) { 4795 SDValue InnerZExt = N0.getOperand(0); 4796 // If the original shl may be shifting out bits, do not perform this 4797 // transformation. 4798 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4799 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4800 if (ShAmtVal > KnownZeroBits) 4801 return SDValue(); 4802 } 4803 4804 DebugLoc DL = N->getDebugLoc(); 4805 4806 // Ensure that the shift amount is wide enough for the shifted value. 4807 if (VT.getSizeInBits() >= 256) 4808 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4809 4810 return DAG.getNode(N0.getOpcode(), DL, VT, 4811 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4812 ShAmt); 4813 } 4814 4815 return SDValue(); 4816} 4817 4818SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4819 SDValue N0 = N->getOperand(0); 4820 EVT VT = N->getValueType(0); 4821 4822 // fold (aext c1) -> c1 4823 if (isa<ConstantSDNode>(N0)) 4824 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4825 // fold (aext (aext x)) -> (aext x) 4826 // fold (aext (zext x)) -> (zext x) 4827 // fold (aext (sext x)) -> (sext x) 4828 if (N0.getOpcode() == ISD::ANY_EXTEND || 4829 N0.getOpcode() == ISD::ZERO_EXTEND || 4830 N0.getOpcode() == ISD::SIGN_EXTEND) 4831 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4832 4833 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4834 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4835 if (N0.getOpcode() == ISD::TRUNCATE) { 4836 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4837 if (NarrowLoad.getNode()) { 4838 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4839 if (NarrowLoad.getNode() != N0.getNode()) { 4840 CombineTo(N0.getNode(), NarrowLoad); 4841 // CombineTo deleted the truncate, if needed, but not what's under it. 4842 AddToWorkList(oye); 4843 } 4844 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4845 } 4846 } 4847 4848 // fold (aext (truncate x)) 4849 if (N0.getOpcode() == ISD::TRUNCATE) { 4850 SDValue TruncOp = N0.getOperand(0); 4851 if (TruncOp.getValueType() == VT) 4852 return TruncOp; // x iff x size == zext size. 4853 if (TruncOp.getValueType().bitsGT(VT)) 4854 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4855 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4856 } 4857 4858 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4859 // if the trunc is not free. 4860 if (N0.getOpcode() == ISD::AND && 4861 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4862 N0.getOperand(1).getOpcode() == ISD::Constant && 4863 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4864 N0.getValueType())) { 4865 SDValue X = N0.getOperand(0).getOperand(0); 4866 if (X.getValueType().bitsLT(VT)) { 4867 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4868 } else if (X.getValueType().bitsGT(VT)) { 4869 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4870 } 4871 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4872 Mask = Mask.zext(VT.getSizeInBits()); 4873 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4874 X, DAG.getConstant(Mask, VT)); 4875 } 4876 4877 // fold (aext (load x)) -> (aext (truncate (extload x))) 4878 // None of the supported targets knows how to perform load and any_ext 4879 // on vectors in one instruction. We only perform this transformation on 4880 // scalars. 4881 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4882 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4883 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4884 bool DoXform = true; 4885 SmallVector<SDNode*, 4> SetCCs; 4886 if (!N0.hasOneUse()) 4887 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4888 if (DoXform) { 4889 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4890 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4891 LN0->getChain(), 4892 LN0->getBasePtr(), LN0->getPointerInfo(), 4893 N0.getValueType(), 4894 LN0->isVolatile(), LN0->isNonTemporal(), 4895 LN0->getAlignment()); 4896 CombineTo(N, ExtLoad); 4897 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4898 N0.getValueType(), ExtLoad); 4899 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4900 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4901 ISD::ANY_EXTEND); 4902 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4903 } 4904 } 4905 4906 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4907 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4908 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4909 if (N0.getOpcode() == ISD::LOAD && 4910 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4911 N0.hasOneUse()) { 4912 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4913 EVT MemVT = LN0->getMemoryVT(); 4914 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4915 VT, LN0->getChain(), LN0->getBasePtr(), 4916 LN0->getPointerInfo(), MemVT, 4917 LN0->isVolatile(), LN0->isNonTemporal(), 4918 LN0->getAlignment()); 4919 CombineTo(N, ExtLoad); 4920 CombineTo(N0.getNode(), 4921 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4922 N0.getValueType(), ExtLoad), 4923 ExtLoad.getValue(1)); 4924 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4925 } 4926 4927 if (N0.getOpcode() == ISD::SETCC) { 4928 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4929 // Only do this before legalize for now. 4930 if (VT.isVector() && !LegalOperations) { 4931 EVT N0VT = N0.getOperand(0).getValueType(); 4932 // We know that the # elements of the results is the same as the 4933 // # elements of the compare (and the # elements of the compare result 4934 // for that matter). Check to see that they are the same size. If so, 4935 // we know that the element size of the sext'd result matches the 4936 // element size of the compare operands. 4937 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4938 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4939 N0.getOperand(1), 4940 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4941 // If the desired elements are smaller or larger than the source 4942 // elements we can use a matching integer vector type and then 4943 // truncate/sign extend 4944 else { 4945 EVT MatchingElementType = 4946 EVT::getIntegerVT(*DAG.getContext(), 4947 N0VT.getScalarType().getSizeInBits()); 4948 EVT MatchingVectorType = 4949 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4950 N0VT.getVectorNumElements()); 4951 SDValue VsetCC = 4952 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4953 N0.getOperand(1), 4954 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4955 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4956 } 4957 } 4958 4959 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4960 SDValue SCC = 4961 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4962 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4963 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4964 if (SCC.getNode()) 4965 return SCC; 4966 } 4967 4968 return SDValue(); 4969} 4970 4971/// GetDemandedBits - See if the specified operand can be simplified with the 4972/// knowledge that only the bits specified by Mask are used. If so, return the 4973/// simpler operand, otherwise return a null SDValue. 4974SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4975 switch (V.getOpcode()) { 4976 default: break; 4977 case ISD::Constant: { 4978 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4979 assert(CV != 0 && "Const value should be ConstSDNode."); 4980 const APInt &CVal = CV->getAPIntValue(); 4981 APInt NewVal = CVal & Mask; 4982 if (NewVal != CVal) { 4983 return DAG.getConstant(NewVal, V.getValueType()); 4984 } 4985 break; 4986 } 4987 case ISD::OR: 4988 case ISD::XOR: 4989 // If the LHS or RHS don't contribute bits to the or, drop them. 4990 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4991 return V.getOperand(1); 4992 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4993 return V.getOperand(0); 4994 break; 4995 case ISD::SRL: 4996 // Only look at single-use SRLs. 4997 if (!V.getNode()->hasOneUse()) 4998 break; 4999 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 5000 // See if we can recursively simplify the LHS. 5001 unsigned Amt = RHSC->getZExtValue(); 5002 5003 // Watch out for shift count overflow though. 5004 if (Amt >= Mask.getBitWidth()) break; 5005 APInt NewMask = Mask << Amt; 5006 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 5007 if (SimplifyLHS.getNode()) 5008 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 5009 SimplifyLHS, V.getOperand(1)); 5010 } 5011 } 5012 return SDValue(); 5013} 5014 5015/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 5016/// bits and then truncated to a narrower type and where N is a multiple 5017/// of number of bits of the narrower type, transform it to a narrower load 5018/// from address + N / num of bits of new type. If the result is to be 5019/// extended, also fold the extension to form a extending load. 5020SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 5021 unsigned Opc = N->getOpcode(); 5022 5023 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 5024 SDValue N0 = N->getOperand(0); 5025 EVT VT = N->getValueType(0); 5026 EVT ExtVT = VT; 5027 5028 // This transformation isn't valid for vector loads. 5029 if (VT.isVector()) 5030 return SDValue(); 5031 5032 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 5033 // extended to VT. 5034 if (Opc == ISD::SIGN_EXTEND_INREG) { 5035 ExtType = ISD::SEXTLOAD; 5036 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5037 } else if (Opc == ISD::SRL) { 5038 // Another special-case: SRL is basically zero-extending a narrower value. 5039 ExtType = ISD::ZEXTLOAD; 5040 N0 = SDValue(N, 0); 5041 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 5042 if (!N01) return SDValue(); 5043 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 5044 VT.getSizeInBits() - N01->getZExtValue()); 5045 } 5046 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5047 return SDValue(); 5048 5049 unsigned EVTBits = ExtVT.getSizeInBits(); 5050 5051 // Do not generate loads of non-round integer types since these can 5052 // be expensive (and would be wrong if the type is not byte sized). 5053 if (!ExtVT.isRound()) 5054 return SDValue(); 5055 5056 unsigned ShAmt = 0; 5057 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5058 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5059 ShAmt = N01->getZExtValue(); 5060 // Is the shift amount a multiple of size of VT? 5061 if ((ShAmt & (EVTBits-1)) == 0) { 5062 N0 = N0.getOperand(0); 5063 // Is the load width a multiple of size of VT? 5064 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5065 return SDValue(); 5066 } 5067 5068 // At this point, we must have a load or else we can't do the transform. 5069 if (!isa<LoadSDNode>(N0)) return SDValue(); 5070 5071 // Because a SRL must be assumed to *need* to zero-extend the high bits 5072 // (as opposed to anyext the high bits), we can't combine the zextload 5073 // lowering of SRL and an sextload. 5074 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD) 5075 return SDValue(); 5076 5077 // If the shift amount is larger than the input type then we're not 5078 // accessing any of the loaded bytes. If the load was a zextload/extload 5079 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5080 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5081 return SDValue(); 5082 } 5083 } 5084 5085 // If the load is shifted left (and the result isn't shifted back right), 5086 // we can fold the truncate through the shift. 5087 unsigned ShLeftAmt = 0; 5088 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5089 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5090 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5091 ShLeftAmt = N01->getZExtValue(); 5092 N0 = N0.getOperand(0); 5093 } 5094 } 5095 5096 // If we haven't found a load, we can't narrow it. Don't transform one with 5097 // multiple uses, this would require adding a new load. 5098 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 5099 // Don't change the width of a volatile load. 5100 cast<LoadSDNode>(N0)->isVolatile()) 5101 return SDValue(); 5102 5103 // Verify that we are actually reducing a load width here. 5104 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 5105 return SDValue(); 5106 5107 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5108 EVT PtrType = N0.getOperand(1).getValueType(); 5109 5110 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5111 // It's not possible to generate a constant of extended or untyped type. 5112 return SDValue(); 5113 5114 // For big endian targets, we need to adjust the offset to the pointer to 5115 // load the correct bytes. 5116 if (TLI.isBigEndian()) { 5117 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5118 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5119 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5120 } 5121 5122 uint64_t PtrOff = ShAmt / 8; 5123 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5124 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5125 PtrType, LN0->getBasePtr(), 5126 DAG.getConstant(PtrOff, PtrType)); 5127 AddToWorkList(NewPtr.getNode()); 5128 5129 SDValue Load; 5130 if (ExtType == ISD::NON_EXTLOAD) 5131 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5132 LN0->getPointerInfo().getWithOffset(PtrOff), 5133 LN0->isVolatile(), LN0->isNonTemporal(), 5134 LN0->isInvariant(), NewAlign); 5135 else 5136 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5137 LN0->getPointerInfo().getWithOffset(PtrOff), 5138 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5139 NewAlign); 5140 5141 // Replace the old load's chain with the new load's chain. 5142 WorkListRemover DeadNodes(*this); 5143 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5144 5145 // Shift the result left, if we've swallowed a left shift. 5146 SDValue Result = Load; 5147 if (ShLeftAmt != 0) { 5148 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5149 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5150 ShImmTy = VT; 5151 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5152 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5153 } 5154 5155 // Return the new loaded value. 5156 return Result; 5157} 5158 5159SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5160 SDValue N0 = N->getOperand(0); 5161 SDValue N1 = N->getOperand(1); 5162 EVT VT = N->getValueType(0); 5163 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5164 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5165 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5166 5167 // fold (sext_in_reg c1) -> c1 5168 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5169 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5170 5171 // If the input is already sign extended, just drop the extension. 5172 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5173 return N0; 5174 5175 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5176 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5177 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5178 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5179 N0.getOperand(0), N1); 5180 } 5181 5182 // fold (sext_in_reg (sext x)) -> (sext x) 5183 // fold (sext_in_reg (aext x)) -> (sext x) 5184 // if x is small enough. 5185 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5186 SDValue N00 = N0.getOperand(0); 5187 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5188 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5189 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5190 } 5191 5192 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5193 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5194 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5195 5196 // fold operands of sext_in_reg based on knowledge that the top bits are not 5197 // demanded. 5198 if (SimplifyDemandedBits(SDValue(N, 0))) 5199 return SDValue(N, 0); 5200 5201 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5202 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5203 SDValue NarrowLoad = ReduceLoadWidth(N); 5204 if (NarrowLoad.getNode()) 5205 return NarrowLoad; 5206 5207 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5208 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5209 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5210 if (N0.getOpcode() == ISD::SRL) { 5211 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5212 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5213 // We can turn this into an SRA iff the input to the SRL is already sign 5214 // extended enough. 5215 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5216 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5217 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5218 N0.getOperand(0), N0.getOperand(1)); 5219 } 5220 } 5221 5222 // fold (sext_inreg (extload x)) -> (sextload x) 5223 if (ISD::isEXTLoad(N0.getNode()) && 5224 ISD::isUNINDEXEDLoad(N0.getNode()) && 5225 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5226 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5227 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5228 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5229 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5230 LN0->getChain(), 5231 LN0->getBasePtr(), LN0->getPointerInfo(), 5232 EVT, 5233 LN0->isVolatile(), LN0->isNonTemporal(), 5234 LN0->getAlignment()); 5235 CombineTo(N, ExtLoad); 5236 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5237 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5238 } 5239 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5240 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5241 N0.hasOneUse() && 5242 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5243 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5244 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5245 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5246 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5247 LN0->getChain(), 5248 LN0->getBasePtr(), LN0->getPointerInfo(), 5249 EVT, 5250 LN0->isVolatile(), LN0->isNonTemporal(), 5251 LN0->getAlignment()); 5252 CombineTo(N, ExtLoad); 5253 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5254 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5255 } 5256 5257 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5258 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5259 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5260 N0.getOperand(1), false); 5261 if (BSwap.getNode() != 0) 5262 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5263 BSwap, N1); 5264 } 5265 5266 return SDValue(); 5267} 5268 5269SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5270 SDValue N0 = N->getOperand(0); 5271 EVT VT = N->getValueType(0); 5272 bool isLE = TLI.isLittleEndian(); 5273 5274 // noop truncate 5275 if (N0.getValueType() == N->getValueType(0)) 5276 return N0; 5277 // fold (truncate c1) -> c1 5278 if (isa<ConstantSDNode>(N0)) 5279 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5280 // fold (truncate (truncate x)) -> (truncate x) 5281 if (N0.getOpcode() == ISD::TRUNCATE) 5282 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5283 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5284 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5285 N0.getOpcode() == ISD::SIGN_EXTEND || 5286 N0.getOpcode() == ISD::ANY_EXTEND) { 5287 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5288 // if the source is smaller than the dest, we still need an extend 5289 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5290 N0.getOperand(0)); 5291 if (N0.getOperand(0).getValueType().bitsGT(VT)) 5292 // if the source is larger than the dest, than we just need the truncate 5293 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5294 // if the source and dest are the same type, we can drop both the extend 5295 // and the truncate. 5296 return N0.getOperand(0); 5297 } 5298 5299 // Fold extract-and-trunc into a narrow extract. For example: 5300 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5301 // i32 y = TRUNCATE(i64 x) 5302 // -- becomes -- 5303 // v16i8 b = BITCAST (v2i64 val) 5304 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5305 // 5306 // Note: We only run this optimization after type legalization (which often 5307 // creates this pattern) and before operation legalization after which 5308 // we need to be more careful about the vector instructions that we generate. 5309 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5310 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5311 5312 EVT VecTy = N0.getOperand(0).getValueType(); 5313 EVT ExTy = N0.getValueType(); 5314 EVT TrTy = N->getValueType(0); 5315 5316 unsigned NumElem = VecTy.getVectorNumElements(); 5317 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5318 5319 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5320 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5321 5322 SDValue EltNo = N0->getOperand(1); 5323 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5324 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5325 EVT IndexTy = N0->getOperand(1).getValueType(); 5326 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5327 5328 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5329 NVT, N0.getOperand(0)); 5330 5331 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5332 N->getDebugLoc(), TrTy, V, 5333 DAG.getConstant(Index, IndexTy)); 5334 } 5335 } 5336 5337 // See if we can simplify the input to this truncate through knowledge that 5338 // only the low bits are being used. 5339 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5340 // Currently we only perform this optimization on scalars because vectors 5341 // may have different active low bits. 5342 if (!VT.isVector()) { 5343 SDValue Shorter = 5344 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5345 VT.getSizeInBits())); 5346 if (Shorter.getNode()) 5347 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5348 } 5349 // fold (truncate (load x)) -> (smaller load x) 5350 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5351 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5352 SDValue Reduced = ReduceLoadWidth(N); 5353 if (Reduced.getNode()) 5354 return Reduced; 5355 } 5356 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)), 5357 // where ... are all 'undef'. 5358 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { 5359 SmallVector<EVT, 8> VTs; 5360 SDValue V; 5361 unsigned Idx = 0; 5362 unsigned NumDefs = 0; 5363 5364 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 5365 SDValue X = N0.getOperand(i); 5366 if (X.getOpcode() != ISD::UNDEF) { 5367 V = X; 5368 Idx = i; 5369 NumDefs++; 5370 } 5371 // Stop if more than one members are non-undef. 5372 if (NumDefs > 1) 5373 break; 5374 VTs.push_back(EVT::getVectorVT(*DAG.getContext(), 5375 VT.getVectorElementType(), 5376 X.getValueType().getVectorNumElements())); 5377 } 5378 5379 if (NumDefs == 0) 5380 return DAG.getUNDEF(VT); 5381 5382 if (NumDefs == 1) { 5383 assert(V.getNode() && "The single defined operand is empty!"); 5384 SmallVector<SDValue, 8> Opnds; 5385 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 5386 if (i != Idx) { 5387 Opnds.push_back(DAG.getUNDEF(VTs[i])); 5388 continue; 5389 } 5390 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V); 5391 AddToWorkList(NV.getNode()); 5392 Opnds.push_back(NV); 5393 } 5394 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 5395 &Opnds[0], Opnds.size()); 5396 } 5397 } 5398 5399 // Simplify the operands using demanded-bits information. 5400 if (!VT.isVector() && 5401 SimplifyDemandedBits(SDValue(N, 0))) 5402 return SDValue(N, 0); 5403 5404 return SDValue(); 5405} 5406 5407static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5408 SDValue Elt = N->getOperand(i); 5409 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5410 return Elt.getNode(); 5411 return Elt.getOperand(Elt.getResNo()).getNode(); 5412} 5413 5414/// CombineConsecutiveLoads - build_pair (load, load) -> load 5415/// if load locations are consecutive. 5416SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5417 assert(N->getOpcode() == ISD::BUILD_PAIR); 5418 5419 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5420 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5421 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5422 LD1->getPointerInfo().getAddrSpace() != 5423 LD2->getPointerInfo().getAddrSpace()) 5424 return SDValue(); 5425 EVT LD1VT = LD1->getValueType(0); 5426 5427 if (ISD::isNON_EXTLoad(LD2) && 5428 LD2->hasOneUse() && 5429 // If both are volatile this would reduce the number of volatile loads. 5430 // If one is volatile it might be ok, but play conservative and bail out. 5431 !LD1->isVolatile() && 5432 !LD2->isVolatile() && 5433 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5434 unsigned Align = LD1->getAlignment(); 5435 unsigned NewAlign = TLI.getDataLayout()-> 5436 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5437 5438 if (NewAlign <= Align && 5439 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5440 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5441 LD1->getBasePtr(), LD1->getPointerInfo(), 5442 false, false, false, Align); 5443 } 5444 5445 return SDValue(); 5446} 5447 5448SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5449 SDValue N0 = N->getOperand(0); 5450 EVT VT = N->getValueType(0); 5451 5452 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5453 // Only do this before legalize, since afterward the target may be depending 5454 // on the bitconvert. 5455 // First check to see if this is all constant. 5456 if (!LegalTypes && 5457 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5458 VT.isVector()) { 5459 bool isSimple = true; 5460 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5461 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5462 N0.getOperand(i).getOpcode() != ISD::Constant && 5463 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5464 isSimple = false; 5465 break; 5466 } 5467 5468 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5469 assert(!DestEltVT.isVector() && 5470 "Element type of vector ValueType must not be vector!"); 5471 if (isSimple) 5472 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5473 } 5474 5475 // If the input is a constant, let getNode fold it. 5476 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5477 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5478 if (Res.getNode() != N) { 5479 if (!LegalOperations || 5480 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5481 return Res; 5482 5483 // Folding it resulted in an illegal node, and it's too late to 5484 // do that. Clean up the old node and forego the transformation. 5485 // Ideally this won't happen very often, because instcombine 5486 // and the earlier dagcombine runs (where illegal nodes are 5487 // permitted) should have folded most of them already. 5488 DAG.DeleteNode(Res.getNode()); 5489 } 5490 } 5491 5492 // (conv (conv x, t1), t2) -> (conv x, t2) 5493 if (N0.getOpcode() == ISD::BITCAST) 5494 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5495 N0.getOperand(0)); 5496 5497 // fold (conv (load x)) -> (load (conv*)x) 5498 // If the resultant load doesn't need a higher alignment than the original! 5499 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5500 // Do not change the width of a volatile load. 5501 !cast<LoadSDNode>(N0)->isVolatile() && 5502 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5503 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5504 unsigned Align = TLI.getDataLayout()-> 5505 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5506 unsigned OrigAlign = LN0->getAlignment(); 5507 5508 if (Align <= OrigAlign) { 5509 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5510 LN0->getBasePtr(), LN0->getPointerInfo(), 5511 LN0->isVolatile(), LN0->isNonTemporal(), 5512 LN0->isInvariant(), OrigAlign); 5513 AddToWorkList(N); 5514 CombineTo(N0.getNode(), 5515 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5516 N0.getValueType(), Load), 5517 Load.getValue(1)); 5518 return Load; 5519 } 5520 } 5521 5522 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5523 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5524 // This often reduces constant pool loads. 5525 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5526 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5527 N0.getNode()->hasOneUse() && VT.isInteger() && 5528 !VT.isVector() && !N0.getValueType().isVector()) { 5529 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5530 N0.getOperand(0)); 5531 AddToWorkList(NewConv.getNode()); 5532 5533 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5534 if (N0.getOpcode() == ISD::FNEG) 5535 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5536 NewConv, DAG.getConstant(SignBit, VT)); 5537 assert(N0.getOpcode() == ISD::FABS); 5538 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5539 NewConv, DAG.getConstant(~SignBit, VT)); 5540 } 5541 5542 // fold (bitconvert (fcopysign cst, x)) -> 5543 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5544 // Note that we don't handle (copysign x, cst) because this can always be 5545 // folded to an fneg or fabs. 5546 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5547 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5548 VT.isInteger() && !VT.isVector()) { 5549 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5550 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5551 if (isTypeLegal(IntXVT)) { 5552 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5553 IntXVT, N0.getOperand(1)); 5554 AddToWorkList(X.getNode()); 5555 5556 // If X has a different width than the result/lhs, sext it or truncate it. 5557 unsigned VTWidth = VT.getSizeInBits(); 5558 if (OrigXWidth < VTWidth) { 5559 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5560 AddToWorkList(X.getNode()); 5561 } else if (OrigXWidth > VTWidth) { 5562 // To get the sign bit in the right place, we have to shift it right 5563 // before truncating. 5564 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5565 X.getValueType(), X, 5566 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5567 AddToWorkList(X.getNode()); 5568 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5569 AddToWorkList(X.getNode()); 5570 } 5571 5572 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5573 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5574 X, DAG.getConstant(SignBit, VT)); 5575 AddToWorkList(X.getNode()); 5576 5577 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5578 VT, N0.getOperand(0)); 5579 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5580 Cst, DAG.getConstant(~SignBit, VT)); 5581 AddToWorkList(Cst.getNode()); 5582 5583 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5584 } 5585 } 5586 5587 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5588 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5589 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5590 if (CombineLD.getNode()) 5591 return CombineLD; 5592 } 5593 5594 return SDValue(); 5595} 5596 5597SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5598 EVT VT = N->getValueType(0); 5599 return CombineConsecutiveLoads(N, VT); 5600} 5601 5602/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5603/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5604/// destination element value type. 5605SDValue DAGCombiner:: 5606ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5607 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5608 5609 // If this is already the right type, we're done. 5610 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5611 5612 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5613 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5614 5615 // If this is a conversion of N elements of one type to N elements of another 5616 // type, convert each element. This handles FP<->INT cases. 5617 if (SrcBitSize == DstBitSize) { 5618 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5619 BV->getValueType(0).getVectorNumElements()); 5620 5621 // Due to the FP element handling below calling this routine recursively, 5622 // we can end up with a scalar-to-vector node here. 5623 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5624 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5625 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5626 DstEltVT, BV->getOperand(0))); 5627 5628 SmallVector<SDValue, 8> Ops; 5629 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5630 SDValue Op = BV->getOperand(i); 5631 // If the vector element type is not legal, the BUILD_VECTOR operands 5632 // are promoted and implicitly truncated. Make that explicit here. 5633 if (Op.getValueType() != SrcEltVT) 5634 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5635 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5636 DstEltVT, Op)); 5637 AddToWorkList(Ops.back().getNode()); 5638 } 5639 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5640 &Ops[0], Ops.size()); 5641 } 5642 5643 // Otherwise, we're growing or shrinking the elements. To avoid having to 5644 // handle annoying details of growing/shrinking FP values, we convert them to 5645 // int first. 5646 if (SrcEltVT.isFloatingPoint()) { 5647 // Convert the input float vector to a int vector where the elements are the 5648 // same sizes. 5649 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5650 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5651 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5652 SrcEltVT = IntVT; 5653 } 5654 5655 // Now we know the input is an integer vector. If the output is a FP type, 5656 // convert to integer first, then to FP of the right size. 5657 if (DstEltVT.isFloatingPoint()) { 5658 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5659 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5660 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5661 5662 // Next, convert to FP elements of the same size. 5663 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5664 } 5665 5666 // Okay, we know the src/dst types are both integers of differing types. 5667 // Handling growing first. 5668 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5669 if (SrcBitSize < DstBitSize) { 5670 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5671 5672 SmallVector<SDValue, 8> Ops; 5673 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5674 i += NumInputsPerOutput) { 5675 bool isLE = TLI.isLittleEndian(); 5676 APInt NewBits = APInt(DstBitSize, 0); 5677 bool EltIsUndef = true; 5678 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5679 // Shift the previously computed bits over. 5680 NewBits <<= SrcBitSize; 5681 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5682 if (Op.getOpcode() == ISD::UNDEF) continue; 5683 EltIsUndef = false; 5684 5685 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5686 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5687 } 5688 5689 if (EltIsUndef) 5690 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5691 else 5692 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5693 } 5694 5695 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5696 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5697 &Ops[0], Ops.size()); 5698 } 5699 5700 // Finally, this must be the case where we are shrinking elements: each input 5701 // turns into multiple outputs. 5702 bool isS2V = ISD::isScalarToVector(BV); 5703 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5704 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5705 NumOutputsPerInput*BV->getNumOperands()); 5706 SmallVector<SDValue, 8> Ops; 5707 5708 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5709 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5710 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5711 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5712 continue; 5713 } 5714 5715 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5716 getAPIntValue().zextOrTrunc(SrcBitSize); 5717 5718 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5719 APInt ThisVal = OpVal.trunc(DstBitSize); 5720 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5721 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5722 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5723 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5724 Ops[0]); 5725 OpVal = OpVal.lshr(DstBitSize); 5726 } 5727 5728 // For big endian targets, swap the order of the pieces of each element. 5729 if (TLI.isBigEndian()) 5730 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5731 } 5732 5733 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5734 &Ops[0], Ops.size()); 5735} 5736 5737SDValue DAGCombiner::visitFADD(SDNode *N) { 5738 SDValue N0 = N->getOperand(0); 5739 SDValue N1 = N->getOperand(1); 5740 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5741 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5742 EVT VT = N->getValueType(0); 5743 5744 // fold vector ops 5745 if (VT.isVector()) { 5746 SDValue FoldedVOp = SimplifyVBinOp(N); 5747 if (FoldedVOp.getNode()) return FoldedVOp; 5748 } 5749 5750 // fold (fadd c1, c2) -> c1 + c2 5751 if (N0CFP && N1CFP) 5752 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5753 // canonicalize constant to RHS 5754 if (N0CFP && !N1CFP) 5755 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5756 // fold (fadd A, 0) -> A 5757 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5758 N1CFP->getValueAPF().isZero()) 5759 return N0; 5760 // fold (fadd A, (fneg B)) -> (fsub A, B) 5761 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5762 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5763 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5764 GetNegatedExpression(N1, DAG, LegalOperations)); 5765 // fold (fadd (fneg A), B) -> (fsub B, A) 5766 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5767 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5768 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5769 GetNegatedExpression(N0, DAG, LegalOperations)); 5770 5771 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5772 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5773 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5774 isa<ConstantFPSDNode>(N0.getOperand(1))) 5775 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5776 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5777 N0.getOperand(1), N1)); 5778 5779 // If allow, fold (fadd (fneg x), x) -> 0.0 5780 if (DAG.getTarget().Options.UnsafeFPMath && 5781 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) { 5782 return DAG.getConstantFP(0.0, VT); 5783 } 5784 5785 // If allow, fold (fadd x, (fneg x)) -> 0.0 5786 if (DAG.getTarget().Options.UnsafeFPMath && 5787 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) { 5788 return DAG.getConstantFP(0.0, VT); 5789 } 5790 5791 // In unsafe math mode, we can fold chains of FADD's of the same value 5792 // into multiplications. This transform is not safe in general because 5793 // we are reducing the number of rounding steps. 5794 if (DAG.getTarget().Options.UnsafeFPMath && 5795 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5796 !N0CFP && !N1CFP) { 5797 if (N0.getOpcode() == ISD::FMUL) { 5798 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5799 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 5800 5801 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5802 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 5803 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5804 SDValue(CFP00, 0), 5805 DAG.getConstantFP(1.0, VT)); 5806 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5807 N1, NewCFP); 5808 } 5809 5810 // (fadd (fmul x, c), x) -> (fmul c+1, x) 5811 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 5812 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5813 SDValue(CFP01, 0), 5814 DAG.getConstantFP(1.0, VT)); 5815 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5816 N1, NewCFP); 5817 } 5818 5819 // (fadd (fadd x, x), x) -> (fmul 3.0, x) 5820 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) && 5821 N0.getOperand(0) == N1) { 5822 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5823 N1, DAG.getConstantFP(3.0, VT)); 5824 } 5825 5826 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x) 5827 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 5828 N1.getOperand(0) == N1.getOperand(1) && 5829 N0.getOperand(1) == N1.getOperand(0)) { 5830 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5831 SDValue(CFP00, 0), 5832 DAG.getConstantFP(2.0, VT)); 5833 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5834 N0.getOperand(1), NewCFP); 5835 } 5836 5837 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x) 5838 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 5839 N1.getOperand(0) == N1.getOperand(1) && 5840 N0.getOperand(0) == N1.getOperand(0)) { 5841 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5842 SDValue(CFP01, 0), 5843 DAG.getConstantFP(2.0, VT)); 5844 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5845 N0.getOperand(0), NewCFP); 5846 } 5847 } 5848 5849 if (N1.getOpcode() == ISD::FMUL) { 5850 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5851 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 5852 5853 // (fadd x, (fmul c, x)) -> (fmul c+1, x) 5854 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 5855 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5856 SDValue(CFP10, 0), 5857 DAG.getConstantFP(1.0, VT)); 5858 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5859 N0, NewCFP); 5860 } 5861 5862 // (fadd x, (fmul x, c)) -> (fmul c+1, x) 5863 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 5864 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5865 SDValue(CFP11, 0), 5866 DAG.getConstantFP(1.0, VT)); 5867 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5868 N0, NewCFP); 5869 } 5870 5871 // (fadd x, (fadd x, x)) -> (fmul 3.0, x) 5872 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) && 5873 N1.getOperand(0) == N0) { 5874 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5875 N0, DAG.getConstantFP(3.0, VT)); 5876 } 5877 5878 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x) 5879 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD && 5880 N1.getOperand(0) == N1.getOperand(1) && 5881 N0.getOperand(1) == N1.getOperand(0)) { 5882 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5883 SDValue(CFP10, 0), 5884 DAG.getConstantFP(2.0, VT)); 5885 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5886 N0.getOperand(1), NewCFP); 5887 } 5888 5889 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x) 5890 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD && 5891 N1.getOperand(0) == N1.getOperand(1) && 5892 N0.getOperand(0) == N1.getOperand(0)) { 5893 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5894 SDValue(CFP11, 0), 5895 DAG.getConstantFP(2.0, VT)); 5896 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5897 N0.getOperand(0), NewCFP); 5898 } 5899 } 5900 5901 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x) 5902 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 5903 N0.getOperand(0) == N0.getOperand(1) && 5904 N1.getOperand(0) == N1.getOperand(1) && 5905 N0.getOperand(0) == N1.getOperand(0)) { 5906 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5907 N0.getOperand(0), 5908 DAG.getConstantFP(4.0, VT)); 5909 } 5910 } 5911 5912 // FADD -> FMA combines: 5913 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5914 DAG.getTarget().Options.UnsafeFPMath) && 5915 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5916 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5917 5918 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 5919 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5920 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5921 N0.getOperand(0), N0.getOperand(1), N1); 5922 } 5923 5924 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 5925 // Note: Commutes FADD operands. 5926 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5927 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5928 N1.getOperand(0), N1.getOperand(1), N0); 5929 } 5930 } 5931 5932 return SDValue(); 5933} 5934 5935SDValue DAGCombiner::visitFSUB(SDNode *N) { 5936 SDValue N0 = N->getOperand(0); 5937 SDValue N1 = N->getOperand(1); 5938 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5939 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5940 EVT VT = N->getValueType(0); 5941 DebugLoc dl = N->getDebugLoc(); 5942 5943 // fold vector ops 5944 if (VT.isVector()) { 5945 SDValue FoldedVOp = SimplifyVBinOp(N); 5946 if (FoldedVOp.getNode()) return FoldedVOp; 5947 } 5948 5949 // fold (fsub c1, c2) -> c1-c2 5950 if (N0CFP && N1CFP) 5951 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5952 // fold (fsub A, 0) -> A 5953 if (DAG.getTarget().Options.UnsafeFPMath && 5954 N1CFP && N1CFP->getValueAPF().isZero()) 5955 return N0; 5956 // fold (fsub 0, B) -> -B 5957 if (DAG.getTarget().Options.UnsafeFPMath && 5958 N0CFP && N0CFP->getValueAPF().isZero()) { 5959 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5960 return GetNegatedExpression(N1, DAG, LegalOperations); 5961 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5962 return DAG.getNode(ISD::FNEG, dl, VT, N1); 5963 } 5964 // fold (fsub A, (fneg B)) -> (fadd A, B) 5965 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5966 return DAG.getNode(ISD::FADD, dl, VT, N0, 5967 GetNegatedExpression(N1, DAG, LegalOperations)); 5968 5969 // If 'unsafe math' is enabled, fold 5970 // (fsub x, x) -> 0.0 & 5971 // (fsub x, (fadd x, y)) -> (fneg y) & 5972 // (fsub x, (fadd y, x)) -> (fneg y) 5973 if (DAG.getTarget().Options.UnsafeFPMath) { 5974 if (N0 == N1) 5975 return DAG.getConstantFP(0.0f, VT); 5976 5977 if (N1.getOpcode() == ISD::FADD) { 5978 SDValue N10 = N1->getOperand(0); 5979 SDValue N11 = N1->getOperand(1); 5980 5981 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5982 &DAG.getTarget().Options)) 5983 return GetNegatedExpression(N11, DAG, LegalOperations); 5984 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5985 &DAG.getTarget().Options)) 5986 return GetNegatedExpression(N10, DAG, LegalOperations); 5987 } 5988 } 5989 5990 // FSUB -> FMA combines: 5991 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5992 DAG.getTarget().Options.UnsafeFPMath) && 5993 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5994 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5995 5996 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 5997 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5998 return DAG.getNode(ISD::FMA, dl, VT, 5999 N0.getOperand(0), N0.getOperand(1), 6000 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6001 } 6002 6003 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 6004 // Note: Commutes FSUB operands. 6005 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 6006 return DAG.getNode(ISD::FMA, dl, VT, 6007 DAG.getNode(ISD::FNEG, dl, VT, 6008 N1.getOperand(0)), 6009 N1.getOperand(1), N0); 6010 } 6011 6012 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 6013 if (N0.getOpcode() == ISD::FNEG && 6014 N0.getOperand(0).getOpcode() == ISD::FMUL && 6015 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 6016 SDValue N00 = N0.getOperand(0).getOperand(0); 6017 SDValue N01 = N0.getOperand(0).getOperand(1); 6018 return DAG.getNode(ISD::FMA, dl, VT, 6019 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 6020 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6021 } 6022 } 6023 6024 return SDValue(); 6025} 6026 6027SDValue DAGCombiner::visitFMUL(SDNode *N) { 6028 SDValue N0 = N->getOperand(0); 6029 SDValue N1 = N->getOperand(1); 6030 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6031 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6032 EVT VT = N->getValueType(0); 6033 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6034 6035 // fold vector ops 6036 if (VT.isVector()) { 6037 SDValue FoldedVOp = SimplifyVBinOp(N); 6038 if (FoldedVOp.getNode()) return FoldedVOp; 6039 } 6040 6041 // fold (fmul c1, c2) -> c1*c2 6042 if (N0CFP && N1CFP) 6043 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 6044 // canonicalize constant to RHS 6045 if (N0CFP && !N1CFP) 6046 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 6047 // fold (fmul A, 0) -> 0 6048 if (DAG.getTarget().Options.UnsafeFPMath && 6049 N1CFP && N1CFP->getValueAPF().isZero()) 6050 return N1; 6051 // fold (fmul A, 0) -> 0, vector edition. 6052 if (DAG.getTarget().Options.UnsafeFPMath && 6053 ISD::isBuildVectorAllZeros(N1.getNode())) 6054 return N1; 6055 // fold (fmul A, 1.0) -> A 6056 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6057 return N0; 6058 // fold (fmul X, 2.0) -> (fadd X, X) 6059 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 6060 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 6061 // fold (fmul X, -1.0) -> (fneg X) 6062 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 6063 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6064 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 6065 6066 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 6067 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6068 &DAG.getTarget().Options)) { 6069 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6070 &DAG.getTarget().Options)) { 6071 // Both can be negated for free, check to see if at least one is cheaper 6072 // negated. 6073 if (LHSNeg == 2 || RHSNeg == 2) 6074 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6075 GetNegatedExpression(N0, DAG, LegalOperations), 6076 GetNegatedExpression(N1, DAG, LegalOperations)); 6077 } 6078 } 6079 6080 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 6081 if (DAG.getTarget().Options.UnsafeFPMath && 6082 N1CFP && N0.getOpcode() == ISD::FMUL && 6083 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 6084 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 6085 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6086 N0.getOperand(1), N1)); 6087 6088 return SDValue(); 6089} 6090 6091SDValue DAGCombiner::visitFMA(SDNode *N) { 6092 SDValue N0 = N->getOperand(0); 6093 SDValue N1 = N->getOperand(1); 6094 SDValue N2 = N->getOperand(2); 6095 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6096 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6097 EVT VT = N->getValueType(0); 6098 DebugLoc dl = N->getDebugLoc(); 6099 6100 if (DAG.getTarget().Options.UnsafeFPMath) { 6101 if (N0CFP && N0CFP->isZero()) 6102 return N2; 6103 if (N1CFP && N1CFP->isZero()) 6104 return N2; 6105 } 6106 if (N0CFP && N0CFP->isExactlyValue(1.0)) 6107 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); 6108 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6109 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); 6110 6111 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6112 if (N0CFP && !N1CFP) 6113 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); 6114 6115 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6116 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6117 N2.getOpcode() == ISD::FMUL && 6118 N0 == N2.getOperand(0) && 6119 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6120 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6121 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6122 } 6123 6124 6125 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6126 if (DAG.getTarget().Options.UnsafeFPMath && 6127 N0.getOpcode() == ISD::FMUL && N1CFP && 6128 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6129 return DAG.getNode(ISD::FMA, dl, VT, 6130 N0.getOperand(0), 6131 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6132 N2); 6133 } 6134 6135 // (fma x, 1, y) -> (fadd x, y) 6136 // (fma x, -1, y) -> (fadd (fneg x), y) 6137 if (N1CFP) { 6138 if (N1CFP->isExactlyValue(1.0)) 6139 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6140 6141 if (N1CFP->isExactlyValue(-1.0) && 6142 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6143 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6144 AddToWorkList(RHSNeg.getNode()); 6145 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6146 } 6147 } 6148 6149 // (fma x, c, x) -> (fmul x, (c+1)) 6150 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) { 6151 return DAG.getNode(ISD::FMUL, dl, VT, 6152 N0, 6153 DAG.getNode(ISD::FADD, dl, VT, 6154 N1, DAG.getConstantFP(1.0, VT))); 6155 } 6156 6157 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6158 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6159 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { 6160 return DAG.getNode(ISD::FMUL, dl, VT, 6161 N0, 6162 DAG.getNode(ISD::FADD, dl, VT, 6163 N1, DAG.getConstantFP(-1.0, VT))); 6164 } 6165 6166 6167 return SDValue(); 6168} 6169 6170SDValue DAGCombiner::visitFDIV(SDNode *N) { 6171 SDValue N0 = N->getOperand(0); 6172 SDValue N1 = N->getOperand(1); 6173 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6174 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6175 EVT VT = N->getValueType(0); 6176 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6177 6178 // fold vector ops 6179 if (VT.isVector()) { 6180 SDValue FoldedVOp = SimplifyVBinOp(N); 6181 if (FoldedVOp.getNode()) return FoldedVOp; 6182 } 6183 6184 // fold (fdiv c1, c2) -> c1/c2 6185 if (N0CFP && N1CFP) 6186 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 6187 6188 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6189 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) { 6190 // Compute the reciprocal 1.0 / c2. 6191 APFloat N1APF = N1CFP->getValueAPF(); 6192 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6193 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6194 // Only do the transform if the reciprocal is a legal fp immediate that 6195 // isn't too nasty (eg NaN, denormal, ...). 6196 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6197 (!LegalOperations || 6198 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6199 // backend)... we should handle this gracefully after Legalize. 6200 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6201 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6202 TLI.isFPImmLegal(Recip, VT))) 6203 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 6204 DAG.getConstantFP(Recip, VT)); 6205 } 6206 6207 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6208 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6209 &DAG.getTarget().Options)) { 6210 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6211 &DAG.getTarget().Options)) { 6212 // Both can be negated for free, check to see if at least one is cheaper 6213 // negated. 6214 if (LHSNeg == 2 || RHSNeg == 2) 6215 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 6216 GetNegatedExpression(N0, DAG, LegalOperations), 6217 GetNegatedExpression(N1, DAG, LegalOperations)); 6218 } 6219 } 6220 6221 return SDValue(); 6222} 6223 6224SDValue DAGCombiner::visitFREM(SDNode *N) { 6225 SDValue N0 = N->getOperand(0); 6226 SDValue N1 = N->getOperand(1); 6227 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6228 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6229 EVT VT = N->getValueType(0); 6230 6231 // fold (frem c1, c2) -> fmod(c1,c2) 6232 if (N0CFP && N1CFP) 6233 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 6234 6235 return SDValue(); 6236} 6237 6238SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6239 SDValue N0 = N->getOperand(0); 6240 SDValue N1 = N->getOperand(1); 6241 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6242 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6243 EVT VT = N->getValueType(0); 6244 6245 if (N0CFP && N1CFP) // Constant fold 6246 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 6247 6248 if (N1CFP) { 6249 const APFloat& V = N1CFP->getValueAPF(); 6250 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6251 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6252 if (!V.isNegative()) { 6253 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6254 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6255 } else { 6256 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6257 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6258 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 6259 } 6260 } 6261 6262 // copysign(fabs(x), y) -> copysign(x, y) 6263 // copysign(fneg(x), y) -> copysign(x, y) 6264 // copysign(copysign(x,z), y) -> copysign(x, y) 6265 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6266 N0.getOpcode() == ISD::FCOPYSIGN) 6267 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6268 N0.getOperand(0), N1); 6269 6270 // copysign(x, abs(y)) -> abs(x) 6271 if (N1.getOpcode() == ISD::FABS) 6272 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6273 6274 // copysign(x, copysign(y,z)) -> copysign(x, z) 6275 if (N1.getOpcode() == ISD::FCOPYSIGN) 6276 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6277 N0, N1.getOperand(1)); 6278 6279 // copysign(x, fp_extend(y)) -> copysign(x, y) 6280 // copysign(x, fp_round(y)) -> copysign(x, y) 6281 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6282 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6283 N0, N1.getOperand(0)); 6284 6285 return SDValue(); 6286} 6287 6288SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6289 SDValue N0 = N->getOperand(0); 6290 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6291 EVT VT = N->getValueType(0); 6292 EVT OpVT = N0.getValueType(); 6293 6294 // fold (sint_to_fp c1) -> c1fp 6295 if (N0C && 6296 // ...but only if the target supports immediate floating-point values 6297 (!LegalOperations || 6298 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6299 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6300 6301 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6302 // but UINT_TO_FP is legal on this target, try to convert. 6303 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6304 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6305 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6306 if (DAG.SignBitIsZero(N0)) 6307 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6308 } 6309 6310 // The next optimizations are desireable only if SELECT_CC can be lowered. 6311 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6312 // having to say they don't support SELECT_CC on every type the DAG knows 6313 // about, since there is no way to mark an opcode illegal at all value types 6314 // (See also visitSELECT) 6315 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6316 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6317 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6318 !VT.isVector() && 6319 (!LegalOperations || 6320 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6321 SDValue Ops[] = 6322 { N0.getOperand(0), N0.getOperand(1), 6323 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6324 N0.getOperand(2) }; 6325 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6326 } 6327 6328 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6329 // (select_cc x, y, 1.0, 0.0,, cc) 6330 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6331 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6332 (!LegalOperations || 6333 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6334 SDValue Ops[] = 6335 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6336 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6337 N0.getOperand(0).getOperand(2) }; 6338 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6339 } 6340 } 6341 6342 return SDValue(); 6343} 6344 6345SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6346 SDValue N0 = N->getOperand(0); 6347 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6348 EVT VT = N->getValueType(0); 6349 EVT OpVT = N0.getValueType(); 6350 6351 // fold (uint_to_fp c1) -> c1fp 6352 if (N0C && 6353 // ...but only if the target supports immediate floating-point values 6354 (!LegalOperations || 6355 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6356 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6357 6358 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6359 // but SINT_TO_FP is legal on this target, try to convert. 6360 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6361 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6362 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6363 if (DAG.SignBitIsZero(N0)) 6364 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6365 } 6366 6367 // The next optimizations are desireable only if SELECT_CC can be lowered. 6368 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6369 // having to say they don't support SELECT_CC on every type the DAG knows 6370 // about, since there is no way to mark an opcode illegal at all value types 6371 // (See also visitSELECT) 6372 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6373 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6374 6375 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6376 (!LegalOperations || 6377 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6378 SDValue Ops[] = 6379 { N0.getOperand(0), N0.getOperand(1), 6380 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6381 N0.getOperand(2) }; 6382 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6383 } 6384 } 6385 6386 return SDValue(); 6387} 6388 6389SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6390 SDValue N0 = N->getOperand(0); 6391 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6392 EVT VT = N->getValueType(0); 6393 6394 // fold (fp_to_sint c1fp) -> c1 6395 if (N0CFP) 6396 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 6397 6398 return SDValue(); 6399} 6400 6401SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6402 SDValue N0 = N->getOperand(0); 6403 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6404 EVT VT = N->getValueType(0); 6405 6406 // fold (fp_to_uint c1fp) -> c1 6407 if (N0CFP) 6408 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 6409 6410 return SDValue(); 6411} 6412 6413SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6414 SDValue N0 = N->getOperand(0); 6415 SDValue N1 = N->getOperand(1); 6416 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6417 EVT VT = N->getValueType(0); 6418 6419 // fold (fp_round c1fp) -> c1fp 6420 if (N0CFP) 6421 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 6422 6423 // fold (fp_round (fp_extend x)) -> x 6424 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6425 return N0.getOperand(0); 6426 6427 // fold (fp_round (fp_round x)) -> (fp_round x) 6428 if (N0.getOpcode() == ISD::FP_ROUND) { 6429 // This is a value preserving truncation if both round's are. 6430 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6431 N0.getNode()->getConstantOperandVal(1) == 1; 6432 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 6433 DAG.getIntPtrConstant(IsTrunc)); 6434 } 6435 6436 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6437 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6438 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 6439 N0.getOperand(0), N1); 6440 AddToWorkList(Tmp.getNode()); 6441 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6442 Tmp, N0.getOperand(1)); 6443 } 6444 6445 return SDValue(); 6446} 6447 6448SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6449 SDValue N0 = N->getOperand(0); 6450 EVT VT = N->getValueType(0); 6451 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6452 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6453 6454 // fold (fp_round_inreg c1fp) -> c1fp 6455 if (N0CFP && isTypeLegal(EVT)) { 6456 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6457 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 6458 } 6459 6460 return SDValue(); 6461} 6462 6463SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6464 SDValue N0 = N->getOperand(0); 6465 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6466 EVT VT = N->getValueType(0); 6467 6468 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6469 if (N->hasOneUse() && 6470 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6471 return SDValue(); 6472 6473 // fold (fp_extend c1fp) -> c1fp 6474 if (N0CFP) 6475 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6476 6477 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6478 // value of X. 6479 if (N0.getOpcode() == ISD::FP_ROUND 6480 && N0.getNode()->getConstantOperandVal(1) == 1) { 6481 SDValue In = N0.getOperand(0); 6482 if (In.getValueType() == VT) return In; 6483 if (VT.bitsLT(In.getValueType())) 6484 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6485 In, N0.getOperand(1)); 6486 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6487 } 6488 6489 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6490 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6491 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6492 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6493 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6494 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6495 LN0->getChain(), 6496 LN0->getBasePtr(), LN0->getPointerInfo(), 6497 N0.getValueType(), 6498 LN0->isVolatile(), LN0->isNonTemporal(), 6499 LN0->getAlignment()); 6500 CombineTo(N, ExtLoad); 6501 CombineTo(N0.getNode(), 6502 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6503 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6504 ExtLoad.getValue(1)); 6505 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6506 } 6507 6508 return SDValue(); 6509} 6510 6511SDValue DAGCombiner::visitFNEG(SDNode *N) { 6512 SDValue N0 = N->getOperand(0); 6513 EVT VT = N->getValueType(0); 6514 6515 if (VT.isVector()) { 6516 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6517 if (FoldedVOp.getNode()) return FoldedVOp; 6518 } 6519 6520 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6521 &DAG.getTarget().Options)) 6522 return GetNegatedExpression(N0, DAG, LegalOperations); 6523 6524 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6525 // constant pool values. 6526 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6527 !VT.isVector() && 6528 N0.getNode()->hasOneUse() && 6529 N0.getOperand(0).getValueType().isInteger()) { 6530 SDValue Int = N0.getOperand(0); 6531 EVT IntVT = Int.getValueType(); 6532 if (IntVT.isInteger() && !IntVT.isVector()) { 6533 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6534 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6535 AddToWorkList(Int.getNode()); 6536 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6537 VT, Int); 6538 } 6539 } 6540 6541 // (fneg (fmul c, x)) -> (fmul -c, x) 6542 if (N0.getOpcode() == ISD::FMUL) { 6543 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6544 if (CFP1) { 6545 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6546 N0.getOperand(0), 6547 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6548 N0.getOperand(1))); 6549 } 6550 } 6551 6552 return SDValue(); 6553} 6554 6555SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6556 SDValue N0 = N->getOperand(0); 6557 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6558 EVT VT = N->getValueType(0); 6559 6560 // fold (fceil c1) -> fceil(c1) 6561 if (N0CFP) 6562 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0); 6563 6564 return SDValue(); 6565} 6566 6567SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6568 SDValue N0 = N->getOperand(0); 6569 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6570 EVT VT = N->getValueType(0); 6571 6572 // fold (ftrunc c1) -> ftrunc(c1) 6573 if (N0CFP) 6574 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0); 6575 6576 return SDValue(); 6577} 6578 6579SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6580 SDValue N0 = N->getOperand(0); 6581 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6582 EVT VT = N->getValueType(0); 6583 6584 // fold (ffloor c1) -> ffloor(c1) 6585 if (N0CFP) 6586 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0); 6587 6588 return SDValue(); 6589} 6590 6591SDValue DAGCombiner::visitFABS(SDNode *N) { 6592 SDValue N0 = N->getOperand(0); 6593 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6594 EVT VT = N->getValueType(0); 6595 6596 if (VT.isVector()) { 6597 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6598 if (FoldedVOp.getNode()) return FoldedVOp; 6599 } 6600 6601 // fold (fabs c1) -> fabs(c1) 6602 if (N0CFP) 6603 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6604 // fold (fabs (fabs x)) -> (fabs x) 6605 if (N0.getOpcode() == ISD::FABS) 6606 return N->getOperand(0); 6607 // fold (fabs (fneg x)) -> (fabs x) 6608 // fold (fabs (fcopysign x, y)) -> (fabs x) 6609 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6610 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6611 6612 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6613 // constant pool values. 6614 if (!TLI.isFAbsFree(VT) && 6615 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6616 N0.getOperand(0).getValueType().isInteger() && 6617 !N0.getOperand(0).getValueType().isVector()) { 6618 SDValue Int = N0.getOperand(0); 6619 EVT IntVT = Int.getValueType(); 6620 if (IntVT.isInteger() && !IntVT.isVector()) { 6621 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6622 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6623 AddToWorkList(Int.getNode()); 6624 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6625 N->getValueType(0), Int); 6626 } 6627 } 6628 6629 return SDValue(); 6630} 6631 6632SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6633 SDValue Chain = N->getOperand(0); 6634 SDValue N1 = N->getOperand(1); 6635 SDValue N2 = N->getOperand(2); 6636 6637 // If N is a constant we could fold this into a fallthrough or unconditional 6638 // branch. However that doesn't happen very often in normal code, because 6639 // Instcombine/SimplifyCFG should have handled the available opportunities. 6640 // If we did this folding here, it would be necessary to update the 6641 // MachineBasicBlock CFG, which is awkward. 6642 6643 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6644 // on the target. 6645 if (N1.getOpcode() == ISD::SETCC && 6646 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6647 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6648 Chain, N1.getOperand(2), 6649 N1.getOperand(0), N1.getOperand(1), N2); 6650 } 6651 6652 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6653 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6654 (N1.getOperand(0).hasOneUse() && 6655 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6656 SDNode *Trunc = 0; 6657 if (N1.getOpcode() == ISD::TRUNCATE) { 6658 // Look pass the truncate. 6659 Trunc = N1.getNode(); 6660 N1 = N1.getOperand(0); 6661 } 6662 6663 // Match this pattern so that we can generate simpler code: 6664 // 6665 // %a = ... 6666 // %b = and i32 %a, 2 6667 // %c = srl i32 %b, 1 6668 // brcond i32 %c ... 6669 // 6670 // into 6671 // 6672 // %a = ... 6673 // %b = and i32 %a, 2 6674 // %c = setcc eq %b, 0 6675 // brcond %c ... 6676 // 6677 // This applies only when the AND constant value has one bit set and the 6678 // SRL constant is equal to the log2 of the AND constant. The back-end is 6679 // smart enough to convert the result into a TEST/JMP sequence. 6680 SDValue Op0 = N1.getOperand(0); 6681 SDValue Op1 = N1.getOperand(1); 6682 6683 if (Op0.getOpcode() == ISD::AND && 6684 Op1.getOpcode() == ISD::Constant) { 6685 SDValue AndOp1 = Op0.getOperand(1); 6686 6687 if (AndOp1.getOpcode() == ISD::Constant) { 6688 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6689 6690 if (AndConst.isPowerOf2() && 6691 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6692 SDValue SetCC = 6693 DAG.getSetCC(N->getDebugLoc(), 6694 TLI.getSetCCResultType(Op0.getValueType()), 6695 Op0, DAG.getConstant(0, Op0.getValueType()), 6696 ISD::SETNE); 6697 6698 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6699 MVT::Other, Chain, SetCC, N2); 6700 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6701 // will convert it back to (X & C1) >> C2. 6702 CombineTo(N, NewBRCond, false); 6703 // Truncate is dead. 6704 if (Trunc) { 6705 removeFromWorkList(Trunc); 6706 DAG.DeleteNode(Trunc); 6707 } 6708 // Replace the uses of SRL with SETCC 6709 WorkListRemover DeadNodes(*this); 6710 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6711 removeFromWorkList(N1.getNode()); 6712 DAG.DeleteNode(N1.getNode()); 6713 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6714 } 6715 } 6716 } 6717 6718 if (Trunc) 6719 // Restore N1 if the above transformation doesn't match. 6720 N1 = N->getOperand(1); 6721 } 6722 6723 // Transform br(xor(x, y)) -> br(x != y) 6724 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6725 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6726 SDNode *TheXor = N1.getNode(); 6727 SDValue Op0 = TheXor->getOperand(0); 6728 SDValue Op1 = TheXor->getOperand(1); 6729 if (Op0.getOpcode() == Op1.getOpcode()) { 6730 // Avoid missing important xor optimizations. 6731 SDValue Tmp = visitXOR(TheXor); 6732 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6733 DEBUG(dbgs() << "\nReplacing.8 "; 6734 TheXor->dump(&DAG); 6735 dbgs() << "\nWith: "; 6736 Tmp.getNode()->dump(&DAG); 6737 dbgs() << '\n'); 6738 WorkListRemover DeadNodes(*this); 6739 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6740 removeFromWorkList(TheXor); 6741 DAG.DeleteNode(TheXor); 6742 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6743 MVT::Other, Chain, Tmp, N2); 6744 } 6745 } 6746 6747 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6748 bool Equal = false; 6749 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6750 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6751 Op0.getOpcode() == ISD::XOR) { 6752 TheXor = Op0.getNode(); 6753 Equal = true; 6754 } 6755 6756 EVT SetCCVT = N1.getValueType(); 6757 if (LegalTypes) 6758 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6759 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6760 SetCCVT, 6761 Op0, Op1, 6762 Equal ? ISD::SETEQ : ISD::SETNE); 6763 // Replace the uses of XOR with SETCC 6764 WorkListRemover DeadNodes(*this); 6765 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6766 removeFromWorkList(N1.getNode()); 6767 DAG.DeleteNode(N1.getNode()); 6768 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6769 MVT::Other, Chain, SetCC, N2); 6770 } 6771 } 6772 6773 return SDValue(); 6774} 6775 6776// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6777// 6778SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6779 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6780 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6781 6782 // If N is a constant we could fold this into a fallthrough or unconditional 6783 // branch. However that doesn't happen very often in normal code, because 6784 // Instcombine/SimplifyCFG should have handled the available opportunities. 6785 // If we did this folding here, it would be necessary to update the 6786 // MachineBasicBlock CFG, which is awkward. 6787 6788 // Use SimplifySetCC to simplify SETCC's. 6789 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6790 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6791 false); 6792 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6793 6794 // fold to a simpler setcc 6795 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6796 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6797 N->getOperand(0), Simp.getOperand(2), 6798 Simp.getOperand(0), Simp.getOperand(1), 6799 N->getOperand(4)); 6800 6801 return SDValue(); 6802} 6803 6804/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6805/// uses N as its base pointer and that N may be folded in the load / store 6806/// addressing mode. 6807static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6808 SelectionDAG &DAG, 6809 const TargetLowering &TLI) { 6810 EVT VT; 6811 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6812 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6813 return false; 6814 VT = Use->getValueType(0); 6815 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6816 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6817 return false; 6818 VT = ST->getValue().getValueType(); 6819 } else 6820 return false; 6821 6822 AddrMode AM; 6823 if (N->getOpcode() == ISD::ADD) { 6824 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6825 if (Offset) 6826 // [reg +/- imm] 6827 AM.BaseOffs = Offset->getSExtValue(); 6828 else 6829 // [reg +/- reg] 6830 AM.Scale = 1; 6831 } else if (N->getOpcode() == ISD::SUB) { 6832 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6833 if (Offset) 6834 // [reg +/- imm] 6835 AM.BaseOffs = -Offset->getSExtValue(); 6836 else 6837 // [reg +/- reg] 6838 AM.Scale = 1; 6839 } else 6840 return false; 6841 6842 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6843} 6844 6845/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6846/// pre-indexed load / store when the base pointer is an add or subtract 6847/// and it has other uses besides the load / store. After the 6848/// transformation, the new indexed load / store has effectively folded 6849/// the add / subtract in and all of its other uses are redirected to the 6850/// new load / store. 6851bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6852 if (Level < AfterLegalizeDAG) 6853 return false; 6854 6855 bool isLoad = true; 6856 SDValue Ptr; 6857 EVT VT; 6858 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6859 if (LD->isIndexed()) 6860 return false; 6861 VT = LD->getMemoryVT(); 6862 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6863 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6864 return false; 6865 Ptr = LD->getBasePtr(); 6866 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6867 if (ST->isIndexed()) 6868 return false; 6869 VT = ST->getMemoryVT(); 6870 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6871 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6872 return false; 6873 Ptr = ST->getBasePtr(); 6874 isLoad = false; 6875 } else { 6876 return false; 6877 } 6878 6879 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6880 // out. There is no reason to make this a preinc/predec. 6881 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6882 Ptr.getNode()->hasOneUse()) 6883 return false; 6884 6885 // Ask the target to do addressing mode selection. 6886 SDValue BasePtr; 6887 SDValue Offset; 6888 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6889 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6890 return false; 6891 // Don't create a indexed load / store with zero offset. 6892 if (isa<ConstantSDNode>(Offset) && 6893 cast<ConstantSDNode>(Offset)->isNullValue()) 6894 return false; 6895 6896 // Try turning it into a pre-indexed load / store except when: 6897 // 1) The new base ptr is a frame index. 6898 // 2) If N is a store and the new base ptr is either the same as or is a 6899 // predecessor of the value being stored. 6900 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6901 // that would create a cycle. 6902 // 4) All uses are load / store ops that use it as old base ptr. 6903 6904 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6905 // (plus the implicit offset) to a register to preinc anyway. 6906 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6907 return false; 6908 6909 // Check #2. 6910 if (!isLoad) { 6911 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6912 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6913 return false; 6914 } 6915 6916 // Now check for #3 and #4. 6917 bool RealUse = false; 6918 6919 // Caches for hasPredecessorHelper 6920 SmallPtrSet<const SDNode *, 32> Visited; 6921 SmallVector<const SDNode *, 16> Worklist; 6922 6923 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6924 E = Ptr.getNode()->use_end(); I != E; ++I) { 6925 SDNode *Use = *I; 6926 if (Use == N) 6927 continue; 6928 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6929 return false; 6930 6931 // If Ptr may be folded in addressing mode of other use, then it's 6932 // not profitable to do this transformation. 6933 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6934 RealUse = true; 6935 } 6936 6937 if (!RealUse) 6938 return false; 6939 6940 SDValue Result; 6941 if (isLoad) 6942 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6943 BasePtr, Offset, AM); 6944 else 6945 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6946 BasePtr, Offset, AM); 6947 ++PreIndexedNodes; 6948 ++NodesCombined; 6949 DEBUG(dbgs() << "\nReplacing.4 "; 6950 N->dump(&DAG); 6951 dbgs() << "\nWith: "; 6952 Result.getNode()->dump(&DAG); 6953 dbgs() << '\n'); 6954 WorkListRemover DeadNodes(*this); 6955 if (isLoad) { 6956 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6957 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6958 } else { 6959 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6960 } 6961 6962 // Finally, since the node is now dead, remove it from the graph. 6963 DAG.DeleteNode(N); 6964 6965 // Replace the uses of Ptr with uses of the updated base value. 6966 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 6967 removeFromWorkList(Ptr.getNode()); 6968 DAG.DeleteNode(Ptr.getNode()); 6969 6970 return true; 6971} 6972 6973/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6974/// add / sub of the base pointer node into a post-indexed load / store. 6975/// The transformation folded the add / subtract into the new indexed 6976/// load / store effectively and all of its uses are redirected to the 6977/// new load / store. 6978bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6979 if (Level < AfterLegalizeDAG) 6980 return false; 6981 6982 bool isLoad = true; 6983 SDValue Ptr; 6984 EVT VT; 6985 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6986 if (LD->isIndexed()) 6987 return false; 6988 VT = LD->getMemoryVT(); 6989 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6990 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6991 return false; 6992 Ptr = LD->getBasePtr(); 6993 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6994 if (ST->isIndexed()) 6995 return false; 6996 VT = ST->getMemoryVT(); 6997 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6998 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6999 return false; 7000 Ptr = ST->getBasePtr(); 7001 isLoad = false; 7002 } else { 7003 return false; 7004 } 7005 7006 if (Ptr.getNode()->hasOneUse()) 7007 return false; 7008 7009 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 7010 E = Ptr.getNode()->use_end(); I != E; ++I) { 7011 SDNode *Op = *I; 7012 if (Op == N || 7013 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 7014 continue; 7015 7016 SDValue BasePtr; 7017 SDValue Offset; 7018 ISD::MemIndexedMode AM = ISD::UNINDEXED; 7019 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 7020 // Don't create a indexed load / store with zero offset. 7021 if (isa<ConstantSDNode>(Offset) && 7022 cast<ConstantSDNode>(Offset)->isNullValue()) 7023 continue; 7024 7025 // Try turning it into a post-indexed load / store except when 7026 // 1) All uses are load / store ops that use it as base ptr (and 7027 // it may be folded as addressing mmode). 7028 // 2) Op must be independent of N, i.e. Op is neither a predecessor 7029 // nor a successor of N. Otherwise, if Op is folded that would 7030 // create a cycle. 7031 7032 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 7033 continue; 7034 7035 // Check for #1. 7036 bool TryNext = false; 7037 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 7038 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 7039 SDNode *Use = *II; 7040 if (Use == Ptr.getNode()) 7041 continue; 7042 7043 // If all the uses are load / store addresses, then don't do the 7044 // transformation. 7045 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 7046 bool RealUse = false; 7047 for (SDNode::use_iterator III = Use->use_begin(), 7048 EEE = Use->use_end(); III != EEE; ++III) { 7049 SDNode *UseUse = *III; 7050 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 7051 RealUse = true; 7052 } 7053 7054 if (!RealUse) { 7055 TryNext = true; 7056 break; 7057 } 7058 } 7059 } 7060 7061 if (TryNext) 7062 continue; 7063 7064 // Check for #2 7065 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 7066 SDValue Result = isLoad 7067 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 7068 BasePtr, Offset, AM) 7069 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 7070 BasePtr, Offset, AM); 7071 ++PostIndexedNodes; 7072 ++NodesCombined; 7073 DEBUG(dbgs() << "\nReplacing.5 "; 7074 N->dump(&DAG); 7075 dbgs() << "\nWith: "; 7076 Result.getNode()->dump(&DAG); 7077 dbgs() << '\n'); 7078 WorkListRemover DeadNodes(*this); 7079 if (isLoad) { 7080 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7081 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7082 } else { 7083 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7084 } 7085 7086 // Finally, since the node is now dead, remove it from the graph. 7087 DAG.DeleteNode(N); 7088 7089 // Replace the uses of Use with uses of the updated base value. 7090 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 7091 Result.getValue(isLoad ? 1 : 0)); 7092 removeFromWorkList(Op); 7093 DAG.DeleteNode(Op); 7094 return true; 7095 } 7096 } 7097 } 7098 7099 return false; 7100} 7101 7102SDValue DAGCombiner::visitLOAD(SDNode *N) { 7103 LoadSDNode *LD = cast<LoadSDNode>(N); 7104 SDValue Chain = LD->getChain(); 7105 SDValue Ptr = LD->getBasePtr(); 7106 7107 // If load is not volatile and there are no uses of the loaded value (and 7108 // the updated indexed value in case of indexed loads), change uses of the 7109 // chain value into uses of the chain input (i.e. delete the dead load). 7110 if (!LD->isVolatile()) { 7111 if (N->getValueType(1) == MVT::Other) { 7112 // Unindexed loads. 7113 if (!N->hasAnyUseOfValue(0)) { 7114 // It's not safe to use the two value CombineTo variant here. e.g. 7115 // v1, chain2 = load chain1, loc 7116 // v2, chain3 = load chain2, loc 7117 // v3 = add v2, c 7118 // Now we replace use of chain2 with chain1. This makes the second load 7119 // isomorphic to the one we are deleting, and thus makes this load live. 7120 DEBUG(dbgs() << "\nReplacing.6 "; 7121 N->dump(&DAG); 7122 dbgs() << "\nWith chain: "; 7123 Chain.getNode()->dump(&DAG); 7124 dbgs() << "\n"); 7125 WorkListRemover DeadNodes(*this); 7126 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7127 7128 if (N->use_empty()) { 7129 removeFromWorkList(N); 7130 DAG.DeleteNode(N); 7131 } 7132 7133 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7134 } 7135 } else { 7136 // Indexed loads. 7137 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7138 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7139 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7140 DEBUG(dbgs() << "\nReplacing.7 "; 7141 N->dump(&DAG); 7142 dbgs() << "\nWith: "; 7143 Undef.getNode()->dump(&DAG); 7144 dbgs() << " and 2 other values\n"); 7145 WorkListRemover DeadNodes(*this); 7146 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7147 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7148 DAG.getUNDEF(N->getValueType(1))); 7149 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7150 removeFromWorkList(N); 7151 DAG.DeleteNode(N); 7152 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7153 } 7154 } 7155 } 7156 7157 // If this load is directly stored, replace the load value with the stored 7158 // value. 7159 // TODO: Handle store large -> read small portion. 7160 // TODO: Handle TRUNCSTORE/LOADEXT 7161 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7162 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7163 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7164 if (PrevST->getBasePtr() == Ptr && 7165 PrevST->getValue().getValueType() == N->getValueType(0)) 7166 return CombineTo(N, Chain.getOperand(1), Chain); 7167 } 7168 } 7169 7170 // Try to infer better alignment information than the load already has. 7171 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7172 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7173 if (Align > LD->getAlignment()) 7174 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 7175 LD->getValueType(0), 7176 Chain, Ptr, LD->getPointerInfo(), 7177 LD->getMemoryVT(), 7178 LD->isVolatile(), LD->isNonTemporal(), Align); 7179 } 7180 } 7181 7182 if (CombinerAA) { 7183 // Walk up chain skipping non-aliasing memory nodes. 7184 SDValue BetterChain = FindBetterChain(N, Chain); 7185 7186 // If there is a better chain. 7187 if (Chain != BetterChain) { 7188 SDValue ReplLoad; 7189 7190 // Replace the chain to void dependency. 7191 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7192 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 7193 BetterChain, Ptr, LD->getPointerInfo(), 7194 LD->isVolatile(), LD->isNonTemporal(), 7195 LD->isInvariant(), LD->getAlignment()); 7196 } else { 7197 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 7198 LD->getValueType(0), 7199 BetterChain, Ptr, LD->getPointerInfo(), 7200 LD->getMemoryVT(), 7201 LD->isVolatile(), 7202 LD->isNonTemporal(), 7203 LD->getAlignment()); 7204 } 7205 7206 // Create token factor to keep old chain connected. 7207 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7208 MVT::Other, Chain, ReplLoad.getValue(1)); 7209 7210 // Make sure the new and old chains are cleaned up. 7211 AddToWorkList(Token.getNode()); 7212 7213 // Replace uses with load result and token factor. Don't add users 7214 // to work list. 7215 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7216 } 7217 } 7218 7219 // Try transforming N to an indexed load. 7220 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7221 return SDValue(N, 0); 7222 7223 return SDValue(); 7224} 7225 7226/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 7227/// load is having specific bytes cleared out. If so, return the byte size 7228/// being masked out and the shift amount. 7229static std::pair<unsigned, unsigned> 7230CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 7231 std::pair<unsigned, unsigned> Result(0, 0); 7232 7233 // Check for the structure we're looking for. 7234 if (V->getOpcode() != ISD::AND || 7235 !isa<ConstantSDNode>(V->getOperand(1)) || 7236 !ISD::isNormalLoad(V->getOperand(0).getNode())) 7237 return Result; 7238 7239 // Check the chain and pointer. 7240 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 7241 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 7242 7243 // The store should be chained directly to the load or be an operand of a 7244 // tokenfactor. 7245 if (LD == Chain.getNode()) 7246 ; // ok. 7247 else if (Chain->getOpcode() != ISD::TokenFactor) 7248 return Result; // Fail. 7249 else { 7250 bool isOk = false; 7251 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 7252 if (Chain->getOperand(i).getNode() == LD) { 7253 isOk = true; 7254 break; 7255 } 7256 if (!isOk) return Result; 7257 } 7258 7259 // This only handles simple types. 7260 if (V.getValueType() != MVT::i16 && 7261 V.getValueType() != MVT::i32 && 7262 V.getValueType() != MVT::i64) 7263 return Result; 7264 7265 // Check the constant mask. Invert it so that the bits being masked out are 7266 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 7267 // follow the sign bit for uniformity. 7268 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 7269 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 7270 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 7271 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 7272 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 7273 if (NotMaskLZ == 64) return Result; // All zero mask. 7274 7275 // See if we have a continuous run of bits. If so, we have 0*1+0* 7276 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 7277 return Result; 7278 7279 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 7280 if (V.getValueType() != MVT::i64 && NotMaskLZ) 7281 NotMaskLZ -= 64-V.getValueSizeInBits(); 7282 7283 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 7284 switch (MaskedBytes) { 7285 case 1: 7286 case 2: 7287 case 4: break; 7288 default: return Result; // All one mask, or 5-byte mask. 7289 } 7290 7291 // Verify that the first bit starts at a multiple of mask so that the access 7292 // is aligned the same as the access width. 7293 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 7294 7295 Result.first = MaskedBytes; 7296 Result.second = NotMaskTZ/8; 7297 return Result; 7298} 7299 7300 7301/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 7302/// provides a value as specified by MaskInfo. If so, replace the specified 7303/// store with a narrower store of truncated IVal. 7304static SDNode * 7305ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 7306 SDValue IVal, StoreSDNode *St, 7307 DAGCombiner *DC) { 7308 unsigned NumBytes = MaskInfo.first; 7309 unsigned ByteShift = MaskInfo.second; 7310 SelectionDAG &DAG = DC->getDAG(); 7311 7312 // Check to see if IVal is all zeros in the part being masked in by the 'or' 7313 // that uses this. If not, this is not a replacement. 7314 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 7315 ByteShift*8, (ByteShift+NumBytes)*8); 7316 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 7317 7318 // Check that it is legal on the target to do this. It is legal if the new 7319 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 7320 // legalization. 7321 MVT VT = MVT::getIntegerVT(NumBytes*8); 7322 if (!DC->isTypeLegal(VT)) 7323 return 0; 7324 7325 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 7326 // shifted by ByteShift and truncated down to NumBytes. 7327 if (ByteShift) 7328 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 7329 DAG.getConstant(ByteShift*8, 7330 DC->getShiftAmountTy(IVal.getValueType()))); 7331 7332 // Figure out the offset for the store and the alignment of the access. 7333 unsigned StOffset; 7334 unsigned NewAlign = St->getAlignment(); 7335 7336 if (DAG.getTargetLoweringInfo().isLittleEndian()) 7337 StOffset = ByteShift; 7338 else 7339 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 7340 7341 SDValue Ptr = St->getBasePtr(); 7342 if (StOffset) { 7343 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 7344 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 7345 NewAlign = MinAlign(NewAlign, StOffset); 7346 } 7347 7348 // Truncate down to the new size. 7349 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 7350 7351 ++OpsNarrowed; 7352 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 7353 St->getPointerInfo().getWithOffset(StOffset), 7354 false, false, NewAlign).getNode(); 7355} 7356 7357 7358/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 7359/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 7360/// of the loaded bits, try narrowing the load and store if it would end up 7361/// being a win for performance or code size. 7362SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 7363 StoreSDNode *ST = cast<StoreSDNode>(N); 7364 if (ST->isVolatile()) 7365 return SDValue(); 7366 7367 SDValue Chain = ST->getChain(); 7368 SDValue Value = ST->getValue(); 7369 SDValue Ptr = ST->getBasePtr(); 7370 EVT VT = Value.getValueType(); 7371 7372 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 7373 return SDValue(); 7374 7375 unsigned Opc = Value.getOpcode(); 7376 7377 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 7378 // is a byte mask indicating a consecutive number of bytes, check to see if 7379 // Y is known to provide just those bytes. If so, we try to replace the 7380 // load + replace + store sequence with a single (narrower) store, which makes 7381 // the load dead. 7382 if (Opc == ISD::OR) { 7383 std::pair<unsigned, unsigned> MaskedLoad; 7384 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 7385 if (MaskedLoad.first) 7386 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7387 Value.getOperand(1), ST,this)) 7388 return SDValue(NewST, 0); 7389 7390 // Or is commutative, so try swapping X and Y. 7391 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 7392 if (MaskedLoad.first) 7393 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7394 Value.getOperand(0), ST,this)) 7395 return SDValue(NewST, 0); 7396 } 7397 7398 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 7399 Value.getOperand(1).getOpcode() != ISD::Constant) 7400 return SDValue(); 7401 7402 SDValue N0 = Value.getOperand(0); 7403 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 7404 Chain == SDValue(N0.getNode(), 1)) { 7405 LoadSDNode *LD = cast<LoadSDNode>(N0); 7406 if (LD->getBasePtr() != Ptr || 7407 LD->getPointerInfo().getAddrSpace() != 7408 ST->getPointerInfo().getAddrSpace()) 7409 return SDValue(); 7410 7411 // Find the type to narrow it the load / op / store to. 7412 SDValue N1 = Value.getOperand(1); 7413 unsigned BitWidth = N1.getValueSizeInBits(); 7414 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 7415 if (Opc == ISD::AND) 7416 Imm ^= APInt::getAllOnesValue(BitWidth); 7417 if (Imm == 0 || Imm.isAllOnesValue()) 7418 return SDValue(); 7419 unsigned ShAmt = Imm.countTrailingZeros(); 7420 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 7421 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 7422 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7423 while (NewBW < BitWidth && 7424 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 7425 TLI.isNarrowingProfitable(VT, NewVT))) { 7426 NewBW = NextPowerOf2(NewBW); 7427 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7428 } 7429 if (NewBW >= BitWidth) 7430 return SDValue(); 7431 7432 // If the lsb changed does not start at the type bitwidth boundary, 7433 // start at the previous one. 7434 if (ShAmt % NewBW) 7435 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 7436 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 7437 if ((Imm & Mask) == Imm) { 7438 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 7439 if (Opc == ISD::AND) 7440 NewImm ^= APInt::getAllOnesValue(NewBW); 7441 uint64_t PtrOff = ShAmt / 8; 7442 // For big endian targets, we need to adjust the offset to the pointer to 7443 // load the correct bytes. 7444 if (TLI.isBigEndian()) 7445 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 7446 7447 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 7448 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 7449 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy)) 7450 return SDValue(); 7451 7452 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 7453 Ptr.getValueType(), Ptr, 7454 DAG.getConstant(PtrOff, Ptr.getValueType())); 7455 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 7456 LD->getChain(), NewPtr, 7457 LD->getPointerInfo().getWithOffset(PtrOff), 7458 LD->isVolatile(), LD->isNonTemporal(), 7459 LD->isInvariant(), NewAlign); 7460 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 7461 DAG.getConstant(NewImm, NewVT)); 7462 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 7463 NewVal, NewPtr, 7464 ST->getPointerInfo().getWithOffset(PtrOff), 7465 false, false, NewAlign); 7466 7467 AddToWorkList(NewPtr.getNode()); 7468 AddToWorkList(NewLD.getNode()); 7469 AddToWorkList(NewVal.getNode()); 7470 WorkListRemover DeadNodes(*this); 7471 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7472 ++OpsNarrowed; 7473 return NewST; 7474 } 7475 } 7476 7477 return SDValue(); 7478} 7479 7480/// TransformFPLoadStorePair - For a given floating point load / store pair, 7481/// if the load value isn't used by any other operations, then consider 7482/// transforming the pair to integer load / store operations if the target 7483/// deems the transformation profitable. 7484SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7485 StoreSDNode *ST = cast<StoreSDNode>(N); 7486 SDValue Chain = ST->getChain(); 7487 SDValue Value = ST->getValue(); 7488 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7489 Value.hasOneUse() && 7490 Chain == SDValue(Value.getNode(), 1)) { 7491 LoadSDNode *LD = cast<LoadSDNode>(Value); 7492 EVT VT = LD->getMemoryVT(); 7493 if (!VT.isFloatingPoint() || 7494 VT != ST->getMemoryVT() || 7495 LD->isNonTemporal() || 7496 ST->isNonTemporal() || 7497 LD->getPointerInfo().getAddrSpace() != 0 || 7498 ST->getPointerInfo().getAddrSpace() != 0) 7499 return SDValue(); 7500 7501 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7502 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7503 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7504 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7505 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7506 return SDValue(); 7507 7508 unsigned LDAlign = LD->getAlignment(); 7509 unsigned STAlign = ST->getAlignment(); 7510 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7511 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy); 7512 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7513 return SDValue(); 7514 7515 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 7516 LD->getChain(), LD->getBasePtr(), 7517 LD->getPointerInfo(), 7518 false, false, false, LDAlign); 7519 7520 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 7521 NewLD, ST->getBasePtr(), 7522 ST->getPointerInfo(), 7523 false, false, STAlign); 7524 7525 AddToWorkList(NewLD.getNode()); 7526 AddToWorkList(NewST.getNode()); 7527 WorkListRemover DeadNodes(*this); 7528 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7529 ++LdStFP2Int; 7530 return NewST; 7531 } 7532 7533 return SDValue(); 7534} 7535 7536/// Returns the base pointer and an integer offset from that object. 7537static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) { 7538 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) { 7539 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue(); 7540 SDValue Base = Ptr->getOperand(0); 7541 return std::make_pair(Base, Offset); 7542 } 7543 7544 return std::make_pair(Ptr, 0); 7545} 7546 7547/// Holds a pointer to an LSBaseSDNode as well as information on where it 7548/// is located in a sequence of memory operations connected by a chain. 7549struct MemOpLink { 7550 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq): 7551 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { } 7552 // Ptr to the mem node. 7553 LSBaseSDNode *MemNode; 7554 // Offset from the base ptr. 7555 int64_t OffsetFromBase; 7556 // What is the sequence number of this mem node. 7557 // Lowest mem operand in the DAG starts at zero. 7558 unsigned SequenceNum; 7559}; 7560 7561/// Sorts store nodes in a link according to their offset from a shared 7562// base ptr. 7563struct ConsecutiveMemoryChainSorter { 7564 bool operator()(MemOpLink LHS, MemOpLink RHS) { 7565 return LHS.OffsetFromBase < RHS.OffsetFromBase; 7566 } 7567}; 7568 7569bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) { 7570 EVT MemVT = St->getMemoryVT(); 7571 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8; 7572 7573 // Don't merge vectors into wider inputs. 7574 if (MemVT.isVector() || !MemVT.isSimple()) 7575 return false; 7576 7577 // Perform an early exit check. Do not bother looking at stored values that 7578 // are not constants or loads. 7579 SDValue StoredVal = St->getValue(); 7580 bool IsLoadSrc = isa<LoadSDNode>(StoredVal); 7581 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) && 7582 !IsLoadSrc) 7583 return false; 7584 7585 // Only look at ends of store sequences. 7586 SDValue Chain = SDValue(St, 1); 7587 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE) 7588 return false; 7589 7590 // This holds the base pointer and the offset in bytes from the base pointer. 7591 std::pair<SDValue, int64_t> BasePtr = 7592 GetPointerBaseAndOffset(St->getBasePtr()); 7593 7594 // We must have a base and an offset. 7595 if (!BasePtr.first.getNode()) 7596 return false; 7597 7598 // Do not handle stores to undef base pointers. 7599 if (BasePtr.first.getOpcode() == ISD::UNDEF) 7600 return false; 7601 7602 // Save the LoadSDNodes that we find in the chain. 7603 // We need to make sure that these nodes do not interfere with 7604 // any of the store nodes. 7605 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes; 7606 7607 // Save the StoreSDNodes that we find in the chain. 7608 SmallVector<MemOpLink, 8> StoreNodes; 7609 7610 // Walk up the chain and look for nodes with offsets from the same 7611 // base pointer. Stop when reaching an instruction with a different kind 7612 // or instruction which has a different base pointer. 7613 unsigned Seq = 0; 7614 StoreSDNode *Index = St; 7615 while (Index) { 7616 // If the chain has more than one use, then we can't reorder the mem ops. 7617 if (Index != St && !SDValue(Index, 1)->hasOneUse()) 7618 break; 7619 7620 // Find the base pointer and offset for this memory node. 7621 std::pair<SDValue, int64_t> Ptr = 7622 GetPointerBaseAndOffset(Index->getBasePtr()); 7623 7624 // Check that the base pointer is the same as the original one. 7625 if (Ptr.first.getNode() != BasePtr.first.getNode()) 7626 break; 7627 7628 // Check that the alignment is the same. 7629 if (Index->getAlignment() != St->getAlignment()) 7630 break; 7631 7632 // The memory operands must not be volatile. 7633 if (Index->isVolatile() || Index->isIndexed()) 7634 break; 7635 7636 // No truncation. 7637 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index)) 7638 if (St->isTruncatingStore()) 7639 break; 7640 7641 // The stored memory type must be the same. 7642 if (Index->getMemoryVT() != MemVT) 7643 break; 7644 7645 // We do not allow unaligned stores because we want to prevent overriding 7646 // stores. 7647 if (Index->getAlignment()*8 != MemVT.getSizeInBits()) 7648 break; 7649 7650 // We found a potential memory operand to merge. 7651 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++)); 7652 7653 // Find the next memory operand in the chain. If the next operand in the 7654 // chain is a store then move up and continue the scan with the next 7655 // memory operand. If the next operand is a load save it and use alias 7656 // information to check if it interferes with anything. 7657 SDNode *NextInChain = Index->getChain().getNode(); 7658 while (1) { 7659 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) { 7660 // We found a store node. Use it for the next iteration. 7661 Index = STn; 7662 break; 7663 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) { 7664 // Save the load node for later. Continue the scan. 7665 AliasLoadNodes.push_back(Ldn); 7666 NextInChain = Ldn->getChain().getNode(); 7667 continue; 7668 } else { 7669 Index = NULL; 7670 break; 7671 } 7672 } 7673 } 7674 7675 // Check if there is anything to merge. 7676 if (StoreNodes.size() < 2) 7677 return false; 7678 7679 // Sort the memory operands according to their distance from the base pointer. 7680 std::sort(StoreNodes.begin(), StoreNodes.end(), 7681 ConsecutiveMemoryChainSorter()); 7682 7683 // Scan the memory operations on the chain and find the first non-consecutive 7684 // store memory address. 7685 unsigned LastConsecutiveStore = 0; 7686 int64_t StartAddress = StoreNodes[0].OffsetFromBase; 7687 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) { 7688 7689 // Check that the addresses are consecutive starting from the second 7690 // element in the list of stores. 7691 if (i > 0) { 7692 int64_t CurrAddress = StoreNodes[i].OffsetFromBase; 7693 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7694 break; 7695 } 7696 7697 bool Alias = false; 7698 // Check if this store interferes with any of the loads that we found. 7699 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld) 7700 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) { 7701 Alias = true; 7702 break; 7703 } 7704 // We found a load that alias with this store. Stop the sequence. 7705 if (Alias) 7706 break; 7707 7708 // Mark this node as useful. 7709 LastConsecutiveStore = i; 7710 } 7711 7712 // The node with the lowest store address. 7713 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; 7714 7715 // Store the constants into memory as one consecutive store. 7716 if (!IsLoadSrc) { 7717 unsigned LastLegalType = 0; 7718 unsigned LastLegalVectorType = 0; 7719 bool NonZero = false; 7720 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7721 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7722 SDValue StoredVal = St->getValue(); 7723 7724 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) { 7725 NonZero |= !C->isNullValue(); 7726 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) { 7727 NonZero |= !C->getConstantFPValue()->isNullValue(); 7728 } else { 7729 // Non constant. 7730 break; 7731 } 7732 7733 // Find a legal type for the constant store. 7734 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7735 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7736 if (TLI.isTypeLegal(StoreTy)) 7737 LastLegalType = i+1; 7738 7739 // Find a legal type for the vector store. 7740 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7741 if (TLI.isTypeLegal(Ty)) 7742 LastLegalVectorType = i + 1; 7743 } 7744 7745 // We only use vectors if the constant is known to be zero. 7746 if (NonZero) 7747 LastLegalVectorType = 0; 7748 7749 // Check if we found a legal integer type to store. 7750 if (LastLegalType == 0 && LastLegalVectorType == 0) 7751 return false; 7752 7753 bool UseVector = LastLegalVectorType > LastLegalType; 7754 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType; 7755 7756 // Make sure we have something to merge. 7757 if (NumElem < 2) 7758 return false; 7759 7760 unsigned EarliestNodeUsed = 0; 7761 for (unsigned i=0; i < NumElem; ++i) { 7762 // Find a chain for the new wide-store operand. Notice that some 7763 // of the store nodes that we found may not be selected for inclusion 7764 // in the wide store. The chain we use needs to be the chain of the 7765 // earliest store node which is *used* and replaced by the wide store. 7766 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7767 EarliestNodeUsed = i; 7768 } 7769 7770 // The earliest Node in the DAG. 7771 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7772 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc(); 7773 7774 SDValue StoredVal; 7775 if (UseVector) { 7776 // Find a legal type for the vector store. 7777 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7778 assert(TLI.isTypeLegal(Ty) && "Illegal vector store"); 7779 StoredVal = DAG.getConstant(0, Ty); 7780 } else { 7781 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7782 APInt StoreInt(StoreBW, 0); 7783 7784 // Construct a single integer constant which is made of the smaller 7785 // constant inputs. 7786 bool IsLE = TLI.isLittleEndian(); 7787 for (unsigned i = 0; i < NumElem ; ++i) { 7788 unsigned Idx = IsLE ?(NumElem - 1 - i) : i; 7789 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode); 7790 SDValue Val = St->getValue(); 7791 StoreInt<<=ElementSizeBytes*8; 7792 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) { 7793 StoreInt|=C->getAPIntValue().zext(StoreBW); 7794 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) { 7795 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW); 7796 } else { 7797 assert(false && "Invalid constant element type"); 7798 } 7799 } 7800 7801 // Create the new Load and Store operations. 7802 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7803 StoredVal = DAG.getConstant(StoreInt, StoreTy); 7804 } 7805 7806 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal, 7807 FirstInChain->getBasePtr(), 7808 FirstInChain->getPointerInfo(), 7809 false, false, 7810 FirstInChain->getAlignment()); 7811 7812 // Replace the first store with the new store 7813 CombineTo(EarliestOp, NewStore); 7814 // Erase all other stores. 7815 for (unsigned i = 0; i < NumElem ; ++i) { 7816 if (StoreNodes[i].MemNode == EarliestOp) 7817 continue; 7818 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7819 // ReplaceAllUsesWith will replace all uses that existed when it was 7820 // called, but graph optimizations may cause new ones to appear. For 7821 // example, the case in pr14333 looks like 7822 // 7823 // St's chain -> St -> another store -> X 7824 // 7825 // And the only difference from St to the other store is the chain. 7826 // When we change it's chain to be St's chain they become identical, 7827 // get CSEed and the net result is that X is now a use of St. 7828 // Since we know that St is redundant, just iterate. 7829 while (!St->use_empty()) 7830 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain()); 7831 removeFromWorkList(St); 7832 DAG.DeleteNode(St); 7833 } 7834 7835 return true; 7836 } 7837 7838 // Below we handle the case of multiple consecutive stores that 7839 // come from multiple consecutive loads. We merge them into a single 7840 // wide load and a single wide store. 7841 7842 // Look for load nodes which are used by the stored values. 7843 SmallVector<MemOpLink, 8> LoadNodes; 7844 7845 // Find acceptable loads. Loads need to have the same chain (token factor), 7846 // must not be zext, volatile, indexed, and they must be consecutive. 7847 SDValue LdBasePtr; 7848 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7849 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7850 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue()); 7851 if (!Ld) break; 7852 7853 // Loads must only have one use. 7854 if (!Ld->hasNUsesOfValue(1, 0)) 7855 break; 7856 7857 // Check that the alignment is the same as the stores. 7858 if (Ld->getAlignment() != St->getAlignment()) 7859 break; 7860 7861 // The memory operands must not be volatile. 7862 if (Ld->isVolatile() || Ld->isIndexed()) 7863 break; 7864 7865 // We do not accept ext loads. 7866 if (Ld->getExtensionType() != ISD::NON_EXTLOAD) 7867 break; 7868 7869 // The stored memory type must be the same. 7870 if (Ld->getMemoryVT() != MemVT) 7871 break; 7872 7873 std::pair<SDValue, int64_t> LdPtr = 7874 GetPointerBaseAndOffset(Ld->getBasePtr()); 7875 7876 // If this is not the first ptr that we check. 7877 if (LdBasePtr.getNode()) { 7878 // The base ptr must be the same. 7879 if (LdPtr.first != LdBasePtr) 7880 break; 7881 } else { 7882 // Check that all other base pointers are the same as this one. 7883 LdBasePtr = LdPtr.first; 7884 } 7885 7886 // We found a potential memory operand to merge. 7887 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0)); 7888 } 7889 7890 if (LoadNodes.size() < 2) 7891 return false; 7892 7893 // Scan the memory operations on the chain and find the first non-consecutive 7894 // load memory address. These variables hold the index in the store node 7895 // array. 7896 unsigned LastConsecutiveLoad = 0; 7897 // This variable refers to the size and not index in the array. 7898 unsigned LastLegalVectorType = 0; 7899 unsigned LastLegalIntegerType = 0; 7900 StartAddress = LoadNodes[0].OffsetFromBase; 7901 SDValue FirstChain = LoadNodes[0].MemNode->getChain(); 7902 for (unsigned i = 1; i < LoadNodes.size(); ++i) { 7903 // All loads much share the same chain. 7904 if (LoadNodes[i].MemNode->getChain() != FirstChain) 7905 break; 7906 7907 int64_t CurrAddress = LoadNodes[i].OffsetFromBase; 7908 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7909 break; 7910 LastConsecutiveLoad = i; 7911 7912 // Find a legal type for the vector store. 7913 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7914 if (TLI.isTypeLegal(StoreTy)) 7915 LastLegalVectorType = i + 1; 7916 7917 // Find a legal type for the integer store. 7918 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7919 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7920 if (TLI.isTypeLegal(StoreTy)) 7921 LastLegalIntegerType = i + 1; 7922 } 7923 7924 // Only use vector types if the vector type is larger than the integer type. 7925 // If they are the same, use integers. 7926 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType; 7927 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType); 7928 7929 // We add +1 here because the LastXXX variables refer to location while 7930 // the NumElem refers to array/index size. 7931 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1; 7932 NumElem = std::min(LastLegalType, NumElem); 7933 7934 if (NumElem < 2) 7935 return false; 7936 7937 // The earliest Node in the DAG. 7938 unsigned EarliestNodeUsed = 0; 7939 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7940 for (unsigned i=1; i<NumElem; ++i) { 7941 // Find a chain for the new wide-store operand. Notice that some 7942 // of the store nodes that we found may not be selected for inclusion 7943 // in the wide store. The chain we use needs to be the chain of the 7944 // earliest store node which is *used* and replaced by the wide store. 7945 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7946 EarliestNodeUsed = i; 7947 } 7948 7949 // Find if it is better to use vectors or integers to load and store 7950 // to memory. 7951 EVT JointMemOpVT; 7952 if (UseVectorTy) { 7953 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7954 } else { 7955 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7956 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7957 } 7958 7959 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc(); 7960 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc(); 7961 7962 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode); 7963 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL, 7964 FirstLoad->getChain(), 7965 FirstLoad->getBasePtr(), 7966 FirstLoad->getPointerInfo(), 7967 false, false, false, 7968 FirstLoad->getAlignment()); 7969 7970 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad, 7971 FirstInChain->getBasePtr(), 7972 FirstInChain->getPointerInfo(), false, false, 7973 FirstInChain->getAlignment()); 7974 7975 // Replace one of the loads with the new load. 7976 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode); 7977 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), 7978 SDValue(NewLoad.getNode(), 1)); 7979 7980 // Remove the rest of the load chains. 7981 for (unsigned i = 1; i < NumElem ; ++i) { 7982 // Replace all chain users of the old load nodes with the chain of the new 7983 // load node. 7984 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode); 7985 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain()); 7986 } 7987 7988 // Replace the first store with the new store. 7989 CombineTo(EarliestOp, NewStore); 7990 // Erase all other stores. 7991 for (unsigned i = 0; i < NumElem ; ++i) { 7992 // Remove all Store nodes. 7993 if (StoreNodes[i].MemNode == EarliestOp) 7994 continue; 7995 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7996 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain()); 7997 removeFromWorkList(St); 7998 DAG.DeleteNode(St); 7999 } 8000 8001 return true; 8002} 8003 8004SDValue DAGCombiner::visitSTORE(SDNode *N) { 8005 StoreSDNode *ST = cast<StoreSDNode>(N); 8006 SDValue Chain = ST->getChain(); 8007 SDValue Value = ST->getValue(); 8008 SDValue Ptr = ST->getBasePtr(); 8009 8010 // If this is a store of a bit convert, store the input value if the 8011 // resultant store does not need a higher alignment than the original. 8012 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 8013 ST->isUnindexed()) { 8014 unsigned OrigAlign = ST->getAlignment(); 8015 EVT SVT = Value.getOperand(0).getValueType(); 8016 unsigned Align = TLI.getDataLayout()-> 8017 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 8018 if (Align <= OrigAlign && 8019 ((!LegalOperations && !ST->isVolatile()) || 8020 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 8021 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8022 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8023 ST->isNonTemporal(), OrigAlign); 8024 } 8025 8026 // Turn 'store undef, Ptr' -> nothing. 8027 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 8028 return Chain; 8029 8030 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 8031 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 8032 // NOTE: If the original store is volatile, this transform must not increase 8033 // the number of stores. For example, on x86-32 an f64 can be stored in one 8034 // processor operation but an i64 (which is not legal) requires two. So the 8035 // transform should not be done in this case. 8036 if (Value.getOpcode() != ISD::TargetConstantFP) { 8037 SDValue Tmp; 8038 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 8039 default: llvm_unreachable("Unknown FP type"); 8040 case MVT::f16: // We don't do this for these yet. 8041 case MVT::f80: 8042 case MVT::f128: 8043 case MVT::ppcf128: 8044 break; 8045 case MVT::f32: 8046 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 8047 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8048 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 8049 bitcastToAPInt().getZExtValue(), MVT::i32); 8050 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 8051 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8052 ST->isNonTemporal(), ST->getAlignment()); 8053 } 8054 break; 8055 case MVT::f64: 8056 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 8057 !ST->isVolatile()) || 8058 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 8059 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 8060 getZExtValue(), MVT::i64); 8061 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 8062 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8063 ST->isNonTemporal(), ST->getAlignment()); 8064 } 8065 8066 if (!ST->isVolatile() && 8067 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8068 // Many FP stores are not made apparent until after legalize, e.g. for 8069 // argument passing. Since this is so common, custom legalize the 8070 // 64-bit integer store into two 32-bit stores. 8071 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 8072 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 8073 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 8074 if (TLI.isBigEndian()) std::swap(Lo, Hi); 8075 8076 unsigned Alignment = ST->getAlignment(); 8077 bool isVolatile = ST->isVolatile(); 8078 bool isNonTemporal = ST->isNonTemporal(); 8079 8080 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 8081 Ptr, ST->getPointerInfo(), 8082 isVolatile, isNonTemporal, 8083 ST->getAlignment()); 8084 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 8085 DAG.getConstant(4, Ptr.getValueType())); 8086 Alignment = MinAlign(Alignment, 4U); 8087 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 8088 Ptr, ST->getPointerInfo().getWithOffset(4), 8089 isVolatile, isNonTemporal, 8090 Alignment); 8091 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8092 St0, St1); 8093 } 8094 8095 break; 8096 } 8097 } 8098 } 8099 8100 // Try to infer better alignment information than the store already has. 8101 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 8102 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 8103 if (Align > ST->getAlignment()) 8104 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 8105 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8106 ST->isVolatile(), ST->isNonTemporal(), Align); 8107 } 8108 } 8109 8110 // Try transforming a pair floating point load / store ops to integer 8111 // load / store ops. 8112 SDValue NewST = TransformFPLoadStorePair(N); 8113 if (NewST.getNode()) 8114 return NewST; 8115 8116 if (CombinerAA) { 8117 // Walk up chain skipping non-aliasing memory nodes. 8118 SDValue BetterChain = FindBetterChain(N, Chain); 8119 8120 // If there is a better chain. 8121 if (Chain != BetterChain) { 8122 SDValue ReplStore; 8123 8124 // Replace the chain to avoid dependency. 8125 if (ST->isTruncatingStore()) { 8126 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8127 ST->getPointerInfo(), 8128 ST->getMemoryVT(), ST->isVolatile(), 8129 ST->isNonTemporal(), ST->getAlignment()); 8130 } else { 8131 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8132 ST->getPointerInfo(), 8133 ST->isVolatile(), ST->isNonTemporal(), 8134 ST->getAlignment()); 8135 } 8136 8137 // Create token to keep both nodes around. 8138 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 8139 MVT::Other, Chain, ReplStore); 8140 8141 // Make sure the new and old chains are cleaned up. 8142 AddToWorkList(Token.getNode()); 8143 8144 // Don't add users to work list. 8145 return CombineTo(N, Token, false); 8146 } 8147 } 8148 8149 // Try transforming N to an indexed store. 8150 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 8151 return SDValue(N, 0); 8152 8153 // FIXME: is there such a thing as a truncating indexed store? 8154 if (ST->isTruncatingStore() && ST->isUnindexed() && 8155 Value.getValueType().isInteger()) { 8156 // See if we can simplify the input to this truncstore with knowledge that 8157 // only the low bits are being used. For example: 8158 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 8159 SDValue Shorter = 8160 GetDemandedBits(Value, 8161 APInt::getLowBitsSet( 8162 Value.getValueType().getScalarType().getSizeInBits(), 8163 ST->getMemoryVT().getScalarType().getSizeInBits())); 8164 AddToWorkList(Value.getNode()); 8165 if (Shorter.getNode()) 8166 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 8167 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8168 ST->isVolatile(), ST->isNonTemporal(), 8169 ST->getAlignment()); 8170 8171 // Otherwise, see if we can simplify the operation with 8172 // SimplifyDemandedBits, which only works if the value has a single use. 8173 if (SimplifyDemandedBits(Value, 8174 APInt::getLowBitsSet( 8175 Value.getValueType().getScalarType().getSizeInBits(), 8176 ST->getMemoryVT().getScalarType().getSizeInBits()))) 8177 return SDValue(N, 0); 8178 } 8179 8180 // If this is a load followed by a store to the same location, then the store 8181 // is dead/noop. 8182 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 8183 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 8184 ST->isUnindexed() && !ST->isVolatile() && 8185 // There can't be any side effects between the load and store, such as 8186 // a call or store. 8187 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 8188 // The store is dead, remove it. 8189 return Chain; 8190 } 8191 } 8192 8193 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 8194 // truncating store. We can do this even if this is already a truncstore. 8195 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 8196 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 8197 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 8198 ST->getMemoryVT())) { 8199 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8200 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8201 ST->isVolatile(), ST->isNonTemporal(), 8202 ST->getAlignment()); 8203 } 8204 8205 // Only perform this optimization before the types are legal, because we 8206 // don't want to perform this optimization on every DAGCombine invocation. 8207 if (!LegalTypes) { 8208 bool EverChanged = false; 8209 8210 do { 8211 // There can be multiple store sequences on the same chain. 8212 // Keep trying to merge store sequences until we are unable to do so 8213 // or until we merge the last store on the chain. 8214 bool Changed = MergeConsecutiveStores(ST); 8215 EverChanged |= Changed; 8216 if (!Changed) break; 8217 } while (ST->getOpcode() != ISD::DELETED_NODE); 8218 8219 if (EverChanged) 8220 return SDValue(N, 0); 8221 } 8222 8223 return ReduceLoadOpStoreWidth(N); 8224} 8225 8226SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 8227 SDValue InVec = N->getOperand(0); 8228 SDValue InVal = N->getOperand(1); 8229 SDValue EltNo = N->getOperand(2); 8230 DebugLoc dl = N->getDebugLoc(); 8231 8232 // If the inserted element is an UNDEF, just use the input vector. 8233 if (InVal.getOpcode() == ISD::UNDEF) 8234 return InVec; 8235 8236 EVT VT = InVec.getValueType(); 8237 8238 // If we can't generate a legal BUILD_VECTOR, exit 8239 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 8240 return SDValue(); 8241 8242 // Check that we know which element is being inserted 8243 if (!isa<ConstantSDNode>(EltNo)) 8244 return SDValue(); 8245 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8246 8247 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 8248 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 8249 // vector elements. 8250 SmallVector<SDValue, 8> Ops; 8251 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 8252 Ops.append(InVec.getNode()->op_begin(), 8253 InVec.getNode()->op_end()); 8254 } else if (InVec.getOpcode() == ISD::UNDEF) { 8255 unsigned NElts = VT.getVectorNumElements(); 8256 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 8257 } else { 8258 return SDValue(); 8259 } 8260 8261 // Insert the element 8262 if (Elt < Ops.size()) { 8263 // All the operands of BUILD_VECTOR must have the same type; 8264 // we enforce that here. 8265 EVT OpVT = Ops[0].getValueType(); 8266 if (InVal.getValueType() != OpVT) 8267 InVal = OpVT.bitsGT(InVal.getValueType()) ? 8268 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 8269 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 8270 Ops[Elt] = InVal; 8271 } 8272 8273 // Return the new vector 8274 return DAG.getNode(ISD::BUILD_VECTOR, dl, 8275 VT, &Ops[0], Ops.size()); 8276} 8277 8278SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 8279 // (vextract (scalar_to_vector val, 0) -> val 8280 SDValue InVec = N->getOperand(0); 8281 EVT VT = InVec.getValueType(); 8282 EVT NVT = N->getValueType(0); 8283 8284 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 8285 // Check if the result type doesn't match the inserted element type. A 8286 // SCALAR_TO_VECTOR may truncate the inserted element and the 8287 // EXTRACT_VECTOR_ELT may widen the extracted vector. 8288 SDValue InOp = InVec.getOperand(0); 8289 if (InOp.getValueType() != NVT) { 8290 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 8291 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 8292 } 8293 return InOp; 8294 } 8295 8296 SDValue EltNo = N->getOperand(1); 8297 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 8298 8299 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 8300 // We only perform this optimization before the op legalization phase because 8301 // we may introduce new vector instructions which are not backed by TD 8302 // patterns. For example on AVX, extracting elements from a wide vector 8303 // without using extract_subvector. 8304 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 8305 && ConstEltNo && !LegalOperations) { 8306 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8307 int NumElem = VT.getVectorNumElements(); 8308 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 8309 // Find the new index to extract from. 8310 int OrigElt = SVOp->getMaskElt(Elt); 8311 8312 // Extracting an undef index is undef. 8313 if (OrigElt == -1) 8314 return DAG.getUNDEF(NVT); 8315 8316 // Select the right vector half to extract from. 8317 if (OrigElt < NumElem) { 8318 InVec = InVec->getOperand(0); 8319 } else { 8320 InVec = InVec->getOperand(1); 8321 OrigElt -= NumElem; 8322 } 8323 8324 EVT IndexTy = N->getOperand(1).getValueType(); 8325 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 8326 InVec, DAG.getConstant(OrigElt, IndexTy)); 8327 } 8328 8329 // Perform only after legalization to ensure build_vector / vector_shuffle 8330 // optimizations have already been done. 8331 if (!LegalOperations) return SDValue(); 8332 8333 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 8334 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 8335 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 8336 8337 if (ConstEltNo) { 8338 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8339 bool NewLoad = false; 8340 bool BCNumEltsChanged = false; 8341 EVT ExtVT = VT.getVectorElementType(); 8342 EVT LVT = ExtVT; 8343 8344 // If the result of load has to be truncated, then it's not necessarily 8345 // profitable. 8346 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 8347 return SDValue(); 8348 8349 if (InVec.getOpcode() == ISD::BITCAST) { 8350 // Don't duplicate a load with other uses. 8351 if (!InVec.hasOneUse()) 8352 return SDValue(); 8353 8354 EVT BCVT = InVec.getOperand(0).getValueType(); 8355 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 8356 return SDValue(); 8357 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 8358 BCNumEltsChanged = true; 8359 InVec = InVec.getOperand(0); 8360 ExtVT = BCVT.getVectorElementType(); 8361 NewLoad = true; 8362 } 8363 8364 LoadSDNode *LN0 = NULL; 8365 const ShuffleVectorSDNode *SVN = NULL; 8366 if (ISD::isNormalLoad(InVec.getNode())) { 8367 LN0 = cast<LoadSDNode>(InVec); 8368 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 8369 InVec.getOperand(0).getValueType() == ExtVT && 8370 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 8371 // Don't duplicate a load with other uses. 8372 if (!InVec.hasOneUse()) 8373 return SDValue(); 8374 8375 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 8376 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 8377 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 8378 // => 8379 // (load $addr+1*size) 8380 8381 // Don't duplicate a load with other uses. 8382 if (!InVec.hasOneUse()) 8383 return SDValue(); 8384 8385 // If the bit convert changed the number of elements, it is unsafe 8386 // to examine the mask. 8387 if (BCNumEltsChanged) 8388 return SDValue(); 8389 8390 // Select the input vector, guarding against out of range extract vector. 8391 unsigned NumElems = VT.getVectorNumElements(); 8392 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 8393 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 8394 8395 if (InVec.getOpcode() == ISD::BITCAST) { 8396 // Don't duplicate a load with other uses. 8397 if (!InVec.hasOneUse()) 8398 return SDValue(); 8399 8400 InVec = InVec.getOperand(0); 8401 } 8402 if (ISD::isNormalLoad(InVec.getNode())) { 8403 LN0 = cast<LoadSDNode>(InVec); 8404 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 8405 } 8406 } 8407 8408 // Make sure we found a non-volatile load and the extractelement is 8409 // the only use. 8410 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 8411 return SDValue(); 8412 8413 // If Idx was -1 above, Elt is going to be -1, so just return undef. 8414 if (Elt == -1) 8415 return DAG.getUNDEF(LVT); 8416 8417 unsigned Align = LN0->getAlignment(); 8418 if (NewLoad) { 8419 // Check the resultant load doesn't need a higher alignment than the 8420 // original load. 8421 unsigned NewAlign = 8422 TLI.getDataLayout() 8423 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 8424 8425 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 8426 return SDValue(); 8427 8428 Align = NewAlign; 8429 } 8430 8431 SDValue NewPtr = LN0->getBasePtr(); 8432 unsigned PtrOff = 0; 8433 8434 if (Elt) { 8435 PtrOff = LVT.getSizeInBits() * Elt / 8; 8436 EVT PtrType = NewPtr.getValueType(); 8437 if (TLI.isBigEndian()) 8438 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 8439 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 8440 DAG.getConstant(PtrOff, PtrType)); 8441 } 8442 8443 // The replacement we need to do here is a little tricky: we need to 8444 // replace an extractelement of a load with a load. 8445 // Use ReplaceAllUsesOfValuesWith to do the replacement. 8446 // Note that this replacement assumes that the extractvalue is the only 8447 // use of the load; that's okay because we don't want to perform this 8448 // transformation in other cases anyway. 8449 SDValue Load; 8450 SDValue Chain; 8451 if (NVT.bitsGT(LVT)) { 8452 // If the result type of vextract is wider than the load, then issue an 8453 // extending load instead. 8454 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 8455 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 8456 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 8457 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 8458 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 8459 Chain = Load.getValue(1); 8460 } else { 8461 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 8462 LN0->getPointerInfo().getWithOffset(PtrOff), 8463 LN0->isVolatile(), LN0->isNonTemporal(), 8464 LN0->isInvariant(), Align); 8465 Chain = Load.getValue(1); 8466 if (NVT.bitsLT(LVT)) 8467 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 8468 else 8469 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 8470 } 8471 WorkListRemover DeadNodes(*this); 8472 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 8473 SDValue To[] = { Load, Chain }; 8474 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 8475 // Since we're explcitly calling ReplaceAllUses, add the new node to the 8476 // worklist explicitly as well. 8477 AddToWorkList(Load.getNode()); 8478 AddUsersToWorkList(Load.getNode()); // Add users too 8479 // Make sure to revisit this node to clean it up; it will usually be dead. 8480 AddToWorkList(N); 8481 return SDValue(N, 0); 8482 } 8483 8484 return SDValue(); 8485} 8486 8487// Simplify (build_vec (ext )) to (bitcast (build_vec )) 8488SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) { 8489 // We perform this optimization post type-legalization because 8490 // the type-legalizer often scalarizes integer-promoted vectors. 8491 // Performing this optimization before may create bit-casts which 8492 // will be type-legalized to complex code sequences. 8493 // We perform this optimization only before the operation legalizer because we 8494 // may introduce illegal operations. 8495 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) 8496 return SDValue(); 8497 8498 unsigned NumInScalars = N->getNumOperands(); 8499 DebugLoc dl = N->getDebugLoc(); 8500 EVT VT = N->getValueType(0); 8501 8502 // Check to see if this is a BUILD_VECTOR of a bunch of values 8503 // which come from any_extend or zero_extend nodes. If so, we can create 8504 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 8505 // optimizations. We do not handle sign-extend because we can't fill the sign 8506 // using shuffles. 8507 EVT SourceType = MVT::Other; 8508 bool AllAnyExt = true; 8509 8510 for (unsigned i = 0; i != NumInScalars; ++i) { 8511 SDValue In = N->getOperand(i); 8512 // Ignore undef inputs. 8513 if (In.getOpcode() == ISD::UNDEF) continue; 8514 8515 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 8516 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 8517 8518 // Abort if the element is not an extension. 8519 if (!ZeroExt && !AnyExt) { 8520 SourceType = MVT::Other; 8521 break; 8522 } 8523 8524 // The input is a ZeroExt or AnyExt. Check the original type. 8525 EVT InTy = In.getOperand(0).getValueType(); 8526 8527 // Check that all of the widened source types are the same. 8528 if (SourceType == MVT::Other) 8529 // First time. 8530 SourceType = InTy; 8531 else if (InTy != SourceType) { 8532 // Multiple income types. Abort. 8533 SourceType = MVT::Other; 8534 break; 8535 } 8536 8537 // Check if all of the extends are ANY_EXTENDs. 8538 AllAnyExt &= AnyExt; 8539 } 8540 8541 // In order to have valid types, all of the inputs must be extended from the 8542 // same source type and all of the inputs must be any or zero extend. 8543 // Scalar sizes must be a power of two. 8544 EVT OutScalarTy = VT.getScalarType(); 8545 bool ValidTypes = SourceType != MVT::Other && 8546 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 8547 isPowerOf2_32(SourceType.getSizeInBits()); 8548 8549 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 8550 // turn into a single shuffle instruction. 8551 if (!ValidTypes) 8552 return SDValue(); 8553 8554 bool isLE = TLI.isLittleEndian(); 8555 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 8556 assert(ElemRatio > 1 && "Invalid element size ratio"); 8557 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 8558 DAG.getConstant(0, SourceType); 8559 8560 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements(); 8561 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 8562 8563 // Populate the new build_vector 8564 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 8565 SDValue Cast = N->getOperand(i); 8566 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 8567 Cast.getOpcode() == ISD::ZERO_EXTEND || 8568 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 8569 SDValue In; 8570 if (Cast.getOpcode() == ISD::UNDEF) 8571 In = DAG.getUNDEF(SourceType); 8572 else 8573 In = Cast->getOperand(0); 8574 unsigned Index = isLE ? (i * ElemRatio) : 8575 (i * ElemRatio + (ElemRatio - 1)); 8576 8577 assert(Index < Ops.size() && "Invalid index"); 8578 Ops[Index] = In; 8579 } 8580 8581 // The type of the new BUILD_VECTOR node. 8582 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 8583 assert(VecVT.getSizeInBits() == VT.getSizeInBits() && 8584 "Invalid vector size"); 8585 // Check if the new vector type is legal. 8586 if (!isTypeLegal(VecVT)) return SDValue(); 8587 8588 // Make the new BUILD_VECTOR. 8589 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size()); 8590 8591 // The new BUILD_VECTOR node has the potential to be further optimized. 8592 AddToWorkList(BV.getNode()); 8593 // Bitcast to the desired type. 8594 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 8595} 8596 8597SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) { 8598 EVT VT = N->getValueType(0); 8599 8600 unsigned NumInScalars = N->getNumOperands(); 8601 DebugLoc dl = N->getDebugLoc(); 8602 8603 EVT SrcVT = MVT::Other; 8604 unsigned Opcode = ISD::DELETED_NODE; 8605 unsigned NumDefs = 0; 8606 8607 for (unsigned i = 0; i != NumInScalars; ++i) { 8608 SDValue In = N->getOperand(i); 8609 unsigned Opc = In.getOpcode(); 8610 8611 if (Opc == ISD::UNDEF) 8612 continue; 8613 8614 // If all scalar values are floats and converted from integers. 8615 if (Opcode == ISD::DELETED_NODE && 8616 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { 8617 Opcode = Opc; 8618 // If not supported by target, bail out. 8619 if (TLI.getOperationAction(Opcode, VT) != TargetLowering::Legal && 8620 TLI.getOperationAction(Opcode, VT) != TargetLowering::Custom) 8621 return SDValue(); 8622 } 8623 if (Opc != Opcode) 8624 return SDValue(); 8625 8626 EVT InVT = In.getOperand(0).getValueType(); 8627 8628 // If all scalar values are typed differently, bail out. It's chosen to 8629 // simplify BUILD_VECTOR of integer types. 8630 if (SrcVT == MVT::Other) 8631 SrcVT = InVT; 8632 if (SrcVT != InVT) 8633 return SDValue(); 8634 NumDefs++; 8635 } 8636 8637 // If the vector has just one element defined, it's not worth to fold it into 8638 // a vectorized one. 8639 if (NumDefs < 2) 8640 return SDValue(); 8641 8642 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) 8643 && "Should only handle conversion from integer to float."); 8644 assert(SrcVT != MVT::Other && "Cannot determine source type!"); 8645 8646 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars); 8647 SmallVector<SDValue, 8> Opnds; 8648 for (unsigned i = 0; i != NumInScalars; ++i) { 8649 SDValue In = N->getOperand(i); 8650 8651 if (In.getOpcode() == ISD::UNDEF) 8652 Opnds.push_back(DAG.getUNDEF(SrcVT)); 8653 else 8654 Opnds.push_back(In.getOperand(0)); 8655 } 8656 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, 8657 &Opnds[0], Opnds.size()); 8658 AddToWorkList(BV.getNode()); 8659 8660 return DAG.getNode(Opcode, dl, VT, BV); 8661} 8662 8663SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 8664 unsigned NumInScalars = N->getNumOperands(); 8665 DebugLoc dl = N->getDebugLoc(); 8666 EVT VT = N->getValueType(0); 8667 8668 // A vector built entirely of undefs is undef. 8669 if (ISD::allOperandsUndef(N)) 8670 return DAG.getUNDEF(VT); 8671 8672 SDValue V = reduceBuildVecExtToExtBuildVec(N); 8673 if (V.getNode()) 8674 return V; 8675 8676 V = reduceBuildVecConvertToConvertBuildVec(N); 8677 if (V.getNode()) 8678 return V; 8679 8680 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 8681 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 8682 // at most two distinct vectors, turn this into a shuffle node. 8683 8684 // May only combine to shuffle after legalize if shuffle is legal. 8685 if (LegalOperations && 8686 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 8687 return SDValue(); 8688 8689 SDValue VecIn1, VecIn2; 8690 for (unsigned i = 0; i != NumInScalars; ++i) { 8691 // Ignore undef inputs. 8692 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 8693 8694 // If this input is something other than a EXTRACT_VECTOR_ELT with a 8695 // constant index, bail out. 8696 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 8697 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 8698 VecIn1 = VecIn2 = SDValue(0, 0); 8699 break; 8700 } 8701 8702 // We allow up to two distinct input vectors. 8703 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 8704 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 8705 continue; 8706 8707 if (VecIn1.getNode() == 0) { 8708 VecIn1 = ExtractedFromVec; 8709 } else if (VecIn2.getNode() == 0) { 8710 VecIn2 = ExtractedFromVec; 8711 } else { 8712 // Too many inputs. 8713 VecIn1 = VecIn2 = SDValue(0, 0); 8714 break; 8715 } 8716 } 8717 8718 // If everything is good, we can make a shuffle operation. 8719 if (VecIn1.getNode()) { 8720 SmallVector<int, 8> Mask; 8721 for (unsigned i = 0; i != NumInScalars; ++i) { 8722 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 8723 Mask.push_back(-1); 8724 continue; 8725 } 8726 8727 // If extracting from the first vector, just use the index directly. 8728 SDValue Extract = N->getOperand(i); 8729 SDValue ExtVal = Extract.getOperand(1); 8730 if (Extract.getOperand(0) == VecIn1) { 8731 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8732 if (ExtIndex > VT.getVectorNumElements()) 8733 return SDValue(); 8734 8735 Mask.push_back(ExtIndex); 8736 continue; 8737 } 8738 8739 // Otherwise, use InIdx + VecSize 8740 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8741 Mask.push_back(Idx+NumInScalars); 8742 } 8743 8744 // We can't generate a shuffle node with mismatched input and output types. 8745 // Attempt to transform a single input vector to the correct type. 8746 if ((VT != VecIn1.getValueType())) { 8747 // We don't support shuffeling between TWO values of different types. 8748 if (VecIn2.getNode() != 0) 8749 return SDValue(); 8750 8751 // We only support widening of vectors which are half the size of the 8752 // output registers. For example XMM->YMM widening on X86 with AVX. 8753 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 8754 return SDValue(); 8755 8756 // If the input vector type has a different base type to the output 8757 // vector type, bail out. 8758 if (VecIn1.getValueType().getVectorElementType() != 8759 VT.getVectorElementType()) 8760 return SDValue(); 8761 8762 // Widen the input vector by adding undef values. 8763 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8764 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 8765 } 8766 8767 // If VecIn2 is unused then change it to undef. 8768 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 8769 8770 // Check that we were able to transform all incoming values to the same 8771 // type. 8772 if (VecIn2.getValueType() != VecIn1.getValueType() || 8773 VecIn1.getValueType() != VT) 8774 return SDValue(); 8775 8776 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 8777 if (!isTypeLegal(VT)) 8778 return SDValue(); 8779 8780 // Return the new VECTOR_SHUFFLE node. 8781 SDValue Ops[2]; 8782 Ops[0] = VecIn1; 8783 Ops[1] = VecIn2; 8784 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]); 8785 } 8786 8787 return SDValue(); 8788} 8789 8790SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 8791 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 8792 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 8793 // inputs come from at most two distinct vectors, turn this into a shuffle 8794 // node. 8795 8796 // If we only have one input vector, we don't need to do any concatenation. 8797 if (N->getNumOperands() == 1) 8798 return N->getOperand(0); 8799 8800 // Check if all of the operands are undefs. 8801 if (ISD::allOperandsUndef(N)) 8802 return DAG.getUNDEF(N->getValueType(0)); 8803 8804 return SDValue(); 8805} 8806 8807SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 8808 EVT NVT = N->getValueType(0); 8809 SDValue V = N->getOperand(0); 8810 8811 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 8812 // Handle only simple case where vector being inserted and vector 8813 // being extracted are of same type, and are half size of larger vectors. 8814 EVT BigVT = V->getOperand(0).getValueType(); 8815 EVT SmallVT = V->getOperand(1).getValueType(); 8816 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 8817 return SDValue(); 8818 8819 // Only handle cases where both indexes are constants with the same type. 8820 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8821 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 8822 8823 if (InsIdx && ExtIdx && 8824 InsIdx->getValueType(0).getSizeInBits() <= 64 && 8825 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 8826 // Combine: 8827 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 8828 // Into: 8829 // indices are equal => V1 8830 // otherwise => (extract_subvec V1, ExtIdx) 8831 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 8832 return V->getOperand(1); 8833 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 8834 V->getOperand(0), N->getOperand(1)); 8835 } 8836 } 8837 8838 if (V->getOpcode() == ISD::CONCAT_VECTORS) { 8839 // Combine: 8840 // (extract_subvec (concat V1, V2, ...), i) 8841 // Into: 8842 // Vi if possible 8843 // Only operand 0 is checked as 'concat' assumes all inputs of the same type. 8844 if (V->getOperand(0).getValueType() != NVT) 8845 return SDValue(); 8846 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 8847 unsigned NumElems = NVT.getVectorNumElements(); 8848 assert((Idx % NumElems) == 0 && 8849 "IDX in concat is not a multiple of the result vector length."); 8850 return V->getOperand(Idx / NumElems); 8851 } 8852 8853 return SDValue(); 8854} 8855 8856SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 8857 EVT VT = N->getValueType(0); 8858 unsigned NumElts = VT.getVectorNumElements(); 8859 8860 SDValue N0 = N->getOperand(0); 8861 SDValue N1 = N->getOperand(1); 8862 8863 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 8864 8865 // Canonicalize shuffle undef, undef -> undef 8866 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 8867 return DAG.getUNDEF(VT); 8868 8869 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8870 8871 // Canonicalize shuffle v, v -> v, undef 8872 if (N0 == N1) { 8873 SmallVector<int, 8> NewMask; 8874 for (unsigned i = 0; i != NumElts; ++i) { 8875 int Idx = SVN->getMaskElt(i); 8876 if (Idx >= (int)NumElts) Idx -= NumElts; 8877 NewMask.push_back(Idx); 8878 } 8879 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 8880 &NewMask[0]); 8881 } 8882 8883 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 8884 if (N0.getOpcode() == ISD::UNDEF) { 8885 SmallVector<int, 8> NewMask; 8886 for (unsigned i = 0; i != NumElts; ++i) { 8887 int Idx = SVN->getMaskElt(i); 8888 if (Idx >= 0) { 8889 if (Idx < (int)NumElts) 8890 Idx += NumElts; 8891 else 8892 Idx -= NumElts; 8893 } 8894 NewMask.push_back(Idx); 8895 } 8896 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 8897 &NewMask[0]); 8898 } 8899 8900 // Remove references to rhs if it is undef 8901 if (N1.getOpcode() == ISD::UNDEF) { 8902 bool Changed = false; 8903 SmallVector<int, 8> NewMask; 8904 for (unsigned i = 0; i != NumElts; ++i) { 8905 int Idx = SVN->getMaskElt(i); 8906 if (Idx >= (int)NumElts) { 8907 Idx = -1; 8908 Changed = true; 8909 } 8910 NewMask.push_back(Idx); 8911 } 8912 if (Changed) 8913 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 8914 } 8915 8916 // If it is a splat, check if the argument vector is another splat or a 8917 // build_vector with all scalar elements the same. 8918 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 8919 SDNode *V = N0.getNode(); 8920 8921 // If this is a bit convert that changes the element type of the vector but 8922 // not the number of vector elements, look through it. Be careful not to 8923 // look though conversions that change things like v4f32 to v2f64. 8924 if (V->getOpcode() == ISD::BITCAST) { 8925 SDValue ConvInput = V->getOperand(0); 8926 if (ConvInput.getValueType().isVector() && 8927 ConvInput.getValueType().getVectorNumElements() == NumElts) 8928 V = ConvInput.getNode(); 8929 } 8930 8931 if (V->getOpcode() == ISD::BUILD_VECTOR) { 8932 assert(V->getNumOperands() == NumElts && 8933 "BUILD_VECTOR has wrong number of operands"); 8934 SDValue Base; 8935 bool AllSame = true; 8936 for (unsigned i = 0; i != NumElts; ++i) { 8937 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 8938 Base = V->getOperand(i); 8939 break; 8940 } 8941 } 8942 // Splat of <u, u, u, u>, return <u, u, u, u> 8943 if (!Base.getNode()) 8944 return N0; 8945 for (unsigned i = 0; i != NumElts; ++i) { 8946 if (V->getOperand(i) != Base) { 8947 AllSame = false; 8948 break; 8949 } 8950 } 8951 // Splat of <x, x, x, x>, return <x, x, x, x> 8952 if (AllSame) 8953 return N0; 8954 } 8955 } 8956 8957 // If this shuffle node is simply a swizzle of another shuffle node, 8958 // and it reverses the swizzle of the previous shuffle then we can 8959 // optimize shuffle(shuffle(x, undef), undef) -> x. 8960 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 8961 N1.getOpcode() == ISD::UNDEF) { 8962 8963 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 8964 8965 // Shuffle nodes can only reverse shuffles with a single non-undef value. 8966 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 8967 return SDValue(); 8968 8969 // The incoming shuffle must be of the same type as the result of the 8970 // current shuffle. 8971 assert(OtherSV->getOperand(0).getValueType() == VT && 8972 "Shuffle types don't match"); 8973 8974 for (unsigned i = 0; i != NumElts; ++i) { 8975 int Idx = SVN->getMaskElt(i); 8976 assert(Idx < (int)NumElts && "Index references undef operand"); 8977 // Next, this index comes from the first value, which is the incoming 8978 // shuffle. Adopt the incoming index. 8979 if (Idx >= 0) 8980 Idx = OtherSV->getMaskElt(Idx); 8981 8982 // The combined shuffle must map each index to itself. 8983 if (Idx >= 0 && (unsigned)Idx != i) 8984 return SDValue(); 8985 } 8986 8987 return OtherSV->getOperand(0); 8988 } 8989 8990 return SDValue(); 8991} 8992 8993SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 8994 if (!TLI.getShouldFoldAtomicFences()) 8995 return SDValue(); 8996 8997 SDValue atomic = N->getOperand(0); 8998 switch (atomic.getOpcode()) { 8999 case ISD::ATOMIC_CMP_SWAP: 9000 case ISD::ATOMIC_SWAP: 9001 case ISD::ATOMIC_LOAD_ADD: 9002 case ISD::ATOMIC_LOAD_SUB: 9003 case ISD::ATOMIC_LOAD_AND: 9004 case ISD::ATOMIC_LOAD_OR: 9005 case ISD::ATOMIC_LOAD_XOR: 9006 case ISD::ATOMIC_LOAD_NAND: 9007 case ISD::ATOMIC_LOAD_MIN: 9008 case ISD::ATOMIC_LOAD_MAX: 9009 case ISD::ATOMIC_LOAD_UMIN: 9010 case ISD::ATOMIC_LOAD_UMAX: 9011 break; 9012 default: 9013 return SDValue(); 9014 } 9015 9016 SDValue fence = atomic.getOperand(0); 9017 if (fence.getOpcode() != ISD::MEMBARRIER) 9018 return SDValue(); 9019 9020 switch (atomic.getOpcode()) { 9021 case ISD::ATOMIC_CMP_SWAP: 9022 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 9023 fence.getOperand(0), 9024 atomic.getOperand(1), atomic.getOperand(2), 9025 atomic.getOperand(3)), atomic.getResNo()); 9026 case ISD::ATOMIC_SWAP: 9027 case ISD::ATOMIC_LOAD_ADD: 9028 case ISD::ATOMIC_LOAD_SUB: 9029 case ISD::ATOMIC_LOAD_AND: 9030 case ISD::ATOMIC_LOAD_OR: 9031 case ISD::ATOMIC_LOAD_XOR: 9032 case ISD::ATOMIC_LOAD_NAND: 9033 case ISD::ATOMIC_LOAD_MIN: 9034 case ISD::ATOMIC_LOAD_MAX: 9035 case ISD::ATOMIC_LOAD_UMIN: 9036 case ISD::ATOMIC_LOAD_UMAX: 9037 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 9038 fence.getOperand(0), 9039 atomic.getOperand(1), atomic.getOperand(2)), 9040 atomic.getResNo()); 9041 default: 9042 return SDValue(); 9043 } 9044} 9045 9046/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 9047/// an AND to a vector_shuffle with the destination vector and a zero vector. 9048/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 9049/// vector_shuffle V, Zero, <0, 4, 2, 4> 9050SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 9051 EVT VT = N->getValueType(0); 9052 DebugLoc dl = N->getDebugLoc(); 9053 SDValue LHS = N->getOperand(0); 9054 SDValue RHS = N->getOperand(1); 9055 if (N->getOpcode() == ISD::AND) { 9056 if (RHS.getOpcode() == ISD::BITCAST) 9057 RHS = RHS.getOperand(0); 9058 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 9059 SmallVector<int, 8> Indices; 9060 unsigned NumElts = RHS.getNumOperands(); 9061 for (unsigned i = 0; i != NumElts; ++i) { 9062 SDValue Elt = RHS.getOperand(i); 9063 if (!isa<ConstantSDNode>(Elt)) 9064 return SDValue(); 9065 9066 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 9067 Indices.push_back(i); 9068 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 9069 Indices.push_back(NumElts); 9070 else 9071 return SDValue(); 9072 } 9073 9074 // Let's see if the target supports this vector_shuffle. 9075 EVT RVT = RHS.getValueType(); 9076 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 9077 return SDValue(); 9078 9079 // Return the new VECTOR_SHUFFLE node. 9080 EVT EltVT = RVT.getVectorElementType(); 9081 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 9082 DAG.getConstant(0, EltVT)); 9083 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9084 RVT, &ZeroOps[0], ZeroOps.size()); 9085 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 9086 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 9087 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 9088 } 9089 } 9090 9091 return SDValue(); 9092} 9093 9094/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 9095SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 9096 // After legalize, the target may be depending on adds and other 9097 // binary ops to provide legal ways to construct constants or other 9098 // things. Simplifying them may result in a loss of legality. 9099 if (LegalOperations) return SDValue(); 9100 9101 assert(N->getValueType(0).isVector() && 9102 "SimplifyVBinOp only works on vectors!"); 9103 9104 SDValue LHS = N->getOperand(0); 9105 SDValue RHS = N->getOperand(1); 9106 SDValue Shuffle = XformToShuffleWithZero(N); 9107 if (Shuffle.getNode()) return Shuffle; 9108 9109 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 9110 // this operation. 9111 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 9112 RHS.getOpcode() == ISD::BUILD_VECTOR) { 9113 SmallVector<SDValue, 8> Ops; 9114 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 9115 SDValue LHSOp = LHS.getOperand(i); 9116 SDValue RHSOp = RHS.getOperand(i); 9117 // If these two elements can't be folded, bail out. 9118 if ((LHSOp.getOpcode() != ISD::UNDEF && 9119 LHSOp.getOpcode() != ISD::Constant && 9120 LHSOp.getOpcode() != ISD::ConstantFP) || 9121 (RHSOp.getOpcode() != ISD::UNDEF && 9122 RHSOp.getOpcode() != ISD::Constant && 9123 RHSOp.getOpcode() != ISD::ConstantFP)) 9124 break; 9125 9126 // Can't fold divide by zero. 9127 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 9128 N->getOpcode() == ISD::FDIV) { 9129 if ((RHSOp.getOpcode() == ISD::Constant && 9130 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 9131 (RHSOp.getOpcode() == ISD::ConstantFP && 9132 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 9133 break; 9134 } 9135 9136 EVT VT = LHSOp.getValueType(); 9137 EVT RVT = RHSOp.getValueType(); 9138 if (RVT != VT) { 9139 // Integer BUILD_VECTOR operands may have types larger than the element 9140 // size (e.g., when the element type is not legal). Prior to type 9141 // legalization, the types may not match between the two BUILD_VECTORS. 9142 // Truncate one of the operands to make them match. 9143 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 9144 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 9145 } else { 9146 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 9147 VT = RVT; 9148 } 9149 } 9150 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 9151 LHSOp, RHSOp); 9152 if (FoldOp.getOpcode() != ISD::UNDEF && 9153 FoldOp.getOpcode() != ISD::Constant && 9154 FoldOp.getOpcode() != ISD::ConstantFP) 9155 break; 9156 Ops.push_back(FoldOp); 9157 AddToWorkList(FoldOp.getNode()); 9158 } 9159 9160 if (Ops.size() == LHS.getNumOperands()) 9161 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9162 LHS.getValueType(), &Ops[0], Ops.size()); 9163 } 9164 9165 return SDValue(); 9166} 9167 9168/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 9169SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 9170 // After legalize, the target may be depending on adds and other 9171 // binary ops to provide legal ways to construct constants or other 9172 // things. Simplifying them may result in a loss of legality. 9173 if (LegalOperations) return SDValue(); 9174 9175 assert(N->getValueType(0).isVector() && 9176 "SimplifyVUnaryOp only works on vectors!"); 9177 9178 SDValue N0 = N->getOperand(0); 9179 9180 if (N0.getOpcode() != ISD::BUILD_VECTOR) 9181 return SDValue(); 9182 9183 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 9184 SmallVector<SDValue, 8> Ops; 9185 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 9186 SDValue Op = N0.getOperand(i); 9187 if (Op.getOpcode() != ISD::UNDEF && 9188 Op.getOpcode() != ISD::ConstantFP) 9189 break; 9190 EVT EltVT = Op.getValueType(); 9191 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op); 9192 if (FoldOp.getOpcode() != ISD::UNDEF && 9193 FoldOp.getOpcode() != ISD::ConstantFP) 9194 break; 9195 Ops.push_back(FoldOp); 9196 AddToWorkList(FoldOp.getNode()); 9197 } 9198 9199 if (Ops.size() != N0.getNumOperands()) 9200 return SDValue(); 9201 9202 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9203 N0.getValueType(), &Ops[0], Ops.size()); 9204} 9205 9206SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 9207 SDValue N1, SDValue N2){ 9208 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 9209 9210 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 9211 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 9212 9213 // If we got a simplified select_cc node back from SimplifySelectCC, then 9214 // break it down into a new SETCC node, and a new SELECT node, and then return 9215 // the SELECT node, since we were called with a SELECT node. 9216 if (SCC.getNode()) { 9217 // Check to see if we got a select_cc back (to turn into setcc/select). 9218 // Otherwise, just return whatever node we got back, like fabs. 9219 if (SCC.getOpcode() == ISD::SELECT_CC) { 9220 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 9221 N0.getValueType(), 9222 SCC.getOperand(0), SCC.getOperand(1), 9223 SCC.getOperand(4)); 9224 AddToWorkList(SETCC.getNode()); 9225 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 9226 SCC.getOperand(2), SCC.getOperand(3), SETCC); 9227 } 9228 9229 return SCC; 9230 } 9231 return SDValue(); 9232} 9233 9234/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 9235/// are the two values being selected between, see if we can simplify the 9236/// select. Callers of this should assume that TheSelect is deleted if this 9237/// returns true. As such, they should return the appropriate thing (e.g. the 9238/// node) back to the top-level of the DAG combiner loop to avoid it being 9239/// looked at. 9240bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 9241 SDValue RHS) { 9242 9243 // Cannot simplify select with vector condition 9244 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 9245 9246 // If this is a select from two identical things, try to pull the operation 9247 // through the select. 9248 if (LHS.getOpcode() != RHS.getOpcode() || 9249 !LHS.hasOneUse() || !RHS.hasOneUse()) 9250 return false; 9251 9252 // If this is a load and the token chain is identical, replace the select 9253 // of two loads with a load through a select of the address to load from. 9254 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 9255 // constants have been dropped into the constant pool. 9256 if (LHS.getOpcode() == ISD::LOAD) { 9257 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 9258 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 9259 9260 // Token chains must be identical. 9261 if (LHS.getOperand(0) != RHS.getOperand(0) || 9262 // Do not let this transformation reduce the number of volatile loads. 9263 LLD->isVolatile() || RLD->isVolatile() || 9264 // If this is an EXTLOAD, the VT's must match. 9265 LLD->getMemoryVT() != RLD->getMemoryVT() || 9266 // If this is an EXTLOAD, the kind of extension must match. 9267 (LLD->getExtensionType() != RLD->getExtensionType() && 9268 // The only exception is if one of the extensions is anyext. 9269 LLD->getExtensionType() != ISD::EXTLOAD && 9270 RLD->getExtensionType() != ISD::EXTLOAD) || 9271 // FIXME: this discards src value information. This is 9272 // over-conservative. It would be beneficial to be able to remember 9273 // both potential memory locations. Since we are discarding 9274 // src value info, don't do the transformation if the memory 9275 // locations are not in the default address space. 9276 LLD->getPointerInfo().getAddrSpace() != 0 || 9277 RLD->getPointerInfo().getAddrSpace() != 0) 9278 return false; 9279 9280 // Check that the select condition doesn't reach either load. If so, 9281 // folding this will induce a cycle into the DAG. If not, this is safe to 9282 // xform, so create a select of the addresses. 9283 SDValue Addr; 9284 if (TheSelect->getOpcode() == ISD::SELECT) { 9285 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 9286 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 9287 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 9288 return false; 9289 // The loads must not depend on one another. 9290 if (LLD->isPredecessorOf(RLD) || 9291 RLD->isPredecessorOf(LLD)) 9292 return false; 9293 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 9294 LLD->getBasePtr().getValueType(), 9295 TheSelect->getOperand(0), LLD->getBasePtr(), 9296 RLD->getBasePtr()); 9297 } else { // Otherwise SELECT_CC 9298 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 9299 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 9300 9301 if ((LLD->hasAnyUseOfValue(1) && 9302 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 9303 (RLD->hasAnyUseOfValue(1) && 9304 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 9305 return false; 9306 9307 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 9308 LLD->getBasePtr().getValueType(), 9309 TheSelect->getOperand(0), 9310 TheSelect->getOperand(1), 9311 LLD->getBasePtr(), RLD->getBasePtr(), 9312 TheSelect->getOperand(4)); 9313 } 9314 9315 SDValue Load; 9316 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 9317 Load = DAG.getLoad(TheSelect->getValueType(0), 9318 TheSelect->getDebugLoc(), 9319 // FIXME: Discards pointer info. 9320 LLD->getChain(), Addr, MachinePointerInfo(), 9321 LLD->isVolatile(), LLD->isNonTemporal(), 9322 LLD->isInvariant(), LLD->getAlignment()); 9323 } else { 9324 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 9325 RLD->getExtensionType() : LLD->getExtensionType(), 9326 TheSelect->getDebugLoc(), 9327 TheSelect->getValueType(0), 9328 // FIXME: Discards pointer info. 9329 LLD->getChain(), Addr, MachinePointerInfo(), 9330 LLD->getMemoryVT(), LLD->isVolatile(), 9331 LLD->isNonTemporal(), LLD->getAlignment()); 9332 } 9333 9334 // Users of the select now use the result of the load. 9335 CombineTo(TheSelect, Load); 9336 9337 // Users of the old loads now use the new load's chain. We know the 9338 // old-load value is dead now. 9339 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 9340 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 9341 return true; 9342 } 9343 9344 return false; 9345} 9346 9347/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 9348/// where 'cond' is the comparison specified by CC. 9349SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 9350 SDValue N2, SDValue N3, 9351 ISD::CondCode CC, bool NotExtCompare) { 9352 // (x ? y : y) -> y. 9353 if (N2 == N3) return N2; 9354 9355 EVT VT = N2.getValueType(); 9356 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 9357 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 9358 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 9359 9360 // Determine if the condition we're dealing with is constant 9361 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 9362 N0, N1, CC, DL, false); 9363 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 9364 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 9365 9366 // fold select_cc true, x, y -> x 9367 if (SCCC && !SCCC->isNullValue()) 9368 return N2; 9369 // fold select_cc false, x, y -> y 9370 if (SCCC && SCCC->isNullValue()) 9371 return N3; 9372 9373 // Check to see if we can simplify the select into an fabs node 9374 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 9375 // Allow either -0.0 or 0.0 9376 if (CFP->getValueAPF().isZero()) { 9377 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 9378 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 9379 N0 == N2 && N3.getOpcode() == ISD::FNEG && 9380 N2 == N3.getOperand(0)) 9381 return DAG.getNode(ISD::FABS, DL, VT, N0); 9382 9383 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 9384 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 9385 N0 == N3 && N2.getOpcode() == ISD::FNEG && 9386 N2.getOperand(0) == N3) 9387 return DAG.getNode(ISD::FABS, DL, VT, N3); 9388 } 9389 } 9390 9391 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 9392 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 9393 // in it. This is a win when the constant is not otherwise available because 9394 // it replaces two constant pool loads with one. We only do this if the FP 9395 // type is known to be legal, because if it isn't, then we are before legalize 9396 // types an we want the other legalization to happen first (e.g. to avoid 9397 // messing with soft float) and if the ConstantFP is not legal, because if 9398 // it is legal, we may not need to store the FP constant in a constant pool. 9399 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 9400 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 9401 if (TLI.isTypeLegal(N2.getValueType()) && 9402 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 9403 TargetLowering::Legal) && 9404 // If both constants have multiple uses, then we won't need to do an 9405 // extra load, they are likely around in registers for other users. 9406 (TV->hasOneUse() || FV->hasOneUse())) { 9407 Constant *Elts[] = { 9408 const_cast<ConstantFP*>(FV->getConstantFPValue()), 9409 const_cast<ConstantFP*>(TV->getConstantFPValue()) 9410 }; 9411 Type *FPTy = Elts[0]->getType(); 9412 const DataLayout &TD = *TLI.getDataLayout(); 9413 9414 // Create a ConstantArray of the two constants. 9415 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 9416 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 9417 TD.getPrefTypeAlignment(FPTy)); 9418 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 9419 9420 // Get the offsets to the 0 and 1 element of the array so that we can 9421 // select between them. 9422 SDValue Zero = DAG.getIntPtrConstant(0); 9423 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 9424 SDValue One = DAG.getIntPtrConstant(EltSize); 9425 9426 SDValue Cond = DAG.getSetCC(DL, 9427 TLI.getSetCCResultType(N0.getValueType()), 9428 N0, N1, CC); 9429 AddToWorkList(Cond.getNode()); 9430 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 9431 Cond, One, Zero); 9432 AddToWorkList(CstOffset.getNode()); 9433 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 9434 CstOffset); 9435 AddToWorkList(CPIdx.getNode()); 9436 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 9437 MachinePointerInfo::getConstantPool(), false, 9438 false, false, Alignment); 9439 9440 } 9441 } 9442 9443 // Check to see if we can perform the "gzip trick", transforming 9444 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 9445 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 9446 (N1C->isNullValue() || // (a < 0) ? b : 0 9447 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 9448 EVT XType = N0.getValueType(); 9449 EVT AType = N2.getValueType(); 9450 if (XType.bitsGE(AType)) { 9451 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 9452 // single-bit constant. 9453 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 9454 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 9455 ShCtV = XType.getSizeInBits()-ShCtV-1; 9456 SDValue ShCt = DAG.getConstant(ShCtV, 9457 getShiftAmountTy(N0.getValueType())); 9458 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 9459 XType, N0, ShCt); 9460 AddToWorkList(Shift.getNode()); 9461 9462 if (XType.bitsGT(AType)) { 9463 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9464 AddToWorkList(Shift.getNode()); 9465 } 9466 9467 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9468 } 9469 9470 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 9471 XType, N0, 9472 DAG.getConstant(XType.getSizeInBits()-1, 9473 getShiftAmountTy(N0.getValueType()))); 9474 AddToWorkList(Shift.getNode()); 9475 9476 if (XType.bitsGT(AType)) { 9477 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9478 AddToWorkList(Shift.getNode()); 9479 } 9480 9481 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9482 } 9483 } 9484 9485 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 9486 // where y is has a single bit set. 9487 // A plaintext description would be, we can turn the SELECT_CC into an AND 9488 // when the condition can be materialized as an all-ones register. Any 9489 // single bit-test can be materialized as an all-ones register with 9490 // shift-left and shift-right-arith. 9491 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 9492 N0->getValueType(0) == VT && 9493 N1C && N1C->isNullValue() && 9494 N2C && N2C->isNullValue()) { 9495 SDValue AndLHS = N0->getOperand(0); 9496 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 9497 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 9498 // Shift the tested bit over the sign bit. 9499 APInt AndMask = ConstAndRHS->getAPIntValue(); 9500 SDValue ShlAmt = 9501 DAG.getConstant(AndMask.countLeadingZeros(), 9502 getShiftAmountTy(AndLHS.getValueType())); 9503 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 9504 9505 // Now arithmetic right shift it all the way over, so the result is either 9506 // all-ones, or zero. 9507 SDValue ShrAmt = 9508 DAG.getConstant(AndMask.getBitWidth()-1, 9509 getShiftAmountTy(Shl.getValueType())); 9510 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 9511 9512 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 9513 } 9514 } 9515 9516 // fold select C, 16, 0 -> shl C, 4 9517 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 9518 TLI.getBooleanContents(N0.getValueType().isVector()) == 9519 TargetLowering::ZeroOrOneBooleanContent) { 9520 9521 // If the caller doesn't want us to simplify this into a zext of a compare, 9522 // don't do it. 9523 if (NotExtCompare && N2C->getAPIntValue() == 1) 9524 return SDValue(); 9525 9526 // Get a SetCC of the condition 9527 // NOTE: Don't create a SETCC if it's not legal on this target. 9528 if (!LegalOperations || 9529 TLI.isOperationLegal(ISD::SETCC, 9530 LegalTypes ? TLI.getSetCCResultType(N0.getValueType()) : MVT::i1)) { 9531 SDValue Temp, SCC; 9532 // cast from setcc result type to select result type 9533 if (LegalTypes) { 9534 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 9535 N0, N1, CC); 9536 if (N2.getValueType().bitsLT(SCC.getValueType())) 9537 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), 9538 N2.getValueType()); 9539 else 9540 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9541 N2.getValueType(), SCC); 9542 } else { 9543 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 9544 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9545 N2.getValueType(), SCC); 9546 } 9547 9548 AddToWorkList(SCC.getNode()); 9549 AddToWorkList(Temp.getNode()); 9550 9551 if (N2C->getAPIntValue() == 1) 9552 return Temp; 9553 9554 // shl setcc result by log2 n2c 9555 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 9556 DAG.getConstant(N2C->getAPIntValue().logBase2(), 9557 getShiftAmountTy(Temp.getValueType()))); 9558 } 9559 } 9560 9561 // Check to see if this is the equivalent of setcc 9562 // FIXME: Turn all of these into setcc if setcc if setcc is legal 9563 // otherwise, go ahead with the folds. 9564 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 9565 EVT XType = N0.getValueType(); 9566 if (!LegalOperations || 9567 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 9568 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 9569 if (Res.getValueType() != VT) 9570 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 9571 return Res; 9572 } 9573 9574 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 9575 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 9576 (!LegalOperations || 9577 TLI.isOperationLegal(ISD::CTLZ, XType))) { 9578 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 9579 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 9580 DAG.getConstant(Log2_32(XType.getSizeInBits()), 9581 getShiftAmountTy(Ctlz.getValueType()))); 9582 } 9583 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 9584 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 9585 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 9586 XType, DAG.getConstant(0, XType), N0); 9587 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 9588 return DAG.getNode(ISD::SRL, DL, XType, 9589 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 9590 DAG.getConstant(XType.getSizeInBits()-1, 9591 getShiftAmountTy(XType))); 9592 } 9593 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 9594 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 9595 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 9596 DAG.getConstant(XType.getSizeInBits()-1, 9597 getShiftAmountTy(N0.getValueType()))); 9598 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 9599 } 9600 } 9601 9602 // Check to see if this is an integer abs. 9603 // select_cc setg[te] X, 0, X, -X -> 9604 // select_cc setgt X, -1, X, -X -> 9605 // select_cc setl[te] X, 0, -X, X -> 9606 // select_cc setlt X, 1, -X, X -> 9607 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 9608 if (N1C) { 9609 ConstantSDNode *SubC = NULL; 9610 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 9611 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 9612 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 9613 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 9614 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 9615 (N1C->isOne() && CC == ISD::SETLT)) && 9616 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 9617 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 9618 9619 EVT XType = N0.getValueType(); 9620 if (SubC && SubC->isNullValue() && XType.isInteger()) { 9621 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 9622 N0, 9623 DAG.getConstant(XType.getSizeInBits()-1, 9624 getShiftAmountTy(N0.getValueType()))); 9625 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 9626 XType, N0, Shift); 9627 AddToWorkList(Shift.getNode()); 9628 AddToWorkList(Add.getNode()); 9629 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 9630 } 9631 } 9632 9633 return SDValue(); 9634} 9635 9636/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 9637SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 9638 SDValue N1, ISD::CondCode Cond, 9639 DebugLoc DL, bool foldBooleans) { 9640 TargetLowering::DAGCombinerInfo 9641 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 9642 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 9643} 9644 9645/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 9646/// return a DAG expression to select that will generate the same value by 9647/// multiplying by a magic number. See: 9648/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9649SDValue DAGCombiner::BuildSDIV(SDNode *N) { 9650 std::vector<SDNode*> Built; 9651 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 9652 9653 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9654 ii != ee; ++ii) 9655 AddToWorkList(*ii); 9656 return S; 9657} 9658 9659/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 9660/// return a DAG expression to select that will generate the same value by 9661/// multiplying by a magic number. See: 9662/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9663SDValue DAGCombiner::BuildUDIV(SDNode *N) { 9664 std::vector<SDNode*> Built; 9665 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 9666 9667 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9668 ii != ee; ++ii) 9669 AddToWorkList(*ii); 9670 return S; 9671} 9672 9673/// FindBaseOffset - Return true if base is a frame index, which is known not 9674// to alias with anything but itself. Provides base object and offset as 9675// results. 9676static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 9677 const GlobalValue *&GV, const void *&CV) { 9678 // Assume it is a primitive operation. 9679 Base = Ptr; Offset = 0; GV = 0; CV = 0; 9680 9681 // If it's an adding a simple constant then integrate the offset. 9682 if (Base.getOpcode() == ISD::ADD) { 9683 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 9684 Base = Base.getOperand(0); 9685 Offset += C->getZExtValue(); 9686 } 9687 } 9688 9689 // Return the underlying GlobalValue, and update the Offset. Return false 9690 // for GlobalAddressSDNode since the same GlobalAddress may be represented 9691 // by multiple nodes with different offsets. 9692 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 9693 GV = G->getGlobal(); 9694 Offset += G->getOffset(); 9695 return false; 9696 } 9697 9698 // Return the underlying Constant value, and update the Offset. Return false 9699 // for ConstantSDNodes since the same constant pool entry may be represented 9700 // by multiple nodes with different offsets. 9701 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 9702 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 9703 : (const void *)C->getConstVal(); 9704 Offset += C->getOffset(); 9705 return false; 9706 } 9707 // If it's any of the following then it can't alias with anything but itself. 9708 return isa<FrameIndexSDNode>(Base); 9709} 9710 9711/// isAlias - Return true if there is any possibility that the two addresses 9712/// overlap. 9713bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 9714 const Value *SrcValue1, int SrcValueOffset1, 9715 unsigned SrcValueAlign1, 9716 const MDNode *TBAAInfo1, 9717 SDValue Ptr2, int64_t Size2, 9718 const Value *SrcValue2, int SrcValueOffset2, 9719 unsigned SrcValueAlign2, 9720 const MDNode *TBAAInfo2) const { 9721 // If they are the same then they must be aliases. 9722 if (Ptr1 == Ptr2) return true; 9723 9724 // Gather base node and offset information. 9725 SDValue Base1, Base2; 9726 int64_t Offset1, Offset2; 9727 const GlobalValue *GV1, *GV2; 9728 const void *CV1, *CV2; 9729 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 9730 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 9731 9732 // If they have a same base address then check to see if they overlap. 9733 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 9734 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9735 9736 // It is possible for different frame indices to alias each other, mostly 9737 // when tail call optimization reuses return address slots for arguments. 9738 // To catch this case, look up the actual index of frame indices to compute 9739 // the real alias relationship. 9740 if (isFrameIndex1 && isFrameIndex2) { 9741 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9742 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 9743 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 9744 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9745 } 9746 9747 // Otherwise, if we know what the bases are, and they aren't identical, then 9748 // we know they cannot alias. 9749 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 9750 return false; 9751 9752 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 9753 // compared to the size and offset of the access, we may be able to prove they 9754 // do not alias. This check is conservative for now to catch cases created by 9755 // splitting vector types. 9756 if ((SrcValueAlign1 == SrcValueAlign2) && 9757 (SrcValueOffset1 != SrcValueOffset2) && 9758 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 9759 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 9760 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 9761 9762 // There is no overlap between these relatively aligned accesses of similar 9763 // size, return no alias. 9764 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 9765 return false; 9766 } 9767 9768 if (CombinerGlobalAA) { 9769 // Use alias analysis information. 9770 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 9771 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 9772 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 9773 AliasAnalysis::AliasResult AAResult = 9774 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 9775 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 9776 if (AAResult == AliasAnalysis::NoAlias) 9777 return false; 9778 } 9779 9780 // Otherwise we have to assume they alias. 9781 return true; 9782} 9783 9784bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) { 9785 SDValue Ptr0, Ptr1; 9786 int64_t Size0, Size1; 9787 const Value *SrcValue0, *SrcValue1; 9788 int SrcValueOffset0, SrcValueOffset1; 9789 unsigned SrcValueAlign0, SrcValueAlign1; 9790 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1; 9791 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0, 9792 SrcValueAlign0, SrcTBAAInfo0); 9793 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1, 9794 SrcValueAlign1, SrcTBAAInfo1); 9795 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0, 9796 SrcValueAlign0, SrcTBAAInfo0, 9797 Ptr1, Size1, SrcValue1, SrcValueOffset1, 9798 SrcValueAlign1, SrcTBAAInfo1); 9799} 9800 9801/// FindAliasInfo - Extracts the relevant alias information from the memory 9802/// node. Returns true if the operand was a load. 9803bool DAGCombiner::FindAliasInfo(SDNode *N, 9804 SDValue &Ptr, int64_t &Size, 9805 const Value *&SrcValue, 9806 int &SrcValueOffset, 9807 unsigned &SrcValueAlign, 9808 const MDNode *&TBAAInfo) const { 9809 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 9810 9811 Ptr = LS->getBasePtr(); 9812 Size = LS->getMemoryVT().getSizeInBits() >> 3; 9813 SrcValue = LS->getSrcValue(); 9814 SrcValueOffset = LS->getSrcValueOffset(); 9815 SrcValueAlign = LS->getOriginalAlignment(); 9816 TBAAInfo = LS->getTBAAInfo(); 9817 return isa<LoadSDNode>(LS); 9818} 9819 9820/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 9821/// looking for aliasing nodes and adding them to the Aliases vector. 9822void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 9823 SmallVector<SDValue, 8> &Aliases) { 9824 SmallVector<SDValue, 8> Chains; // List of chains to visit. 9825 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 9826 9827 // Get alias information for node. 9828 SDValue Ptr; 9829 int64_t Size; 9830 const Value *SrcValue; 9831 int SrcValueOffset; 9832 unsigned SrcValueAlign; 9833 const MDNode *SrcTBAAInfo; 9834 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 9835 SrcValueAlign, SrcTBAAInfo); 9836 9837 // Starting off. 9838 Chains.push_back(OriginalChain); 9839 unsigned Depth = 0; 9840 9841 // Look at each chain and determine if it is an alias. If so, add it to the 9842 // aliases list. If not, then continue up the chain looking for the next 9843 // candidate. 9844 while (!Chains.empty()) { 9845 SDValue Chain = Chains.back(); 9846 Chains.pop_back(); 9847 9848 // For TokenFactor nodes, look at each operand and only continue up the 9849 // chain until we find two aliases. If we've seen two aliases, assume we'll 9850 // find more and revert to original chain since the xform is unlikely to be 9851 // profitable. 9852 // 9853 // FIXME: The depth check could be made to return the last non-aliasing 9854 // chain we found before we hit a tokenfactor rather than the original 9855 // chain. 9856 if (Depth > 6 || Aliases.size() == 2) { 9857 Aliases.clear(); 9858 Aliases.push_back(OriginalChain); 9859 break; 9860 } 9861 9862 // Don't bother if we've been before. 9863 if (!Visited.insert(Chain.getNode())) 9864 continue; 9865 9866 switch (Chain.getOpcode()) { 9867 case ISD::EntryToken: 9868 // Entry token is ideal chain operand, but handled in FindBetterChain. 9869 break; 9870 9871 case ISD::LOAD: 9872 case ISD::STORE: { 9873 // Get alias information for Chain. 9874 SDValue OpPtr; 9875 int64_t OpSize; 9876 const Value *OpSrcValue; 9877 int OpSrcValueOffset; 9878 unsigned OpSrcValueAlign; 9879 const MDNode *OpSrcTBAAInfo; 9880 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 9881 OpSrcValue, OpSrcValueOffset, 9882 OpSrcValueAlign, 9883 OpSrcTBAAInfo); 9884 9885 // If chain is alias then stop here. 9886 if (!(IsLoad && IsOpLoad) && 9887 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 9888 SrcTBAAInfo, 9889 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 9890 OpSrcValueAlign, OpSrcTBAAInfo)) { 9891 Aliases.push_back(Chain); 9892 } else { 9893 // Look further up the chain. 9894 Chains.push_back(Chain.getOperand(0)); 9895 ++Depth; 9896 } 9897 break; 9898 } 9899 9900 case ISD::TokenFactor: 9901 // We have to check each of the operands of the token factor for "small" 9902 // token factors, so we queue them up. Adding the operands to the queue 9903 // (stack) in reverse order maintains the original order and increases the 9904 // likelihood that getNode will find a matching token factor (CSE.) 9905 if (Chain.getNumOperands() > 16) { 9906 Aliases.push_back(Chain); 9907 break; 9908 } 9909 for (unsigned n = Chain.getNumOperands(); n;) 9910 Chains.push_back(Chain.getOperand(--n)); 9911 ++Depth; 9912 break; 9913 9914 default: 9915 // For all other instructions we will just have to take what we can get. 9916 Aliases.push_back(Chain); 9917 break; 9918 } 9919 } 9920} 9921 9922/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 9923/// for a better chain (aliasing node.) 9924SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 9925 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 9926 9927 // Accumulate all the aliases to this node. 9928 GatherAllAliases(N, OldChain, Aliases); 9929 9930 // If no operands then chain to entry token. 9931 if (Aliases.size() == 0) 9932 return DAG.getEntryNode(); 9933 9934 // If a single operand then chain to it. We don't need to revisit it. 9935 if (Aliases.size() == 1) 9936 return Aliases[0]; 9937 9938 // Construct a custom tailored token factor. 9939 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 9940 &Aliases[0], Aliases.size()); 9941} 9942 9943// SelectionDAG::Combine - This is the entry point for the file. 9944// 9945void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 9946 CodeGenOpt::Level OptLevel) { 9947 /// run - This is the main entry point to this class. 9948 /// 9949 DAGCombiner(*this, AA, OptLevel).Run(Level); 9950} 9951