DAGCombiner.cpp revision 2392ae7d7344674dc3d946e324342515f4771b90
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 unsigned SrcValueAlign1, 242 SDValue Ptr2, int64_t Size2, 243 const Value *SrcValue2, int SrcValueOffset2, 244 unsigned SrcValueAlign2) const; 245 246 /// FindAliasInfo - Extracts the relevant alias information from the memory 247 /// node. Returns true if the operand was a load. 248 bool FindAliasInfo(SDNode *N, 249 SDValue &Ptr, int64_t &Size, 250 const Value *&SrcValue, int &SrcValueOffset, 251 unsigned &SrcValueAlignment) const; 252 253 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 254 /// looking for a better chain (aliasing node.) 255 SDValue FindBetterChain(SDNode *N, SDValue Chain); 256 257 public: 258 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 259 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 260 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 261 262 /// Run - runs the dag combiner on all nodes in the work list 263 void Run(CombineLevel AtLevel); 264 265 SelectionDAG &getDAG() const { return DAG; } 266 267 /// getShiftAmountTy - Returns a type large enough to hold any valid 268 /// shift amount - before type legalization these can be huge. 269 EVT getShiftAmountTy() { 270 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 271 } 272 273 /// isTypeLegal - This method returns true if we are running before type 274 /// legalization or if the specified VT is legal. 275 bool isTypeLegal(const EVT &VT) { 276 if (!LegalTypes) return true; 277 return TLI.isTypeLegal(VT); 278 } 279 }; 280} 281 282 283namespace { 284/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 285/// nodes from the worklist. 286class WorkListRemover : public SelectionDAG::DAGUpdateListener { 287 DAGCombiner &DC; 288public: 289 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 290 291 virtual void NodeDeleted(SDNode *N, SDNode *E) { 292 DC.removeFromWorkList(N); 293 } 294 295 virtual void NodeUpdated(SDNode *N) { 296 // Ignore updates. 297 } 298}; 299} 300 301//===----------------------------------------------------------------------===// 302// TargetLowering::DAGCombinerInfo implementation 303//===----------------------------------------------------------------------===// 304 305void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 306 ((DAGCombiner*)DC)->AddToWorkList(N); 307} 308 309SDValue TargetLowering::DAGCombinerInfo:: 310CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 311 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 312} 313 314SDValue TargetLowering::DAGCombinerInfo:: 315CombineTo(SDNode *N, SDValue Res, bool AddTo) { 316 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 317} 318 319 320SDValue TargetLowering::DAGCombinerInfo:: 321CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 322 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 323} 324 325void TargetLowering::DAGCombinerInfo:: 326CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 327 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 328} 329 330//===----------------------------------------------------------------------===// 331// Helper Functions 332//===----------------------------------------------------------------------===// 333 334/// isNegatibleForFree - Return 1 if we can compute the negated form of the 335/// specified expression for the same cost as the expression itself, or 2 if we 336/// can compute the negated form more cheaply than the expression itself. 337static char isNegatibleForFree(SDValue Op, bool LegalOperations, 338 unsigned Depth = 0) { 339 // No compile time optimizations on this type. 340 if (Op.getValueType() == MVT::ppcf128) 341 return 0; 342 343 // fneg is removable even if it has multiple uses. 344 if (Op.getOpcode() == ISD::FNEG) return 2; 345 346 // Don't allow anything with multiple uses. 347 if (!Op.hasOneUse()) return 0; 348 349 // Don't recurse exponentially. 350 if (Depth > 6) return 0; 351 352 switch (Op.getOpcode()) { 353 default: return false; 354 case ISD::ConstantFP: 355 // Don't invert constant FP values after legalize. The negated constant 356 // isn't necessarily legal. 357 return LegalOperations ? 0 : 1; 358 case ISD::FADD: 359 // FIXME: determine better conditions for this xform. 360 if (!UnsafeFPMath) return 0; 361 362 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 363 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 364 return V; 365 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 366 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 367 case ISD::FSUB: 368 // We can't turn -(A-B) into B-A when we honor signed zeros. 369 if (!UnsafeFPMath) return 0; 370 371 // fold (fneg (fsub A, B)) -> (fsub B, A) 372 return 1; 373 374 case ISD::FMUL: 375 case ISD::FDIV: 376 if (HonorSignDependentRoundingFPMath()) return 0; 377 378 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 379 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 380 return V; 381 382 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 383 384 case ISD::FP_EXTEND: 385 case ISD::FP_ROUND: 386 case ISD::FSIN: 387 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 388 } 389} 390 391/// GetNegatedExpression - If isNegatibleForFree returns true, this function 392/// returns the newly negated expression. 393static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 394 bool LegalOperations, unsigned Depth = 0) { 395 // fneg is removable even if it has multiple uses. 396 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 397 398 // Don't allow anything with multiple uses. 399 assert(Op.hasOneUse() && "Unknown reuse!"); 400 401 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 402 switch (Op.getOpcode()) { 403 default: llvm_unreachable("Unknown code"); 404 case ISD::ConstantFP: { 405 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 406 V.changeSign(); 407 return DAG.getConstantFP(V, Op.getValueType()); 408 } 409 case ISD::FADD: 410 // FIXME: determine better conditions for this xform. 411 assert(UnsafeFPMath); 412 413 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 414 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 415 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 416 GetNegatedExpression(Op.getOperand(0), DAG, 417 LegalOperations, Depth+1), 418 Op.getOperand(1)); 419 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 420 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 421 GetNegatedExpression(Op.getOperand(1), DAG, 422 LegalOperations, Depth+1), 423 Op.getOperand(0)); 424 case ISD::FSUB: 425 // We can't turn -(A-B) into B-A when we honor signed zeros. 426 assert(UnsafeFPMath); 427 428 // fold (fneg (fsub 0, B)) -> B 429 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 430 if (N0CFP->getValueAPF().isZero()) 431 return Op.getOperand(1); 432 433 // fold (fneg (fsub A, B)) -> (fsub B, A) 434 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 435 Op.getOperand(1), Op.getOperand(0)); 436 437 case ISD::FMUL: 438 case ISD::FDIV: 439 assert(!HonorSignDependentRoundingFPMath()); 440 441 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 442 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 443 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 444 GetNegatedExpression(Op.getOperand(0), DAG, 445 LegalOperations, Depth+1), 446 Op.getOperand(1)); 447 448 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 449 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 450 Op.getOperand(0), 451 GetNegatedExpression(Op.getOperand(1), DAG, 452 LegalOperations, Depth+1)); 453 454 case ISD::FP_EXTEND: 455 case ISD::FSIN: 456 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 457 GetNegatedExpression(Op.getOperand(0), DAG, 458 LegalOperations, Depth+1)); 459 case ISD::FP_ROUND: 460 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 461 GetNegatedExpression(Op.getOperand(0), DAG, 462 LegalOperations, Depth+1), 463 Op.getOperand(1)); 464 } 465} 466 467 468// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 469// that selects between the values 1 and 0, making it equivalent to a setcc. 470// Also, set the incoming LHS, RHS, and CC references to the appropriate 471// nodes based on the type of node we are checking. This simplifies life a 472// bit for the callers. 473static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 474 SDValue &CC) { 475 if (N.getOpcode() == ISD::SETCC) { 476 LHS = N.getOperand(0); 477 RHS = N.getOperand(1); 478 CC = N.getOperand(2); 479 return true; 480 } 481 if (N.getOpcode() == ISD::SELECT_CC && 482 N.getOperand(2).getOpcode() == ISD::Constant && 483 N.getOperand(3).getOpcode() == ISD::Constant && 484 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 485 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 486 LHS = N.getOperand(0); 487 RHS = N.getOperand(1); 488 CC = N.getOperand(4); 489 return true; 490 } 491 return false; 492} 493 494// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 495// one use. If this is true, it allows the users to invert the operation for 496// free when it is profitable to do so. 497static bool isOneUseSetCC(SDValue N) { 498 SDValue N0, N1, N2; 499 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 500 return true; 501 return false; 502} 503 504SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 505 SDValue N0, SDValue N1) { 506 EVT VT = N0.getValueType(); 507 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 508 if (isa<ConstantSDNode>(N1)) { 509 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 510 SDValue OpNode = 511 DAG.FoldConstantArithmetic(Opc, VT, 512 cast<ConstantSDNode>(N0.getOperand(1)), 513 cast<ConstantSDNode>(N1)); 514 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 515 } else if (N0.hasOneUse()) { 516 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 517 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 518 N0.getOperand(0), N1); 519 AddToWorkList(OpNode.getNode()); 520 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 521 } 522 } 523 524 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 525 if (isa<ConstantSDNode>(N0)) { 526 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 527 SDValue OpNode = 528 DAG.FoldConstantArithmetic(Opc, VT, 529 cast<ConstantSDNode>(N1.getOperand(1)), 530 cast<ConstantSDNode>(N0)); 531 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 532 } else if (N1.hasOneUse()) { 533 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 534 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 535 N1.getOperand(0), N0); 536 AddToWorkList(OpNode.getNode()); 537 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 538 } 539 } 540 541 return SDValue(); 542} 543 544SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 545 bool AddTo) { 546 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 547 ++NodesCombined; 548 DEBUG(dbgs() << "\nReplacing.1 "; 549 N->dump(&DAG); 550 dbgs() << "\nWith: "; 551 To[0].getNode()->dump(&DAG); 552 dbgs() << " and " << NumTo-1 << " other values\n"; 553 for (unsigned i = 0, e = NumTo; i != e; ++i) 554 assert((!To[i].getNode() || 555 N->getValueType(i) == To[i].getValueType()) && 556 "Cannot combine value to value of different type!")); 557 WorkListRemover DeadNodes(*this); 558 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 559 560 if (AddTo) { 561 // Push the new nodes and any users onto the worklist 562 for (unsigned i = 0, e = NumTo; i != e; ++i) { 563 if (To[i].getNode()) { 564 AddToWorkList(To[i].getNode()); 565 AddUsersToWorkList(To[i].getNode()); 566 } 567 } 568 } 569 570 // Finally, if the node is now dead, remove it from the graph. The node 571 // may not be dead if the replacement process recursively simplified to 572 // something else needing this node. 573 if (N->use_empty()) { 574 // Nodes can be reintroduced into the worklist. Make sure we do not 575 // process a node that has been replaced. 576 removeFromWorkList(N); 577 578 // Finally, since the node is now dead, remove it from the graph. 579 DAG.DeleteNode(N); 580 } 581 return SDValue(N, 0); 582} 583 584void 585DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 586 TLO) { 587 // Replace all uses. If any nodes become isomorphic to other nodes and 588 // are deleted, make sure to remove them from our worklist. 589 WorkListRemover DeadNodes(*this); 590 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 591 592 // Push the new node and any (possibly new) users onto the worklist. 593 AddToWorkList(TLO.New.getNode()); 594 AddUsersToWorkList(TLO.New.getNode()); 595 596 // Finally, if the node is now dead, remove it from the graph. The node 597 // may not be dead if the replacement process recursively simplified to 598 // something else needing this node. 599 if (TLO.Old.getNode()->use_empty()) { 600 removeFromWorkList(TLO.Old.getNode()); 601 602 // If the operands of this node are only used by the node, they will now 603 // be dead. Make sure to visit them first to delete dead nodes early. 604 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 605 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 606 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 607 608 DAG.DeleteNode(TLO.Old.getNode()); 609 } 610} 611 612/// SimplifyDemandedBits - Check the specified integer node value to see if 613/// it can be simplified or if things it uses can be simplified by bit 614/// propagation. If so, return true. 615bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 616 TargetLowering::TargetLoweringOpt TLO(DAG); 617 APInt KnownZero, KnownOne; 618 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 619 return false; 620 621 // Revisit the node. 622 AddToWorkList(Op.getNode()); 623 624 // Replace the old value with the new one. 625 ++NodesCombined; 626 DEBUG(dbgs() << "\nReplacing.2 "; 627 TLO.Old.getNode()->dump(&DAG); 628 dbgs() << "\nWith: "; 629 TLO.New.getNode()->dump(&DAG); 630 dbgs() << '\n'); 631 632 CommitTargetLoweringOpt(TLO); 633 return true; 634} 635 636//===----------------------------------------------------------------------===// 637// Main DAG Combiner implementation 638//===----------------------------------------------------------------------===// 639 640void DAGCombiner::Run(CombineLevel AtLevel) { 641 // set the instance variables, so that the various visit routines may use it. 642 Level = AtLevel; 643 LegalOperations = Level >= NoIllegalOperations; 644 LegalTypes = Level >= NoIllegalTypes; 645 646 // Add all the dag nodes to the worklist. 647 WorkList.reserve(DAG.allnodes_size()); 648 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 649 E = DAG.allnodes_end(); I != E; ++I) 650 WorkList.push_back(I); 651 652 // Create a dummy node (which is not added to allnodes), that adds a reference 653 // to the root node, preventing it from being deleted, and tracking any 654 // changes of the root. 655 HandleSDNode Dummy(DAG.getRoot()); 656 657 // The root of the dag may dangle to deleted nodes until the dag combiner is 658 // done. Set it to null to avoid confusion. 659 DAG.setRoot(SDValue()); 660 661 // while the worklist isn't empty, inspect the node on the end of it and 662 // try and combine it. 663 while (!WorkList.empty()) { 664 SDNode *N = WorkList.back(); 665 WorkList.pop_back(); 666 667 // If N has no uses, it is dead. Make sure to revisit all N's operands once 668 // N is deleted from the DAG, since they too may now be dead or may have a 669 // reduced number of uses, allowing other xforms. 670 if (N->use_empty() && N != &Dummy) { 671 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 672 AddToWorkList(N->getOperand(i).getNode()); 673 674 DAG.DeleteNode(N); 675 continue; 676 } 677 678 SDValue RV = combine(N); 679 680 if (RV.getNode() == 0) 681 continue; 682 683 ++NodesCombined; 684 685 // If we get back the same node we passed in, rather than a new node or 686 // zero, we know that the node must have defined multiple values and 687 // CombineTo was used. Since CombineTo takes care of the worklist 688 // mechanics for us, we have no work to do in this case. 689 if (RV.getNode() == N) 690 continue; 691 692 assert(N->getOpcode() != ISD::DELETED_NODE && 693 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 694 "Node was deleted but visit returned new node!"); 695 696 DEBUG(dbgs() << "\nReplacing.3 "; 697 N->dump(&DAG); 698 dbgs() << "\nWith: "; 699 RV.getNode()->dump(&DAG); 700 dbgs() << '\n'); 701 WorkListRemover DeadNodes(*this); 702 if (N->getNumValues() == RV.getNode()->getNumValues()) 703 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 704 else { 705 assert(N->getValueType(0) == RV.getValueType() && 706 N->getNumValues() == 1 && "Type mismatch"); 707 SDValue OpV = RV; 708 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 709 } 710 711 // Push the new node and any users onto the worklist 712 AddToWorkList(RV.getNode()); 713 AddUsersToWorkList(RV.getNode()); 714 715 // Add any uses of the old node to the worklist in case this node is the 716 // last one that uses them. They may become dead after this node is 717 // deleted. 718 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 719 AddToWorkList(N->getOperand(i).getNode()); 720 721 // Finally, if the node is now dead, remove it from the graph. The node 722 // may not be dead if the replacement process recursively simplified to 723 // something else needing this node. 724 if (N->use_empty()) { 725 // Nodes can be reintroduced into the worklist. Make sure we do not 726 // process a node that has been replaced. 727 removeFromWorkList(N); 728 729 // Finally, since the node is now dead, remove it from the graph. 730 DAG.DeleteNode(N); 731 } 732 } 733 734 // If the root changed (e.g. it was a dead load, update the root). 735 DAG.setRoot(Dummy.getValue()); 736} 737 738SDValue DAGCombiner::visit(SDNode *N) { 739 switch(N->getOpcode()) { 740 default: break; 741 case ISD::TokenFactor: return visitTokenFactor(N); 742 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 743 case ISD::ADD: return visitADD(N); 744 case ISD::SUB: return visitSUB(N); 745 case ISD::ADDC: return visitADDC(N); 746 case ISD::ADDE: return visitADDE(N); 747 case ISD::MUL: return visitMUL(N); 748 case ISD::SDIV: return visitSDIV(N); 749 case ISD::UDIV: return visitUDIV(N); 750 case ISD::SREM: return visitSREM(N); 751 case ISD::UREM: return visitUREM(N); 752 case ISD::MULHU: return visitMULHU(N); 753 case ISD::MULHS: return visitMULHS(N); 754 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 755 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 756 case ISD::SDIVREM: return visitSDIVREM(N); 757 case ISD::UDIVREM: return visitUDIVREM(N); 758 case ISD::AND: return visitAND(N); 759 case ISD::OR: return visitOR(N); 760 case ISD::XOR: return visitXOR(N); 761 case ISD::SHL: return visitSHL(N); 762 case ISD::SRA: return visitSRA(N); 763 case ISD::SRL: return visitSRL(N); 764 case ISD::CTLZ: return visitCTLZ(N); 765 case ISD::CTTZ: return visitCTTZ(N); 766 case ISD::CTPOP: return visitCTPOP(N); 767 case ISD::SELECT: return visitSELECT(N); 768 case ISD::SELECT_CC: return visitSELECT_CC(N); 769 case ISD::SETCC: return visitSETCC(N); 770 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 771 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 772 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 773 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 774 case ISD::TRUNCATE: return visitTRUNCATE(N); 775 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 776 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 777 case ISD::FADD: return visitFADD(N); 778 case ISD::FSUB: return visitFSUB(N); 779 case ISD::FMUL: return visitFMUL(N); 780 case ISD::FDIV: return visitFDIV(N); 781 case ISD::FREM: return visitFREM(N); 782 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 783 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 784 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 785 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 786 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 787 case ISD::FP_ROUND: return visitFP_ROUND(N); 788 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 789 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 790 case ISD::FNEG: return visitFNEG(N); 791 case ISD::FABS: return visitFABS(N); 792 case ISD::BRCOND: return visitBRCOND(N); 793 case ISD::BR_CC: return visitBR_CC(N); 794 case ISD::LOAD: return visitLOAD(N); 795 case ISD::STORE: return visitSTORE(N); 796 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 797 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 798 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 799 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 800 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 801 } 802 return SDValue(); 803} 804 805SDValue DAGCombiner::combine(SDNode *N) { 806 SDValue RV = visit(N); 807 808 // If nothing happened, try a target-specific DAG combine. 809 if (RV.getNode() == 0) { 810 assert(N->getOpcode() != ISD::DELETED_NODE && 811 "Node was deleted but visit returned NULL!"); 812 813 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 814 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 815 816 // Expose the DAG combiner to the target combiner impls. 817 TargetLowering::DAGCombinerInfo 818 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 819 820 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 821 } 822 } 823 824 // If N is a commutative binary node, try commuting it to enable more 825 // sdisel CSE. 826 if (RV.getNode() == 0 && 827 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 828 N->getNumValues() == 1) { 829 SDValue N0 = N->getOperand(0); 830 SDValue N1 = N->getOperand(1); 831 832 // Constant operands are canonicalized to RHS. 833 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 834 SDValue Ops[] = { N1, N0 }; 835 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 836 Ops, 2); 837 if (CSENode) 838 return SDValue(CSENode, 0); 839 } 840 } 841 842 return RV; 843} 844 845/// getInputChainForNode - Given a node, return its input chain if it has one, 846/// otherwise return a null sd operand. 847static SDValue getInputChainForNode(SDNode *N) { 848 if (unsigned NumOps = N->getNumOperands()) { 849 if (N->getOperand(0).getValueType() == MVT::Other) 850 return N->getOperand(0); 851 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 852 return N->getOperand(NumOps-1); 853 for (unsigned i = 1; i < NumOps-1; ++i) 854 if (N->getOperand(i).getValueType() == MVT::Other) 855 return N->getOperand(i); 856 } 857 return SDValue(); 858} 859 860SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 861 // If N has two operands, where one has an input chain equal to the other, 862 // the 'other' chain is redundant. 863 if (N->getNumOperands() == 2) { 864 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 865 return N->getOperand(0); 866 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 867 return N->getOperand(1); 868 } 869 870 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 871 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 872 SmallPtrSet<SDNode*, 16> SeenOps; 873 bool Changed = false; // If we should replace this token factor. 874 875 // Start out with this token factor. 876 TFs.push_back(N); 877 878 // Iterate through token factors. The TFs grows when new token factors are 879 // encountered. 880 for (unsigned i = 0; i < TFs.size(); ++i) { 881 SDNode *TF = TFs[i]; 882 883 // Check each of the operands. 884 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 885 SDValue Op = TF->getOperand(i); 886 887 switch (Op.getOpcode()) { 888 case ISD::EntryToken: 889 // Entry tokens don't need to be added to the list. They are 890 // rededundant. 891 Changed = true; 892 break; 893 894 case ISD::TokenFactor: 895 if (Op.hasOneUse() && 896 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 897 // Queue up for processing. 898 TFs.push_back(Op.getNode()); 899 // Clean up in case the token factor is removed. 900 AddToWorkList(Op.getNode()); 901 Changed = true; 902 break; 903 } 904 // Fall thru 905 906 default: 907 // Only add if it isn't already in the list. 908 if (SeenOps.insert(Op.getNode())) 909 Ops.push_back(Op); 910 else 911 Changed = true; 912 break; 913 } 914 } 915 } 916 917 SDValue Result; 918 919 // If we've change things around then replace token factor. 920 if (Changed) { 921 if (Ops.empty()) { 922 // The entry token is the only possible outcome. 923 Result = DAG.getEntryNode(); 924 } else { 925 // New and improved token factor. 926 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 927 MVT::Other, &Ops[0], Ops.size()); 928 } 929 930 // Don't add users to work list. 931 return CombineTo(N, Result, false); 932 } 933 934 return Result; 935} 936 937/// MERGE_VALUES can always be eliminated. 938SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 939 WorkListRemover DeadNodes(*this); 940 // Replacing results may cause a different MERGE_VALUES to suddenly 941 // be CSE'd with N, and carry its uses with it. Iterate until no 942 // uses remain, to ensure that the node can be safely deleted. 943 do { 944 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 945 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 946 &DeadNodes); 947 } while (!N->use_empty()); 948 removeFromWorkList(N); 949 DAG.DeleteNode(N); 950 return SDValue(N, 0); // Return N so it doesn't get rechecked! 951} 952 953static 954SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 955 SelectionDAG &DAG) { 956 EVT VT = N0.getValueType(); 957 SDValue N00 = N0.getOperand(0); 958 SDValue N01 = N0.getOperand(1); 959 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 960 961 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 962 isa<ConstantSDNode>(N00.getOperand(1))) { 963 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 964 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 965 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 966 N00.getOperand(0), N01), 967 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 968 N00.getOperand(1), N01)); 969 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 970 } 971 972 return SDValue(); 973} 974 975SDValue DAGCombiner::visitADD(SDNode *N) { 976 SDValue N0 = N->getOperand(0); 977 SDValue N1 = N->getOperand(1); 978 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 979 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 980 EVT VT = N0.getValueType(); 981 982 // fold vector ops 983 if (VT.isVector()) { 984 SDValue FoldedVOp = SimplifyVBinOp(N); 985 if (FoldedVOp.getNode()) return FoldedVOp; 986 } 987 988 // fold (add x, undef) -> undef 989 if (N0.getOpcode() == ISD::UNDEF) 990 return N0; 991 if (N1.getOpcode() == ISD::UNDEF) 992 return N1; 993 // fold (add c1, c2) -> c1+c2 994 if (N0C && N1C) 995 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 996 // canonicalize constant to RHS 997 if (N0C && !N1C) 998 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 999 // fold (add x, 0) -> x 1000 if (N1C && N1C->isNullValue()) 1001 return N0; 1002 // fold (add Sym, c) -> Sym+c 1003 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1004 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1005 GA->getOpcode() == ISD::GlobalAddress) 1006 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1007 GA->getOffset() + 1008 (uint64_t)N1C->getSExtValue()); 1009 // fold ((c1-A)+c2) -> (c1+c2)-A 1010 if (N1C && N0.getOpcode() == ISD::SUB) 1011 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1012 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1013 DAG.getConstant(N1C->getAPIntValue()+ 1014 N0C->getAPIntValue(), VT), 1015 N0.getOperand(1)); 1016 // reassociate add 1017 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1018 if (RADD.getNode() != 0) 1019 return RADD; 1020 // fold ((0-A) + B) -> B-A 1021 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1022 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1023 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1024 // fold (A + (0-B)) -> A-B 1025 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1026 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1027 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1028 // fold (A+(B-A)) -> B 1029 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1030 return N1.getOperand(0); 1031 // fold ((B-A)+A) -> B 1032 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1033 return N0.getOperand(0); 1034 // fold (A+(B-(A+C))) to (B-C) 1035 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1036 N0 == N1.getOperand(1).getOperand(0)) 1037 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1038 N1.getOperand(1).getOperand(1)); 1039 // fold (A+(B-(C+A))) to (B-C) 1040 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1041 N0 == N1.getOperand(1).getOperand(1)) 1042 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1043 N1.getOperand(1).getOperand(0)); 1044 // fold (A+((B-A)+or-C)) to (B+or-C) 1045 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1046 N1.getOperand(0).getOpcode() == ISD::SUB && 1047 N0 == N1.getOperand(0).getOperand(1)) 1048 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1049 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1050 1051 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1052 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1053 SDValue N00 = N0.getOperand(0); 1054 SDValue N01 = N0.getOperand(1); 1055 SDValue N10 = N1.getOperand(0); 1056 SDValue N11 = N1.getOperand(1); 1057 1058 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1059 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1060 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1061 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1062 } 1063 1064 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1065 return SDValue(N, 0); 1066 1067 // fold (a+b) -> (a|b) iff a and b share no bits. 1068 if (VT.isInteger() && !VT.isVector()) { 1069 APInt LHSZero, LHSOne; 1070 APInt RHSZero, RHSOne; 1071 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1072 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1073 1074 if (LHSZero.getBoolValue()) { 1075 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1076 1077 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1078 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1079 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1080 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1081 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1082 } 1083 } 1084 1085 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1086 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1087 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1088 if (Result.getNode()) return Result; 1089 } 1090 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1091 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1092 if (Result.getNode()) return Result; 1093 } 1094 1095 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1096 if (N1.getOpcode() == ISD::SHL && 1097 N1.getOperand(0).getOpcode() == ISD::SUB) 1098 if (ConstantSDNode *C = 1099 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1100 if (C->getAPIntValue() == 0) 1101 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1102 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1103 N1.getOperand(0).getOperand(1), 1104 N1.getOperand(1))); 1105 if (N0.getOpcode() == ISD::SHL && 1106 N0.getOperand(0).getOpcode() == ISD::SUB) 1107 if (ConstantSDNode *C = 1108 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1109 if (C->getAPIntValue() == 0) 1110 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1111 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1112 N0.getOperand(0).getOperand(1), 1113 N0.getOperand(1))); 1114 1115 return SDValue(); 1116} 1117 1118SDValue DAGCombiner::visitADDC(SDNode *N) { 1119 SDValue N0 = N->getOperand(0); 1120 SDValue N1 = N->getOperand(1); 1121 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1122 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1123 EVT VT = N0.getValueType(); 1124 1125 // If the flag result is dead, turn this into an ADD. 1126 if (N->hasNUsesOfValue(0, 1)) 1127 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1128 DAG.getNode(ISD::CARRY_FALSE, 1129 N->getDebugLoc(), MVT::Flag)); 1130 1131 // canonicalize constant to RHS. 1132 if (N0C && !N1C) 1133 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1134 1135 // fold (addc x, 0) -> x + no carry out 1136 if (N1C && N1C->isNullValue()) 1137 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1138 N->getDebugLoc(), MVT::Flag)); 1139 1140 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1141 APInt LHSZero, LHSOne; 1142 APInt RHSZero, RHSOne; 1143 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1144 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1145 1146 if (LHSZero.getBoolValue()) { 1147 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1148 1149 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1150 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1151 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1152 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1153 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1154 DAG.getNode(ISD::CARRY_FALSE, 1155 N->getDebugLoc(), MVT::Flag)); 1156 } 1157 1158 return SDValue(); 1159} 1160 1161SDValue DAGCombiner::visitADDE(SDNode *N) { 1162 SDValue N0 = N->getOperand(0); 1163 SDValue N1 = N->getOperand(1); 1164 SDValue CarryIn = N->getOperand(2); 1165 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1166 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1167 1168 // canonicalize constant to RHS 1169 if (N0C && !N1C) 1170 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1171 N1, N0, CarryIn); 1172 1173 // fold (adde x, y, false) -> (addc x, y) 1174 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1175 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1176 1177 return SDValue(); 1178} 1179 1180SDValue DAGCombiner::visitSUB(SDNode *N) { 1181 SDValue N0 = N->getOperand(0); 1182 SDValue N1 = N->getOperand(1); 1183 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1184 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1185 EVT VT = N0.getValueType(); 1186 1187 // fold vector ops 1188 if (VT.isVector()) { 1189 SDValue FoldedVOp = SimplifyVBinOp(N); 1190 if (FoldedVOp.getNode()) return FoldedVOp; 1191 } 1192 1193 // fold (sub x, x) -> 0 1194 if (N0 == N1) 1195 return DAG.getConstant(0, N->getValueType(0)); 1196 // fold (sub c1, c2) -> c1-c2 1197 if (N0C && N1C) 1198 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1199 // fold (sub x, c) -> (add x, -c) 1200 if (N1C) 1201 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1202 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1203 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1204 if (N0C && N0C->isAllOnesValue()) 1205 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1206 // fold (A+B)-A -> B 1207 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1208 return N0.getOperand(1); 1209 // fold (A+B)-B -> A 1210 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1211 return N0.getOperand(0); 1212 // fold ((A+(B+or-C))-B) -> A+or-C 1213 if (N0.getOpcode() == ISD::ADD && 1214 (N0.getOperand(1).getOpcode() == ISD::SUB || 1215 N0.getOperand(1).getOpcode() == ISD::ADD) && 1216 N0.getOperand(1).getOperand(0) == N1) 1217 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1218 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1219 // fold ((A+(C+B))-B) -> A+C 1220 if (N0.getOpcode() == ISD::ADD && 1221 N0.getOperand(1).getOpcode() == ISD::ADD && 1222 N0.getOperand(1).getOperand(1) == N1) 1223 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1224 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1225 // fold ((A-(B-C))-C) -> A-B 1226 if (N0.getOpcode() == ISD::SUB && 1227 N0.getOperand(1).getOpcode() == ISD::SUB && 1228 N0.getOperand(1).getOperand(1) == N1) 1229 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1230 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1231 1232 // If either operand of a sub is undef, the result is undef 1233 if (N0.getOpcode() == ISD::UNDEF) 1234 return N0; 1235 if (N1.getOpcode() == ISD::UNDEF) 1236 return N1; 1237 1238 // If the relocation model supports it, consider symbol offsets. 1239 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1240 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1241 // fold (sub Sym, c) -> Sym-c 1242 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1243 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1244 GA->getOffset() - 1245 (uint64_t)N1C->getSExtValue()); 1246 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1247 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1248 if (GA->getGlobal() == GB->getGlobal()) 1249 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1250 VT); 1251 } 1252 1253 return SDValue(); 1254} 1255 1256SDValue DAGCombiner::visitMUL(SDNode *N) { 1257 SDValue N0 = N->getOperand(0); 1258 SDValue N1 = N->getOperand(1); 1259 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1260 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1261 EVT VT = N0.getValueType(); 1262 1263 // fold vector ops 1264 if (VT.isVector()) { 1265 SDValue FoldedVOp = SimplifyVBinOp(N); 1266 if (FoldedVOp.getNode()) return FoldedVOp; 1267 } 1268 1269 // fold (mul x, undef) -> 0 1270 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1271 return DAG.getConstant(0, VT); 1272 // fold (mul c1, c2) -> c1*c2 1273 if (N0C && N1C) 1274 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1275 // canonicalize constant to RHS 1276 if (N0C && !N1C) 1277 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1278 // fold (mul x, 0) -> 0 1279 if (N1C && N1C->isNullValue()) 1280 return N1; 1281 // fold (mul x, -1) -> 0-x 1282 if (N1C && N1C->isAllOnesValue()) 1283 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1284 DAG.getConstant(0, VT), N0); 1285 // fold (mul x, (1 << c)) -> x << c 1286 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1287 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1288 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1289 getShiftAmountTy())); 1290 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1291 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1292 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1293 // FIXME: If the input is something that is easily negated (e.g. a 1294 // single-use add), we should put the negate there. 1295 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1296 DAG.getConstant(0, VT), 1297 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1298 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1299 } 1300 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1301 if (N1C && N0.getOpcode() == ISD::SHL && 1302 isa<ConstantSDNode>(N0.getOperand(1))) { 1303 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1304 N1, N0.getOperand(1)); 1305 AddToWorkList(C3.getNode()); 1306 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1307 N0.getOperand(0), C3); 1308 } 1309 1310 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1311 // use. 1312 { 1313 SDValue Sh(0,0), Y(0,0); 1314 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1315 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1316 N0.getNode()->hasOneUse()) { 1317 Sh = N0; Y = N1; 1318 } else if (N1.getOpcode() == ISD::SHL && 1319 isa<ConstantSDNode>(N1.getOperand(1)) && 1320 N1.getNode()->hasOneUse()) { 1321 Sh = N1; Y = N0; 1322 } 1323 1324 if (Sh.getNode()) { 1325 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1326 Sh.getOperand(0), Y); 1327 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1328 Mul, Sh.getOperand(1)); 1329 } 1330 } 1331 1332 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1333 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1334 isa<ConstantSDNode>(N0.getOperand(1))) 1335 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1336 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1337 N0.getOperand(0), N1), 1338 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1339 N0.getOperand(1), N1)); 1340 1341 // reassociate mul 1342 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1343 if (RMUL.getNode() != 0) 1344 return RMUL; 1345 1346 return SDValue(); 1347} 1348 1349SDValue DAGCombiner::visitSDIV(SDNode *N) { 1350 SDValue N0 = N->getOperand(0); 1351 SDValue N1 = N->getOperand(1); 1352 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1353 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1354 EVT VT = N->getValueType(0); 1355 1356 // fold vector ops 1357 if (VT.isVector()) { 1358 SDValue FoldedVOp = SimplifyVBinOp(N); 1359 if (FoldedVOp.getNode()) return FoldedVOp; 1360 } 1361 1362 // fold (sdiv c1, c2) -> c1/c2 1363 if (N0C && N1C && !N1C->isNullValue()) 1364 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1365 // fold (sdiv X, 1) -> X 1366 if (N1C && N1C->getSExtValue() == 1LL) 1367 return N0; 1368 // fold (sdiv X, -1) -> 0-X 1369 if (N1C && N1C->isAllOnesValue()) 1370 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1371 DAG.getConstant(0, VT), N0); 1372 // If we know the sign bits of both operands are zero, strength reduce to a 1373 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1374 if (!VT.isVector()) { 1375 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1376 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1377 N0, N1); 1378 } 1379 // fold (sdiv X, pow2) -> simple ops after legalize 1380 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1381 (isPowerOf2_64(N1C->getSExtValue()) || 1382 isPowerOf2_64(-N1C->getSExtValue()))) { 1383 // If dividing by powers of two is cheap, then don't perform the following 1384 // fold. 1385 if (TLI.isPow2DivCheap()) 1386 return SDValue(); 1387 1388 int64_t pow2 = N1C->getSExtValue(); 1389 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1390 unsigned lg2 = Log2_64(abs2); 1391 1392 // Splat the sign bit into the register 1393 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1394 DAG.getConstant(VT.getSizeInBits()-1, 1395 getShiftAmountTy())); 1396 AddToWorkList(SGN.getNode()); 1397 1398 // Add (N0 < 0) ? abs2 - 1 : 0; 1399 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1400 DAG.getConstant(VT.getSizeInBits() - lg2, 1401 getShiftAmountTy())); 1402 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1403 AddToWorkList(SRL.getNode()); 1404 AddToWorkList(ADD.getNode()); // Divide by pow2 1405 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1406 DAG.getConstant(lg2, getShiftAmountTy())); 1407 1408 // If we're dividing by a positive value, we're done. Otherwise, we must 1409 // negate the result. 1410 if (pow2 > 0) 1411 return SRA; 1412 1413 AddToWorkList(SRA.getNode()); 1414 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1415 DAG.getConstant(0, VT), SRA); 1416 } 1417 1418 // if integer divide is expensive and we satisfy the requirements, emit an 1419 // alternate sequence. 1420 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1421 !TLI.isIntDivCheap()) { 1422 SDValue Op = BuildSDIV(N); 1423 if (Op.getNode()) return Op; 1424 } 1425 1426 // undef / X -> 0 1427 if (N0.getOpcode() == ISD::UNDEF) 1428 return DAG.getConstant(0, VT); 1429 // X / undef -> undef 1430 if (N1.getOpcode() == ISD::UNDEF) 1431 return N1; 1432 1433 return SDValue(); 1434} 1435 1436SDValue DAGCombiner::visitUDIV(SDNode *N) { 1437 SDValue N0 = N->getOperand(0); 1438 SDValue N1 = N->getOperand(1); 1439 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1440 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1441 EVT VT = N->getValueType(0); 1442 1443 // fold vector ops 1444 if (VT.isVector()) { 1445 SDValue FoldedVOp = SimplifyVBinOp(N); 1446 if (FoldedVOp.getNode()) return FoldedVOp; 1447 } 1448 1449 // fold (udiv c1, c2) -> c1/c2 1450 if (N0C && N1C && !N1C->isNullValue()) 1451 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1452 // fold (udiv x, (1 << c)) -> x >>u c 1453 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1454 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1455 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1456 getShiftAmountTy())); 1457 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1458 if (N1.getOpcode() == ISD::SHL) { 1459 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1460 if (SHC->getAPIntValue().isPowerOf2()) { 1461 EVT ADDVT = N1.getOperand(1).getValueType(); 1462 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1463 N1.getOperand(1), 1464 DAG.getConstant(SHC->getAPIntValue() 1465 .logBase2(), 1466 ADDVT)); 1467 AddToWorkList(Add.getNode()); 1468 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1469 } 1470 } 1471 } 1472 // fold (udiv x, c) -> alternate 1473 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1474 SDValue Op = BuildUDIV(N); 1475 if (Op.getNode()) return Op; 1476 } 1477 1478 // undef / X -> 0 1479 if (N0.getOpcode() == ISD::UNDEF) 1480 return DAG.getConstant(0, VT); 1481 // X / undef -> undef 1482 if (N1.getOpcode() == ISD::UNDEF) 1483 return N1; 1484 1485 return SDValue(); 1486} 1487 1488SDValue DAGCombiner::visitSREM(SDNode *N) { 1489 SDValue N0 = N->getOperand(0); 1490 SDValue N1 = N->getOperand(1); 1491 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1492 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1493 EVT VT = N->getValueType(0); 1494 1495 // fold (srem c1, c2) -> c1%c2 1496 if (N0C && N1C && !N1C->isNullValue()) 1497 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1498 // If we know the sign bits of both operands are zero, strength reduce to a 1499 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1500 if (!VT.isVector()) { 1501 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1502 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1503 } 1504 1505 // If X/C can be simplified by the division-by-constant logic, lower 1506 // X%C to the equivalent of X-X/C*C. 1507 if (N1C && !N1C->isNullValue()) { 1508 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1509 AddToWorkList(Div.getNode()); 1510 SDValue OptimizedDiv = combine(Div.getNode()); 1511 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1512 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1513 OptimizedDiv, N1); 1514 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1515 AddToWorkList(Mul.getNode()); 1516 return Sub; 1517 } 1518 } 1519 1520 // undef % X -> 0 1521 if (N0.getOpcode() == ISD::UNDEF) 1522 return DAG.getConstant(0, VT); 1523 // X % undef -> undef 1524 if (N1.getOpcode() == ISD::UNDEF) 1525 return N1; 1526 1527 return SDValue(); 1528} 1529 1530SDValue DAGCombiner::visitUREM(SDNode *N) { 1531 SDValue N0 = N->getOperand(0); 1532 SDValue N1 = N->getOperand(1); 1533 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1534 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1535 EVT VT = N->getValueType(0); 1536 1537 // fold (urem c1, c2) -> c1%c2 1538 if (N0C && N1C && !N1C->isNullValue()) 1539 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1540 // fold (urem x, pow2) -> (and x, pow2-1) 1541 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1542 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1543 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1544 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1545 if (N1.getOpcode() == ISD::SHL) { 1546 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1547 if (SHC->getAPIntValue().isPowerOf2()) { 1548 SDValue Add = 1549 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1550 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1551 VT)); 1552 AddToWorkList(Add.getNode()); 1553 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1554 } 1555 } 1556 } 1557 1558 // If X/C can be simplified by the division-by-constant logic, lower 1559 // X%C to the equivalent of X-X/C*C. 1560 if (N1C && !N1C->isNullValue()) { 1561 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1562 AddToWorkList(Div.getNode()); 1563 SDValue OptimizedDiv = combine(Div.getNode()); 1564 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1565 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1566 OptimizedDiv, N1); 1567 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1568 AddToWorkList(Mul.getNode()); 1569 return Sub; 1570 } 1571 } 1572 1573 // undef % X -> 0 1574 if (N0.getOpcode() == ISD::UNDEF) 1575 return DAG.getConstant(0, VT); 1576 // X % undef -> undef 1577 if (N1.getOpcode() == ISD::UNDEF) 1578 return N1; 1579 1580 return SDValue(); 1581} 1582 1583SDValue DAGCombiner::visitMULHS(SDNode *N) { 1584 SDValue N0 = N->getOperand(0); 1585 SDValue N1 = N->getOperand(1); 1586 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1587 EVT VT = N->getValueType(0); 1588 1589 // fold (mulhs x, 0) -> 0 1590 if (N1C && N1C->isNullValue()) 1591 return N1; 1592 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1593 if (N1C && N1C->getAPIntValue() == 1) 1594 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1595 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1596 getShiftAmountTy())); 1597 // fold (mulhs x, undef) -> 0 1598 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1599 return DAG.getConstant(0, VT); 1600 1601 return SDValue(); 1602} 1603 1604SDValue DAGCombiner::visitMULHU(SDNode *N) { 1605 SDValue N0 = N->getOperand(0); 1606 SDValue N1 = N->getOperand(1); 1607 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1608 EVT VT = N->getValueType(0); 1609 1610 // fold (mulhu x, 0) -> 0 1611 if (N1C && N1C->isNullValue()) 1612 return N1; 1613 // fold (mulhu x, 1) -> 0 1614 if (N1C && N1C->getAPIntValue() == 1) 1615 return DAG.getConstant(0, N0.getValueType()); 1616 // fold (mulhu x, undef) -> 0 1617 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1618 return DAG.getConstant(0, VT); 1619 1620 return SDValue(); 1621} 1622 1623/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1624/// compute two values. LoOp and HiOp give the opcodes for the two computations 1625/// that are being performed. Return true if a simplification was made. 1626/// 1627SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1628 unsigned HiOp) { 1629 // If the high half is not needed, just compute the low half. 1630 bool HiExists = N->hasAnyUseOfValue(1); 1631 if (!HiExists && 1632 (!LegalOperations || 1633 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1634 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1635 N->op_begin(), N->getNumOperands()); 1636 return CombineTo(N, Res, Res); 1637 } 1638 1639 // If the low half is not needed, just compute the high half. 1640 bool LoExists = N->hasAnyUseOfValue(0); 1641 if (!LoExists && 1642 (!LegalOperations || 1643 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1644 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1645 N->op_begin(), N->getNumOperands()); 1646 return CombineTo(N, Res, Res); 1647 } 1648 1649 // If both halves are used, return as it is. 1650 if (LoExists && HiExists) 1651 return SDValue(); 1652 1653 // If the two computed results can be simplified separately, separate them. 1654 if (LoExists) { 1655 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1656 N->op_begin(), N->getNumOperands()); 1657 AddToWorkList(Lo.getNode()); 1658 SDValue LoOpt = combine(Lo.getNode()); 1659 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1660 (!LegalOperations || 1661 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1662 return CombineTo(N, LoOpt, LoOpt); 1663 } 1664 1665 if (HiExists) { 1666 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1667 N->op_begin(), N->getNumOperands()); 1668 AddToWorkList(Hi.getNode()); 1669 SDValue HiOpt = combine(Hi.getNode()); 1670 if (HiOpt.getNode() && HiOpt != Hi && 1671 (!LegalOperations || 1672 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1673 return CombineTo(N, HiOpt, HiOpt); 1674 } 1675 1676 return SDValue(); 1677} 1678 1679SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1680 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1681 if (Res.getNode()) return Res; 1682 1683 return SDValue(); 1684} 1685 1686SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1687 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1688 if (Res.getNode()) return Res; 1689 1690 return SDValue(); 1691} 1692 1693SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1694 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1695 if (Res.getNode()) return Res; 1696 1697 return SDValue(); 1698} 1699 1700SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1701 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1702 if (Res.getNode()) return Res; 1703 1704 return SDValue(); 1705} 1706 1707/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1708/// two operands of the same opcode, try to simplify it. 1709SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1710 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1711 EVT VT = N0.getValueType(); 1712 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1713 1714 // Bail early if none of these transforms apply. 1715 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 1716 1717 // For each of OP in AND/OR/XOR: 1718 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1719 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1720 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1721 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1722 // 1723 // do not sink logical op inside of a vector extend, since it may combine 1724 // into a vsetcc. 1725 EVT Op0VT = N0.getOperand(0).getValueType(); 1726 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 1727 N0.getOpcode() == ISD::ANY_EXTEND || 1728 N0.getOpcode() == ISD::SIGN_EXTEND || 1729 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) && 1730 !VT.isVector() && 1731 Op0VT == N1.getOperand(0).getValueType() && 1732 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 1733 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1734 N0.getOperand(0).getValueType(), 1735 N0.getOperand(0), N1.getOperand(0)); 1736 AddToWorkList(ORNode.getNode()); 1737 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1738 } 1739 1740 // For each of OP in SHL/SRL/SRA/AND... 1741 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1742 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1743 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1744 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1745 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1746 N0.getOperand(1) == N1.getOperand(1)) { 1747 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1748 N0.getOperand(0).getValueType(), 1749 N0.getOperand(0), N1.getOperand(0)); 1750 AddToWorkList(ORNode.getNode()); 1751 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1752 ORNode, N0.getOperand(1)); 1753 } 1754 1755 return SDValue(); 1756} 1757 1758SDValue DAGCombiner::visitAND(SDNode *N) { 1759 SDValue N0 = N->getOperand(0); 1760 SDValue N1 = N->getOperand(1); 1761 SDValue LL, LR, RL, RR, CC0, CC1; 1762 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1763 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1764 EVT VT = N1.getValueType(); 1765 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 1766 1767 // fold vector ops 1768 if (VT.isVector()) { 1769 SDValue FoldedVOp = SimplifyVBinOp(N); 1770 if (FoldedVOp.getNode()) return FoldedVOp; 1771 } 1772 1773 // fold (and x, undef) -> 0 1774 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1775 return DAG.getConstant(0, VT); 1776 // fold (and c1, c2) -> c1&c2 1777 if (N0C && N1C) 1778 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1779 // canonicalize constant to RHS 1780 if (N0C && !N1C) 1781 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1782 // fold (and x, -1) -> x 1783 if (N1C && N1C->isAllOnesValue()) 1784 return N0; 1785 // if (and x, c) is known to be zero, return 0 1786 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1787 APInt::getAllOnesValue(BitWidth))) 1788 return DAG.getConstant(0, VT); 1789 // reassociate and 1790 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1791 if (RAND.getNode() != 0) 1792 return RAND; 1793 // fold (and (or x, C), D) -> D if (C & D) == D 1794 if (N1C && N0.getOpcode() == ISD::OR) 1795 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1796 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1797 return N1; 1798 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1799 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1800 SDValue N0Op0 = N0.getOperand(0); 1801 APInt Mask = ~N1C->getAPIntValue(); 1802 Mask.trunc(N0Op0.getValueSizeInBits()); 1803 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1804 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1805 N0.getValueType(), N0Op0); 1806 1807 // Replace uses of the AND with uses of the Zero extend node. 1808 CombineTo(N, Zext); 1809 1810 // We actually want to replace all uses of the any_extend with the 1811 // zero_extend, to avoid duplicating things. This will later cause this 1812 // AND to be folded. 1813 CombineTo(N0.getNode(), Zext); 1814 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1815 } 1816 } 1817 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1818 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1819 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1820 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1821 1822 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1823 LL.getValueType().isInteger()) { 1824 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1825 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1826 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1827 LR.getValueType(), LL, RL); 1828 AddToWorkList(ORNode.getNode()); 1829 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1830 } 1831 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1832 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1833 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1834 LR.getValueType(), LL, RL); 1835 AddToWorkList(ANDNode.getNode()); 1836 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1837 } 1838 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1839 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1840 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1841 LR.getValueType(), LL, RL); 1842 AddToWorkList(ORNode.getNode()); 1843 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1844 } 1845 } 1846 // canonicalize equivalent to ll == rl 1847 if (LL == RR && LR == RL) { 1848 Op1 = ISD::getSetCCSwappedOperands(Op1); 1849 std::swap(RL, RR); 1850 } 1851 if (LL == RL && LR == RR) { 1852 bool isInteger = LL.getValueType().isInteger(); 1853 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1854 if (Result != ISD::SETCC_INVALID && 1855 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1856 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1857 LL, LR, Result); 1858 } 1859 } 1860 1861 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1862 if (N0.getOpcode() == N1.getOpcode()) { 1863 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1864 if (Tmp.getNode()) return Tmp; 1865 } 1866 1867 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1868 // fold (and (sra)) -> (and (srl)) when possible. 1869 if (!VT.isVector() && 1870 SimplifyDemandedBits(SDValue(N, 0))) 1871 return SDValue(N, 0); 1872 1873 // fold (zext_inreg (extload x)) -> (zextload x) 1874 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1875 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1876 EVT MemVT = LN0->getMemoryVT(); 1877 // If we zero all the possible extended bits, then we can turn this into 1878 // a zextload if we are running before legalize or the operation is legal. 1879 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 1880 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1881 BitWidth - MemVT.getScalarType().getSizeInBits())) && 1882 ((!LegalOperations && !LN0->isVolatile()) || 1883 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1884 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1885 LN0->getChain(), LN0->getBasePtr(), 1886 LN0->getSrcValue(), 1887 LN0->getSrcValueOffset(), MemVT, 1888 LN0->isVolatile(), LN0->isNonTemporal(), 1889 LN0->getAlignment()); 1890 AddToWorkList(N); 1891 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1892 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1893 } 1894 } 1895 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1896 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1897 N0.hasOneUse()) { 1898 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1899 EVT MemVT = LN0->getMemoryVT(); 1900 // If we zero all the possible extended bits, then we can turn this into 1901 // a zextload if we are running before legalize or the operation is legal. 1902 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 1903 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1904 BitWidth - MemVT.getScalarType().getSizeInBits())) && 1905 ((!LegalOperations && !LN0->isVolatile()) || 1906 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1907 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1908 LN0->getChain(), 1909 LN0->getBasePtr(), LN0->getSrcValue(), 1910 LN0->getSrcValueOffset(), MemVT, 1911 LN0->isVolatile(), LN0->isNonTemporal(), 1912 LN0->getAlignment()); 1913 AddToWorkList(N); 1914 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1915 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1916 } 1917 } 1918 1919 // fold (and (load x), 255) -> (zextload x, i8) 1920 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1921 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 1922 if (N1C && (N0.getOpcode() == ISD::LOAD || 1923 (N0.getOpcode() == ISD::ANY_EXTEND && 1924 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 1925 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 1926 LoadSDNode *LN0 = HasAnyExt 1927 ? cast<LoadSDNode>(N0.getOperand(0)) 1928 : cast<LoadSDNode>(N0); 1929 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1930 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 1931 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1932 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 1933 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 1934 EVT LoadedVT = LN0->getMemoryVT(); 1935 1936 if (ExtVT == LoadedVT && 1937 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1938 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1939 1940 SDValue NewLoad = 1941 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1942 LN0->getChain(), LN0->getBasePtr(), 1943 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1944 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 1945 LN0->getAlignment()); 1946 AddToWorkList(N); 1947 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 1948 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1949 } 1950 1951 // Do not change the width of a volatile load. 1952 // Do not generate loads of non-round integer types since these can 1953 // be expensive (and would be wrong if the type is not byte sized). 1954 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 1955 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1956 EVT PtrType = LN0->getOperand(1).getValueType(); 1957 1958 unsigned Alignment = LN0->getAlignment(); 1959 SDValue NewPtr = LN0->getBasePtr(); 1960 1961 // For big endian targets, we need to add an offset to the pointer 1962 // to load the correct bytes. For little endian systems, we merely 1963 // need to read fewer bytes from the same pointer. 1964 if (TLI.isBigEndian()) { 1965 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 1966 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 1967 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1968 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1969 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1970 Alignment = MinAlign(Alignment, PtrOff); 1971 } 1972 1973 AddToWorkList(NewPtr.getNode()); 1974 1975 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1976 SDValue Load = 1977 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1978 LN0->getChain(), NewPtr, 1979 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1980 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 1981 Alignment); 1982 AddToWorkList(N); 1983 CombineTo(LN0, Load, Load.getValue(1)); 1984 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1985 } 1986 } 1987 } 1988 } 1989 1990 return SDValue(); 1991} 1992 1993SDValue DAGCombiner::visitOR(SDNode *N) { 1994 SDValue N0 = N->getOperand(0); 1995 SDValue N1 = N->getOperand(1); 1996 SDValue LL, LR, RL, RR, CC0, CC1; 1997 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1998 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1999 EVT VT = N1.getValueType(); 2000 2001 // fold vector ops 2002 if (VT.isVector()) { 2003 SDValue FoldedVOp = SimplifyVBinOp(N); 2004 if (FoldedVOp.getNode()) return FoldedVOp; 2005 } 2006 2007 // fold (or x, undef) -> -1 2008 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 2009 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2010 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2011 } 2012 // fold (or c1, c2) -> c1|c2 2013 if (N0C && N1C) 2014 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2015 // canonicalize constant to RHS 2016 if (N0C && !N1C) 2017 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2018 // fold (or x, 0) -> x 2019 if (N1C && N1C->isNullValue()) 2020 return N0; 2021 // fold (or x, -1) -> -1 2022 if (N1C && N1C->isAllOnesValue()) 2023 return N1; 2024 // fold (or x, c) -> c iff (x & ~c) == 0 2025 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2026 return N1; 2027 // reassociate or 2028 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2029 if (ROR.getNode() != 0) 2030 return ROR; 2031 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2032 // iff (c1 & c2) == 0. 2033 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2034 isa<ConstantSDNode>(N0.getOperand(1))) { 2035 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2036 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2037 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2038 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2039 N0.getOperand(0), N1), 2040 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2041 } 2042 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2043 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2044 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2045 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2046 2047 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2048 LL.getValueType().isInteger()) { 2049 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2050 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2051 if (cast<ConstantSDNode>(LR)->isNullValue() && 2052 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2053 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2054 LR.getValueType(), LL, RL); 2055 AddToWorkList(ORNode.getNode()); 2056 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2057 } 2058 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2059 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2060 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2061 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2062 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2063 LR.getValueType(), LL, RL); 2064 AddToWorkList(ANDNode.getNode()); 2065 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2066 } 2067 } 2068 // canonicalize equivalent to ll == rl 2069 if (LL == RR && LR == RL) { 2070 Op1 = ISD::getSetCCSwappedOperands(Op1); 2071 std::swap(RL, RR); 2072 } 2073 if (LL == RL && LR == RR) { 2074 bool isInteger = LL.getValueType().isInteger(); 2075 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2076 if (Result != ISD::SETCC_INVALID && 2077 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2078 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2079 LL, LR, Result); 2080 } 2081 } 2082 2083 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2084 if (N0.getOpcode() == N1.getOpcode()) { 2085 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2086 if (Tmp.getNode()) return Tmp; 2087 } 2088 2089 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2090 if (N0.getOpcode() == ISD::AND && 2091 N1.getOpcode() == ISD::AND && 2092 N0.getOperand(1).getOpcode() == ISD::Constant && 2093 N1.getOperand(1).getOpcode() == ISD::Constant && 2094 // Don't increase # computations. 2095 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2096 // We can only do this xform if we know that bits from X that are set in C2 2097 // but not in C1 are already zero. Likewise for Y. 2098 const APInt &LHSMask = 2099 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2100 const APInt &RHSMask = 2101 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2102 2103 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2104 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2105 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2106 N0.getOperand(0), N1.getOperand(0)); 2107 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2108 DAG.getConstant(LHSMask | RHSMask, VT)); 2109 } 2110 } 2111 2112 // See if this is some rotate idiom. 2113 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2114 return SDValue(Rot, 0); 2115 2116 return SDValue(); 2117} 2118 2119/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2120static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2121 if (Op.getOpcode() == ISD::AND) { 2122 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2123 Mask = Op.getOperand(1); 2124 Op = Op.getOperand(0); 2125 } else { 2126 return false; 2127 } 2128 } 2129 2130 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2131 Shift = Op; 2132 return true; 2133 } 2134 2135 return false; 2136} 2137 2138// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2139// idioms for rotate, and if the target supports rotation instructions, generate 2140// a rot[lr]. 2141SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2142 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2143 EVT VT = LHS.getValueType(); 2144 if (!TLI.isTypeLegal(VT)) return 0; 2145 2146 // The target must have at least one rotate flavor. 2147 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2148 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2149 if (!HasROTL && !HasROTR) return 0; 2150 2151 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2152 SDValue LHSShift; // The shift. 2153 SDValue LHSMask; // AND value if any. 2154 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2155 return 0; // Not part of a rotate. 2156 2157 SDValue RHSShift; // The shift. 2158 SDValue RHSMask; // AND value if any. 2159 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2160 return 0; // Not part of a rotate. 2161 2162 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2163 return 0; // Not shifting the same value. 2164 2165 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2166 return 0; // Shifts must disagree. 2167 2168 // Canonicalize shl to left side in a shl/srl pair. 2169 if (RHSShift.getOpcode() == ISD::SHL) { 2170 std::swap(LHS, RHS); 2171 std::swap(LHSShift, RHSShift); 2172 std::swap(LHSMask , RHSMask ); 2173 } 2174 2175 unsigned OpSizeInBits = VT.getSizeInBits(); 2176 SDValue LHSShiftArg = LHSShift.getOperand(0); 2177 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2178 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2179 2180 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2181 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2182 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2183 RHSShiftAmt.getOpcode() == ISD::Constant) { 2184 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2185 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2186 if ((LShVal + RShVal) != OpSizeInBits) 2187 return 0; 2188 2189 SDValue Rot; 2190 if (HasROTL) 2191 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2192 else 2193 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2194 2195 // If there is an AND of either shifted operand, apply it to the result. 2196 if (LHSMask.getNode() || RHSMask.getNode()) { 2197 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2198 2199 if (LHSMask.getNode()) { 2200 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2201 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2202 } 2203 if (RHSMask.getNode()) { 2204 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2205 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2206 } 2207 2208 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2209 } 2210 2211 return Rot.getNode(); 2212 } 2213 2214 // If there is a mask here, and we have a variable shift, we can't be sure 2215 // that we're masking out the right stuff. 2216 if (LHSMask.getNode() || RHSMask.getNode()) 2217 return 0; 2218 2219 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2220 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2221 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2222 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2223 if (ConstantSDNode *SUBC = 2224 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2225 if (SUBC->getAPIntValue() == OpSizeInBits) { 2226 if (HasROTL) 2227 return DAG.getNode(ISD::ROTL, DL, VT, 2228 LHSShiftArg, LHSShiftAmt).getNode(); 2229 else 2230 return DAG.getNode(ISD::ROTR, DL, VT, 2231 LHSShiftArg, RHSShiftAmt).getNode(); 2232 } 2233 } 2234 } 2235 2236 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2237 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2238 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2239 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2240 if (ConstantSDNode *SUBC = 2241 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2242 if (SUBC->getAPIntValue() == OpSizeInBits) { 2243 if (HasROTR) 2244 return DAG.getNode(ISD::ROTR, DL, VT, 2245 LHSShiftArg, RHSShiftAmt).getNode(); 2246 else 2247 return DAG.getNode(ISD::ROTL, DL, VT, 2248 LHSShiftArg, LHSShiftAmt).getNode(); 2249 } 2250 } 2251 } 2252 2253 // Look for sign/zext/any-extended or truncate cases: 2254 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2255 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2256 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2257 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2258 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2259 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2260 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2261 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2262 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2263 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2264 if (RExtOp0.getOpcode() == ISD::SUB && 2265 RExtOp0.getOperand(1) == LExtOp0) { 2266 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2267 // (rotl x, y) 2268 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2269 // (rotr x, (sub 32, y)) 2270 if (ConstantSDNode *SUBC = 2271 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2272 if (SUBC->getAPIntValue() == OpSizeInBits) { 2273 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2274 LHSShiftArg, 2275 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2276 } 2277 } 2278 } else if (LExtOp0.getOpcode() == ISD::SUB && 2279 RExtOp0 == LExtOp0.getOperand(1)) { 2280 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2281 // (rotr x, y) 2282 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2283 // (rotl x, (sub 32, y)) 2284 if (ConstantSDNode *SUBC = 2285 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2286 if (SUBC->getAPIntValue() == OpSizeInBits) { 2287 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2288 LHSShiftArg, 2289 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2290 } 2291 } 2292 } 2293 } 2294 2295 return 0; 2296} 2297 2298SDValue DAGCombiner::visitXOR(SDNode *N) { 2299 SDValue N0 = N->getOperand(0); 2300 SDValue N1 = N->getOperand(1); 2301 SDValue LHS, RHS, CC; 2302 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2303 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2304 EVT VT = N0.getValueType(); 2305 2306 // fold vector ops 2307 if (VT.isVector()) { 2308 SDValue FoldedVOp = SimplifyVBinOp(N); 2309 if (FoldedVOp.getNode()) return FoldedVOp; 2310 } 2311 2312 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2313 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2314 return DAG.getConstant(0, VT); 2315 // fold (xor x, undef) -> undef 2316 if (N0.getOpcode() == ISD::UNDEF) 2317 return N0; 2318 if (N1.getOpcode() == ISD::UNDEF) 2319 return N1; 2320 // fold (xor c1, c2) -> c1^c2 2321 if (N0C && N1C) 2322 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2323 // canonicalize constant to RHS 2324 if (N0C && !N1C) 2325 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2326 // fold (xor x, 0) -> x 2327 if (N1C && N1C->isNullValue()) 2328 return N0; 2329 // reassociate xor 2330 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2331 if (RXOR.getNode() != 0) 2332 return RXOR; 2333 2334 // fold !(x cc y) -> (x !cc y) 2335 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2336 bool isInt = LHS.getValueType().isInteger(); 2337 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2338 isInt); 2339 2340 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2341 switch (N0.getOpcode()) { 2342 default: 2343 llvm_unreachable("Unhandled SetCC Equivalent!"); 2344 case ISD::SETCC: 2345 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2346 case ISD::SELECT_CC: 2347 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2348 N0.getOperand(3), NotCC); 2349 } 2350 } 2351 } 2352 2353 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2354 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2355 N0.getNode()->hasOneUse() && 2356 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2357 SDValue V = N0.getOperand(0); 2358 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2359 DAG.getConstant(1, V.getValueType())); 2360 AddToWorkList(V.getNode()); 2361 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2362 } 2363 2364 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2365 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2366 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2367 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2368 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2369 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2370 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2371 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2372 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2373 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2374 } 2375 } 2376 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2377 if (N1C && N1C->isAllOnesValue() && 2378 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2379 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2380 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2381 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2382 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2383 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2384 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2385 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2386 } 2387 } 2388 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2389 if (N1C && N0.getOpcode() == ISD::XOR) { 2390 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2391 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2392 if (N00C) 2393 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2394 DAG.getConstant(N1C->getAPIntValue() ^ 2395 N00C->getAPIntValue(), VT)); 2396 if (N01C) 2397 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2398 DAG.getConstant(N1C->getAPIntValue() ^ 2399 N01C->getAPIntValue(), VT)); 2400 } 2401 // fold (xor x, x) -> 0 2402 if (N0 == N1) { 2403 if (!VT.isVector()) { 2404 return DAG.getConstant(0, VT); 2405 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2406 // Produce a vector of zeros. 2407 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2408 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2409 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2410 &Ops[0], Ops.size()); 2411 } 2412 } 2413 2414 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2415 if (N0.getOpcode() == N1.getOpcode()) { 2416 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2417 if (Tmp.getNode()) return Tmp; 2418 } 2419 2420 // Simplify the expression using non-local knowledge. 2421 if (!VT.isVector() && 2422 SimplifyDemandedBits(SDValue(N, 0))) 2423 return SDValue(N, 0); 2424 2425 return SDValue(); 2426} 2427 2428/// visitShiftByConstant - Handle transforms common to the three shifts, when 2429/// the shift amount is a constant. 2430SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2431 SDNode *LHS = N->getOperand(0).getNode(); 2432 if (!LHS->hasOneUse()) return SDValue(); 2433 2434 // We want to pull some binops through shifts, so that we have (and (shift)) 2435 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2436 // thing happens with address calculations, so it's important to canonicalize 2437 // it. 2438 bool HighBitSet = false; // Can we transform this if the high bit is set? 2439 2440 switch (LHS->getOpcode()) { 2441 default: return SDValue(); 2442 case ISD::OR: 2443 case ISD::XOR: 2444 HighBitSet = false; // We can only transform sra if the high bit is clear. 2445 break; 2446 case ISD::AND: 2447 HighBitSet = true; // We can only transform sra if the high bit is set. 2448 break; 2449 case ISD::ADD: 2450 if (N->getOpcode() != ISD::SHL) 2451 return SDValue(); // only shl(add) not sr[al](add). 2452 HighBitSet = false; // We can only transform sra if the high bit is clear. 2453 break; 2454 } 2455 2456 // We require the RHS of the binop to be a constant as well. 2457 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2458 if (!BinOpCst) return SDValue(); 2459 2460 // FIXME: disable this unless the input to the binop is a shift by a constant. 2461 // If it is not a shift, it pessimizes some common cases like: 2462 // 2463 // void foo(int *X, int i) { X[i & 1235] = 1; } 2464 // int bar(int *X, int i) { return X[i & 255]; } 2465 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2466 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2467 BinOpLHSVal->getOpcode() != ISD::SRA && 2468 BinOpLHSVal->getOpcode() != ISD::SRL) || 2469 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2470 return SDValue(); 2471 2472 EVT VT = N->getValueType(0); 2473 2474 // If this is a signed shift right, and the high bit is modified by the 2475 // logical operation, do not perform the transformation. The highBitSet 2476 // boolean indicates the value of the high bit of the constant which would 2477 // cause it to be modified for this operation. 2478 if (N->getOpcode() == ISD::SRA) { 2479 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2480 if (BinOpRHSSignSet != HighBitSet) 2481 return SDValue(); 2482 } 2483 2484 // Fold the constants, shifting the binop RHS by the shift amount. 2485 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2486 N->getValueType(0), 2487 LHS->getOperand(1), N->getOperand(1)); 2488 2489 // Create the new shift. 2490 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2491 VT, LHS->getOperand(0), N->getOperand(1)); 2492 2493 // Create the new binop. 2494 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2495} 2496 2497SDValue DAGCombiner::visitSHL(SDNode *N) { 2498 SDValue N0 = N->getOperand(0); 2499 SDValue N1 = N->getOperand(1); 2500 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2501 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2502 EVT VT = N0.getValueType(); 2503 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2504 2505 // fold (shl c1, c2) -> c1<<c2 2506 if (N0C && N1C) 2507 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2508 // fold (shl 0, x) -> 0 2509 if (N0C && N0C->isNullValue()) 2510 return N0; 2511 // fold (shl x, c >= size(x)) -> undef 2512 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2513 return DAG.getUNDEF(VT); 2514 // fold (shl x, 0) -> x 2515 if (N1C && N1C->isNullValue()) 2516 return N0; 2517 // if (shl x, c) is known to be zero, return 0 2518 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2519 APInt::getAllOnesValue(OpSizeInBits))) 2520 return DAG.getConstant(0, VT); 2521 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2522 if (N1.getOpcode() == ISD::TRUNCATE && 2523 N1.getOperand(0).getOpcode() == ISD::AND && 2524 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2525 SDValue N101 = N1.getOperand(0).getOperand(1); 2526 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2527 EVT TruncVT = N1.getValueType(); 2528 SDValue N100 = N1.getOperand(0).getOperand(0); 2529 APInt TruncC = N101C->getAPIntValue(); 2530 TruncC.trunc(TruncVT.getSizeInBits()); 2531 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2532 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2533 DAG.getNode(ISD::TRUNCATE, 2534 N->getDebugLoc(), 2535 TruncVT, N100), 2536 DAG.getConstant(TruncC, TruncVT))); 2537 } 2538 } 2539 2540 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2541 return SDValue(N, 0); 2542 2543 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2544 if (N1C && N0.getOpcode() == ISD::SHL && 2545 N0.getOperand(1).getOpcode() == ISD::Constant) { 2546 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2547 uint64_t c2 = N1C->getZExtValue(); 2548 if (c1 + c2 > OpSizeInBits) 2549 return DAG.getConstant(0, VT); 2550 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2551 DAG.getConstant(c1 + c2, N1.getValueType())); 2552 } 2553 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2554 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2555 if (N1C && N0.getOpcode() == ISD::SRL && 2556 N0.getOperand(1).getOpcode() == ISD::Constant) { 2557 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2558 if (c1 < VT.getSizeInBits()) { 2559 uint64_t c2 = N1C->getZExtValue(); 2560 SDValue HiBitsMask = 2561 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2562 VT.getSizeInBits() - c1), 2563 VT); 2564 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2565 N0.getOperand(0), 2566 HiBitsMask); 2567 if (c2 > c1) 2568 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2569 DAG.getConstant(c2-c1, N1.getValueType())); 2570 else 2571 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2572 DAG.getConstant(c1-c2, N1.getValueType())); 2573 } 2574 } 2575 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2576 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2577 SDValue HiBitsMask = 2578 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2579 VT.getSizeInBits() - 2580 N1C->getZExtValue()), 2581 VT); 2582 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2583 HiBitsMask); 2584 } 2585 2586 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2587} 2588 2589SDValue DAGCombiner::visitSRA(SDNode *N) { 2590 SDValue N0 = N->getOperand(0); 2591 SDValue N1 = N->getOperand(1); 2592 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2593 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2594 EVT VT = N0.getValueType(); 2595 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2596 2597 // fold (sra c1, c2) -> (sra c1, c2) 2598 if (N0C && N1C) 2599 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2600 // fold (sra 0, x) -> 0 2601 if (N0C && N0C->isNullValue()) 2602 return N0; 2603 // fold (sra -1, x) -> -1 2604 if (N0C && N0C->isAllOnesValue()) 2605 return N0; 2606 // fold (sra x, (setge c, size(x))) -> undef 2607 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2608 return DAG.getUNDEF(VT); 2609 // fold (sra x, 0) -> x 2610 if (N1C && N1C->isNullValue()) 2611 return N0; 2612 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2613 // sext_inreg. 2614 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2615 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2616 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2617 if (VT.isVector()) 2618 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2619 ExtVT, VT.getVectorNumElements()); 2620 if ((!LegalOperations || 2621 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2622 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2623 N0.getOperand(0), DAG.getValueType(ExtVT)); 2624 } 2625 2626 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2627 if (N1C && N0.getOpcode() == ISD::SRA) { 2628 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2629 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2630 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2631 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2632 DAG.getConstant(Sum, N1C->getValueType(0))); 2633 } 2634 } 2635 2636 // fold (sra (shl X, m), (sub result_size, n)) 2637 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2638 // result_size - n != m. 2639 // If truncate is free for the target sext(shl) is likely to result in better 2640 // code. 2641 if (N0.getOpcode() == ISD::SHL) { 2642 // Get the two constanst of the shifts, CN0 = m, CN = n. 2643 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2644 if (N01C && N1C) { 2645 // Determine what the truncate's result bitsize and type would be. 2646 EVT TruncVT = 2647 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2648 // Determine the residual right-shift amount. 2649 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2650 2651 // If the shift is not a no-op (in which case this should be just a sign 2652 // extend already), the truncated to type is legal, sign_extend is legal 2653 // on that type, and the truncate to that type is both legal and free, 2654 // perform the transform. 2655 if ((ShiftAmt > 0) && 2656 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2657 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2658 TLI.isTruncateFree(VT, TruncVT)) { 2659 2660 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2661 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2662 N0.getOperand(0), Amt); 2663 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2664 Shift); 2665 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2666 N->getValueType(0), Trunc); 2667 } 2668 } 2669 } 2670 2671 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2672 if (N1.getOpcode() == ISD::TRUNCATE && 2673 N1.getOperand(0).getOpcode() == ISD::AND && 2674 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2675 SDValue N101 = N1.getOperand(0).getOperand(1); 2676 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2677 EVT TruncVT = N1.getValueType(); 2678 SDValue N100 = N1.getOperand(0).getOperand(0); 2679 APInt TruncC = N101C->getAPIntValue(); 2680 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 2681 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2682 DAG.getNode(ISD::AND, N->getDebugLoc(), 2683 TruncVT, 2684 DAG.getNode(ISD::TRUNCATE, 2685 N->getDebugLoc(), 2686 TruncVT, N100), 2687 DAG.getConstant(TruncC, TruncVT))); 2688 } 2689 } 2690 2691 // Simplify, based on bits shifted out of the LHS. 2692 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2693 return SDValue(N, 0); 2694 2695 2696 // If the sign bit is known to be zero, switch this to a SRL. 2697 if (DAG.SignBitIsZero(N0)) 2698 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2699 2700 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2701} 2702 2703SDValue DAGCombiner::visitSRL(SDNode *N) { 2704 SDValue N0 = N->getOperand(0); 2705 SDValue N1 = N->getOperand(1); 2706 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2707 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2708 EVT VT = N0.getValueType(); 2709 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2710 2711 // fold (srl c1, c2) -> c1 >>u c2 2712 if (N0C && N1C) 2713 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2714 // fold (srl 0, x) -> 0 2715 if (N0C && N0C->isNullValue()) 2716 return N0; 2717 // fold (srl x, c >= size(x)) -> undef 2718 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2719 return DAG.getUNDEF(VT); 2720 // fold (srl x, 0) -> x 2721 if (N1C && N1C->isNullValue()) 2722 return N0; 2723 // if (srl x, c) is known to be zero, return 0 2724 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2725 APInt::getAllOnesValue(OpSizeInBits))) 2726 return DAG.getConstant(0, VT); 2727 2728 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2729 if (N1C && N0.getOpcode() == ISD::SRL && 2730 N0.getOperand(1).getOpcode() == ISD::Constant) { 2731 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2732 uint64_t c2 = N1C->getZExtValue(); 2733 if (c1 + c2 > OpSizeInBits) 2734 return DAG.getConstant(0, VT); 2735 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2736 DAG.getConstant(c1 + c2, N1.getValueType())); 2737 } 2738 2739 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2740 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2741 // Shifting in all undef bits? 2742 EVT SmallVT = N0.getOperand(0).getValueType(); 2743 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2744 return DAG.getUNDEF(VT); 2745 2746 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2747 N0.getOperand(0), N1); 2748 AddToWorkList(SmallShift.getNode()); 2749 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2750 } 2751 2752 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2753 // bit, which is unmodified by sra. 2754 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2755 if (N0.getOpcode() == ISD::SRA) 2756 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2757 } 2758 2759 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2760 if (N1C && N0.getOpcode() == ISD::CTLZ && 2761 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2762 APInt KnownZero, KnownOne; 2763 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 2764 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2765 2766 // If any of the input bits are KnownOne, then the input couldn't be all 2767 // zeros, thus the result of the srl will always be zero. 2768 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2769 2770 // If all of the bits input the to ctlz node are known to be zero, then 2771 // the result of the ctlz is "32" and the result of the shift is one. 2772 APInt UnknownBits = ~KnownZero & Mask; 2773 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2774 2775 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2776 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2777 // Okay, we know that only that the single bit specified by UnknownBits 2778 // could be set on input to the CTLZ node. If this bit is set, the SRL 2779 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2780 // to an SRL/XOR pair, which is likely to simplify more. 2781 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2782 SDValue Op = N0.getOperand(0); 2783 2784 if (ShAmt) { 2785 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2786 DAG.getConstant(ShAmt, getShiftAmountTy())); 2787 AddToWorkList(Op.getNode()); 2788 } 2789 2790 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2791 Op, DAG.getConstant(1, VT)); 2792 } 2793 } 2794 2795 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2796 if (N1.getOpcode() == ISD::TRUNCATE && 2797 N1.getOperand(0).getOpcode() == ISD::AND && 2798 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2799 SDValue N101 = N1.getOperand(0).getOperand(1); 2800 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2801 EVT TruncVT = N1.getValueType(); 2802 SDValue N100 = N1.getOperand(0).getOperand(0); 2803 APInt TruncC = N101C->getAPIntValue(); 2804 TruncC.trunc(TruncVT.getSizeInBits()); 2805 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2806 DAG.getNode(ISD::AND, N->getDebugLoc(), 2807 TruncVT, 2808 DAG.getNode(ISD::TRUNCATE, 2809 N->getDebugLoc(), 2810 TruncVT, N100), 2811 DAG.getConstant(TruncC, TruncVT))); 2812 } 2813 } 2814 2815 // fold operands of srl based on knowledge that the low bits are not 2816 // demanded. 2817 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2818 return SDValue(N, 0); 2819 2820 if (N1C) { 2821 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 2822 if (NewSRL.getNode()) 2823 return NewSRL; 2824 } 2825 2826 // Here is a common situation. We want to optimize: 2827 // 2828 // %a = ... 2829 // %b = and i32 %a, 2 2830 // %c = srl i32 %b, 1 2831 // brcond i32 %c ... 2832 // 2833 // into 2834 // 2835 // %a = ... 2836 // %b = and %a, 2 2837 // %c = setcc eq %b, 0 2838 // brcond %c ... 2839 // 2840 // However when after the source operand of SRL is optimized into AND, the SRL 2841 // itself may not be optimized further. Look for it and add the BRCOND into 2842 // the worklist. 2843 if (N->hasOneUse()) { 2844 SDNode *Use = *N->use_begin(); 2845 if (Use->getOpcode() == ISD::BRCOND) 2846 AddToWorkList(Use); 2847 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 2848 // Also look pass the truncate. 2849 Use = *Use->use_begin(); 2850 if (Use->getOpcode() == ISD::BRCOND) 2851 AddToWorkList(Use); 2852 } 2853 } 2854 2855 return SDValue(); 2856} 2857 2858SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2859 SDValue N0 = N->getOperand(0); 2860 EVT VT = N->getValueType(0); 2861 2862 // fold (ctlz c1) -> c2 2863 if (isa<ConstantSDNode>(N0)) 2864 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2865 return SDValue(); 2866} 2867 2868SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2869 SDValue N0 = N->getOperand(0); 2870 EVT VT = N->getValueType(0); 2871 2872 // fold (cttz c1) -> c2 2873 if (isa<ConstantSDNode>(N0)) 2874 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2875 return SDValue(); 2876} 2877 2878SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2879 SDValue N0 = N->getOperand(0); 2880 EVT VT = N->getValueType(0); 2881 2882 // fold (ctpop c1) -> c2 2883 if (isa<ConstantSDNode>(N0)) 2884 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2885 return SDValue(); 2886} 2887 2888SDValue DAGCombiner::visitSELECT(SDNode *N) { 2889 SDValue N0 = N->getOperand(0); 2890 SDValue N1 = N->getOperand(1); 2891 SDValue N2 = N->getOperand(2); 2892 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2893 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2894 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2895 EVT VT = N->getValueType(0); 2896 EVT VT0 = N0.getValueType(); 2897 2898 // fold (select C, X, X) -> X 2899 if (N1 == N2) 2900 return N1; 2901 // fold (select true, X, Y) -> X 2902 if (N0C && !N0C->isNullValue()) 2903 return N1; 2904 // fold (select false, X, Y) -> Y 2905 if (N0C && N0C->isNullValue()) 2906 return N2; 2907 // fold (select C, 1, X) -> (or C, X) 2908 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2909 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2910 // fold (select C, 0, 1) -> (xor C, 1) 2911 if (VT.isInteger() && 2912 (VT0 == MVT::i1 || 2913 (VT0.isInteger() && 2914 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2915 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2916 SDValue XORNode; 2917 if (VT == VT0) 2918 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2919 N0, DAG.getConstant(1, VT0)); 2920 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2921 N0, DAG.getConstant(1, VT0)); 2922 AddToWorkList(XORNode.getNode()); 2923 if (VT.bitsGT(VT0)) 2924 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2925 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2926 } 2927 // fold (select C, 0, X) -> (and (not C), X) 2928 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2929 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2930 AddToWorkList(NOTNode.getNode()); 2931 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2932 } 2933 // fold (select C, X, 1) -> (or (not C), X) 2934 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2935 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2936 AddToWorkList(NOTNode.getNode()); 2937 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2938 } 2939 // fold (select C, X, 0) -> (and C, X) 2940 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2941 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2942 // fold (select X, X, Y) -> (or X, Y) 2943 // fold (select X, 1, Y) -> (or X, Y) 2944 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2945 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2946 // fold (select X, Y, X) -> (and X, Y) 2947 // fold (select X, Y, 0) -> (and X, Y) 2948 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2949 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2950 2951 // If we can fold this based on the true/false value, do so. 2952 if (SimplifySelectOps(N, N1, N2)) 2953 return SDValue(N, 0); // Don't revisit N. 2954 2955 // fold selects based on a setcc into other things, such as min/max/abs 2956 if (N0.getOpcode() == ISD::SETCC) { 2957 // FIXME: 2958 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2959 // having to say they don't support SELECT_CC on every type the DAG knows 2960 // about, since there is no way to mark an opcode illegal at all value types 2961 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2962 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2963 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2964 N0.getOperand(0), N0.getOperand(1), 2965 N1, N2, N0.getOperand(2)); 2966 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2967 } 2968 2969 return SDValue(); 2970} 2971 2972SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2973 SDValue N0 = N->getOperand(0); 2974 SDValue N1 = N->getOperand(1); 2975 SDValue N2 = N->getOperand(2); 2976 SDValue N3 = N->getOperand(3); 2977 SDValue N4 = N->getOperand(4); 2978 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2979 2980 // fold select_cc lhs, rhs, x, x, cc -> x 2981 if (N2 == N3) 2982 return N2; 2983 2984 // Determine if the condition we're dealing with is constant 2985 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2986 N0, N1, CC, N->getDebugLoc(), false); 2987 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2988 2989 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2990 if (!SCCC->isNullValue()) 2991 return N2; // cond always true -> true val 2992 else 2993 return N3; // cond always false -> false val 2994 } 2995 2996 // Fold to a simpler select_cc 2997 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2998 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2999 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3000 SCC.getOperand(2)); 3001 3002 // If we can fold this based on the true/false value, do so. 3003 if (SimplifySelectOps(N, N2, N3)) 3004 return SDValue(N, 0); // Don't revisit N. 3005 3006 // fold select_cc into other things, such as min/max/abs 3007 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3008} 3009 3010SDValue DAGCombiner::visitSETCC(SDNode *N) { 3011 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3012 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3013 N->getDebugLoc()); 3014} 3015 3016// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3017// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3018// transformation. Returns true if extension are possible and the above 3019// mentioned transformation is profitable. 3020static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3021 unsigned ExtOpc, 3022 SmallVector<SDNode*, 4> &ExtendNodes, 3023 const TargetLowering &TLI) { 3024 bool HasCopyToRegUses = false; 3025 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3026 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3027 UE = N0.getNode()->use_end(); 3028 UI != UE; ++UI) { 3029 SDNode *User = *UI; 3030 if (User == N) 3031 continue; 3032 if (UI.getUse().getResNo() != N0.getResNo()) 3033 continue; 3034 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3035 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3036 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3037 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3038 // Sign bits will be lost after a zext. 3039 return false; 3040 bool Add = false; 3041 for (unsigned i = 0; i != 2; ++i) { 3042 SDValue UseOp = User->getOperand(i); 3043 if (UseOp == N0) 3044 continue; 3045 if (!isa<ConstantSDNode>(UseOp)) 3046 return false; 3047 Add = true; 3048 } 3049 if (Add) 3050 ExtendNodes.push_back(User); 3051 continue; 3052 } 3053 // If truncates aren't free and there are users we can't 3054 // extend, it isn't worthwhile. 3055 if (!isTruncFree) 3056 return false; 3057 // Remember if this value is live-out. 3058 if (User->getOpcode() == ISD::CopyToReg) 3059 HasCopyToRegUses = true; 3060 } 3061 3062 if (HasCopyToRegUses) { 3063 bool BothLiveOut = false; 3064 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3065 UI != UE; ++UI) { 3066 SDUse &Use = UI.getUse(); 3067 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3068 BothLiveOut = true; 3069 break; 3070 } 3071 } 3072 if (BothLiveOut) 3073 // Both unextended and extended values are live out. There had better be 3074 // good a reason for the transformation. 3075 return ExtendNodes.size(); 3076 } 3077 return true; 3078} 3079 3080SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3081 SDValue N0 = N->getOperand(0); 3082 EVT VT = N->getValueType(0); 3083 3084 // fold (sext c1) -> c1 3085 if (isa<ConstantSDNode>(N0)) 3086 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3087 3088 // fold (sext (sext x)) -> (sext x) 3089 // fold (sext (aext x)) -> (sext x) 3090 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3091 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3092 N0.getOperand(0)); 3093 3094 if (N0.getOpcode() == ISD::TRUNCATE) { 3095 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3096 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3097 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3098 if (NarrowLoad.getNode()) { 3099 if (NarrowLoad.getNode() != N0.getNode()) 3100 CombineTo(N0.getNode(), NarrowLoad); 3101 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3102 } 3103 3104 // See if the value being truncated is already sign extended. If so, just 3105 // eliminate the trunc/sext pair. 3106 SDValue Op = N0.getOperand(0); 3107 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3108 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3109 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3110 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3111 3112 if (OpBits == DestBits) { 3113 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3114 // bits, it is already ready. 3115 if (NumSignBits > DestBits-MidBits) 3116 return Op; 3117 } else if (OpBits < DestBits) { 3118 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3119 // bits, just sext from i32. 3120 if (NumSignBits > OpBits-MidBits) 3121 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3122 } else { 3123 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3124 // bits, just truncate to i32. 3125 if (NumSignBits > OpBits-MidBits) 3126 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3127 } 3128 3129 // fold (sext (truncate x)) -> (sextinreg x). 3130 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3131 N0.getValueType())) { 3132 if (OpBits < DestBits) 3133 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3134 else if (OpBits > DestBits) 3135 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3136 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3137 DAG.getValueType(N0.getValueType())); 3138 } 3139 } 3140 3141 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3142 if (ISD::isNON_EXTLoad(N0.getNode()) && 3143 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3144 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3145 bool DoXform = true; 3146 SmallVector<SDNode*, 4> SetCCs; 3147 if (!N0.hasOneUse()) 3148 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3149 if (DoXform) { 3150 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3151 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3152 LN0->getChain(), 3153 LN0->getBasePtr(), LN0->getSrcValue(), 3154 LN0->getSrcValueOffset(), 3155 N0.getValueType(), 3156 LN0->isVolatile(), LN0->isNonTemporal(), 3157 LN0->getAlignment()); 3158 CombineTo(N, ExtLoad); 3159 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3160 N0.getValueType(), ExtLoad); 3161 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3162 3163 // Extend SetCC uses if necessary. 3164 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3165 SDNode *SetCC = SetCCs[i]; 3166 SmallVector<SDValue, 4> Ops; 3167 3168 for (unsigned j = 0; j != 2; ++j) { 3169 SDValue SOp = SetCC->getOperand(j); 3170 if (SOp == Trunc) 3171 Ops.push_back(ExtLoad); 3172 else 3173 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3174 N->getDebugLoc(), VT, SOp)); 3175 } 3176 3177 Ops.push_back(SetCC->getOperand(2)); 3178 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3179 SetCC->getValueType(0), 3180 &Ops[0], Ops.size())); 3181 } 3182 3183 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3184 } 3185 } 3186 3187 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3188 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3189 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3190 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3191 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3192 EVT MemVT = LN0->getMemoryVT(); 3193 if ((!LegalOperations && !LN0->isVolatile()) || 3194 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3195 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3196 LN0->getChain(), 3197 LN0->getBasePtr(), LN0->getSrcValue(), 3198 LN0->getSrcValueOffset(), MemVT, 3199 LN0->isVolatile(), LN0->isNonTemporal(), 3200 LN0->getAlignment()); 3201 CombineTo(N, ExtLoad); 3202 CombineTo(N0.getNode(), 3203 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3204 N0.getValueType(), ExtLoad), 3205 ExtLoad.getValue(1)); 3206 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3207 } 3208 } 3209 3210 if (N0.getOpcode() == ISD::SETCC) { 3211 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3212 if (VT.isVector() && 3213 // We know that the # elements of the results is the same as the 3214 // # elements of the compare (and the # elements of the compare result 3215 // for that matter). Check to see that they are the same size. If so, 3216 // we know that the element size of the sext'd result matches the 3217 // element size of the compare operands. 3218 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3219 3220 // Only do this before legalize for now. 3221 !LegalOperations) { 3222 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3223 N0.getOperand(1), 3224 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3225 } 3226 3227 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3228 SDValue NegOne = 3229 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3230 SDValue SCC = 3231 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3232 NegOne, DAG.getConstant(0, VT), 3233 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3234 if (SCC.getNode()) return SCC; 3235 if (!LegalOperations || 3236 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3237 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3238 DAG.getSetCC(N->getDebugLoc(), 3239 TLI.getSetCCResultType(VT), 3240 N0.getOperand(0), N0.getOperand(1), 3241 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3242 NegOne, DAG.getConstant(0, VT)); 3243 } 3244 3245 3246 3247 // fold (sext x) -> (zext x) if the sign bit is known zero. 3248 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3249 DAG.SignBitIsZero(N0)) 3250 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3251 3252 return SDValue(); 3253} 3254 3255SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3256 SDValue N0 = N->getOperand(0); 3257 EVT VT = N->getValueType(0); 3258 3259 // fold (zext c1) -> c1 3260 if (isa<ConstantSDNode>(N0)) 3261 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3262 // fold (zext (zext x)) -> (zext x) 3263 // fold (zext (aext x)) -> (zext x) 3264 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3265 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3266 N0.getOperand(0)); 3267 3268 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3269 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3270 if (N0.getOpcode() == ISD::TRUNCATE) { 3271 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3272 if (NarrowLoad.getNode()) { 3273 if (NarrowLoad.getNode() != N0.getNode()) 3274 CombineTo(N0.getNode(), NarrowLoad); 3275 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3276 } 3277 } 3278 3279 // fold (zext (truncate x)) -> (and x, mask) 3280 if (N0.getOpcode() == ISD::TRUNCATE && 3281 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) && 3282 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(), 3283 N0.getValueType()) || 3284 !TLI.isZExtFree(N0.getValueType(), VT))) { 3285 SDValue Op = N0.getOperand(0); 3286 if (Op.getValueType().bitsLT(VT)) { 3287 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3288 } else if (Op.getValueType().bitsGT(VT)) { 3289 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3290 } 3291 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3292 N0.getValueType().getScalarType()); 3293 } 3294 3295 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3296 // if either of the casts is not free. 3297 if (N0.getOpcode() == ISD::AND && 3298 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3299 N0.getOperand(1).getOpcode() == ISD::Constant && 3300 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3301 N0.getValueType()) || 3302 !TLI.isZExtFree(N0.getValueType(), VT))) { 3303 SDValue X = N0.getOperand(0).getOperand(0); 3304 if (X.getValueType().bitsLT(VT)) { 3305 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3306 } else if (X.getValueType().bitsGT(VT)) { 3307 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3308 } 3309 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3310 Mask.zext(VT.getSizeInBits()); 3311 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3312 X, DAG.getConstant(Mask, VT)); 3313 } 3314 3315 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3316 if (ISD::isNON_EXTLoad(N0.getNode()) && 3317 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3318 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3319 bool DoXform = true; 3320 SmallVector<SDNode*, 4> SetCCs; 3321 if (!N0.hasOneUse()) 3322 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3323 if (DoXform) { 3324 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3325 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3326 LN0->getChain(), 3327 LN0->getBasePtr(), LN0->getSrcValue(), 3328 LN0->getSrcValueOffset(), 3329 N0.getValueType(), 3330 LN0->isVolatile(), LN0->isNonTemporal(), 3331 LN0->getAlignment()); 3332 CombineTo(N, ExtLoad); 3333 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3334 N0.getValueType(), ExtLoad); 3335 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3336 3337 // Extend SetCC uses if necessary. 3338 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3339 SDNode *SetCC = SetCCs[i]; 3340 SmallVector<SDValue, 4> Ops; 3341 3342 for (unsigned j = 0; j != 2; ++j) { 3343 SDValue SOp = SetCC->getOperand(j); 3344 if (SOp == Trunc) 3345 Ops.push_back(ExtLoad); 3346 else 3347 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3348 N->getDebugLoc(), VT, SOp)); 3349 } 3350 3351 Ops.push_back(SetCC->getOperand(2)); 3352 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3353 SetCC->getValueType(0), 3354 &Ops[0], Ops.size())); 3355 } 3356 3357 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3358 } 3359 } 3360 3361 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3362 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3363 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3364 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3365 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3366 EVT MemVT = LN0->getMemoryVT(); 3367 if ((!LegalOperations && !LN0->isVolatile()) || 3368 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3369 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3370 LN0->getChain(), 3371 LN0->getBasePtr(), LN0->getSrcValue(), 3372 LN0->getSrcValueOffset(), MemVT, 3373 LN0->isVolatile(), LN0->isNonTemporal(), 3374 LN0->getAlignment()); 3375 CombineTo(N, ExtLoad); 3376 CombineTo(N0.getNode(), 3377 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3378 ExtLoad), 3379 ExtLoad.getValue(1)); 3380 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3381 } 3382 } 3383 3384 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3385 if (N0.getOpcode() == ISD::SETCC) { 3386 SDValue SCC = 3387 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3388 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3389 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3390 if (SCC.getNode()) return SCC; 3391 } 3392 3393 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3394 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3395 isa<ConstantSDNode>(N0.getOperand(1)) && 3396 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3397 N0.hasOneUse()) { 3398 if (N0.getOpcode() == ISD::SHL) { 3399 // If the original shl may be shifting out bits, do not perform this 3400 // transformation. 3401 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3402 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3403 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3404 if (ShAmt > KnownZeroBits) 3405 return SDValue(); 3406 } 3407 DebugLoc dl = N->getDebugLoc(); 3408 return DAG.getNode(N0.getOpcode(), dl, VT, 3409 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3410 DAG.getNode(ISD::ZERO_EXTEND, dl, 3411 N0.getOperand(1).getValueType(), 3412 N0.getOperand(1))); 3413 } 3414 3415 return SDValue(); 3416} 3417 3418SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3419 SDValue N0 = N->getOperand(0); 3420 EVT VT = N->getValueType(0); 3421 3422 // fold (aext c1) -> c1 3423 if (isa<ConstantSDNode>(N0)) 3424 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3425 // fold (aext (aext x)) -> (aext x) 3426 // fold (aext (zext x)) -> (zext x) 3427 // fold (aext (sext x)) -> (sext x) 3428 if (N0.getOpcode() == ISD::ANY_EXTEND || 3429 N0.getOpcode() == ISD::ZERO_EXTEND || 3430 N0.getOpcode() == ISD::SIGN_EXTEND) 3431 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3432 3433 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3434 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3435 if (N0.getOpcode() == ISD::TRUNCATE) { 3436 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3437 if (NarrowLoad.getNode()) { 3438 if (NarrowLoad.getNode() != N0.getNode()) 3439 CombineTo(N0.getNode(), NarrowLoad); 3440 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3441 } 3442 } 3443 3444 // fold (aext (truncate x)) 3445 if (N0.getOpcode() == ISD::TRUNCATE) { 3446 SDValue TruncOp = N0.getOperand(0); 3447 if (TruncOp.getValueType() == VT) 3448 return TruncOp; // x iff x size == zext size. 3449 if (TruncOp.getValueType().bitsGT(VT)) 3450 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3451 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3452 } 3453 3454 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3455 // if the trunc is not free. 3456 if (N0.getOpcode() == ISD::AND && 3457 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3458 N0.getOperand(1).getOpcode() == ISD::Constant && 3459 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3460 N0.getValueType())) { 3461 SDValue X = N0.getOperand(0).getOperand(0); 3462 if (X.getValueType().bitsLT(VT)) { 3463 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3464 } else if (X.getValueType().bitsGT(VT)) { 3465 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3466 } 3467 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3468 Mask.zext(VT.getSizeInBits()); 3469 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3470 X, DAG.getConstant(Mask, VT)); 3471 } 3472 3473 // fold (aext (load x)) -> (aext (truncate (extload x))) 3474 if (ISD::isNON_EXTLoad(N0.getNode()) && 3475 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3476 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3477 bool DoXform = true; 3478 SmallVector<SDNode*, 4> SetCCs; 3479 if (!N0.hasOneUse()) 3480 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3481 if (DoXform) { 3482 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3483 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3484 LN0->getChain(), 3485 LN0->getBasePtr(), LN0->getSrcValue(), 3486 LN0->getSrcValueOffset(), 3487 N0.getValueType(), 3488 LN0->isVolatile(), LN0->isNonTemporal(), 3489 LN0->getAlignment()); 3490 CombineTo(N, ExtLoad); 3491 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3492 N0.getValueType(), ExtLoad); 3493 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3494 3495 // Extend SetCC uses if necessary. 3496 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3497 SDNode *SetCC = SetCCs[i]; 3498 SmallVector<SDValue, 4> Ops; 3499 3500 for (unsigned j = 0; j != 2; ++j) { 3501 SDValue SOp = SetCC->getOperand(j); 3502 if (SOp == Trunc) 3503 Ops.push_back(ExtLoad); 3504 else 3505 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3506 N->getDebugLoc(), VT, SOp)); 3507 } 3508 3509 Ops.push_back(SetCC->getOperand(2)); 3510 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3511 SetCC->getValueType(0), 3512 &Ops[0], Ops.size())); 3513 } 3514 3515 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3516 } 3517 } 3518 3519 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3520 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3521 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3522 if (N0.getOpcode() == ISD::LOAD && 3523 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3524 N0.hasOneUse()) { 3525 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3526 EVT MemVT = LN0->getMemoryVT(); 3527 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3528 VT, LN0->getChain(), LN0->getBasePtr(), 3529 LN0->getSrcValue(), 3530 LN0->getSrcValueOffset(), MemVT, 3531 LN0->isVolatile(), LN0->isNonTemporal(), 3532 LN0->getAlignment()); 3533 CombineTo(N, ExtLoad); 3534 CombineTo(N0.getNode(), 3535 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3536 N0.getValueType(), ExtLoad), 3537 ExtLoad.getValue(1)); 3538 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3539 } 3540 3541 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3542 if (N0.getOpcode() == ISD::SETCC) { 3543 SDValue SCC = 3544 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3545 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3546 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3547 if (SCC.getNode()) 3548 return SCC; 3549 } 3550 3551 return SDValue(); 3552} 3553 3554/// GetDemandedBits - See if the specified operand can be simplified with the 3555/// knowledge that only the bits specified by Mask are used. If so, return the 3556/// simpler operand, otherwise return a null SDValue. 3557SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3558 switch (V.getOpcode()) { 3559 default: break; 3560 case ISD::OR: 3561 case ISD::XOR: 3562 // If the LHS or RHS don't contribute bits to the or, drop them. 3563 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3564 return V.getOperand(1); 3565 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3566 return V.getOperand(0); 3567 break; 3568 case ISD::SRL: 3569 // Only look at single-use SRLs. 3570 if (!V.getNode()->hasOneUse()) 3571 break; 3572 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3573 // See if we can recursively simplify the LHS. 3574 unsigned Amt = RHSC->getZExtValue(); 3575 3576 // Watch out for shift count overflow though. 3577 if (Amt >= Mask.getBitWidth()) break; 3578 APInt NewMask = Mask << Amt; 3579 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3580 if (SimplifyLHS.getNode()) 3581 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3582 SimplifyLHS, V.getOperand(1)); 3583 } 3584 } 3585 return SDValue(); 3586} 3587 3588/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3589/// bits and then truncated to a narrower type and where N is a multiple 3590/// of number of bits of the narrower type, transform it to a narrower load 3591/// from address + N / num of bits of new type. If the result is to be 3592/// extended, also fold the extension to form a extending load. 3593SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3594 unsigned Opc = N->getOpcode(); 3595 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3596 SDValue N0 = N->getOperand(0); 3597 EVT VT = N->getValueType(0); 3598 EVT ExtVT = VT; 3599 3600 // This transformation isn't valid for vector loads. 3601 if (VT.isVector()) 3602 return SDValue(); 3603 3604 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 3605 // extended to VT. 3606 if (Opc == ISD::SIGN_EXTEND_INREG) { 3607 ExtType = ISD::SEXTLOAD; 3608 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3609 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 3610 return SDValue(); 3611 } 3612 3613 unsigned EVTBits = ExtVT.getSizeInBits(); 3614 unsigned ShAmt = 0; 3615 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 3616 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3617 ShAmt = N01->getZExtValue(); 3618 // Is the shift amount a multiple of size of VT? 3619 if ((ShAmt & (EVTBits-1)) == 0) { 3620 N0 = N0.getOperand(0); 3621 // Is the load width a multiple of size of VT? 3622 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 3623 return SDValue(); 3624 } 3625 } 3626 } 3627 3628 // Do not generate loads of non-round integer types since these can 3629 // be expensive (and would be wrong if the type is not byte sized). 3630 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 3631 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3632 // Do not change the width of a volatile load. 3633 !cast<LoadSDNode>(N0)->isVolatile()) { 3634 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3635 EVT PtrType = N0.getOperand(1).getValueType(); 3636 3637 // For big endian targets, we need to adjust the offset to the pointer to 3638 // load the correct bytes. 3639 if (TLI.isBigEndian()) { 3640 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3641 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 3642 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3643 } 3644 3645 uint64_t PtrOff = ShAmt / 8; 3646 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3647 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3648 PtrType, LN0->getBasePtr(), 3649 DAG.getConstant(PtrOff, PtrType)); 3650 AddToWorkList(NewPtr.getNode()); 3651 3652 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3653 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3654 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3655 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign) 3656 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3657 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3658 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 3659 NewAlign); 3660 3661 // Replace the old load's chain with the new load's chain. 3662 WorkListRemover DeadNodes(*this); 3663 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3664 &DeadNodes); 3665 3666 // Return the new loaded value. 3667 return Load; 3668 } 3669 3670 return SDValue(); 3671} 3672 3673SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3674 SDValue N0 = N->getOperand(0); 3675 SDValue N1 = N->getOperand(1); 3676 EVT VT = N->getValueType(0); 3677 EVT EVT = cast<VTSDNode>(N1)->getVT(); 3678 unsigned VTBits = VT.getScalarType().getSizeInBits(); 3679 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 3680 3681 // fold (sext_in_reg c1) -> c1 3682 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3683 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3684 3685 // If the input is already sign extended, just drop the extension. 3686 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 3687 return N0; 3688 3689 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3690 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3691 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3692 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3693 N0.getOperand(0), N1); 3694 } 3695 3696 // fold (sext_in_reg (sext x)) -> (sext x) 3697 // fold (sext_in_reg (aext x)) -> (sext x) 3698 // if x is small enough. 3699 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3700 SDValue N00 = N0.getOperand(0); 3701 if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits) 3702 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3703 } 3704 3705 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3706 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3707 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3708 3709 // fold operands of sext_in_reg based on knowledge that the top bits are not 3710 // demanded. 3711 if (SimplifyDemandedBits(SDValue(N, 0))) 3712 return SDValue(N, 0); 3713 3714 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3715 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3716 SDValue NarrowLoad = ReduceLoadWidth(N); 3717 if (NarrowLoad.getNode()) 3718 return NarrowLoad; 3719 3720 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3721 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3722 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3723 if (N0.getOpcode() == ISD::SRL) { 3724 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3725 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 3726 // We can turn this into an SRA iff the input to the SRL is already sign 3727 // extended enough. 3728 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3729 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3730 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3731 N0.getOperand(0), N0.getOperand(1)); 3732 } 3733 } 3734 3735 // fold (sext_inreg (extload x)) -> (sextload x) 3736 if (ISD::isEXTLoad(N0.getNode()) && 3737 ISD::isUNINDEXEDLoad(N0.getNode()) && 3738 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3739 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3740 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3741 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3742 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3743 LN0->getChain(), 3744 LN0->getBasePtr(), LN0->getSrcValue(), 3745 LN0->getSrcValueOffset(), EVT, 3746 LN0->isVolatile(), LN0->isNonTemporal(), 3747 LN0->getAlignment()); 3748 CombineTo(N, ExtLoad); 3749 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3750 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3751 } 3752 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3753 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3754 N0.hasOneUse() && 3755 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3756 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3757 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3758 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3759 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3760 LN0->getChain(), 3761 LN0->getBasePtr(), LN0->getSrcValue(), 3762 LN0->getSrcValueOffset(), EVT, 3763 LN0->isVolatile(), LN0->isNonTemporal(), 3764 LN0->getAlignment()); 3765 CombineTo(N, ExtLoad); 3766 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3767 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3768 } 3769 return SDValue(); 3770} 3771 3772SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3773 SDValue N0 = N->getOperand(0); 3774 EVT VT = N->getValueType(0); 3775 3776 // noop truncate 3777 if (N0.getValueType() == N->getValueType(0)) 3778 return N0; 3779 // fold (truncate c1) -> c1 3780 if (isa<ConstantSDNode>(N0)) 3781 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3782 // fold (truncate (truncate x)) -> (truncate x) 3783 if (N0.getOpcode() == ISD::TRUNCATE) 3784 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3785 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3786 if (N0.getOpcode() == ISD::ZERO_EXTEND || 3787 N0.getOpcode() == ISD::SIGN_EXTEND || 3788 N0.getOpcode() == ISD::ANY_EXTEND) { 3789 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3790 // if the source is smaller than the dest, we still need an extend 3791 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3792 N0.getOperand(0)); 3793 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3794 // if the source is larger than the dest, than we just need the truncate 3795 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3796 else 3797 // if the source and dest are the same type, we can drop both the extend 3798 // and the truncate. 3799 return N0.getOperand(0); 3800 } 3801 3802 // See if we can simplify the input to this truncate through knowledge that 3803 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3804 // -> trunc y 3805 SDValue Shorter = 3806 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3807 VT.getSizeInBits())); 3808 if (Shorter.getNode()) 3809 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3810 3811 // fold (truncate (load x)) -> (smaller load x) 3812 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3813 return ReduceLoadWidth(N); 3814} 3815 3816static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3817 SDValue Elt = N->getOperand(i); 3818 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3819 return Elt.getNode(); 3820 return Elt.getOperand(Elt.getResNo()).getNode(); 3821} 3822 3823/// CombineConsecutiveLoads - build_pair (load, load) -> load 3824/// if load locations are consecutive. 3825SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 3826 assert(N->getOpcode() == ISD::BUILD_PAIR); 3827 3828 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3829 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3830 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3831 return SDValue(); 3832 EVT LD1VT = LD1->getValueType(0); 3833 3834 if (ISD::isNON_EXTLoad(LD2) && 3835 LD2->hasOneUse() && 3836 // If both are volatile this would reduce the number of volatile loads. 3837 // If one is volatile it might be ok, but play conservative and bail out. 3838 !LD1->isVolatile() && 3839 !LD2->isVolatile() && 3840 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 3841 unsigned Align = LD1->getAlignment(); 3842 unsigned NewAlign = TLI.getTargetData()-> 3843 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3844 3845 if (NewAlign <= Align && 3846 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3847 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3848 LD1->getBasePtr(), LD1->getSrcValue(), 3849 LD1->getSrcValueOffset(), false, false, Align); 3850 } 3851 3852 return SDValue(); 3853} 3854 3855SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3856 SDValue N0 = N->getOperand(0); 3857 EVT VT = N->getValueType(0); 3858 3859 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3860 // Only do this before legalize, since afterward the target may be depending 3861 // on the bitconvert. 3862 // First check to see if this is all constant. 3863 if (!LegalTypes && 3864 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3865 VT.isVector()) { 3866 bool isSimple = true; 3867 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3868 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3869 N0.getOperand(i).getOpcode() != ISD::Constant && 3870 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3871 isSimple = false; 3872 break; 3873 } 3874 3875 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 3876 assert(!DestEltVT.isVector() && 3877 "Element type of vector ValueType must not be vector!"); 3878 if (isSimple) 3879 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3880 } 3881 3882 // If the input is a constant, let getNode fold it. 3883 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3884 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3885 if (Res.getNode() != N) { 3886 if (!LegalOperations || 3887 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 3888 return Res; 3889 3890 // Folding it resulted in an illegal node, and it's too late to 3891 // do that. Clean up the old node and forego the transformation. 3892 // Ideally this won't happen very often, because instcombine 3893 // and the earlier dagcombine runs (where illegal nodes are 3894 // permitted) should have folded most of them already. 3895 DAG.DeleteNode(Res.getNode()); 3896 } 3897 } 3898 3899 // (conv (conv x, t1), t2) -> (conv x, t2) 3900 if (N0.getOpcode() == ISD::BIT_CONVERT) 3901 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3902 N0.getOperand(0)); 3903 3904 // fold (conv (load x)) -> (load (conv*)x) 3905 // If the resultant load doesn't need a higher alignment than the original! 3906 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3907 // Do not change the width of a volatile load. 3908 !cast<LoadSDNode>(N0)->isVolatile() && 3909 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3910 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3911 unsigned Align = TLI.getTargetData()-> 3912 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3913 unsigned OrigAlign = LN0->getAlignment(); 3914 3915 if (Align <= OrigAlign) { 3916 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3917 LN0->getBasePtr(), 3918 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3919 LN0->isVolatile(), LN0->isNonTemporal(), 3920 OrigAlign); 3921 AddToWorkList(N); 3922 CombineTo(N0.getNode(), 3923 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3924 N0.getValueType(), Load), 3925 Load.getValue(1)); 3926 return Load; 3927 } 3928 } 3929 3930 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3931 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3932 // This often reduces constant pool loads. 3933 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3934 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3935 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3936 N0.getOperand(0)); 3937 AddToWorkList(NewConv.getNode()); 3938 3939 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3940 if (N0.getOpcode() == ISD::FNEG) 3941 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3942 NewConv, DAG.getConstant(SignBit, VT)); 3943 assert(N0.getOpcode() == ISD::FABS); 3944 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3945 NewConv, DAG.getConstant(~SignBit, VT)); 3946 } 3947 3948 // fold (bitconvert (fcopysign cst, x)) -> 3949 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3950 // Note that we don't handle (copysign x, cst) because this can always be 3951 // folded to an fneg or fabs. 3952 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3953 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3954 VT.isInteger() && !VT.isVector()) { 3955 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3956 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 3957 if (isTypeLegal(IntXVT)) { 3958 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3959 IntXVT, N0.getOperand(1)); 3960 AddToWorkList(X.getNode()); 3961 3962 // If X has a different width than the result/lhs, sext it or truncate it. 3963 unsigned VTWidth = VT.getSizeInBits(); 3964 if (OrigXWidth < VTWidth) { 3965 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3966 AddToWorkList(X.getNode()); 3967 } else if (OrigXWidth > VTWidth) { 3968 // To get the sign bit in the right place, we have to shift it right 3969 // before truncating. 3970 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3971 X.getValueType(), X, 3972 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3973 AddToWorkList(X.getNode()); 3974 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3975 AddToWorkList(X.getNode()); 3976 } 3977 3978 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3979 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3980 X, DAG.getConstant(SignBit, VT)); 3981 AddToWorkList(X.getNode()); 3982 3983 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3984 VT, N0.getOperand(0)); 3985 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3986 Cst, DAG.getConstant(~SignBit, VT)); 3987 AddToWorkList(Cst.getNode()); 3988 3989 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3990 } 3991 } 3992 3993 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3994 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3995 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3996 if (CombineLD.getNode()) 3997 return CombineLD; 3998 } 3999 4000 return SDValue(); 4001} 4002 4003SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4004 EVT VT = N->getValueType(0); 4005 return CombineConsecutiveLoads(N, VT); 4006} 4007 4008/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 4009/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4010/// destination element value type. 4011SDValue DAGCombiner:: 4012ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4013 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4014 4015 // If this is already the right type, we're done. 4016 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4017 4018 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4019 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4020 4021 // If this is a conversion of N elements of one type to N elements of another 4022 // type, convert each element. This handles FP<->INT cases. 4023 if (SrcBitSize == DstBitSize) { 4024 SmallVector<SDValue, 8> Ops; 4025 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4026 SDValue Op = BV->getOperand(i); 4027 // If the vector element type is not legal, the BUILD_VECTOR operands 4028 // are promoted and implicitly truncated. Make that explicit here. 4029 if (Op.getValueType() != SrcEltVT) 4030 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4031 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 4032 DstEltVT, Op)); 4033 AddToWorkList(Ops.back().getNode()); 4034 } 4035 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4036 BV->getValueType(0).getVectorNumElements()); 4037 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4038 &Ops[0], Ops.size()); 4039 } 4040 4041 // Otherwise, we're growing or shrinking the elements. To avoid having to 4042 // handle annoying details of growing/shrinking FP values, we convert them to 4043 // int first. 4044 if (SrcEltVT.isFloatingPoint()) { 4045 // Convert the input float vector to a int vector where the elements are the 4046 // same sizes. 4047 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4048 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4049 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 4050 SrcEltVT = IntVT; 4051 } 4052 4053 // Now we know the input is an integer vector. If the output is a FP type, 4054 // convert to integer first, then to FP of the right size. 4055 if (DstEltVT.isFloatingPoint()) { 4056 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4057 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4058 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4059 4060 // Next, convert to FP elements of the same size. 4061 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4062 } 4063 4064 // Okay, we know the src/dst types are both integers of differing types. 4065 // Handling growing first. 4066 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4067 if (SrcBitSize < DstBitSize) { 4068 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4069 4070 SmallVector<SDValue, 8> Ops; 4071 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4072 i += NumInputsPerOutput) { 4073 bool isLE = TLI.isLittleEndian(); 4074 APInt NewBits = APInt(DstBitSize, 0); 4075 bool EltIsUndef = true; 4076 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4077 // Shift the previously computed bits over. 4078 NewBits <<= SrcBitSize; 4079 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4080 if (Op.getOpcode() == ISD::UNDEF) continue; 4081 EltIsUndef = false; 4082 4083 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4084 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4085 } 4086 4087 if (EltIsUndef) 4088 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4089 else 4090 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4091 } 4092 4093 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4094 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4095 &Ops[0], Ops.size()); 4096 } 4097 4098 // Finally, this must be the case where we are shrinking elements: each input 4099 // turns into multiple outputs. 4100 bool isS2V = ISD::isScalarToVector(BV); 4101 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4102 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4103 NumOutputsPerInput*BV->getNumOperands()); 4104 SmallVector<SDValue, 8> Ops; 4105 4106 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4107 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4108 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4109 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4110 continue; 4111 } 4112 4113 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4114 getAPIntValue()).zextOrTrunc(SrcBitSize); 4115 4116 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4117 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4118 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4119 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4120 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4121 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4122 Ops[0]); 4123 OpVal = OpVal.lshr(DstBitSize); 4124 } 4125 4126 // For big endian targets, swap the order of the pieces of each element. 4127 if (TLI.isBigEndian()) 4128 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4129 } 4130 4131 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4132 &Ops[0], Ops.size()); 4133} 4134 4135SDValue DAGCombiner::visitFADD(SDNode *N) { 4136 SDValue N0 = N->getOperand(0); 4137 SDValue N1 = N->getOperand(1); 4138 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4139 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4140 EVT VT = N->getValueType(0); 4141 4142 // fold vector ops 4143 if (VT.isVector()) { 4144 SDValue FoldedVOp = SimplifyVBinOp(N); 4145 if (FoldedVOp.getNode()) return FoldedVOp; 4146 } 4147 4148 // fold (fadd c1, c2) -> (fadd c1, c2) 4149 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4150 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4151 // canonicalize constant to RHS 4152 if (N0CFP && !N1CFP) 4153 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4154 // fold (fadd A, 0) -> A 4155 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4156 return N0; 4157 // fold (fadd A, (fneg B)) -> (fsub A, B) 4158 if (isNegatibleForFree(N1, LegalOperations) == 2) 4159 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4160 GetNegatedExpression(N1, DAG, LegalOperations)); 4161 // fold (fadd (fneg A), B) -> (fsub B, A) 4162 if (isNegatibleForFree(N0, LegalOperations) == 2) 4163 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4164 GetNegatedExpression(N0, DAG, LegalOperations)); 4165 4166 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4167 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4168 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4169 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4170 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4171 N0.getOperand(1), N1)); 4172 4173 return SDValue(); 4174} 4175 4176SDValue DAGCombiner::visitFSUB(SDNode *N) { 4177 SDValue N0 = N->getOperand(0); 4178 SDValue N1 = N->getOperand(1); 4179 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4180 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4181 EVT VT = N->getValueType(0); 4182 4183 // fold vector ops 4184 if (VT.isVector()) { 4185 SDValue FoldedVOp = SimplifyVBinOp(N); 4186 if (FoldedVOp.getNode()) return FoldedVOp; 4187 } 4188 4189 // fold (fsub c1, c2) -> c1-c2 4190 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4191 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4192 // fold (fsub A, 0) -> A 4193 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4194 return N0; 4195 // fold (fsub 0, B) -> -B 4196 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4197 if (isNegatibleForFree(N1, LegalOperations)) 4198 return GetNegatedExpression(N1, DAG, LegalOperations); 4199 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4200 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4201 } 4202 // fold (fsub A, (fneg B)) -> (fadd A, B) 4203 if (isNegatibleForFree(N1, LegalOperations)) 4204 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4205 GetNegatedExpression(N1, DAG, LegalOperations)); 4206 4207 return SDValue(); 4208} 4209 4210SDValue DAGCombiner::visitFMUL(SDNode *N) { 4211 SDValue N0 = N->getOperand(0); 4212 SDValue N1 = N->getOperand(1); 4213 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4214 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4215 EVT VT = N->getValueType(0); 4216 4217 // fold vector ops 4218 if (VT.isVector()) { 4219 SDValue FoldedVOp = SimplifyVBinOp(N); 4220 if (FoldedVOp.getNode()) return FoldedVOp; 4221 } 4222 4223 // fold (fmul c1, c2) -> c1*c2 4224 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4225 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4226 // canonicalize constant to RHS 4227 if (N0CFP && !N1CFP) 4228 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4229 // fold (fmul A, 0) -> 0 4230 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4231 return N1; 4232 // fold (fmul A, 0) -> 0, vector edition. 4233 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4234 return N1; 4235 // fold (fmul X, 2.0) -> (fadd X, X) 4236 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4237 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4238 // fold (fmul X, -1.0) -> (fneg X) 4239 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4240 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4241 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4242 4243 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4244 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4245 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4246 // Both can be negated for free, check to see if at least one is cheaper 4247 // negated. 4248 if (LHSNeg == 2 || RHSNeg == 2) 4249 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4250 GetNegatedExpression(N0, DAG, LegalOperations), 4251 GetNegatedExpression(N1, DAG, LegalOperations)); 4252 } 4253 } 4254 4255 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4256 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4257 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4258 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4259 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4260 N0.getOperand(1), N1)); 4261 4262 return SDValue(); 4263} 4264 4265SDValue DAGCombiner::visitFDIV(SDNode *N) { 4266 SDValue N0 = N->getOperand(0); 4267 SDValue N1 = N->getOperand(1); 4268 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4269 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4270 EVT VT = N->getValueType(0); 4271 4272 // fold vector ops 4273 if (VT.isVector()) { 4274 SDValue FoldedVOp = SimplifyVBinOp(N); 4275 if (FoldedVOp.getNode()) return FoldedVOp; 4276 } 4277 4278 // fold (fdiv c1, c2) -> c1/c2 4279 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4280 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4281 4282 4283 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4284 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4285 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4286 // Both can be negated for free, check to see if at least one is cheaper 4287 // negated. 4288 if (LHSNeg == 2 || RHSNeg == 2) 4289 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4290 GetNegatedExpression(N0, DAG, LegalOperations), 4291 GetNegatedExpression(N1, DAG, LegalOperations)); 4292 } 4293 } 4294 4295 return SDValue(); 4296} 4297 4298SDValue DAGCombiner::visitFREM(SDNode *N) { 4299 SDValue N0 = N->getOperand(0); 4300 SDValue N1 = N->getOperand(1); 4301 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4302 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4303 EVT VT = N->getValueType(0); 4304 4305 // fold (frem c1, c2) -> fmod(c1,c2) 4306 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4307 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4308 4309 return SDValue(); 4310} 4311 4312SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4313 SDValue N0 = N->getOperand(0); 4314 SDValue N1 = N->getOperand(1); 4315 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4316 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4317 EVT VT = N->getValueType(0); 4318 4319 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4320 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4321 4322 if (N1CFP) { 4323 const APFloat& V = N1CFP->getValueAPF(); 4324 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4325 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4326 if (!V.isNegative()) { 4327 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4328 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4329 } else { 4330 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4331 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4332 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4333 } 4334 } 4335 4336 // copysign(fabs(x), y) -> copysign(x, y) 4337 // copysign(fneg(x), y) -> copysign(x, y) 4338 // copysign(copysign(x,z), y) -> copysign(x, y) 4339 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4340 N0.getOpcode() == ISD::FCOPYSIGN) 4341 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4342 N0.getOperand(0), N1); 4343 4344 // copysign(x, abs(y)) -> abs(x) 4345 if (N1.getOpcode() == ISD::FABS) 4346 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4347 4348 // copysign(x, copysign(y,z)) -> copysign(x, z) 4349 if (N1.getOpcode() == ISD::FCOPYSIGN) 4350 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4351 N0, N1.getOperand(1)); 4352 4353 // copysign(x, fp_extend(y)) -> copysign(x, y) 4354 // copysign(x, fp_round(y)) -> copysign(x, y) 4355 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4356 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4357 N0, N1.getOperand(0)); 4358 4359 return SDValue(); 4360} 4361 4362SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4363 SDValue N0 = N->getOperand(0); 4364 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4365 EVT VT = N->getValueType(0); 4366 EVT OpVT = N0.getValueType(); 4367 4368 // fold (sint_to_fp c1) -> c1fp 4369 if (N0C && OpVT != MVT::ppcf128) 4370 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4371 4372 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4373 // but UINT_TO_FP is legal on this target, try to convert. 4374 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4375 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4376 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4377 if (DAG.SignBitIsZero(N0)) 4378 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4379 } 4380 4381 return SDValue(); 4382} 4383 4384SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4385 SDValue N0 = N->getOperand(0); 4386 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4387 EVT VT = N->getValueType(0); 4388 EVT OpVT = N0.getValueType(); 4389 4390 // fold (uint_to_fp c1) -> c1fp 4391 if (N0C && OpVT != MVT::ppcf128) 4392 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4393 4394 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4395 // but SINT_TO_FP is legal on this target, try to convert. 4396 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4397 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4398 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4399 if (DAG.SignBitIsZero(N0)) 4400 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4401 } 4402 4403 return SDValue(); 4404} 4405 4406SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4407 SDValue N0 = N->getOperand(0); 4408 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4409 EVT VT = N->getValueType(0); 4410 4411 // fold (fp_to_sint c1fp) -> c1 4412 if (N0CFP) 4413 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4414 4415 return SDValue(); 4416} 4417 4418SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4419 SDValue N0 = N->getOperand(0); 4420 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4421 EVT VT = N->getValueType(0); 4422 4423 // fold (fp_to_uint c1fp) -> c1 4424 if (N0CFP && VT != MVT::ppcf128) 4425 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4426 4427 return SDValue(); 4428} 4429 4430SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4431 SDValue N0 = N->getOperand(0); 4432 SDValue N1 = N->getOperand(1); 4433 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4434 EVT VT = N->getValueType(0); 4435 4436 // fold (fp_round c1fp) -> c1fp 4437 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4438 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4439 4440 // fold (fp_round (fp_extend x)) -> x 4441 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4442 return N0.getOperand(0); 4443 4444 // fold (fp_round (fp_round x)) -> (fp_round x) 4445 if (N0.getOpcode() == ISD::FP_ROUND) { 4446 // This is a value preserving truncation if both round's are. 4447 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4448 N0.getNode()->getConstantOperandVal(1) == 1; 4449 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4450 DAG.getIntPtrConstant(IsTrunc)); 4451 } 4452 4453 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4454 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4455 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4456 N0.getOperand(0), N1); 4457 AddToWorkList(Tmp.getNode()); 4458 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4459 Tmp, N0.getOperand(1)); 4460 } 4461 4462 return SDValue(); 4463} 4464 4465SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4466 SDValue N0 = N->getOperand(0); 4467 EVT VT = N->getValueType(0); 4468 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4469 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4470 4471 // fold (fp_round_inreg c1fp) -> c1fp 4472 if (N0CFP && isTypeLegal(EVT)) { 4473 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4474 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4475 } 4476 4477 return SDValue(); 4478} 4479 4480SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4481 SDValue N0 = N->getOperand(0); 4482 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4483 EVT VT = N->getValueType(0); 4484 4485 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4486 if (N->hasOneUse() && 4487 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4488 return SDValue(); 4489 4490 // fold (fp_extend c1fp) -> c1fp 4491 if (N0CFP && VT != MVT::ppcf128) 4492 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4493 4494 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4495 // value of X. 4496 if (N0.getOpcode() == ISD::FP_ROUND 4497 && N0.getNode()->getConstantOperandVal(1) == 1) { 4498 SDValue In = N0.getOperand(0); 4499 if (In.getValueType() == VT) return In; 4500 if (VT.bitsLT(In.getValueType())) 4501 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4502 In, N0.getOperand(1)); 4503 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4504 } 4505 4506 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4507 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4508 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4509 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4510 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4511 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4512 LN0->getChain(), 4513 LN0->getBasePtr(), LN0->getSrcValue(), 4514 LN0->getSrcValueOffset(), 4515 N0.getValueType(), 4516 LN0->isVolatile(), LN0->isNonTemporal(), 4517 LN0->getAlignment()); 4518 CombineTo(N, ExtLoad); 4519 CombineTo(N0.getNode(), 4520 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4521 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4522 ExtLoad.getValue(1)); 4523 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4524 } 4525 4526 return SDValue(); 4527} 4528 4529SDValue DAGCombiner::visitFNEG(SDNode *N) { 4530 SDValue N0 = N->getOperand(0); 4531 EVT VT = N->getValueType(0); 4532 4533 if (isNegatibleForFree(N0, LegalOperations)) 4534 return GetNegatedExpression(N0, DAG, LegalOperations); 4535 4536 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4537 // constant pool values. 4538 if (N0.getOpcode() == ISD::BIT_CONVERT && 4539 !VT.isVector() && 4540 N0.getNode()->hasOneUse() && 4541 N0.getOperand(0).getValueType().isInteger()) { 4542 SDValue Int = N0.getOperand(0); 4543 EVT IntVT = Int.getValueType(); 4544 if (IntVT.isInteger() && !IntVT.isVector()) { 4545 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4546 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4547 AddToWorkList(Int.getNode()); 4548 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4549 VT, Int); 4550 } 4551 } 4552 4553 return SDValue(); 4554} 4555 4556SDValue DAGCombiner::visitFABS(SDNode *N) { 4557 SDValue N0 = N->getOperand(0); 4558 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4559 EVT VT = N->getValueType(0); 4560 4561 // fold (fabs c1) -> fabs(c1) 4562 if (N0CFP && VT != MVT::ppcf128) 4563 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4564 // fold (fabs (fabs x)) -> (fabs x) 4565 if (N0.getOpcode() == ISD::FABS) 4566 return N->getOperand(0); 4567 // fold (fabs (fneg x)) -> (fabs x) 4568 // fold (fabs (fcopysign x, y)) -> (fabs x) 4569 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4570 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4571 4572 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4573 // constant pool values. 4574 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4575 N0.getOperand(0).getValueType().isInteger() && 4576 !N0.getOperand(0).getValueType().isVector()) { 4577 SDValue Int = N0.getOperand(0); 4578 EVT IntVT = Int.getValueType(); 4579 if (IntVT.isInteger() && !IntVT.isVector()) { 4580 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4581 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4582 AddToWorkList(Int.getNode()); 4583 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4584 N->getValueType(0), Int); 4585 } 4586 } 4587 4588 return SDValue(); 4589} 4590 4591SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4592 SDValue Chain = N->getOperand(0); 4593 SDValue N1 = N->getOperand(1); 4594 SDValue N2 = N->getOperand(2); 4595 4596 // If N is a constant we could fold this into a fallthrough or unconditional 4597 // branch. However that doesn't happen very often in normal code, because 4598 // Instcombine/SimplifyCFG should have handled the available opportunities. 4599 // If we did this folding here, it would be necessary to update the 4600 // MachineBasicBlock CFG, which is awkward. 4601 4602 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4603 // on the target. 4604 if (N1.getOpcode() == ISD::SETCC && 4605 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4606 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4607 Chain, N1.getOperand(2), 4608 N1.getOperand(0), N1.getOperand(1), N2); 4609 } 4610 4611 SDNode *Trunc = 0; 4612 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 4613 // Look past truncate. 4614 Trunc = N1.getNode(); 4615 N1 = N1.getOperand(0); 4616 } 4617 4618 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4619 // Match this pattern so that we can generate simpler code: 4620 // 4621 // %a = ... 4622 // %b = and i32 %a, 2 4623 // %c = srl i32 %b, 1 4624 // brcond i32 %c ... 4625 // 4626 // into 4627 // 4628 // %a = ... 4629 // %b = and i32 %a, 2 4630 // %c = setcc eq %b, 0 4631 // brcond %c ... 4632 // 4633 // This applies only when the AND constant value has one bit set and the 4634 // SRL constant is equal to the log2 of the AND constant. The back-end is 4635 // smart enough to convert the result into a TEST/JMP sequence. 4636 SDValue Op0 = N1.getOperand(0); 4637 SDValue Op1 = N1.getOperand(1); 4638 4639 if (Op0.getOpcode() == ISD::AND && 4640 Op1.getOpcode() == ISD::Constant) { 4641 SDValue AndOp1 = Op0.getOperand(1); 4642 4643 if (AndOp1.getOpcode() == ISD::Constant) { 4644 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4645 4646 if (AndConst.isPowerOf2() && 4647 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4648 SDValue SetCC = 4649 DAG.getSetCC(N->getDebugLoc(), 4650 TLI.getSetCCResultType(Op0.getValueType()), 4651 Op0, DAG.getConstant(0, Op0.getValueType()), 4652 ISD::SETNE); 4653 4654 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4655 MVT::Other, Chain, SetCC, N2); 4656 // Don't add the new BRCond into the worklist or else SimplifySelectCC 4657 // will convert it back to (X & C1) >> C2. 4658 CombineTo(N, NewBRCond, false); 4659 // Truncate is dead. 4660 if (Trunc) { 4661 removeFromWorkList(Trunc); 4662 DAG.DeleteNode(Trunc); 4663 } 4664 // Replace the uses of SRL with SETCC 4665 WorkListRemover DeadNodes(*this); 4666 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 4667 removeFromWorkList(N1.getNode()); 4668 DAG.DeleteNode(N1.getNode()); 4669 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4670 } 4671 } 4672 } 4673 } 4674 4675 // Transform br(xor(x, y)) -> br(x != y) 4676 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 4677 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 4678 SDNode *TheXor = N1.getNode(); 4679 SDValue Op0 = TheXor->getOperand(0); 4680 SDValue Op1 = TheXor->getOperand(1); 4681 if (Op0.getOpcode() == Op1.getOpcode()) { 4682 // Avoid missing important xor optimizations. 4683 SDValue Tmp = visitXOR(TheXor); 4684 if (Tmp.getNode()) { 4685 DEBUG(dbgs() << "\nReplacing.8 "; 4686 TheXor->dump(&DAG); 4687 dbgs() << "\nWith: "; 4688 Tmp.getNode()->dump(&DAG); 4689 dbgs() << '\n'); 4690 WorkListRemover DeadNodes(*this); 4691 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 4692 removeFromWorkList(TheXor); 4693 DAG.DeleteNode(TheXor); 4694 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4695 MVT::Other, Chain, Tmp, N2); 4696 } 4697 } 4698 4699 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 4700 bool Equal = false; 4701 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 4702 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 4703 Op0.getOpcode() == ISD::XOR) { 4704 TheXor = Op0.getNode(); 4705 Equal = true; 4706 } 4707 4708 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; 4709 4710 EVT SetCCVT = NodeToReplace.getValueType(); 4711 if (LegalTypes) 4712 SetCCVT = TLI.getSetCCResultType(SetCCVT); 4713 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 4714 SetCCVT, 4715 Op0, Op1, 4716 Equal ? ISD::SETEQ : ISD::SETNE); 4717 // Replace the uses of XOR with SETCC 4718 WorkListRemover DeadNodes(*this); 4719 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes); 4720 removeFromWorkList(NodeToReplace.getNode()); 4721 DAG.DeleteNode(NodeToReplace.getNode()); 4722 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4723 MVT::Other, Chain, SetCC, N2); 4724 } 4725 } 4726 4727 return SDValue(); 4728} 4729 4730// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4731// 4732SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4733 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4734 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4735 4736 // If N is a constant we could fold this into a fallthrough or unconditional 4737 // branch. However that doesn't happen very often in normal code, because 4738 // Instcombine/SimplifyCFG should have handled the available opportunities. 4739 // If we did this folding here, it would be necessary to update the 4740 // MachineBasicBlock CFG, which is awkward. 4741 4742 // Use SimplifySetCC to simplify SETCC's. 4743 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4744 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4745 false); 4746 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4747 4748 // fold to a simpler setcc 4749 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4750 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4751 N->getOperand(0), Simp.getOperand(2), 4752 Simp.getOperand(0), Simp.getOperand(1), 4753 N->getOperand(4)); 4754 4755 return SDValue(); 4756} 4757 4758/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4759/// pre-indexed load / store when the base pointer is an add or subtract 4760/// and it has other uses besides the load / store. After the 4761/// transformation, the new indexed load / store has effectively folded 4762/// the add / subtract in and all of its other uses are redirected to the 4763/// new load / store. 4764bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4765 if (!LegalOperations) 4766 return false; 4767 4768 bool isLoad = true; 4769 SDValue Ptr; 4770 EVT VT; 4771 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4772 if (LD->isIndexed()) 4773 return false; 4774 VT = LD->getMemoryVT(); 4775 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4776 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4777 return false; 4778 Ptr = LD->getBasePtr(); 4779 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4780 if (ST->isIndexed()) 4781 return false; 4782 VT = ST->getMemoryVT(); 4783 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4784 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4785 return false; 4786 Ptr = ST->getBasePtr(); 4787 isLoad = false; 4788 } else { 4789 return false; 4790 } 4791 4792 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4793 // out. There is no reason to make this a preinc/predec. 4794 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4795 Ptr.getNode()->hasOneUse()) 4796 return false; 4797 4798 // Ask the target to do addressing mode selection. 4799 SDValue BasePtr; 4800 SDValue Offset; 4801 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4802 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4803 return false; 4804 // Don't create a indexed load / store with zero offset. 4805 if (isa<ConstantSDNode>(Offset) && 4806 cast<ConstantSDNode>(Offset)->isNullValue()) 4807 return false; 4808 4809 // Try turning it into a pre-indexed load / store except when: 4810 // 1) The new base ptr is a frame index. 4811 // 2) If N is a store and the new base ptr is either the same as or is a 4812 // predecessor of the value being stored. 4813 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4814 // that would create a cycle. 4815 // 4) All uses are load / store ops that use it as old base ptr. 4816 4817 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4818 // (plus the implicit offset) to a register to preinc anyway. 4819 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4820 return false; 4821 4822 // Check #2. 4823 if (!isLoad) { 4824 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4825 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4826 return false; 4827 } 4828 4829 // Now check for #3 and #4. 4830 bool RealUse = false; 4831 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4832 E = Ptr.getNode()->use_end(); I != E; ++I) { 4833 SDNode *Use = *I; 4834 if (Use == N) 4835 continue; 4836 if (Use->isPredecessorOf(N)) 4837 return false; 4838 4839 if (!((Use->getOpcode() == ISD::LOAD && 4840 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4841 (Use->getOpcode() == ISD::STORE && 4842 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4843 RealUse = true; 4844 } 4845 4846 if (!RealUse) 4847 return false; 4848 4849 SDValue Result; 4850 if (isLoad) 4851 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4852 BasePtr, Offset, AM); 4853 else 4854 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4855 BasePtr, Offset, AM); 4856 ++PreIndexedNodes; 4857 ++NodesCombined; 4858 DEBUG(dbgs() << "\nReplacing.4 "; 4859 N->dump(&DAG); 4860 dbgs() << "\nWith: "; 4861 Result.getNode()->dump(&DAG); 4862 dbgs() << '\n'); 4863 WorkListRemover DeadNodes(*this); 4864 if (isLoad) { 4865 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4866 &DeadNodes); 4867 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4868 &DeadNodes); 4869 } else { 4870 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4871 &DeadNodes); 4872 } 4873 4874 // Finally, since the node is now dead, remove it from the graph. 4875 DAG.DeleteNode(N); 4876 4877 // Replace the uses of Ptr with uses of the updated base value. 4878 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4879 &DeadNodes); 4880 removeFromWorkList(Ptr.getNode()); 4881 DAG.DeleteNode(Ptr.getNode()); 4882 4883 return true; 4884} 4885 4886/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4887/// add / sub of the base pointer node into a post-indexed load / store. 4888/// The transformation folded the add / subtract into the new indexed 4889/// load / store effectively and all of its uses are redirected to the 4890/// new load / store. 4891bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4892 if (!LegalOperations) 4893 return false; 4894 4895 bool isLoad = true; 4896 SDValue Ptr; 4897 EVT VT; 4898 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4899 if (LD->isIndexed()) 4900 return false; 4901 VT = LD->getMemoryVT(); 4902 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4903 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4904 return false; 4905 Ptr = LD->getBasePtr(); 4906 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4907 if (ST->isIndexed()) 4908 return false; 4909 VT = ST->getMemoryVT(); 4910 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4911 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4912 return false; 4913 Ptr = ST->getBasePtr(); 4914 isLoad = false; 4915 } else { 4916 return false; 4917 } 4918 4919 if (Ptr.getNode()->hasOneUse()) 4920 return false; 4921 4922 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4923 E = Ptr.getNode()->use_end(); I != E; ++I) { 4924 SDNode *Op = *I; 4925 if (Op == N || 4926 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4927 continue; 4928 4929 SDValue BasePtr; 4930 SDValue Offset; 4931 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4932 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4933 if (Ptr == Offset && Op->getOpcode() == ISD::ADD) 4934 std::swap(BasePtr, Offset); 4935 if (Ptr != BasePtr) 4936 continue; 4937 // Don't create a indexed load / store with zero offset. 4938 if (isa<ConstantSDNode>(Offset) && 4939 cast<ConstantSDNode>(Offset)->isNullValue()) 4940 continue; 4941 4942 // Try turning it into a post-indexed load / store except when 4943 // 1) All uses are load / store ops that use it as base ptr. 4944 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4945 // nor a successor of N. Otherwise, if Op is folded that would 4946 // create a cycle. 4947 4948 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4949 continue; 4950 4951 // Check for #1. 4952 bool TryNext = false; 4953 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4954 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4955 SDNode *Use = *II; 4956 if (Use == Ptr.getNode()) 4957 continue; 4958 4959 // If all the uses are load / store addresses, then don't do the 4960 // transformation. 4961 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4962 bool RealUse = false; 4963 for (SDNode::use_iterator III = Use->use_begin(), 4964 EEE = Use->use_end(); III != EEE; ++III) { 4965 SDNode *UseUse = *III; 4966 if (!((UseUse->getOpcode() == ISD::LOAD && 4967 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4968 (UseUse->getOpcode() == ISD::STORE && 4969 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4970 RealUse = true; 4971 } 4972 4973 if (!RealUse) { 4974 TryNext = true; 4975 break; 4976 } 4977 } 4978 } 4979 4980 if (TryNext) 4981 continue; 4982 4983 // Check for #2 4984 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4985 SDValue Result = isLoad 4986 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4987 BasePtr, Offset, AM) 4988 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4989 BasePtr, Offset, AM); 4990 ++PostIndexedNodes; 4991 ++NodesCombined; 4992 DEBUG(dbgs() << "\nReplacing.5 "; 4993 N->dump(&DAG); 4994 dbgs() << "\nWith: "; 4995 Result.getNode()->dump(&DAG); 4996 dbgs() << '\n'); 4997 WorkListRemover DeadNodes(*this); 4998 if (isLoad) { 4999 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5000 &DeadNodes); 5001 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5002 &DeadNodes); 5003 } else { 5004 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5005 &DeadNodes); 5006 } 5007 5008 // Finally, since the node is now dead, remove it from the graph. 5009 DAG.DeleteNode(N); 5010 5011 // Replace the uses of Use with uses of the updated base value. 5012 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5013 Result.getValue(isLoad ? 1 : 0), 5014 &DeadNodes); 5015 removeFromWorkList(Op); 5016 DAG.DeleteNode(Op); 5017 return true; 5018 } 5019 } 5020 } 5021 5022 return false; 5023} 5024 5025SDValue DAGCombiner::visitLOAD(SDNode *N) { 5026 LoadSDNode *LD = cast<LoadSDNode>(N); 5027 SDValue Chain = LD->getChain(); 5028 SDValue Ptr = LD->getBasePtr(); 5029 5030 // If load is not volatile and there are no uses of the loaded value (and 5031 // the updated indexed value in case of indexed loads), change uses of the 5032 // chain value into uses of the chain input (i.e. delete the dead load). 5033 if (!LD->isVolatile()) { 5034 if (N->getValueType(1) == MVT::Other) { 5035 // Unindexed loads. 5036 if (N->hasNUsesOfValue(0, 0)) { 5037 // It's not safe to use the two value CombineTo variant here. e.g. 5038 // v1, chain2 = load chain1, loc 5039 // v2, chain3 = load chain2, loc 5040 // v3 = add v2, c 5041 // Now we replace use of chain2 with chain1. This makes the second load 5042 // isomorphic to the one we are deleting, and thus makes this load live. 5043 DEBUG(dbgs() << "\nReplacing.6 "; 5044 N->dump(&DAG); 5045 dbgs() << "\nWith chain: "; 5046 Chain.getNode()->dump(&DAG); 5047 dbgs() << "\n"); 5048 WorkListRemover DeadNodes(*this); 5049 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5050 5051 if (N->use_empty()) { 5052 removeFromWorkList(N); 5053 DAG.DeleteNode(N); 5054 } 5055 5056 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5057 } 5058 } else { 5059 // Indexed loads. 5060 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5061 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5062 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5063 DEBUG(dbgs() << "\nReplacing.7 "; 5064 N->dump(&DAG); 5065 dbgs() << "\nWith: "; 5066 Undef.getNode()->dump(&DAG); 5067 dbgs() << " and 2 other values\n"); 5068 WorkListRemover DeadNodes(*this); 5069 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5070 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5071 DAG.getUNDEF(N->getValueType(1)), 5072 &DeadNodes); 5073 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5074 removeFromWorkList(N); 5075 DAG.DeleteNode(N); 5076 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5077 } 5078 } 5079 } 5080 5081 // If this load is directly stored, replace the load value with the stored 5082 // value. 5083 // TODO: Handle store large -> read small portion. 5084 // TODO: Handle TRUNCSTORE/LOADEXT 5085 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5086 !LD->isVolatile()) { 5087 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5088 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5089 if (PrevST->getBasePtr() == Ptr && 5090 PrevST->getValue().getValueType() == N->getValueType(0)) 5091 return CombineTo(N, Chain.getOperand(1), Chain); 5092 } 5093 } 5094 5095 // Try to infer better alignment information than the load already has. 5096 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5097 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5098 if (Align > LD->getAlignment()) 5099 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5100 LD->getValueType(0), 5101 Chain, Ptr, LD->getSrcValue(), 5102 LD->getSrcValueOffset(), LD->getMemoryVT(), 5103 LD->isVolatile(), LD->isNonTemporal(), Align); 5104 } 5105 } 5106 5107 if (CombinerAA) { 5108 // Walk up chain skipping non-aliasing memory nodes. 5109 SDValue BetterChain = FindBetterChain(N, Chain); 5110 5111 // If there is a better chain. 5112 if (Chain != BetterChain) { 5113 SDValue ReplLoad; 5114 5115 // Replace the chain to void dependency. 5116 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5117 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5118 BetterChain, Ptr, 5119 LD->getSrcValue(), LD->getSrcValueOffset(), 5120 LD->isVolatile(), LD->isNonTemporal(), 5121 LD->getAlignment()); 5122 } else { 5123 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5124 LD->getValueType(0), 5125 BetterChain, Ptr, LD->getSrcValue(), 5126 LD->getSrcValueOffset(), 5127 LD->getMemoryVT(), 5128 LD->isVolatile(), 5129 LD->isNonTemporal(), 5130 LD->getAlignment()); 5131 } 5132 5133 // Create token factor to keep old chain connected. 5134 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5135 MVT::Other, Chain, ReplLoad.getValue(1)); 5136 5137 // Make sure the new and old chains are cleaned up. 5138 AddToWorkList(Token.getNode()); 5139 5140 // Replace uses with load result and token factor. Don't add users 5141 // to work list. 5142 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5143 } 5144 } 5145 5146 // Try transforming N to an indexed load. 5147 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5148 return SDValue(N, 0); 5149 5150 return SDValue(); 5151} 5152 5153/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5154/// load is having specific bytes cleared out. If so, return the byte size 5155/// being masked out and the shift amount. 5156static std::pair<unsigned, unsigned> 5157CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5158 std::pair<unsigned, unsigned> Result(0, 0); 5159 5160 // Check for the structure we're looking for. 5161 if (V->getOpcode() != ISD::AND || 5162 !isa<ConstantSDNode>(V->getOperand(1)) || 5163 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5164 return Result; 5165 5166 // Check the chain and pointer. The store should be chained directly to the 5167 // load (TODO: Or through a TF node!) since it's to the same address. 5168 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5169 if (LD->getBasePtr() != Ptr || 5170 V->getOperand(0).getNode() != Chain.getNode()) 5171 return Result; 5172 5173 // This only handles simple types. 5174 if (V.getValueType() != MVT::i16 && 5175 V.getValueType() != MVT::i32 && 5176 V.getValueType() != MVT::i64) 5177 return Result; 5178 5179 // Check the constant mask. Invert it so that the bits being masked out are 5180 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5181 // follow the sign bit for uniformity. 5182 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5183 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5184 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5185 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5186 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5187 if (NotMaskLZ == 64) return Result; // All zero mask. 5188 5189 // See if we have a continuous run of bits. If so, we have 0*1+0* 5190 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5191 return Result; 5192 5193 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5194 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5195 NotMaskLZ -= 64-V.getValueSizeInBits(); 5196 5197 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5198 switch (MaskedBytes) { 5199 case 1: 5200 case 2: 5201 case 4: break; 5202 default: return Result; // All one mask, or 5-byte mask. 5203 } 5204 5205 // Verify that the first bit starts at a multiple of mask so that the access 5206 // is aligned the same as the access width. 5207 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 5208 5209 Result.first = MaskedBytes; 5210 Result.second = NotMaskTZ/8; 5211 return Result; 5212} 5213 5214 5215/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 5216/// provides a value as specified by MaskInfo. If so, replace the specified 5217/// store with a narrower store of truncated IVal. 5218static SDNode * 5219ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 5220 SDValue IVal, StoreSDNode *St, 5221 DAGCombiner *DC) { 5222 unsigned NumBytes = MaskInfo.first; 5223 unsigned ByteShift = MaskInfo.second; 5224 SelectionDAG &DAG = DC->getDAG(); 5225 5226 // Check to see if IVal is all zeros in the part being masked in by the 'or' 5227 // that uses this. If not, this is not a replacement. 5228 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 5229 ByteShift*8, (ByteShift+NumBytes)*8); 5230 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 5231 5232 // Check that it is legal on the target to do this. It is legal if the new 5233 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 5234 // legalization. 5235 MVT VT = MVT::getIntegerVT(NumBytes*8); 5236 if (!DC->isTypeLegal(VT)) 5237 return 0; 5238 5239 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 5240 // shifted by ByteShift and truncated down to NumBytes. 5241 if (ByteShift) 5242 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 5243 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy())); 5244 5245 // Figure out the offset for the store and the alignment of the access. 5246 unsigned StOffset; 5247 unsigned NewAlign = St->getAlignment(); 5248 5249 if (DAG.getTargetLoweringInfo().isLittleEndian()) 5250 StOffset = ByteShift; 5251 else 5252 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 5253 5254 SDValue Ptr = St->getBasePtr(); 5255 if (StOffset) { 5256 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 5257 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 5258 NewAlign = MinAlign(NewAlign, StOffset); 5259 } 5260 5261 // Truncate down to the new size. 5262 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 5263 5264 ++OpsNarrowed; 5265 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 5266 St->getSrcValue(), St->getSrcValueOffset()+StOffset, 5267 false, false, NewAlign).getNode(); 5268} 5269 5270 5271/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5272/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5273/// of the loaded bits, try narrowing the load and store if it would end up 5274/// being a win for performance or code size. 5275SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5276 StoreSDNode *ST = cast<StoreSDNode>(N); 5277 if (ST->isVolatile()) 5278 return SDValue(); 5279 5280 SDValue Chain = ST->getChain(); 5281 SDValue Value = ST->getValue(); 5282 SDValue Ptr = ST->getBasePtr(); 5283 EVT VT = Value.getValueType(); 5284 5285 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5286 return SDValue(); 5287 5288 unsigned Opc = Value.getOpcode(); 5289 5290 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 5291 // is a byte mask indicating a consecutive number of bytes, check to see if 5292 // Y is known to provide just those bytes. If so, we try to replace the 5293 // load + replace + store sequence with a single (narrower) store, which makes 5294 // the load dead. 5295 if (Opc == ISD::OR) { 5296 std::pair<unsigned, unsigned> MaskedLoad; 5297 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 5298 if (MaskedLoad.first) 5299 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5300 Value.getOperand(1), ST,this)) 5301 return SDValue(NewST, 0); 5302 5303 // Or is commutative, so try swapping X and Y. 5304 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 5305 if (MaskedLoad.first) 5306 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5307 Value.getOperand(0), ST,this)) 5308 return SDValue(NewST, 0); 5309 } 5310 5311 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5312 Value.getOperand(1).getOpcode() != ISD::Constant) 5313 return SDValue(); 5314 5315 SDValue N0 = Value.getOperand(0); 5316 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5317 LoadSDNode *LD = cast<LoadSDNode>(N0); 5318 if (LD->getBasePtr() != Ptr) 5319 return SDValue(); 5320 5321 // Find the type to narrow it the load / op / store to. 5322 SDValue N1 = Value.getOperand(1); 5323 unsigned BitWidth = N1.getValueSizeInBits(); 5324 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5325 if (Opc == ISD::AND) 5326 Imm ^= APInt::getAllOnesValue(BitWidth); 5327 if (Imm == 0 || Imm.isAllOnesValue()) 5328 return SDValue(); 5329 unsigned ShAmt = Imm.countTrailingZeros(); 5330 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5331 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5332 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5333 while (NewBW < BitWidth && 5334 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5335 TLI.isNarrowingProfitable(VT, NewVT))) { 5336 NewBW = NextPowerOf2(NewBW); 5337 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5338 } 5339 if (NewBW >= BitWidth) 5340 return SDValue(); 5341 5342 // If the lsb changed does not start at the type bitwidth boundary, 5343 // start at the previous one. 5344 if (ShAmt % NewBW) 5345 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5346 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5347 if ((Imm & Mask) == Imm) { 5348 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5349 if (Opc == ISD::AND) 5350 NewImm ^= APInt::getAllOnesValue(NewBW); 5351 uint64_t PtrOff = ShAmt / 8; 5352 // For big endian targets, we need to adjust the offset to the pointer to 5353 // load the correct bytes. 5354 if (TLI.isBigEndian()) 5355 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5356 5357 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5358 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 5359 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 5360 return SDValue(); 5361 5362 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5363 Ptr.getValueType(), Ptr, 5364 DAG.getConstant(PtrOff, Ptr.getValueType())); 5365 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5366 LD->getChain(), NewPtr, 5367 LD->getSrcValue(), LD->getSrcValueOffset(), 5368 LD->isVolatile(), LD->isNonTemporal(), 5369 NewAlign); 5370 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5371 DAG.getConstant(NewImm, NewVT)); 5372 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5373 NewVal, NewPtr, 5374 ST->getSrcValue(), ST->getSrcValueOffset(), 5375 false, false, NewAlign); 5376 5377 AddToWorkList(NewPtr.getNode()); 5378 AddToWorkList(NewLD.getNode()); 5379 AddToWorkList(NewVal.getNode()); 5380 WorkListRemover DeadNodes(*this); 5381 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5382 &DeadNodes); 5383 ++OpsNarrowed; 5384 return NewST; 5385 } 5386 } 5387 5388 return SDValue(); 5389} 5390 5391SDValue DAGCombiner::visitSTORE(SDNode *N) { 5392 StoreSDNode *ST = cast<StoreSDNode>(N); 5393 SDValue Chain = ST->getChain(); 5394 SDValue Value = ST->getValue(); 5395 SDValue Ptr = ST->getBasePtr(); 5396 5397 // If this is a store of a bit convert, store the input value if the 5398 // resultant store does not need a higher alignment than the original. 5399 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5400 ST->isUnindexed()) { 5401 unsigned OrigAlign = ST->getAlignment(); 5402 EVT SVT = Value.getOperand(0).getValueType(); 5403 unsigned Align = TLI.getTargetData()-> 5404 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5405 if (Align <= OrigAlign && 5406 ((!LegalOperations && !ST->isVolatile()) || 5407 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5408 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5409 Ptr, ST->getSrcValue(), 5410 ST->getSrcValueOffset(), ST->isVolatile(), 5411 ST->isNonTemporal(), OrigAlign); 5412 } 5413 5414 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5415 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5416 // NOTE: If the original store is volatile, this transform must not increase 5417 // the number of stores. For example, on x86-32 an f64 can be stored in one 5418 // processor operation but an i64 (which is not legal) requires two. So the 5419 // transform should not be done in this case. 5420 if (Value.getOpcode() != ISD::TargetConstantFP) { 5421 SDValue Tmp; 5422 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5423 default: llvm_unreachable("Unknown FP type"); 5424 case MVT::f80: // We don't do this for these yet. 5425 case MVT::f128: 5426 case MVT::ppcf128: 5427 break; 5428 case MVT::f32: 5429 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 5430 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5431 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5432 bitcastToAPInt().getZExtValue(), MVT::i32); 5433 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5434 Ptr, ST->getSrcValue(), 5435 ST->getSrcValueOffset(), ST->isVolatile(), 5436 ST->isNonTemporal(), ST->getAlignment()); 5437 } 5438 break; 5439 case MVT::f64: 5440 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 5441 !ST->isVolatile()) || 5442 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5443 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5444 getZExtValue(), MVT::i64); 5445 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5446 Ptr, ST->getSrcValue(), 5447 ST->getSrcValueOffset(), ST->isVolatile(), 5448 ST->isNonTemporal(), ST->getAlignment()); 5449 } else if (!ST->isVolatile() && 5450 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5451 // Many FP stores are not made apparent until after legalize, e.g. for 5452 // argument passing. Since this is so common, custom legalize the 5453 // 64-bit integer store into two 32-bit stores. 5454 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5455 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5456 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5457 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5458 5459 int SVOffset = ST->getSrcValueOffset(); 5460 unsigned Alignment = ST->getAlignment(); 5461 bool isVolatile = ST->isVolatile(); 5462 bool isNonTemporal = ST->isNonTemporal(); 5463 5464 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5465 Ptr, ST->getSrcValue(), 5466 ST->getSrcValueOffset(), 5467 isVolatile, isNonTemporal, 5468 ST->getAlignment()); 5469 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5470 DAG.getConstant(4, Ptr.getValueType())); 5471 SVOffset += 4; 5472 Alignment = MinAlign(Alignment, 4U); 5473 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5474 Ptr, ST->getSrcValue(), 5475 SVOffset, isVolatile, isNonTemporal, 5476 Alignment); 5477 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5478 St0, St1); 5479 } 5480 5481 break; 5482 } 5483 } 5484 } 5485 5486 // Try to infer better alignment information than the store already has. 5487 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5488 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5489 if (Align > ST->getAlignment()) 5490 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5491 Ptr, ST->getSrcValue(), 5492 ST->getSrcValueOffset(), ST->getMemoryVT(), 5493 ST->isVolatile(), ST->isNonTemporal(), Align); 5494 } 5495 } 5496 5497 if (CombinerAA) { 5498 // Walk up chain skipping non-aliasing memory nodes. 5499 SDValue BetterChain = FindBetterChain(N, Chain); 5500 5501 // If there is a better chain. 5502 if (Chain != BetterChain) { 5503 SDValue ReplStore; 5504 5505 // Replace the chain to avoid dependency. 5506 if (ST->isTruncatingStore()) { 5507 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5508 ST->getSrcValue(),ST->getSrcValueOffset(), 5509 ST->getMemoryVT(), ST->isVolatile(), 5510 ST->isNonTemporal(), ST->getAlignment()); 5511 } else { 5512 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5513 ST->getSrcValue(), ST->getSrcValueOffset(), 5514 ST->isVolatile(), ST->isNonTemporal(), 5515 ST->getAlignment()); 5516 } 5517 5518 // Create token to keep both nodes around. 5519 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5520 MVT::Other, Chain, ReplStore); 5521 5522 // Make sure the new and old chains are cleaned up. 5523 AddToWorkList(Token.getNode()); 5524 5525 // Don't add users to work list. 5526 return CombineTo(N, Token, false); 5527 } 5528 } 5529 5530 // Try transforming N to an indexed store. 5531 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5532 return SDValue(N, 0); 5533 5534 // FIXME: is there such a thing as a truncating indexed store? 5535 if (ST->isTruncatingStore() && ST->isUnindexed() && 5536 Value.getValueType().isInteger()) { 5537 // See if we can simplify the input to this truncstore with knowledge that 5538 // only the low bits are being used. For example: 5539 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5540 SDValue Shorter = 5541 GetDemandedBits(Value, 5542 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5543 ST->getMemoryVT().getSizeInBits())); 5544 AddToWorkList(Value.getNode()); 5545 if (Shorter.getNode()) 5546 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5547 Ptr, ST->getSrcValue(), 5548 ST->getSrcValueOffset(), ST->getMemoryVT(), 5549 ST->isVolatile(), ST->isNonTemporal(), 5550 ST->getAlignment()); 5551 5552 // Otherwise, see if we can simplify the operation with 5553 // SimplifyDemandedBits, which only works if the value has a single use. 5554 if (SimplifyDemandedBits(Value, 5555 APInt::getLowBitsSet( 5556 Value.getValueType().getScalarType().getSizeInBits(), 5557 ST->getMemoryVT().getScalarType().getSizeInBits()))) 5558 return SDValue(N, 0); 5559 } 5560 5561 // If this is a load followed by a store to the same location, then the store 5562 // is dead/noop. 5563 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5564 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5565 ST->isUnindexed() && !ST->isVolatile() && 5566 // There can't be any side effects between the load and store, such as 5567 // a call or store. 5568 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5569 // The store is dead, remove it. 5570 return Chain; 5571 } 5572 } 5573 5574 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5575 // truncating store. We can do this even if this is already a truncstore. 5576 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5577 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5578 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5579 ST->getMemoryVT())) { 5580 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5581 Ptr, ST->getSrcValue(), 5582 ST->getSrcValueOffset(), ST->getMemoryVT(), 5583 ST->isVolatile(), ST->isNonTemporal(), 5584 ST->getAlignment()); 5585 } 5586 5587 return ReduceLoadOpStoreWidth(N); 5588} 5589 5590SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5591 SDValue InVec = N->getOperand(0); 5592 SDValue InVal = N->getOperand(1); 5593 SDValue EltNo = N->getOperand(2); 5594 5595 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5596 // vector with the inserted element. 5597 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5598 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5599 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5600 InVec.getNode()->op_end()); 5601 if (Elt < Ops.size()) 5602 Ops[Elt] = InVal; 5603 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5604 InVec.getValueType(), &Ops[0], Ops.size()); 5605 } 5606 // If the invec is an UNDEF and if EltNo is a constant, create a new 5607 // BUILD_VECTOR with undef elements and the inserted element. 5608 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5609 isa<ConstantSDNode>(EltNo)) { 5610 EVT VT = InVec.getValueType(); 5611 EVT EltVT = VT.getVectorElementType(); 5612 unsigned NElts = VT.getVectorNumElements(); 5613 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 5614 5615 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5616 if (Elt < Ops.size()) 5617 Ops[Elt] = InVal; 5618 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5619 InVec.getValueType(), &Ops[0], Ops.size()); 5620 } 5621 return SDValue(); 5622} 5623 5624SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5625 // (vextract (scalar_to_vector val, 0) -> val 5626 SDValue InVec = N->getOperand(0); 5627 5628 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5629 // Check if the result type doesn't match the inserted element type. A 5630 // SCALAR_TO_VECTOR may truncate the inserted element and the 5631 // EXTRACT_VECTOR_ELT may widen the extracted vector. 5632 EVT EltVT = InVec.getValueType().getVectorElementType(); 5633 SDValue InOp = InVec.getOperand(0); 5634 EVT NVT = N->getValueType(0); 5635 if (InOp.getValueType() != NVT) { 5636 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 5637 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 5638 } 5639 return InOp; 5640 } 5641 5642 // Perform only after legalization to ensure build_vector / vector_shuffle 5643 // optimizations have already been done. 5644 if (!LegalOperations) return SDValue(); 5645 5646 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5647 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5648 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5649 SDValue EltNo = N->getOperand(1); 5650 5651 if (isa<ConstantSDNode>(EltNo)) { 5652 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5653 bool NewLoad = false; 5654 bool BCNumEltsChanged = false; 5655 EVT VT = InVec.getValueType(); 5656 EVT ExtVT = VT.getVectorElementType(); 5657 EVT LVT = ExtVT; 5658 5659 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5660 EVT BCVT = InVec.getOperand(0).getValueType(); 5661 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 5662 return SDValue(); 5663 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5664 BCNumEltsChanged = true; 5665 InVec = InVec.getOperand(0); 5666 ExtVT = BCVT.getVectorElementType(); 5667 NewLoad = true; 5668 } 5669 5670 LoadSDNode *LN0 = NULL; 5671 const ShuffleVectorSDNode *SVN = NULL; 5672 if (ISD::isNormalLoad(InVec.getNode())) { 5673 LN0 = cast<LoadSDNode>(InVec); 5674 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5675 InVec.getOperand(0).getValueType() == ExtVT && 5676 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5677 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5678 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5679 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5680 // => 5681 // (load $addr+1*size) 5682 5683 // If the bit convert changed the number of elements, it is unsafe 5684 // to examine the mask. 5685 if (BCNumEltsChanged) 5686 return SDValue(); 5687 5688 // Select the input vector, guarding against out of range extract vector. 5689 unsigned NumElems = VT.getVectorNumElements(); 5690 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5691 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5692 5693 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5694 InVec = InVec.getOperand(0); 5695 if (ISD::isNormalLoad(InVec.getNode())) { 5696 LN0 = cast<LoadSDNode>(InVec); 5697 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 5698 } 5699 } 5700 5701 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5702 return SDValue(); 5703 5704 unsigned Align = LN0->getAlignment(); 5705 if (NewLoad) { 5706 // Check the resultant load doesn't need a higher alignment than the 5707 // original load. 5708 unsigned NewAlign = 5709 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 5710 5711 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5712 return SDValue(); 5713 5714 Align = NewAlign; 5715 } 5716 5717 SDValue NewPtr = LN0->getBasePtr(); 5718 if (Elt) { 5719 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5720 EVT PtrType = NewPtr.getValueType(); 5721 if (TLI.isBigEndian()) 5722 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5723 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5724 DAG.getConstant(PtrOff, PtrType)); 5725 } 5726 5727 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5728 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5729 LN0->isVolatile(), LN0->isNonTemporal(), Align); 5730 } 5731 5732 return SDValue(); 5733} 5734 5735SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5736 unsigned NumInScalars = N->getNumOperands(); 5737 EVT VT = N->getValueType(0); 5738 5739 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5740 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5741 // at most two distinct vectors, turn this into a shuffle node. 5742 SDValue VecIn1, VecIn2; 5743 for (unsigned i = 0; i != NumInScalars; ++i) { 5744 // Ignore undef inputs. 5745 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5746 5747 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5748 // constant index, bail out. 5749 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5750 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5751 VecIn1 = VecIn2 = SDValue(0, 0); 5752 break; 5753 } 5754 5755 // If the input vector type disagrees with the result of the build_vector, 5756 // we can't make a shuffle. 5757 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5758 if (ExtractedFromVec.getValueType() != VT) { 5759 VecIn1 = VecIn2 = SDValue(0, 0); 5760 break; 5761 } 5762 5763 // Otherwise, remember this. We allow up to two distinct input vectors. 5764 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5765 continue; 5766 5767 if (VecIn1.getNode() == 0) { 5768 VecIn1 = ExtractedFromVec; 5769 } else if (VecIn2.getNode() == 0) { 5770 VecIn2 = ExtractedFromVec; 5771 } else { 5772 // Too many inputs. 5773 VecIn1 = VecIn2 = SDValue(0, 0); 5774 break; 5775 } 5776 } 5777 5778 // If everything is good, we can make a shuffle operation. 5779 if (VecIn1.getNode()) { 5780 SmallVector<int, 8> Mask; 5781 for (unsigned i = 0; i != NumInScalars; ++i) { 5782 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5783 Mask.push_back(-1); 5784 continue; 5785 } 5786 5787 // If extracting from the first vector, just use the index directly. 5788 SDValue Extract = N->getOperand(i); 5789 SDValue ExtVal = Extract.getOperand(1); 5790 if (Extract.getOperand(0) == VecIn1) { 5791 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5792 if (ExtIndex > VT.getVectorNumElements()) 5793 return SDValue(); 5794 5795 Mask.push_back(ExtIndex); 5796 continue; 5797 } 5798 5799 // Otherwise, use InIdx + VecSize 5800 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5801 Mask.push_back(Idx+NumInScalars); 5802 } 5803 5804 // Add count and size info. 5805 if (!isTypeLegal(VT)) 5806 return SDValue(); 5807 5808 // Return the new VECTOR_SHUFFLE node. 5809 SDValue Ops[2]; 5810 Ops[0] = VecIn1; 5811 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5812 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5813 } 5814 5815 return SDValue(); 5816} 5817 5818SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5819 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5820 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5821 // inputs come from at most two distinct vectors, turn this into a shuffle 5822 // node. 5823 5824 // If we only have one input vector, we don't need to do any concatenation. 5825 if (N->getNumOperands() == 1) 5826 return N->getOperand(0); 5827 5828 return SDValue(); 5829} 5830 5831SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5832 return SDValue(); 5833 5834 EVT VT = N->getValueType(0); 5835 unsigned NumElts = VT.getVectorNumElements(); 5836 5837 SDValue N0 = N->getOperand(0); 5838 5839 assert(N0.getValueType().getVectorNumElements() == NumElts && 5840 "Vector shuffle must be normalized in DAG"); 5841 5842 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5843 5844 // If it is a splat, check if the argument vector is a build_vector with 5845 // all scalar elements the same. 5846 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5847 SDNode *V = N0.getNode(); 5848 5849 5850 // If this is a bit convert that changes the element type of the vector but 5851 // not the number of vector elements, look through it. Be careful not to 5852 // look though conversions that change things like v4f32 to v2f64. 5853 if (V->getOpcode() == ISD::BIT_CONVERT) { 5854 SDValue ConvInput = V->getOperand(0); 5855 if (ConvInput.getValueType().isVector() && 5856 ConvInput.getValueType().getVectorNumElements() == NumElts) 5857 V = ConvInput.getNode(); 5858 } 5859 5860 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5861 unsigned NumElems = V->getNumOperands(); 5862 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5863 if (NumElems > BaseIdx) { 5864 SDValue Base; 5865 bool AllSame = true; 5866 for (unsigned i = 0; i != NumElems; ++i) { 5867 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5868 Base = V->getOperand(i); 5869 break; 5870 } 5871 } 5872 // Splat of <u, u, u, u>, return <u, u, u, u> 5873 if (!Base.getNode()) 5874 return N0; 5875 for (unsigned i = 0; i != NumElems; ++i) { 5876 if (V->getOperand(i) != Base) { 5877 AllSame = false; 5878 break; 5879 } 5880 } 5881 // Splat of <x, x, x, x>, return <x, x, x, x> 5882 if (AllSame) 5883 return N0; 5884 } 5885 } 5886 } 5887 return SDValue(); 5888} 5889 5890/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5891/// an AND to a vector_shuffle with the destination vector and a zero vector. 5892/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5893/// vector_shuffle V, Zero, <0, 4, 2, 4> 5894SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5895 EVT VT = N->getValueType(0); 5896 DebugLoc dl = N->getDebugLoc(); 5897 SDValue LHS = N->getOperand(0); 5898 SDValue RHS = N->getOperand(1); 5899 if (N->getOpcode() == ISD::AND) { 5900 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5901 RHS = RHS.getOperand(0); 5902 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5903 SmallVector<int, 8> Indices; 5904 unsigned NumElts = RHS.getNumOperands(); 5905 for (unsigned i = 0; i != NumElts; ++i) { 5906 SDValue Elt = RHS.getOperand(i); 5907 if (!isa<ConstantSDNode>(Elt)) 5908 return SDValue(); 5909 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5910 Indices.push_back(i); 5911 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5912 Indices.push_back(NumElts); 5913 else 5914 return SDValue(); 5915 } 5916 5917 // Let's see if the target supports this vector_shuffle. 5918 EVT RVT = RHS.getValueType(); 5919 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5920 return SDValue(); 5921 5922 // Return the new VECTOR_SHUFFLE node. 5923 EVT EltVT = RVT.getVectorElementType(); 5924 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5925 DAG.getConstant(0, EltVT)); 5926 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5927 RVT, &ZeroOps[0], ZeroOps.size()); 5928 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5929 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5930 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5931 } 5932 } 5933 5934 return SDValue(); 5935} 5936 5937/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5938SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5939 // After legalize, the target may be depending on adds and other 5940 // binary ops to provide legal ways to construct constants or other 5941 // things. Simplifying them may result in a loss of legality. 5942 if (LegalOperations) return SDValue(); 5943 5944 EVT VT = N->getValueType(0); 5945 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5946 5947 EVT EltType = VT.getVectorElementType(); 5948 SDValue LHS = N->getOperand(0); 5949 SDValue RHS = N->getOperand(1); 5950 SDValue Shuffle = XformToShuffleWithZero(N); 5951 if (Shuffle.getNode()) return Shuffle; 5952 5953 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5954 // this operation. 5955 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5956 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5957 SmallVector<SDValue, 8> Ops; 5958 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5959 SDValue LHSOp = LHS.getOperand(i); 5960 SDValue RHSOp = RHS.getOperand(i); 5961 // If these two elements can't be folded, bail out. 5962 if ((LHSOp.getOpcode() != ISD::UNDEF && 5963 LHSOp.getOpcode() != ISD::Constant && 5964 LHSOp.getOpcode() != ISD::ConstantFP) || 5965 (RHSOp.getOpcode() != ISD::UNDEF && 5966 RHSOp.getOpcode() != ISD::Constant && 5967 RHSOp.getOpcode() != ISD::ConstantFP)) 5968 break; 5969 5970 // Can't fold divide by zero. 5971 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5972 N->getOpcode() == ISD::FDIV) { 5973 if ((RHSOp.getOpcode() == ISD::Constant && 5974 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5975 (RHSOp.getOpcode() == ISD::ConstantFP && 5976 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5977 break; 5978 } 5979 5980 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5981 EltType, LHSOp, RHSOp)); 5982 AddToWorkList(Ops.back().getNode()); 5983 assert((Ops.back().getOpcode() == ISD::UNDEF || 5984 Ops.back().getOpcode() == ISD::Constant || 5985 Ops.back().getOpcode() == ISD::ConstantFP) && 5986 "Scalar binop didn't fold!"); 5987 } 5988 5989 if (Ops.size() == LHS.getNumOperands()) { 5990 EVT VT = LHS.getValueType(); 5991 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5992 &Ops[0], Ops.size()); 5993 } 5994 } 5995 5996 return SDValue(); 5997} 5998 5999SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6000 SDValue N1, SDValue N2){ 6001 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6002 6003 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6004 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6005 6006 // If we got a simplified select_cc node back from SimplifySelectCC, then 6007 // break it down into a new SETCC node, and a new SELECT node, and then return 6008 // the SELECT node, since we were called with a SELECT node. 6009 if (SCC.getNode()) { 6010 // Check to see if we got a select_cc back (to turn into setcc/select). 6011 // Otherwise, just return whatever node we got back, like fabs. 6012 if (SCC.getOpcode() == ISD::SELECT_CC) { 6013 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6014 N0.getValueType(), 6015 SCC.getOperand(0), SCC.getOperand(1), 6016 SCC.getOperand(4)); 6017 AddToWorkList(SETCC.getNode()); 6018 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6019 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6020 } 6021 6022 return SCC; 6023 } 6024 return SDValue(); 6025} 6026 6027/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6028/// are the two values being selected between, see if we can simplify the 6029/// select. Callers of this should assume that TheSelect is deleted if this 6030/// returns true. As such, they should return the appropriate thing (e.g. the 6031/// node) back to the top-level of the DAG combiner loop to avoid it being 6032/// looked at. 6033bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6034 SDValue RHS) { 6035 6036 // If this is a select from two identical things, try to pull the operation 6037 // through the select. 6038 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 6039 // If this is a load and the token chain is identical, replace the select 6040 // of two loads with a load through a select of the address to load from. 6041 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6042 // constants have been dropped into the constant pool. 6043 if (LHS.getOpcode() == ISD::LOAD && 6044 // Do not let this transformation reduce the number of volatile loads. 6045 !cast<LoadSDNode>(LHS)->isVolatile() && 6046 !cast<LoadSDNode>(RHS)->isVolatile() && 6047 // Token chains must be identical. 6048 LHS.getOperand(0) == RHS.getOperand(0)) { 6049 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6050 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6051 6052 // If this is an EXTLOAD, the VT's must match. 6053 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 6054 // FIXME: this discards src value information. This is 6055 // over-conservative. It would be beneficial to be able to remember 6056 // both potential memory locations. Since we are discarding 6057 // src value info, don't do the transformation if the memory 6058 // locations are not in the default address space. 6059 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0; 6060 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) { 6061 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType())) 6062 LLDAddrSpace = PT->getAddressSpace(); 6063 } 6064 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) { 6065 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType())) 6066 RLDAddrSpace = PT->getAddressSpace(); 6067 } 6068 SDValue Addr; 6069 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) { 6070 if (TheSelect->getOpcode() == ISD::SELECT) { 6071 // Check that the condition doesn't reach either load. If so, folding 6072 // this will induce a cycle into the DAG. 6073 if ((!LLD->hasAnyUseOfValue(1) || 6074 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 6075 (!RLD->hasAnyUseOfValue(1) || 6076 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 6077 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 6078 LLD->getBasePtr().getValueType(), 6079 TheSelect->getOperand(0), LLD->getBasePtr(), 6080 RLD->getBasePtr()); 6081 } 6082 } else { 6083 // Check that the condition doesn't reach either load. If so, folding 6084 // this will induce a cycle into the DAG. 6085 if ((!LLD->hasAnyUseOfValue(1) || 6086 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 6087 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 6088 (!RLD->hasAnyUseOfValue(1) || 6089 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 6090 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 6091 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 6092 LLD->getBasePtr().getValueType(), 6093 TheSelect->getOperand(0), 6094 TheSelect->getOperand(1), 6095 LLD->getBasePtr(), RLD->getBasePtr(), 6096 TheSelect->getOperand(4)); 6097 } 6098 } 6099 } 6100 6101 if (Addr.getNode()) { 6102 SDValue Load; 6103 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 6104 Load = DAG.getLoad(TheSelect->getValueType(0), 6105 TheSelect->getDebugLoc(), 6106 LLD->getChain(), 6107 Addr, 0, 0, 6108 LLD->isVolatile(), 6109 LLD->isNonTemporal(), 6110 LLD->getAlignment()); 6111 } else { 6112 Load = DAG.getExtLoad(LLD->getExtensionType(), 6113 TheSelect->getDebugLoc(), 6114 TheSelect->getValueType(0), 6115 LLD->getChain(), Addr, 0, 0, 6116 LLD->getMemoryVT(), 6117 LLD->isVolatile(), 6118 LLD->isNonTemporal(), 6119 LLD->getAlignment()); 6120 } 6121 6122 // Users of the select now use the result of the load. 6123 CombineTo(TheSelect, Load); 6124 6125 // Users of the old loads now use the new load's chain. We know the 6126 // old-load value is dead now. 6127 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 6128 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 6129 return true; 6130 } 6131 } 6132 } 6133 } 6134 6135 return false; 6136} 6137 6138/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 6139/// where 'cond' is the comparison specified by CC. 6140SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 6141 SDValue N2, SDValue N3, 6142 ISD::CondCode CC, bool NotExtCompare) { 6143 // (x ? y : y) -> y. 6144 if (N2 == N3) return N2; 6145 6146 EVT VT = N2.getValueType(); 6147 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 6148 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 6149 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 6150 6151 // Determine if the condition we're dealing with is constant 6152 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 6153 N0, N1, CC, DL, false); 6154 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 6155 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 6156 6157 // fold select_cc true, x, y -> x 6158 if (SCCC && !SCCC->isNullValue()) 6159 return N2; 6160 // fold select_cc false, x, y -> y 6161 if (SCCC && SCCC->isNullValue()) 6162 return N3; 6163 6164 // Check to see if we can simplify the select into an fabs node 6165 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 6166 // Allow either -0.0 or 0.0 6167 if (CFP->getValueAPF().isZero()) { 6168 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 6169 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 6170 N0 == N2 && N3.getOpcode() == ISD::FNEG && 6171 N2 == N3.getOperand(0)) 6172 return DAG.getNode(ISD::FABS, DL, VT, N0); 6173 6174 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 6175 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 6176 N0 == N3 && N2.getOpcode() == ISD::FNEG && 6177 N2.getOperand(0) == N3) 6178 return DAG.getNode(ISD::FABS, DL, VT, N3); 6179 } 6180 } 6181 6182 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 6183 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 6184 // in it. This is a win when the constant is not otherwise available because 6185 // it replaces two constant pool loads with one. We only do this if the FP 6186 // type is known to be legal, because if it isn't, then we are before legalize 6187 // types an we want the other legalization to happen first (e.g. to avoid 6188 // messing with soft float) and if the ConstantFP is not legal, because if 6189 // it is legal, we may not need to store the FP constant in a constant pool. 6190 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 6191 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 6192 if (TLI.isTypeLegal(N2.getValueType()) && 6193 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 6194 TargetLowering::Legal) && 6195 // If both constants have multiple uses, then we won't need to do an 6196 // extra load, they are likely around in registers for other users. 6197 (TV->hasOneUse() || FV->hasOneUse())) { 6198 Constant *Elts[] = { 6199 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6200 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6201 }; 6202 const Type *FPTy = Elts[0]->getType(); 6203 const TargetData &TD = *TLI.getTargetData(); 6204 6205 // Create a ConstantArray of the two constants. 6206 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6207 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6208 TD.getPrefTypeAlignment(FPTy)); 6209 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6210 6211 // Get the offsets to the 0 and 1 element of the array so that we can 6212 // select between them. 6213 SDValue Zero = DAG.getIntPtrConstant(0); 6214 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6215 SDValue One = DAG.getIntPtrConstant(EltSize); 6216 6217 SDValue Cond = DAG.getSetCC(DL, 6218 TLI.getSetCCResultType(N0.getValueType()), 6219 N0, N1, CC); 6220 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6221 Cond, One, Zero); 6222 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6223 CstOffset); 6224 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6225 PseudoSourceValue::getConstantPool(), 0, false, 6226 false, Alignment); 6227 6228 } 6229 } 6230 6231 // Check to see if we can perform the "gzip trick", transforming 6232 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6233 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6234 N0.getValueType().isInteger() && 6235 N2.getValueType().isInteger() && 6236 (N1C->isNullValue() || // (a < 0) ? b : 0 6237 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6238 EVT XType = N0.getValueType(); 6239 EVT AType = N2.getValueType(); 6240 if (XType.bitsGE(AType)) { 6241 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6242 // single-bit constant. 6243 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6244 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6245 ShCtV = XType.getSizeInBits()-ShCtV-1; 6246 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6247 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6248 XType, N0, ShCt); 6249 AddToWorkList(Shift.getNode()); 6250 6251 if (XType.bitsGT(AType)) { 6252 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6253 AddToWorkList(Shift.getNode()); 6254 } 6255 6256 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6257 } 6258 6259 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6260 XType, N0, 6261 DAG.getConstant(XType.getSizeInBits()-1, 6262 getShiftAmountTy())); 6263 AddToWorkList(Shift.getNode()); 6264 6265 if (XType.bitsGT(AType)) { 6266 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6267 AddToWorkList(Shift.getNode()); 6268 } 6269 6270 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6271 } 6272 } 6273 6274 // fold select C, 16, 0 -> shl C, 4 6275 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6276 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6277 6278 // If the caller doesn't want us to simplify this into a zext of a compare, 6279 // don't do it. 6280 if (NotExtCompare && N2C->getAPIntValue() == 1) 6281 return SDValue(); 6282 6283 // Get a SetCC of the condition 6284 // FIXME: Should probably make sure that setcc is legal if we ever have a 6285 // target where it isn't. 6286 SDValue Temp, SCC; 6287 // cast from setcc result type to select result type 6288 if (LegalTypes) { 6289 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6290 N0, N1, CC); 6291 if (N2.getValueType().bitsLT(SCC.getValueType())) 6292 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6293 else 6294 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6295 N2.getValueType(), SCC); 6296 } else { 6297 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6298 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6299 N2.getValueType(), SCC); 6300 } 6301 6302 AddToWorkList(SCC.getNode()); 6303 AddToWorkList(Temp.getNode()); 6304 6305 if (N2C->getAPIntValue() == 1) 6306 return Temp; 6307 6308 // shl setcc result by log2 n2c 6309 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6310 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6311 getShiftAmountTy())); 6312 } 6313 6314 // Check to see if this is the equivalent of setcc 6315 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6316 // otherwise, go ahead with the folds. 6317 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6318 EVT XType = N0.getValueType(); 6319 if (!LegalOperations || 6320 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6321 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6322 if (Res.getValueType() != VT) 6323 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6324 return Res; 6325 } 6326 6327 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6328 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6329 (!LegalOperations || 6330 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6331 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6332 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6333 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6334 getShiftAmountTy())); 6335 } 6336 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6337 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6338 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6339 XType, DAG.getConstant(0, XType), N0); 6340 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6341 return DAG.getNode(ISD::SRL, DL, XType, 6342 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6343 DAG.getConstant(XType.getSizeInBits()-1, 6344 getShiftAmountTy())); 6345 } 6346 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6347 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6348 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6349 DAG.getConstant(XType.getSizeInBits()-1, 6350 getShiftAmountTy())); 6351 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6352 } 6353 } 6354 6355 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6356 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6357 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6358 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6359 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6360 EVT XType = N0.getValueType(); 6361 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6362 DAG.getConstant(XType.getSizeInBits()-1, 6363 getShiftAmountTy())); 6364 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6365 N0, Shift); 6366 AddToWorkList(Shift.getNode()); 6367 AddToWorkList(Add.getNode()); 6368 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6369 } 6370 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6371 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6372 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6373 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6374 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6375 EVT XType = N0.getValueType(); 6376 if (SubC->isNullValue() && XType.isInteger()) { 6377 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6378 N0, 6379 DAG.getConstant(XType.getSizeInBits()-1, 6380 getShiftAmountTy())); 6381 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6382 XType, N0, Shift); 6383 AddToWorkList(Shift.getNode()); 6384 AddToWorkList(Add.getNode()); 6385 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6386 } 6387 } 6388 } 6389 6390 return SDValue(); 6391} 6392 6393/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6394SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6395 SDValue N1, ISD::CondCode Cond, 6396 DebugLoc DL, bool foldBooleans) { 6397 TargetLowering::DAGCombinerInfo 6398 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6399 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6400} 6401 6402/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6403/// return a DAG expression to select that will generate the same value by 6404/// multiplying by a magic number. See: 6405/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6406SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6407 std::vector<SDNode*> Built; 6408 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6409 6410 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6411 ii != ee; ++ii) 6412 AddToWorkList(*ii); 6413 return S; 6414} 6415 6416/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6417/// return a DAG expression to select that will generate the same value by 6418/// multiplying by a magic number. See: 6419/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6420SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6421 std::vector<SDNode*> Built; 6422 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6423 6424 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6425 ii != ee; ++ii) 6426 AddToWorkList(*ii); 6427 return S; 6428} 6429 6430/// FindBaseOffset - Return true if base is a frame index, which is known not 6431// to alias with anything but itself. Provides base object and offset as results. 6432static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6433 const GlobalValue *&GV, void *&CV) { 6434 // Assume it is a primitive operation. 6435 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6436 6437 // If it's an adding a simple constant then integrate the offset. 6438 if (Base.getOpcode() == ISD::ADD) { 6439 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6440 Base = Base.getOperand(0); 6441 Offset += C->getZExtValue(); 6442 } 6443 } 6444 6445 // Return the underlying GlobalValue, and update the Offset. Return false 6446 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6447 // by multiple nodes with different offsets. 6448 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6449 GV = G->getGlobal(); 6450 Offset += G->getOffset(); 6451 return false; 6452 } 6453 6454 // Return the underlying Constant value, and update the Offset. Return false 6455 // for ConstantSDNodes since the same constant pool entry may be represented 6456 // by multiple nodes with different offsets. 6457 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6458 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6459 : (void *)C->getConstVal(); 6460 Offset += C->getOffset(); 6461 return false; 6462 } 6463 // If it's any of the following then it can't alias with anything but itself. 6464 return isa<FrameIndexSDNode>(Base); 6465} 6466 6467/// isAlias - Return true if there is any possibility that the two addresses 6468/// overlap. 6469bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6470 const Value *SrcValue1, int SrcValueOffset1, 6471 unsigned SrcValueAlign1, 6472 SDValue Ptr2, int64_t Size2, 6473 const Value *SrcValue2, int SrcValueOffset2, 6474 unsigned SrcValueAlign2) const { 6475 // If they are the same then they must be aliases. 6476 if (Ptr1 == Ptr2) return true; 6477 6478 // Gather base node and offset information. 6479 SDValue Base1, Base2; 6480 int64_t Offset1, Offset2; 6481 const GlobalValue *GV1, *GV2; 6482 void *CV1, *CV2; 6483 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6484 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6485 6486 // If they have a same base address then check to see if they overlap. 6487 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6488 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6489 6490 // If we know what the bases are, and they aren't identical, then we know they 6491 // cannot alias. 6492 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6493 return false; 6494 6495 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6496 // compared to the size and offset of the access, we may be able to prove they 6497 // do not alias. This check is conservative for now to catch cases created by 6498 // splitting vector types. 6499 if ((SrcValueAlign1 == SrcValueAlign2) && 6500 (SrcValueOffset1 != SrcValueOffset2) && 6501 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6502 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6503 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6504 6505 // There is no overlap between these relatively aligned accesses of similar 6506 // size, return no alias. 6507 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6508 return false; 6509 } 6510 6511 if (CombinerGlobalAA) { 6512 // Use alias analysis information. 6513 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6514 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6515 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6516 AliasAnalysis::AliasResult AAResult = 6517 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6518 if (AAResult == AliasAnalysis::NoAlias) 6519 return false; 6520 } 6521 6522 // Otherwise we have to assume they alias. 6523 return true; 6524} 6525 6526/// FindAliasInfo - Extracts the relevant alias information from the memory 6527/// node. Returns true if the operand was a load. 6528bool DAGCombiner::FindAliasInfo(SDNode *N, 6529 SDValue &Ptr, int64_t &Size, 6530 const Value *&SrcValue, 6531 int &SrcValueOffset, 6532 unsigned &SrcValueAlign) const { 6533 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6534 Ptr = LD->getBasePtr(); 6535 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6536 SrcValue = LD->getSrcValue(); 6537 SrcValueOffset = LD->getSrcValueOffset(); 6538 SrcValueAlign = LD->getOriginalAlignment(); 6539 return true; 6540 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6541 Ptr = ST->getBasePtr(); 6542 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6543 SrcValue = ST->getSrcValue(); 6544 SrcValueOffset = ST->getSrcValueOffset(); 6545 SrcValueAlign = ST->getOriginalAlignment(); 6546 } else { 6547 llvm_unreachable("FindAliasInfo expected a memory operand"); 6548 } 6549 6550 return false; 6551} 6552 6553/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6554/// looking for aliasing nodes and adding them to the Aliases vector. 6555void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6556 SmallVector<SDValue, 8> &Aliases) { 6557 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6558 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 6559 6560 // Get alias information for node. 6561 SDValue Ptr; 6562 int64_t Size; 6563 const Value *SrcValue; 6564 int SrcValueOffset; 6565 unsigned SrcValueAlign; 6566 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 6567 SrcValueAlign); 6568 6569 // Starting off. 6570 Chains.push_back(OriginalChain); 6571 unsigned Depth = 0; 6572 6573 // Look at each chain and determine if it is an alias. If so, add it to the 6574 // aliases list. If not, then continue up the chain looking for the next 6575 // candidate. 6576 while (!Chains.empty()) { 6577 SDValue Chain = Chains.back(); 6578 Chains.pop_back(); 6579 6580 // For TokenFactor nodes, look at each operand and only continue up the 6581 // chain until we find two aliases. If we've seen two aliases, assume we'll 6582 // find more and revert to original chain since the xform is unlikely to be 6583 // profitable. 6584 // 6585 // FIXME: The depth check could be made to return the last non-aliasing 6586 // chain we found before we hit a tokenfactor rather than the original 6587 // chain. 6588 if (Depth > 6 || Aliases.size() == 2) { 6589 Aliases.clear(); 6590 Aliases.push_back(OriginalChain); 6591 break; 6592 } 6593 6594 // Don't bother if we've been before. 6595 if (!Visited.insert(Chain.getNode())) 6596 continue; 6597 6598 switch (Chain.getOpcode()) { 6599 case ISD::EntryToken: 6600 // Entry token is ideal chain operand, but handled in FindBetterChain. 6601 break; 6602 6603 case ISD::LOAD: 6604 case ISD::STORE: { 6605 // Get alias information for Chain. 6606 SDValue OpPtr; 6607 int64_t OpSize; 6608 const Value *OpSrcValue; 6609 int OpSrcValueOffset; 6610 unsigned OpSrcValueAlign; 6611 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6612 OpSrcValue, OpSrcValueOffset, 6613 OpSrcValueAlign); 6614 6615 // If chain is alias then stop here. 6616 if (!(IsLoad && IsOpLoad) && 6617 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 6618 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 6619 OpSrcValueAlign)) { 6620 Aliases.push_back(Chain); 6621 } else { 6622 // Look further up the chain. 6623 Chains.push_back(Chain.getOperand(0)); 6624 ++Depth; 6625 } 6626 break; 6627 } 6628 6629 case ISD::TokenFactor: 6630 // We have to check each of the operands of the token factor for "small" 6631 // token factors, so we queue them up. Adding the operands to the queue 6632 // (stack) in reverse order maintains the original order and increases the 6633 // likelihood that getNode will find a matching token factor (CSE.) 6634 if (Chain.getNumOperands() > 16) { 6635 Aliases.push_back(Chain); 6636 break; 6637 } 6638 for (unsigned n = Chain.getNumOperands(); n;) 6639 Chains.push_back(Chain.getOperand(--n)); 6640 ++Depth; 6641 break; 6642 6643 default: 6644 // For all other instructions we will just have to take what we can get. 6645 Aliases.push_back(Chain); 6646 break; 6647 } 6648 } 6649} 6650 6651/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6652/// for a better chain (aliasing node.) 6653SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6654 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6655 6656 // Accumulate all the aliases to this node. 6657 GatherAllAliases(N, OldChain, Aliases); 6658 6659 if (Aliases.size() == 0) { 6660 // If no operands then chain to entry token. 6661 return DAG.getEntryNode(); 6662 } else if (Aliases.size() == 1) { 6663 // If a single operand then chain to it. We don't need to revisit it. 6664 return Aliases[0]; 6665 } 6666 6667 // Construct a custom tailored token factor. 6668 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6669 &Aliases[0], Aliases.size()); 6670} 6671 6672// SelectionDAG::Combine - This is the entry point for the file. 6673// 6674void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6675 CodeGenOpt::Level OptLevel) { 6676 /// run - This is the main entry point to this class. 6677 /// 6678 DAGCombiner(*this, AA, OptLevel).Run(Level); 6679} 6680