DAGCombiner.cpp revision 23b9b19b1a5a00faa9fce0788155c7dbfd00bfb1
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/Compiler.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/MathExtras.h" 39#include <algorithm> 40#include <set> 41using namespace llvm; 42 43STATISTIC(NodesCombined , "Number of dag nodes combined"); 44STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 45STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 46STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 47 48namespace { 49 static cl::opt<bool> 50 CombinerAA("combiner-alias-analysis", cl::Hidden, 51 cl::desc("Turn on alias analysis during testing")); 52 53 static cl::opt<bool> 54 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 55 cl::desc("Include global information in alias analysis")); 56 57//------------------------------ DAGCombiner ---------------------------------// 58 59 class VISIBILITY_HIDDEN DAGCombiner { 60 SelectionDAG &DAG; 61 const TargetLowering &TLI; 62 CombineLevel Level; 63 CodeGenOpt::Level OptLevel; 64 bool LegalOperations; 65 bool LegalTypes; 66 67 // Worklist of all of the nodes that need to be simplified. 68 std::vector<SDNode*> WorkList; 69 70 // AA - Used for DAG load/store alias analysis. 71 AliasAnalysis &AA; 72 73 /// AddUsersToWorkList - When an instruction is simplified, add all users of 74 /// the instruction to the work lists because they might get more simplified 75 /// now. 76 /// 77 void AddUsersToWorkList(SDNode *N) { 78 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 79 UI != UE; ++UI) 80 AddToWorkList(*UI); 81 } 82 83 /// visit - call the node-specific routine that knows how to fold each 84 /// particular type of node. 85 SDValue visit(SDNode *N); 86 87 public: 88 /// AddToWorkList - Add to the work list making sure it's instance is at the 89 /// the back (next to be processed.) 90 void AddToWorkList(SDNode *N) { 91 removeFromWorkList(N); 92 WorkList.push_back(N); 93 } 94 95 /// removeFromWorkList - remove all instances of N from the worklist. 96 /// 97 void removeFromWorkList(SDNode *N) { 98 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 99 WorkList.end()); 100 } 101 102 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 103 bool AddTo = true); 104 105 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 106 return CombineTo(N, &Res, 1, AddTo); 107 } 108 109 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 110 bool AddTo = true) { 111 SDValue To[] = { Res0, Res1 }; 112 return CombineTo(N, To, 2, AddTo); 113 } 114 115 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 116 117 private: 118 119 /// SimplifyDemandedBits - Check the specified integer node value to see if 120 /// it can be simplified or if things it uses can be simplified by bit 121 /// propagation. If so, return true. 122 bool SimplifyDemandedBits(SDValue Op) { 123 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 SDValue Ptr2, int64_t Size2, 242 const Value *SrcValue2, int SrcValueOffset2) const; 243 244 /// FindAliasInfo - Extracts the relevant alias information from the memory 245 /// node. Returns true if the operand was a load. 246 bool FindAliasInfo(SDNode *N, 247 SDValue &Ptr, int64_t &Size, 248 const Value *&SrcValue, int &SrcValueOffset) const; 249 250 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 251 /// looking for a better chain (aliasing node.) 252 SDValue FindBetterChain(SDNode *N, SDValue Chain); 253 254 /// getShiftAmountTy - Returns a type large enough to hold any valid 255 /// shift amount - before type legalization these can be huge. 256 EVT getShiftAmountTy() { 257 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 258 } 259 260public: 261 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 262 : DAG(D), 263 TLI(D.getTargetLoweringInfo()), 264 Level(Unrestricted), 265 OptLevel(OL), 266 LegalOperations(false), 267 LegalTypes(false), 268 AA(A) {} 269 270 /// Run - runs the dag combiner on all nodes in the work list 271 void Run(CombineLevel AtLevel); 272 }; 273} 274 275 276namespace { 277/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 278/// nodes from the worklist. 279class VISIBILITY_HIDDEN WorkListRemover : 280 public SelectionDAG::DAGUpdateListener { 281 DAGCombiner &DC; 282public: 283 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 284 285 virtual void NodeDeleted(SDNode *N, SDNode *E) { 286 DC.removeFromWorkList(N); 287 } 288 289 virtual void NodeUpdated(SDNode *N) { 290 // Ignore updates. 291 } 292}; 293} 294 295//===----------------------------------------------------------------------===// 296// TargetLowering::DAGCombinerInfo implementation 297//===----------------------------------------------------------------------===// 298 299void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 300 ((DAGCombiner*)DC)->AddToWorkList(N); 301} 302 303SDValue TargetLowering::DAGCombinerInfo:: 304CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 305 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 306} 307 308SDValue TargetLowering::DAGCombinerInfo:: 309CombineTo(SDNode *N, SDValue Res, bool AddTo) { 310 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 311} 312 313 314SDValue TargetLowering::DAGCombinerInfo:: 315CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 316 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 317} 318 319void TargetLowering::DAGCombinerInfo:: 320CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 321 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 322} 323 324//===----------------------------------------------------------------------===// 325// Helper Functions 326//===----------------------------------------------------------------------===// 327 328/// isNegatibleForFree - Return 1 if we can compute the negated form of the 329/// specified expression for the same cost as the expression itself, or 2 if we 330/// can compute the negated form more cheaply than the expression itself. 331static char isNegatibleForFree(SDValue Op, bool LegalOperations, 332 unsigned Depth = 0) { 333 // No compile time optimizations on this type. 334 if (Op.getValueType() == MVT::ppcf128) 335 return 0; 336 337 // fneg is removable even if it has multiple uses. 338 if (Op.getOpcode() == ISD::FNEG) return 2; 339 340 // Don't allow anything with multiple uses. 341 if (!Op.hasOneUse()) return 0; 342 343 // Don't recurse exponentially. 344 if (Depth > 6) return 0; 345 346 switch (Op.getOpcode()) { 347 default: return false; 348 case ISD::ConstantFP: 349 // Don't invert constant FP values after legalize. The negated constant 350 // isn't necessarily legal. 351 return LegalOperations ? 0 : 1; 352 case ISD::FADD: 353 // FIXME: determine better conditions for this xform. 354 if (!UnsafeFPMath) return 0; 355 356 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 357 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 358 return V; 359 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 360 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 361 case ISD::FSUB: 362 // We can't turn -(A-B) into B-A when we honor signed zeros. 363 if (!UnsafeFPMath) return 0; 364 365 // fold (fneg (fsub A, B)) -> (fsub B, A) 366 return 1; 367 368 case ISD::FMUL: 369 case ISD::FDIV: 370 if (HonorSignDependentRoundingFPMath()) return 0; 371 372 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 373 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 374 return V; 375 376 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 377 378 case ISD::FP_EXTEND: 379 case ISD::FP_ROUND: 380 case ISD::FSIN: 381 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 382 } 383} 384 385/// GetNegatedExpression - If isNegatibleForFree returns true, this function 386/// returns the newly negated expression. 387static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 388 bool LegalOperations, unsigned Depth = 0) { 389 // fneg is removable even if it has multiple uses. 390 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 391 392 // Don't allow anything with multiple uses. 393 assert(Op.hasOneUse() && "Unknown reuse!"); 394 395 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 396 switch (Op.getOpcode()) { 397 default: llvm_unreachable("Unknown code"); 398 case ISD::ConstantFP: { 399 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 400 V.changeSign(); 401 return DAG.getConstantFP(V, Op.getValueType()); 402 } 403 case ISD::FADD: 404 // FIXME: determine better conditions for this xform. 405 assert(UnsafeFPMath); 406 407 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 408 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 409 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 410 GetNegatedExpression(Op.getOperand(0), DAG, 411 LegalOperations, Depth+1), 412 Op.getOperand(1)); 413 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 414 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 415 GetNegatedExpression(Op.getOperand(1), DAG, 416 LegalOperations, Depth+1), 417 Op.getOperand(0)); 418 case ISD::FSUB: 419 // We can't turn -(A-B) into B-A when we honor signed zeros. 420 assert(UnsafeFPMath); 421 422 // fold (fneg (fsub 0, B)) -> B 423 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 424 if (N0CFP->getValueAPF().isZero()) 425 return Op.getOperand(1); 426 427 // fold (fneg (fsub A, B)) -> (fsub B, A) 428 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 429 Op.getOperand(1), Op.getOperand(0)); 430 431 case ISD::FMUL: 432 case ISD::FDIV: 433 assert(!HonorSignDependentRoundingFPMath()); 434 435 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 436 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 437 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(0), DAG, 439 LegalOperations, Depth+1), 440 Op.getOperand(1)); 441 442 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 443 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 444 Op.getOperand(0), 445 GetNegatedExpression(Op.getOperand(1), DAG, 446 LegalOperations, Depth+1)); 447 448 case ISD::FP_EXTEND: 449 case ISD::FSIN: 450 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 451 GetNegatedExpression(Op.getOperand(0), DAG, 452 LegalOperations, Depth+1)); 453 case ISD::FP_ROUND: 454 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 455 GetNegatedExpression(Op.getOperand(0), DAG, 456 LegalOperations, Depth+1), 457 Op.getOperand(1)); 458 } 459} 460 461 462// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 463// that selects between the values 1 and 0, making it equivalent to a setcc. 464// Also, set the incoming LHS, RHS, and CC references to the appropriate 465// nodes based on the type of node we are checking. This simplifies life a 466// bit for the callers. 467static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 468 SDValue &CC) { 469 if (N.getOpcode() == ISD::SETCC) { 470 LHS = N.getOperand(0); 471 RHS = N.getOperand(1); 472 CC = N.getOperand(2); 473 return true; 474 } 475 if (N.getOpcode() == ISD::SELECT_CC && 476 N.getOperand(2).getOpcode() == ISD::Constant && 477 N.getOperand(3).getOpcode() == ISD::Constant && 478 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 479 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 480 LHS = N.getOperand(0); 481 RHS = N.getOperand(1); 482 CC = N.getOperand(4); 483 return true; 484 } 485 return false; 486} 487 488// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 489// one use. If this is true, it allows the users to invert the operation for 490// free when it is profitable to do so. 491static bool isOneUseSetCC(SDValue N) { 492 SDValue N0, N1, N2; 493 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 494 return true; 495 return false; 496} 497 498SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 499 SDValue N0, SDValue N1) { 500 EVT VT = N0.getValueType(); 501 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 502 if (isa<ConstantSDNode>(N1)) { 503 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 504 SDValue OpNode = 505 DAG.FoldConstantArithmetic(Opc, VT, 506 cast<ConstantSDNode>(N0.getOperand(1)), 507 cast<ConstantSDNode>(N1)); 508 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 509 } else if (N0.hasOneUse()) { 510 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 511 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 512 N0.getOperand(0), N1); 513 AddToWorkList(OpNode.getNode()); 514 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 515 } 516 } 517 518 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 519 if (isa<ConstantSDNode>(N0)) { 520 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 521 SDValue OpNode = 522 DAG.FoldConstantArithmetic(Opc, VT, 523 cast<ConstantSDNode>(N1.getOperand(1)), 524 cast<ConstantSDNode>(N0)); 525 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 526 } else if (N1.hasOneUse()) { 527 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 528 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 529 N1.getOperand(0), N0); 530 AddToWorkList(OpNode.getNode()); 531 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 532 } 533 } 534 535 return SDValue(); 536} 537 538SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 539 bool AddTo) { 540 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 541 ++NodesCombined; 542 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 543 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 544 DOUT << " and " << NumTo-1 << " other values\n"; 545 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 546 assert(N->getValueType(i) == To[i].getValueType() && 547 "Cannot combine value to value of different type!")); 548 WorkListRemover DeadNodes(*this); 549 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 550 551 if (AddTo) { 552 // Push the new nodes and any users onto the worklist 553 for (unsigned i = 0, e = NumTo; i != e; ++i) { 554 if (To[i].getNode()) { 555 AddToWorkList(To[i].getNode()); 556 AddUsersToWorkList(To[i].getNode()); 557 } 558 } 559 } 560 561 // Finally, if the node is now dead, remove it from the graph. The node 562 // may not be dead if the replacement process recursively simplified to 563 // something else needing this node. 564 if (N->use_empty()) { 565 // Nodes can be reintroduced into the worklist. Make sure we do not 566 // process a node that has been replaced. 567 removeFromWorkList(N); 568 569 // Finally, since the node is now dead, remove it from the graph. 570 DAG.DeleteNode(N); 571 } 572 return SDValue(N, 0); 573} 574 575void 576DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 577 TLO) { 578 // Replace all uses. If any nodes become isomorphic to other nodes and 579 // are deleted, make sure to remove them from our worklist. 580 WorkListRemover DeadNodes(*this); 581 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 582 583 // Push the new node and any (possibly new) users onto the worklist. 584 AddToWorkList(TLO.New.getNode()); 585 AddUsersToWorkList(TLO.New.getNode()); 586 587 // Finally, if the node is now dead, remove it from the graph. The node 588 // may not be dead if the replacement process recursively simplified to 589 // something else needing this node. 590 if (TLO.Old.getNode()->use_empty()) { 591 removeFromWorkList(TLO.Old.getNode()); 592 593 // If the operands of this node are only used by the node, they will now 594 // be dead. Make sure to visit them first to delete dead nodes early. 595 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 596 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 597 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 598 599 DAG.DeleteNode(TLO.Old.getNode()); 600 } 601} 602 603/// SimplifyDemandedBits - Check the specified integer node value to see if 604/// it can be simplified or if things it uses can be simplified by bit 605/// propagation. If so, return true. 606bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 607 TargetLowering::TargetLoweringOpt TLO(DAG); 608 APInt KnownZero, KnownOne; 609 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 610 return false; 611 612 // Revisit the node. 613 AddToWorkList(Op.getNode()); 614 615 // Replace the old value with the new one. 616 ++NodesCombined; 617 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 618 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 619 DOUT << '\n'; 620 621 CommitTargetLoweringOpt(TLO); 622 return true; 623} 624 625//===----------------------------------------------------------------------===// 626// Main DAG Combiner implementation 627//===----------------------------------------------------------------------===// 628 629void DAGCombiner::Run(CombineLevel AtLevel) { 630 // set the instance variables, so that the various visit routines may use it. 631 Level = AtLevel; 632 LegalOperations = Level >= NoIllegalOperations; 633 LegalTypes = Level >= NoIllegalTypes; 634 635 // Add all the dag nodes to the worklist. 636 WorkList.reserve(DAG.allnodes_size()); 637 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 638 E = DAG.allnodes_end(); I != E; ++I) 639 WorkList.push_back(I); 640 641 // Create a dummy node (which is not added to allnodes), that adds a reference 642 // to the root node, preventing it from being deleted, and tracking any 643 // changes of the root. 644 HandleSDNode Dummy(DAG.getRoot()); 645 646 // The root of the dag may dangle to deleted nodes until the dag combiner is 647 // done. Set it to null to avoid confusion. 648 DAG.setRoot(SDValue()); 649 650 // while the worklist isn't empty, inspect the node on the end of it and 651 // try and combine it. 652 while (!WorkList.empty()) { 653 SDNode *N = WorkList.back(); 654 WorkList.pop_back(); 655 656 // If N has no uses, it is dead. Make sure to revisit all N's operands once 657 // N is deleted from the DAG, since they too may now be dead or may have a 658 // reduced number of uses, allowing other xforms. 659 if (N->use_empty() && N != &Dummy) { 660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 661 AddToWorkList(N->getOperand(i).getNode()); 662 663 DAG.DeleteNode(N); 664 continue; 665 } 666 667 SDValue RV = combine(N); 668 669 if (RV.getNode() == 0) 670 continue; 671 672 ++NodesCombined; 673 674 // If we get back the same node we passed in, rather than a new node or 675 // zero, we know that the node must have defined multiple values and 676 // CombineTo was used. Since CombineTo takes care of the worklist 677 // mechanics for us, we have no work to do in this case. 678 if (RV.getNode() == N) 679 continue; 680 681 assert(N->getOpcode() != ISD::DELETED_NODE && 682 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 683 "Node was deleted but visit returned new node!"); 684 685 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 686 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 687 DOUT << '\n'; 688 WorkListRemover DeadNodes(*this); 689 if (N->getNumValues() == RV.getNode()->getNumValues()) 690 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 691 else { 692 assert(N->getValueType(0) == RV.getValueType() && 693 N->getNumValues() == 1 && "Type mismatch"); 694 SDValue OpV = RV; 695 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 696 } 697 698 // Push the new node and any users onto the worklist 699 AddToWorkList(RV.getNode()); 700 AddUsersToWorkList(RV.getNode()); 701 702 // Add any uses of the old node to the worklist in case this node is the 703 // last one that uses them. They may become dead after this node is 704 // deleted. 705 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 706 AddToWorkList(N->getOperand(i).getNode()); 707 708 // Finally, if the node is now dead, remove it from the graph. The node 709 // may not be dead if the replacement process recursively simplified to 710 // something else needing this node. 711 if (N->use_empty()) { 712 // Nodes can be reintroduced into the worklist. Make sure we do not 713 // process a node that has been replaced. 714 removeFromWorkList(N); 715 716 // Finally, since the node is now dead, remove it from the graph. 717 DAG.DeleteNode(N); 718 } 719 } 720 721 // If the root changed (e.g. it was a dead load, update the root). 722 DAG.setRoot(Dummy.getValue()); 723} 724 725SDValue DAGCombiner::visit(SDNode *N) { 726 switch(N->getOpcode()) { 727 default: break; 728 case ISD::TokenFactor: return visitTokenFactor(N); 729 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 730 case ISD::ADD: return visitADD(N); 731 case ISD::SUB: return visitSUB(N); 732 case ISD::ADDC: return visitADDC(N); 733 case ISD::ADDE: return visitADDE(N); 734 case ISD::MUL: return visitMUL(N); 735 case ISD::SDIV: return visitSDIV(N); 736 case ISD::UDIV: return visitUDIV(N); 737 case ISD::SREM: return visitSREM(N); 738 case ISD::UREM: return visitUREM(N); 739 case ISD::MULHU: return visitMULHU(N); 740 case ISD::MULHS: return visitMULHS(N); 741 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 742 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 743 case ISD::SDIVREM: return visitSDIVREM(N); 744 case ISD::UDIVREM: return visitUDIVREM(N); 745 case ISD::AND: return visitAND(N); 746 case ISD::OR: return visitOR(N); 747 case ISD::XOR: return visitXOR(N); 748 case ISD::SHL: return visitSHL(N); 749 case ISD::SRA: return visitSRA(N); 750 case ISD::SRL: return visitSRL(N); 751 case ISD::CTLZ: return visitCTLZ(N); 752 case ISD::CTTZ: return visitCTTZ(N); 753 case ISD::CTPOP: return visitCTPOP(N); 754 case ISD::SELECT: return visitSELECT(N); 755 case ISD::SELECT_CC: return visitSELECT_CC(N); 756 case ISD::SETCC: return visitSETCC(N); 757 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 758 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 759 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 760 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 761 case ISD::TRUNCATE: return visitTRUNCATE(N); 762 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 763 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 764 case ISD::FADD: return visitFADD(N); 765 case ISD::FSUB: return visitFSUB(N); 766 case ISD::FMUL: return visitFMUL(N); 767 case ISD::FDIV: return visitFDIV(N); 768 case ISD::FREM: return visitFREM(N); 769 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 770 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 771 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 772 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 773 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 774 case ISD::FP_ROUND: return visitFP_ROUND(N); 775 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 776 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 777 case ISD::FNEG: return visitFNEG(N); 778 case ISD::FABS: return visitFABS(N); 779 case ISD::BRCOND: return visitBRCOND(N); 780 case ISD::BR_CC: return visitBR_CC(N); 781 case ISD::LOAD: return visitLOAD(N); 782 case ISD::STORE: return visitSTORE(N); 783 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 784 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 785 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 786 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 787 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 788 } 789 return SDValue(); 790} 791 792SDValue DAGCombiner::combine(SDNode *N) { 793 SDValue RV = visit(N); 794 795 // If nothing happened, try a target-specific DAG combine. 796 if (RV.getNode() == 0) { 797 assert(N->getOpcode() != ISD::DELETED_NODE && 798 "Node was deleted but visit returned NULL!"); 799 800 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 801 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 802 803 // Expose the DAG combiner to the target combiner impls. 804 TargetLowering::DAGCombinerInfo 805 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 806 807 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 808 } 809 } 810 811 // If N is a commutative binary node, try commuting it to enable more 812 // sdisel CSE. 813 if (RV.getNode() == 0 && 814 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 815 N->getNumValues() == 1) { 816 SDValue N0 = N->getOperand(0); 817 SDValue N1 = N->getOperand(1); 818 819 // Constant operands are canonicalized to RHS. 820 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 821 SDValue Ops[] = { N1, N0 }; 822 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 823 Ops, 2); 824 if (CSENode) 825 return SDValue(CSENode, 0); 826 } 827 } 828 829 return RV; 830} 831 832/// getInputChainForNode - Given a node, return its input chain if it has one, 833/// otherwise return a null sd operand. 834static SDValue getInputChainForNode(SDNode *N) { 835 if (unsigned NumOps = N->getNumOperands()) { 836 if (N->getOperand(0).getValueType() == MVT::Other) 837 return N->getOperand(0); 838 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 839 return N->getOperand(NumOps-1); 840 for (unsigned i = 1; i < NumOps-1; ++i) 841 if (N->getOperand(i).getValueType() == MVT::Other) 842 return N->getOperand(i); 843 } 844 return SDValue(); 845} 846 847SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 848 // If N has two operands, where one has an input chain equal to the other, 849 // the 'other' chain is redundant. 850 if (N->getNumOperands() == 2) { 851 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 852 return N->getOperand(0); 853 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 854 return N->getOperand(1); 855 } 856 857 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 858 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 859 SmallPtrSet<SDNode*, 16> SeenOps; 860 bool Changed = false; // If we should replace this token factor. 861 862 // Start out with this token factor. 863 TFs.push_back(N); 864 865 // Iterate through token factors. The TFs grows when new token factors are 866 // encountered. 867 for (unsigned i = 0; i < TFs.size(); ++i) { 868 SDNode *TF = TFs[i]; 869 870 // Check each of the operands. 871 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 872 SDValue Op = TF->getOperand(i); 873 874 switch (Op.getOpcode()) { 875 case ISD::EntryToken: 876 // Entry tokens don't need to be added to the list. They are 877 // rededundant. 878 Changed = true; 879 break; 880 881 case ISD::TokenFactor: 882 if ((CombinerAA || Op.hasOneUse()) && 883 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 884 // Queue up for processing. 885 TFs.push_back(Op.getNode()); 886 // Clean up in case the token factor is removed. 887 AddToWorkList(Op.getNode()); 888 Changed = true; 889 break; 890 } 891 // Fall thru 892 893 default: 894 // Only add if it isn't already in the list. 895 if (SeenOps.insert(Op.getNode())) 896 Ops.push_back(Op); 897 else 898 Changed = true; 899 break; 900 } 901 } 902 } 903 904 SDValue Result; 905 906 // If we've change things around then replace token factor. 907 if (Changed) { 908 if (Ops.empty()) { 909 // The entry token is the only possible outcome. 910 Result = DAG.getEntryNode(); 911 } else { 912 // New and improved token factor. 913 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 914 MVT::Other, &Ops[0], Ops.size()); 915 } 916 917 // Don't add users to work list. 918 return CombineTo(N, Result, false); 919 } 920 921 return Result; 922} 923 924/// MERGE_VALUES can always be eliminated. 925SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 926 WorkListRemover DeadNodes(*this); 927 // Replacing results may cause a different MERGE_VALUES to suddenly 928 // be CSE'd with N, and carry its uses with it. Iterate until no 929 // uses remain, to ensure that the node can be safely deleted. 930 do { 931 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 932 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 933 &DeadNodes); 934 } while (!N->use_empty()); 935 removeFromWorkList(N); 936 DAG.DeleteNode(N); 937 return SDValue(N, 0); // Return N so it doesn't get rechecked! 938} 939 940static 941SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 942 SelectionDAG &DAG) { 943 EVT VT = N0.getValueType(); 944 SDValue N00 = N0.getOperand(0); 945 SDValue N01 = N0.getOperand(1); 946 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 947 948 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 949 isa<ConstantSDNode>(N00.getOperand(1))) { 950 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 951 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 952 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 953 N00.getOperand(0), N01), 954 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 955 N00.getOperand(1), N01)); 956 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 957 } 958 959 return SDValue(); 960} 961 962SDValue DAGCombiner::visitADD(SDNode *N) { 963 SDValue N0 = N->getOperand(0); 964 SDValue N1 = N->getOperand(1); 965 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 966 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 967 EVT VT = N0.getValueType(); 968 969 // fold vector ops 970 if (VT.isVector()) { 971 SDValue FoldedVOp = SimplifyVBinOp(N); 972 if (FoldedVOp.getNode()) return FoldedVOp; 973 } 974 975 // fold (add x, undef) -> undef 976 if (N0.getOpcode() == ISD::UNDEF) 977 return N0; 978 if (N1.getOpcode() == ISD::UNDEF) 979 return N1; 980 // fold (add c1, c2) -> c1+c2 981 if (N0C && N1C) 982 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 983 // canonicalize constant to RHS 984 if (N0C && !N1C) 985 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 986 // fold (add x, 0) -> x 987 if (N1C && N1C->isNullValue()) 988 return N0; 989 // fold (add Sym, c) -> Sym+c 990 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 991 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 992 GA->getOpcode() == ISD::GlobalAddress) 993 return DAG.getGlobalAddress(GA->getGlobal(), VT, 994 GA->getOffset() + 995 (uint64_t)N1C->getSExtValue()); 996 // fold ((c1-A)+c2) -> (c1+c2)-A 997 if (N1C && N0.getOpcode() == ISD::SUB) 998 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 999 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1000 DAG.getConstant(N1C->getAPIntValue()+ 1001 N0C->getAPIntValue(), VT), 1002 N0.getOperand(1)); 1003 // reassociate add 1004 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1005 if (RADD.getNode() != 0) 1006 return RADD; 1007 // fold ((0-A) + B) -> B-A 1008 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1009 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1010 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1011 // fold (A + (0-B)) -> A-B 1012 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1013 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1014 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1015 // fold (A+(B-A)) -> B 1016 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1017 return N1.getOperand(0); 1018 // fold ((B-A)+A) -> B 1019 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1020 return N0.getOperand(0); 1021 // fold (A+(B-(A+C))) to (B-C) 1022 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1023 N0 == N1.getOperand(1).getOperand(0)) 1024 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1025 N1.getOperand(1).getOperand(1)); 1026 // fold (A+(B-(C+A))) to (B-C) 1027 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1028 N0 == N1.getOperand(1).getOperand(1)) 1029 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1030 N1.getOperand(1).getOperand(0)); 1031 // fold (A+((B-A)+or-C)) to (B+or-C) 1032 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1033 N1.getOperand(0).getOpcode() == ISD::SUB && 1034 N0 == N1.getOperand(0).getOperand(1)) 1035 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1036 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1037 1038 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1039 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1040 SDValue N00 = N0.getOperand(0); 1041 SDValue N01 = N0.getOperand(1); 1042 SDValue N10 = N1.getOperand(0); 1043 SDValue N11 = N1.getOperand(1); 1044 1045 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1046 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1047 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1048 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1049 } 1050 1051 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1052 return SDValue(N, 0); 1053 1054 // fold (a+b) -> (a|b) iff a and b share no bits. 1055 if (VT.isInteger() && !VT.isVector()) { 1056 APInt LHSZero, LHSOne; 1057 APInt RHSZero, RHSOne; 1058 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1059 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1060 1061 if (LHSZero.getBoolValue()) { 1062 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1063 1064 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1065 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1066 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1067 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1068 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1069 } 1070 } 1071 1072 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1073 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1074 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1075 if (Result.getNode()) return Result; 1076 } 1077 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1078 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1079 if (Result.getNode()) return Result; 1080 } 1081 1082 return SDValue(); 1083} 1084 1085SDValue DAGCombiner::visitADDC(SDNode *N) { 1086 SDValue N0 = N->getOperand(0); 1087 SDValue N1 = N->getOperand(1); 1088 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1090 EVT VT = N0.getValueType(); 1091 1092 // If the flag result is dead, turn this into an ADD. 1093 if (N->hasNUsesOfValue(0, 1)) 1094 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1095 DAG.getNode(ISD::CARRY_FALSE, 1096 N->getDebugLoc(), MVT::Flag)); 1097 1098 // canonicalize constant to RHS. 1099 if (N0C && !N1C) 1100 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1101 1102 // fold (addc x, 0) -> x + no carry out 1103 if (N1C && N1C->isNullValue()) 1104 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1105 N->getDebugLoc(), MVT::Flag)); 1106 1107 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1108 APInt LHSZero, LHSOne; 1109 APInt RHSZero, RHSOne; 1110 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1111 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1112 1113 if (LHSZero.getBoolValue()) { 1114 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1115 1116 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1117 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1118 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1119 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1120 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1121 DAG.getNode(ISD::CARRY_FALSE, 1122 N->getDebugLoc(), MVT::Flag)); 1123 } 1124 1125 return SDValue(); 1126} 1127 1128SDValue DAGCombiner::visitADDE(SDNode *N) { 1129 SDValue N0 = N->getOperand(0); 1130 SDValue N1 = N->getOperand(1); 1131 SDValue CarryIn = N->getOperand(2); 1132 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1133 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1134 1135 // canonicalize constant to RHS 1136 if (N0C && !N1C) 1137 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1138 N1, N0, CarryIn); 1139 1140 // fold (adde x, y, false) -> (addc x, y) 1141 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1142 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1143 1144 return SDValue(); 1145} 1146 1147SDValue DAGCombiner::visitSUB(SDNode *N) { 1148 SDValue N0 = N->getOperand(0); 1149 SDValue N1 = N->getOperand(1); 1150 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1151 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1152 EVT VT = N0.getValueType(); 1153 1154 // fold vector ops 1155 if (VT.isVector()) { 1156 SDValue FoldedVOp = SimplifyVBinOp(N); 1157 if (FoldedVOp.getNode()) return FoldedVOp; 1158 } 1159 1160 // fold (sub x, x) -> 0 1161 if (N0 == N1) 1162 return DAG.getConstant(0, N->getValueType(0)); 1163 // fold (sub c1, c2) -> c1-c2 1164 if (N0C && N1C) 1165 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1166 // fold (sub x, c) -> (add x, -c) 1167 if (N1C) 1168 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1169 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1170 // fold (A+B)-A -> B 1171 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1172 return N0.getOperand(1); 1173 // fold (A+B)-B -> A 1174 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1175 return N0.getOperand(0); 1176 // fold ((A+(B+or-C))-B) -> A+or-C 1177 if (N0.getOpcode() == ISD::ADD && 1178 (N0.getOperand(1).getOpcode() == ISD::SUB || 1179 N0.getOperand(1).getOpcode() == ISD::ADD) && 1180 N0.getOperand(1).getOperand(0) == N1) 1181 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1182 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1183 // fold ((A+(C+B))-B) -> A+C 1184 if (N0.getOpcode() == ISD::ADD && 1185 N0.getOperand(1).getOpcode() == ISD::ADD && 1186 N0.getOperand(1).getOperand(1) == N1) 1187 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1188 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1189 // fold ((A-(B-C))-C) -> A-B 1190 if (N0.getOpcode() == ISD::SUB && 1191 N0.getOperand(1).getOpcode() == ISD::SUB && 1192 N0.getOperand(1).getOperand(1) == N1) 1193 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1194 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1195 1196 // If either operand of a sub is undef, the result is undef 1197 if (N0.getOpcode() == ISD::UNDEF) 1198 return N0; 1199 if (N1.getOpcode() == ISD::UNDEF) 1200 return N1; 1201 1202 // If the relocation model supports it, consider symbol offsets. 1203 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1204 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1205 // fold (sub Sym, c) -> Sym-c 1206 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1207 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1208 GA->getOffset() - 1209 (uint64_t)N1C->getSExtValue()); 1210 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1211 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1212 if (GA->getGlobal() == GB->getGlobal()) 1213 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1214 VT); 1215 } 1216 1217 return SDValue(); 1218} 1219 1220SDValue DAGCombiner::visitMUL(SDNode *N) { 1221 SDValue N0 = N->getOperand(0); 1222 SDValue N1 = N->getOperand(1); 1223 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1224 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1225 EVT VT = N0.getValueType(); 1226 1227 // fold vector ops 1228 if (VT.isVector()) { 1229 SDValue FoldedVOp = SimplifyVBinOp(N); 1230 if (FoldedVOp.getNode()) return FoldedVOp; 1231 } 1232 1233 // fold (mul x, undef) -> 0 1234 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1235 return DAG.getConstant(0, VT); 1236 // fold (mul c1, c2) -> c1*c2 1237 if (N0C && N1C) 1238 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1239 // canonicalize constant to RHS 1240 if (N0C && !N1C) 1241 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1242 // fold (mul x, 0) -> 0 1243 if (N1C && N1C->isNullValue()) 1244 return N1; 1245 // fold (mul x, -1) -> 0-x 1246 if (N1C && N1C->isAllOnesValue()) 1247 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1248 DAG.getConstant(0, VT), N0); 1249 // fold (mul x, (1 << c)) -> x << c 1250 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1251 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1252 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1253 getShiftAmountTy())); 1254 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1255 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1256 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1257 // FIXME: If the input is something that is easily negated (e.g. a 1258 // single-use add), we should put the negate there. 1259 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1260 DAG.getConstant(0, VT), 1261 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1262 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1263 } 1264 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1265 if (N1C && N0.getOpcode() == ISD::SHL && 1266 isa<ConstantSDNode>(N0.getOperand(1))) { 1267 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1268 N1, N0.getOperand(1)); 1269 AddToWorkList(C3.getNode()); 1270 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1271 N0.getOperand(0), C3); 1272 } 1273 1274 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1275 // use. 1276 { 1277 SDValue Sh(0,0), Y(0,0); 1278 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1279 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1280 N0.getNode()->hasOneUse()) { 1281 Sh = N0; Y = N1; 1282 } else if (N1.getOpcode() == ISD::SHL && 1283 isa<ConstantSDNode>(N1.getOperand(1)) && 1284 N1.getNode()->hasOneUse()) { 1285 Sh = N1; Y = N0; 1286 } 1287 1288 if (Sh.getNode()) { 1289 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1290 Sh.getOperand(0), Y); 1291 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1292 Mul, Sh.getOperand(1)); 1293 } 1294 } 1295 1296 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1297 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1298 isa<ConstantSDNode>(N0.getOperand(1))) 1299 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1300 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1301 N0.getOperand(0), N1), 1302 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1303 N0.getOperand(1), N1)); 1304 1305 // reassociate mul 1306 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1307 if (RMUL.getNode() != 0) 1308 return RMUL; 1309 1310 return SDValue(); 1311} 1312 1313SDValue DAGCombiner::visitSDIV(SDNode *N) { 1314 SDValue N0 = N->getOperand(0); 1315 SDValue N1 = N->getOperand(1); 1316 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1317 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1318 EVT VT = N->getValueType(0); 1319 1320 // fold vector ops 1321 if (VT.isVector()) { 1322 SDValue FoldedVOp = SimplifyVBinOp(N); 1323 if (FoldedVOp.getNode()) return FoldedVOp; 1324 } 1325 1326 // fold (sdiv c1, c2) -> c1/c2 1327 if (N0C && N1C && !N1C->isNullValue()) 1328 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1329 // fold (sdiv X, 1) -> X 1330 if (N1C && N1C->getSExtValue() == 1LL) 1331 return N0; 1332 // fold (sdiv X, -1) -> 0-X 1333 if (N1C && N1C->isAllOnesValue()) 1334 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1335 DAG.getConstant(0, VT), N0); 1336 // If we know the sign bits of both operands are zero, strength reduce to a 1337 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1338 if (!VT.isVector()) { 1339 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1340 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1341 N0, N1); 1342 } 1343 // fold (sdiv X, pow2) -> simple ops after legalize 1344 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1345 (isPowerOf2_64(N1C->getSExtValue()) || 1346 isPowerOf2_64(-N1C->getSExtValue()))) { 1347 // If dividing by powers of two is cheap, then don't perform the following 1348 // fold. 1349 if (TLI.isPow2DivCheap()) 1350 return SDValue(); 1351 1352 int64_t pow2 = N1C->getSExtValue(); 1353 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1354 unsigned lg2 = Log2_64(abs2); 1355 1356 // Splat the sign bit into the register 1357 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1358 DAG.getConstant(VT.getSizeInBits()-1, 1359 getShiftAmountTy())); 1360 AddToWorkList(SGN.getNode()); 1361 1362 // Add (N0 < 0) ? abs2 - 1 : 0; 1363 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1364 DAG.getConstant(VT.getSizeInBits() - lg2, 1365 getShiftAmountTy())); 1366 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1367 AddToWorkList(SRL.getNode()); 1368 AddToWorkList(ADD.getNode()); // Divide by pow2 1369 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1370 DAG.getConstant(lg2, getShiftAmountTy())); 1371 1372 // If we're dividing by a positive value, we're done. Otherwise, we must 1373 // negate the result. 1374 if (pow2 > 0) 1375 return SRA; 1376 1377 AddToWorkList(SRA.getNode()); 1378 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1379 DAG.getConstant(0, VT), SRA); 1380 } 1381 1382 // if integer divide is expensive and we satisfy the requirements, emit an 1383 // alternate sequence. 1384 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1385 !TLI.isIntDivCheap()) { 1386 SDValue Op = BuildSDIV(N); 1387 if (Op.getNode()) return Op; 1388 } 1389 1390 // undef / X -> 0 1391 if (N0.getOpcode() == ISD::UNDEF) 1392 return DAG.getConstant(0, VT); 1393 // X / undef -> undef 1394 if (N1.getOpcode() == ISD::UNDEF) 1395 return N1; 1396 1397 return SDValue(); 1398} 1399 1400SDValue DAGCombiner::visitUDIV(SDNode *N) { 1401 SDValue N0 = N->getOperand(0); 1402 SDValue N1 = N->getOperand(1); 1403 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1404 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1405 EVT VT = N->getValueType(0); 1406 1407 // fold vector ops 1408 if (VT.isVector()) { 1409 SDValue FoldedVOp = SimplifyVBinOp(N); 1410 if (FoldedVOp.getNode()) return FoldedVOp; 1411 } 1412 1413 // fold (udiv c1, c2) -> c1/c2 1414 if (N0C && N1C && !N1C->isNullValue()) 1415 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1416 // fold (udiv x, (1 << c)) -> x >>u c 1417 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1418 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1419 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1420 getShiftAmountTy())); 1421 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1422 if (N1.getOpcode() == ISD::SHL) { 1423 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1424 if (SHC->getAPIntValue().isPowerOf2()) { 1425 EVT ADDVT = N1.getOperand(1).getValueType(); 1426 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1427 N1.getOperand(1), 1428 DAG.getConstant(SHC->getAPIntValue() 1429 .logBase2(), 1430 ADDVT)); 1431 AddToWorkList(Add.getNode()); 1432 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1433 } 1434 } 1435 } 1436 // fold (udiv x, c) -> alternate 1437 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1438 SDValue Op = BuildUDIV(N); 1439 if (Op.getNode()) return Op; 1440 } 1441 1442 // undef / X -> 0 1443 if (N0.getOpcode() == ISD::UNDEF) 1444 return DAG.getConstant(0, VT); 1445 // X / undef -> undef 1446 if (N1.getOpcode() == ISD::UNDEF) 1447 return N1; 1448 1449 return SDValue(); 1450} 1451 1452SDValue DAGCombiner::visitSREM(SDNode *N) { 1453 SDValue N0 = N->getOperand(0); 1454 SDValue N1 = N->getOperand(1); 1455 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1456 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1457 EVT VT = N->getValueType(0); 1458 1459 // fold (srem c1, c2) -> c1%c2 1460 if (N0C && N1C && !N1C->isNullValue()) 1461 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1462 // If we know the sign bits of both operands are zero, strength reduce to a 1463 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1464 if (!VT.isVector()) { 1465 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1466 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1467 } 1468 1469 // If X/C can be simplified by the division-by-constant logic, lower 1470 // X%C to the equivalent of X-X/C*C. 1471 if (N1C && !N1C->isNullValue()) { 1472 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1473 AddToWorkList(Div.getNode()); 1474 SDValue OptimizedDiv = combine(Div.getNode()); 1475 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1476 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1477 OptimizedDiv, N1); 1478 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1479 AddToWorkList(Mul.getNode()); 1480 return Sub; 1481 } 1482 } 1483 1484 // undef % X -> 0 1485 if (N0.getOpcode() == ISD::UNDEF) 1486 return DAG.getConstant(0, VT); 1487 // X % undef -> undef 1488 if (N1.getOpcode() == ISD::UNDEF) 1489 return N1; 1490 1491 return SDValue(); 1492} 1493 1494SDValue DAGCombiner::visitUREM(SDNode *N) { 1495 SDValue N0 = N->getOperand(0); 1496 SDValue N1 = N->getOperand(1); 1497 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1498 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1499 EVT VT = N->getValueType(0); 1500 1501 // fold (urem c1, c2) -> c1%c2 1502 if (N0C && N1C && !N1C->isNullValue()) 1503 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1504 // fold (urem x, pow2) -> (and x, pow2-1) 1505 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1506 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1507 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1508 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1509 if (N1.getOpcode() == ISD::SHL) { 1510 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1511 if (SHC->getAPIntValue().isPowerOf2()) { 1512 SDValue Add = 1513 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1514 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1515 VT)); 1516 AddToWorkList(Add.getNode()); 1517 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1518 } 1519 } 1520 } 1521 1522 // If X/C can be simplified by the division-by-constant logic, lower 1523 // X%C to the equivalent of X-X/C*C. 1524 if (N1C && !N1C->isNullValue()) { 1525 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1526 AddToWorkList(Div.getNode()); 1527 SDValue OptimizedDiv = combine(Div.getNode()); 1528 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1529 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1530 OptimizedDiv, N1); 1531 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1532 AddToWorkList(Mul.getNode()); 1533 return Sub; 1534 } 1535 } 1536 1537 // undef % X -> 0 1538 if (N0.getOpcode() == ISD::UNDEF) 1539 return DAG.getConstant(0, VT); 1540 // X % undef -> undef 1541 if (N1.getOpcode() == ISD::UNDEF) 1542 return N1; 1543 1544 return SDValue(); 1545} 1546 1547SDValue DAGCombiner::visitMULHS(SDNode *N) { 1548 SDValue N0 = N->getOperand(0); 1549 SDValue N1 = N->getOperand(1); 1550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1551 EVT VT = N->getValueType(0); 1552 1553 // fold (mulhs x, 0) -> 0 1554 if (N1C && N1C->isNullValue()) 1555 return N1; 1556 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1557 if (N1C && N1C->getAPIntValue() == 1) 1558 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1559 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1560 getShiftAmountTy())); 1561 // fold (mulhs x, undef) -> 0 1562 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1563 return DAG.getConstant(0, VT); 1564 1565 return SDValue(); 1566} 1567 1568SDValue DAGCombiner::visitMULHU(SDNode *N) { 1569 SDValue N0 = N->getOperand(0); 1570 SDValue N1 = N->getOperand(1); 1571 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1572 EVT VT = N->getValueType(0); 1573 1574 // fold (mulhu x, 0) -> 0 1575 if (N1C && N1C->isNullValue()) 1576 return N1; 1577 // fold (mulhu x, 1) -> 0 1578 if (N1C && N1C->getAPIntValue() == 1) 1579 return DAG.getConstant(0, N0.getValueType()); 1580 // fold (mulhu x, undef) -> 0 1581 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1582 return DAG.getConstant(0, VT); 1583 1584 return SDValue(); 1585} 1586 1587/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1588/// compute two values. LoOp and HiOp give the opcodes for the two computations 1589/// that are being performed. Return true if a simplification was made. 1590/// 1591SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1592 unsigned HiOp) { 1593 // If the high half is not needed, just compute the low half. 1594 bool HiExists = N->hasAnyUseOfValue(1); 1595 if (!HiExists && 1596 (!LegalOperations || 1597 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1598 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1599 N->op_begin(), N->getNumOperands()); 1600 return CombineTo(N, Res, Res); 1601 } 1602 1603 // If the low half is not needed, just compute the high half. 1604 bool LoExists = N->hasAnyUseOfValue(0); 1605 if (!LoExists && 1606 (!LegalOperations || 1607 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1608 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1609 N->op_begin(), N->getNumOperands()); 1610 return CombineTo(N, Res, Res); 1611 } 1612 1613 // If both halves are used, return as it is. 1614 if (LoExists && HiExists) 1615 return SDValue(); 1616 1617 // If the two computed results can be simplified separately, separate them. 1618 if (LoExists) { 1619 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1620 N->op_begin(), N->getNumOperands()); 1621 AddToWorkList(Lo.getNode()); 1622 SDValue LoOpt = combine(Lo.getNode()); 1623 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1624 (!LegalOperations || 1625 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1626 return CombineTo(N, LoOpt, LoOpt); 1627 } 1628 1629 if (HiExists) { 1630 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1631 N->op_begin(), N->getNumOperands()); 1632 AddToWorkList(Hi.getNode()); 1633 SDValue HiOpt = combine(Hi.getNode()); 1634 if (HiOpt.getNode() && HiOpt != Hi && 1635 (!LegalOperations || 1636 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1637 return CombineTo(N, HiOpt, HiOpt); 1638 } 1639 1640 return SDValue(); 1641} 1642 1643SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1644 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1645 if (Res.getNode()) return Res; 1646 1647 return SDValue(); 1648} 1649 1650SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1651 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1652 if (Res.getNode()) return Res; 1653 1654 return SDValue(); 1655} 1656 1657SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1658 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1659 if (Res.getNode()) return Res; 1660 1661 return SDValue(); 1662} 1663 1664SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1665 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1666 if (Res.getNode()) return Res; 1667 1668 return SDValue(); 1669} 1670 1671/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1672/// two operands of the same opcode, try to simplify it. 1673SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1674 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1675 EVT VT = N0.getValueType(); 1676 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1677 1678 // For each of OP in AND/OR/XOR: 1679 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1680 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1681 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1682 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1683 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1684 N0.getOpcode() == ISD::SIGN_EXTEND || 1685 (N0.getOpcode() == ISD::TRUNCATE && 1686 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1687 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() && 1688 (!LegalOperations || 1689 TLI.isOperationLegal(N->getOpcode(), N0.getOperand(0).getValueType()))) { 1690 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1691 N0.getOperand(0).getValueType(), 1692 N0.getOperand(0), N1.getOperand(0)); 1693 AddToWorkList(ORNode.getNode()); 1694 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1695 } 1696 1697 // For each of OP in SHL/SRL/SRA/AND... 1698 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1699 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1700 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1701 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1702 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1703 N0.getOperand(1) == N1.getOperand(1)) { 1704 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1705 N0.getOperand(0).getValueType(), 1706 N0.getOperand(0), N1.getOperand(0)); 1707 AddToWorkList(ORNode.getNode()); 1708 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1709 ORNode, N0.getOperand(1)); 1710 } 1711 1712 return SDValue(); 1713} 1714 1715SDValue DAGCombiner::visitAND(SDNode *N) { 1716 SDValue N0 = N->getOperand(0); 1717 SDValue N1 = N->getOperand(1); 1718 SDValue LL, LR, RL, RR, CC0, CC1; 1719 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1720 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1721 EVT VT = N1.getValueType(); 1722 unsigned BitWidth = VT.getSizeInBits(); 1723 1724 // fold vector ops 1725 if (VT.isVector()) { 1726 SDValue FoldedVOp = SimplifyVBinOp(N); 1727 if (FoldedVOp.getNode()) return FoldedVOp; 1728 } 1729 1730 // fold (and x, undef) -> 0 1731 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1732 return DAG.getConstant(0, VT); 1733 // fold (and c1, c2) -> c1&c2 1734 if (N0C && N1C) 1735 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1736 // canonicalize constant to RHS 1737 if (N0C && !N1C) 1738 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1739 // fold (and x, -1) -> x 1740 if (N1C && N1C->isAllOnesValue()) 1741 return N0; 1742 // if (and x, c) is known to be zero, return 0 1743 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1744 APInt::getAllOnesValue(BitWidth))) 1745 return DAG.getConstant(0, VT); 1746 // reassociate and 1747 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1748 if (RAND.getNode() != 0) 1749 return RAND; 1750 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1751 if (N1C && N0.getOpcode() == ISD::OR) 1752 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1753 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1754 return N1; 1755 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1756 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1757 SDValue N0Op0 = N0.getOperand(0); 1758 APInt Mask = ~N1C->getAPIntValue(); 1759 Mask.trunc(N0Op0.getValueSizeInBits()); 1760 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1761 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1762 N0.getValueType(), N0Op0); 1763 1764 // Replace uses of the AND with uses of the Zero extend node. 1765 CombineTo(N, Zext); 1766 1767 // We actually want to replace all uses of the any_extend with the 1768 // zero_extend, to avoid duplicating things. This will later cause this 1769 // AND to be folded. 1770 CombineTo(N0.getNode(), Zext); 1771 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1772 } 1773 } 1774 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1775 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1776 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1777 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1778 1779 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1780 LL.getValueType().isInteger()) { 1781 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1782 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1783 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1784 LR.getValueType(), LL, RL); 1785 AddToWorkList(ORNode.getNode()); 1786 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1787 } 1788 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1789 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1790 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1791 LR.getValueType(), LL, RL); 1792 AddToWorkList(ANDNode.getNode()); 1793 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1794 } 1795 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1796 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1797 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1798 LR.getValueType(), LL, RL); 1799 AddToWorkList(ORNode.getNode()); 1800 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1801 } 1802 } 1803 // canonicalize equivalent to ll == rl 1804 if (LL == RR && LR == RL) { 1805 Op1 = ISD::getSetCCSwappedOperands(Op1); 1806 std::swap(RL, RR); 1807 } 1808 if (LL == RL && LR == RR) { 1809 bool isInteger = LL.getValueType().isInteger(); 1810 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1811 if (Result != ISD::SETCC_INVALID && 1812 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1813 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1814 LL, LR, Result); 1815 } 1816 } 1817 1818 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1819 if (N0.getOpcode() == N1.getOpcode()) { 1820 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1821 if (Tmp.getNode()) return Tmp; 1822 } 1823 1824 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1825 // fold (and (sra)) -> (and (srl)) when possible. 1826 if (!VT.isVector() && 1827 SimplifyDemandedBits(SDValue(N, 0))) 1828 return SDValue(N, 0); 1829 // fold (zext_inreg (extload x)) -> (zextload x) 1830 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1831 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1832 EVT EVT = LN0->getMemoryVT(); 1833 // If we zero all the possible extended bits, then we can turn this into 1834 // a zextload if we are running before legalize or the operation is legal. 1835 unsigned BitWidth = N1.getValueSizeInBits(); 1836 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1837 BitWidth - EVT.getSizeInBits())) && 1838 ((!LegalOperations && !LN0->isVolatile()) || 1839 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1840 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1841 LN0->getChain(), LN0->getBasePtr(), 1842 LN0->getSrcValue(), 1843 LN0->getSrcValueOffset(), EVT, 1844 LN0->isVolatile(), LN0->getAlignment()); 1845 AddToWorkList(N); 1846 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1847 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1848 } 1849 } 1850 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1851 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1852 N0.hasOneUse()) { 1853 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1854 EVT EVT = LN0->getMemoryVT(); 1855 // If we zero all the possible extended bits, then we can turn this into 1856 // a zextload if we are running before legalize or the operation is legal. 1857 unsigned BitWidth = N1.getValueSizeInBits(); 1858 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1859 BitWidth - EVT.getSizeInBits())) && 1860 ((!LegalOperations && !LN0->isVolatile()) || 1861 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1862 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1863 LN0->getChain(), 1864 LN0->getBasePtr(), LN0->getSrcValue(), 1865 LN0->getSrcValueOffset(), EVT, 1866 LN0->isVolatile(), LN0->getAlignment()); 1867 AddToWorkList(N); 1868 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1869 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1870 } 1871 } 1872 1873 // fold (and (load x), 255) -> (zextload x, i8) 1874 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1875 if (N1C && N0.getOpcode() == ISD::LOAD) { 1876 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1877 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1878 LN0->isUnindexed() && N0.hasOneUse() && 1879 // Do not change the width of a volatile load. 1880 !LN0->isVolatile()) { 1881 EVT ExtVT = MVT::Other; 1882 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1883 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1884 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 1885 1886 EVT LoadedVT = LN0->getMemoryVT(); 1887 1888 // Do not generate loads of non-round integer types since these can 1889 // be expensive (and would be wrong if the type is not byte sized). 1890 if (ExtVT != MVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 1891 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1892 EVT PtrType = N0.getOperand(1).getValueType(); 1893 1894 // For big endian targets, we need to add an offset to the pointer to 1895 // load the correct bytes. For little endian systems, we merely need to 1896 // read fewer bytes from the same pointer. 1897 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1898 unsigned EVTStoreBytes = ExtVT.getStoreSizeInBits()/8; 1899 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1900 unsigned Alignment = LN0->getAlignment(); 1901 SDValue NewPtr = LN0->getBasePtr(); 1902 1903 if (TLI.isBigEndian()) { 1904 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1905 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1906 Alignment = MinAlign(Alignment, PtrOff); 1907 } 1908 1909 AddToWorkList(NewPtr.getNode()); 1910 SDValue Load = 1911 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1912 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1913 ExtVT, LN0->isVolatile(), Alignment); 1914 AddToWorkList(N); 1915 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1916 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1917 } 1918 } 1919 } 1920 1921 return SDValue(); 1922} 1923 1924SDValue DAGCombiner::visitOR(SDNode *N) { 1925 SDValue N0 = N->getOperand(0); 1926 SDValue N1 = N->getOperand(1); 1927 SDValue LL, LR, RL, RR, CC0, CC1; 1928 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1929 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1930 EVT VT = N1.getValueType(); 1931 1932 // fold vector ops 1933 if (VT.isVector()) { 1934 SDValue FoldedVOp = SimplifyVBinOp(N); 1935 if (FoldedVOp.getNode()) return FoldedVOp; 1936 } 1937 1938 // fold (or x, undef) -> -1 1939 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1940 return DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 1941 // fold (or c1, c2) -> c1|c2 1942 if (N0C && N1C) 1943 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1944 // canonicalize constant to RHS 1945 if (N0C && !N1C) 1946 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1947 // fold (or x, 0) -> x 1948 if (N1C && N1C->isNullValue()) 1949 return N0; 1950 // fold (or x, -1) -> -1 1951 if (N1C && N1C->isAllOnesValue()) 1952 return N1; 1953 // fold (or x, c) -> c iff (x & ~c) == 0 1954 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1955 return N1; 1956 // reassociate or 1957 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1958 if (ROR.getNode() != 0) 1959 return ROR; 1960 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1961 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1962 isa<ConstantSDNode>(N0.getOperand(1))) { 1963 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1964 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1965 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1966 N0.getOperand(0), N1), 1967 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1968 } 1969 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1970 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1971 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1972 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1973 1974 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1975 LL.getValueType().isInteger()) { 1976 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1977 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1978 if (cast<ConstantSDNode>(LR)->isNullValue() && 1979 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1980 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1981 LR.getValueType(), LL, RL); 1982 AddToWorkList(ORNode.getNode()); 1983 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1984 } 1985 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 1986 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 1987 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1988 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1989 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 1990 LR.getValueType(), LL, RL); 1991 AddToWorkList(ANDNode.getNode()); 1992 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1993 } 1994 } 1995 // canonicalize equivalent to ll == rl 1996 if (LL == RR && LR == RL) { 1997 Op1 = ISD::getSetCCSwappedOperands(Op1); 1998 std::swap(RL, RR); 1999 } 2000 if (LL == RL && LR == RR) { 2001 bool isInteger = LL.getValueType().isInteger(); 2002 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2003 if (Result != ISD::SETCC_INVALID && 2004 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2005 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2006 LL, LR, Result); 2007 } 2008 } 2009 2010 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2011 if (N0.getOpcode() == N1.getOpcode()) { 2012 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2013 if (Tmp.getNode()) return Tmp; 2014 } 2015 2016 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2017 if (N0.getOpcode() == ISD::AND && 2018 N1.getOpcode() == ISD::AND && 2019 N0.getOperand(1).getOpcode() == ISD::Constant && 2020 N1.getOperand(1).getOpcode() == ISD::Constant && 2021 // Don't increase # computations. 2022 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2023 // We can only do this xform if we know that bits from X that are set in C2 2024 // but not in C1 are already zero. Likewise for Y. 2025 const APInt &LHSMask = 2026 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2027 const APInt &RHSMask = 2028 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2029 2030 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2031 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2032 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2033 N0.getOperand(0), N1.getOperand(0)); 2034 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2035 DAG.getConstant(LHSMask | RHSMask, VT)); 2036 } 2037 } 2038 2039 // See if this is some rotate idiom. 2040 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2041 return SDValue(Rot, 0); 2042 2043 return SDValue(); 2044} 2045 2046/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2047static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2048 if (Op.getOpcode() == ISD::AND) { 2049 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2050 Mask = Op.getOperand(1); 2051 Op = Op.getOperand(0); 2052 } else { 2053 return false; 2054 } 2055 } 2056 2057 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2058 Shift = Op; 2059 return true; 2060 } 2061 2062 return false; 2063} 2064 2065// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2066// idioms for rotate, and if the target supports rotation instructions, generate 2067// a rot[lr]. 2068SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2069 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2070 EVT VT = LHS.getValueType(); 2071 if (!TLI.isTypeLegal(VT)) return 0; 2072 2073 // The target must have at least one rotate flavor. 2074 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2075 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2076 if (!HasROTL && !HasROTR) return 0; 2077 2078 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2079 SDValue LHSShift; // The shift. 2080 SDValue LHSMask; // AND value if any. 2081 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2082 return 0; // Not part of a rotate. 2083 2084 SDValue RHSShift; // The shift. 2085 SDValue RHSMask; // AND value if any. 2086 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2087 return 0; // Not part of a rotate. 2088 2089 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2090 return 0; // Not shifting the same value. 2091 2092 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2093 return 0; // Shifts must disagree. 2094 2095 // Canonicalize shl to left side in a shl/srl pair. 2096 if (RHSShift.getOpcode() == ISD::SHL) { 2097 std::swap(LHS, RHS); 2098 std::swap(LHSShift, RHSShift); 2099 std::swap(LHSMask , RHSMask ); 2100 } 2101 2102 unsigned OpSizeInBits = VT.getSizeInBits(); 2103 SDValue LHSShiftArg = LHSShift.getOperand(0); 2104 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2105 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2106 2107 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2108 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2109 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2110 RHSShiftAmt.getOpcode() == ISD::Constant) { 2111 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2112 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2113 if ((LShVal + RShVal) != OpSizeInBits) 2114 return 0; 2115 2116 SDValue Rot; 2117 if (HasROTL) 2118 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2119 else 2120 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2121 2122 // If there is an AND of either shifted operand, apply it to the result. 2123 if (LHSMask.getNode() || RHSMask.getNode()) { 2124 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2125 2126 if (LHSMask.getNode()) { 2127 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2128 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2129 } 2130 if (RHSMask.getNode()) { 2131 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2132 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2133 } 2134 2135 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2136 } 2137 2138 return Rot.getNode(); 2139 } 2140 2141 // If there is a mask here, and we have a variable shift, we can't be sure 2142 // that we're masking out the right stuff. 2143 if (LHSMask.getNode() || RHSMask.getNode()) 2144 return 0; 2145 2146 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2147 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2148 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2149 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2150 if (ConstantSDNode *SUBC = 2151 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2152 if (SUBC->getAPIntValue() == OpSizeInBits) { 2153 if (HasROTL) 2154 return DAG.getNode(ISD::ROTL, DL, VT, 2155 LHSShiftArg, LHSShiftAmt).getNode(); 2156 else 2157 return DAG.getNode(ISD::ROTR, DL, VT, 2158 LHSShiftArg, RHSShiftAmt).getNode(); 2159 } 2160 } 2161 } 2162 2163 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2164 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2165 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2166 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2167 if (ConstantSDNode *SUBC = 2168 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2169 if (SUBC->getAPIntValue() == OpSizeInBits) { 2170 if (HasROTR) 2171 return DAG.getNode(ISD::ROTR, DL, VT, 2172 LHSShiftArg, RHSShiftAmt).getNode(); 2173 else 2174 return DAG.getNode(ISD::ROTL, DL, VT, 2175 LHSShiftArg, LHSShiftAmt).getNode(); 2176 } 2177 } 2178 } 2179 2180 // Look for sign/zext/any-extended or truncate cases: 2181 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2182 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2183 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2184 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2185 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2186 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2187 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2188 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2189 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2190 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2191 if (RExtOp0.getOpcode() == ISD::SUB && 2192 RExtOp0.getOperand(1) == LExtOp0) { 2193 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2194 // (rotl x, y) 2195 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2196 // (rotr x, (sub 32, y)) 2197 if (ConstantSDNode *SUBC = 2198 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2199 if (SUBC->getAPIntValue() == OpSizeInBits) { 2200 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2201 LHSShiftArg, 2202 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2203 } 2204 } 2205 } else if (LExtOp0.getOpcode() == ISD::SUB && 2206 RExtOp0 == LExtOp0.getOperand(1)) { 2207 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2208 // (rotr x, y) 2209 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2210 // (rotl x, (sub 32, y)) 2211 if (ConstantSDNode *SUBC = 2212 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2213 if (SUBC->getAPIntValue() == OpSizeInBits) { 2214 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2215 LHSShiftArg, 2216 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2217 } 2218 } 2219 } 2220 } 2221 2222 return 0; 2223} 2224 2225SDValue DAGCombiner::visitXOR(SDNode *N) { 2226 SDValue N0 = N->getOperand(0); 2227 SDValue N1 = N->getOperand(1); 2228 SDValue LHS, RHS, CC; 2229 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2230 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2231 EVT VT = N0.getValueType(); 2232 2233 // fold vector ops 2234 if (VT.isVector()) { 2235 SDValue FoldedVOp = SimplifyVBinOp(N); 2236 if (FoldedVOp.getNode()) return FoldedVOp; 2237 } 2238 2239 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2240 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2241 return DAG.getConstant(0, VT); 2242 // fold (xor x, undef) -> undef 2243 if (N0.getOpcode() == ISD::UNDEF) 2244 return N0; 2245 if (N1.getOpcode() == ISD::UNDEF) 2246 return N1; 2247 // fold (xor c1, c2) -> c1^c2 2248 if (N0C && N1C) 2249 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2250 // canonicalize constant to RHS 2251 if (N0C && !N1C) 2252 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2253 // fold (xor x, 0) -> x 2254 if (N1C && N1C->isNullValue()) 2255 return N0; 2256 // reassociate xor 2257 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2258 if (RXOR.getNode() != 0) 2259 return RXOR; 2260 2261 // fold !(x cc y) -> (x !cc y) 2262 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2263 bool isInt = LHS.getValueType().isInteger(); 2264 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2265 isInt); 2266 2267 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2268 switch (N0.getOpcode()) { 2269 default: 2270 llvm_unreachable("Unhandled SetCC Equivalent!"); 2271 case ISD::SETCC: 2272 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2273 case ISD::SELECT_CC: 2274 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2275 N0.getOperand(3), NotCC); 2276 } 2277 } 2278 } 2279 2280 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2281 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2282 N0.getNode()->hasOneUse() && 2283 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2284 SDValue V = N0.getOperand(0); 2285 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2286 DAG.getConstant(1, V.getValueType())); 2287 AddToWorkList(V.getNode()); 2288 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2289 } 2290 2291 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2292 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2293 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2294 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2295 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2296 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2297 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2298 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2299 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2300 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2301 } 2302 } 2303 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2304 if (N1C && N1C->isAllOnesValue() && 2305 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2306 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2307 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2308 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2309 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2310 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2311 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2312 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2313 } 2314 } 2315 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2316 if (N1C && N0.getOpcode() == ISD::XOR) { 2317 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2318 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2319 if (N00C) 2320 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2321 DAG.getConstant(N1C->getAPIntValue() ^ 2322 N00C->getAPIntValue(), VT)); 2323 if (N01C) 2324 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2325 DAG.getConstant(N1C->getAPIntValue() ^ 2326 N01C->getAPIntValue(), VT)); 2327 } 2328 // fold (xor x, x) -> 0 2329 if (N0 == N1) { 2330 if (!VT.isVector()) { 2331 return DAG.getConstant(0, VT); 2332 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2333 // Produce a vector of zeros. 2334 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2335 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2336 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2337 &Ops[0], Ops.size()); 2338 } 2339 } 2340 2341 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2342 if (N0.getOpcode() == N1.getOpcode()) { 2343 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2344 if (Tmp.getNode()) return Tmp; 2345 } 2346 2347 // Simplify the expression using non-local knowledge. 2348 if (!VT.isVector() && 2349 SimplifyDemandedBits(SDValue(N, 0))) 2350 return SDValue(N, 0); 2351 2352 return SDValue(); 2353} 2354 2355/// visitShiftByConstant - Handle transforms common to the three shifts, when 2356/// the shift amount is a constant. 2357SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2358 SDNode *LHS = N->getOperand(0).getNode(); 2359 if (!LHS->hasOneUse()) return SDValue(); 2360 2361 // We want to pull some binops through shifts, so that we have (and (shift)) 2362 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2363 // thing happens with address calculations, so it's important to canonicalize 2364 // it. 2365 bool HighBitSet = false; // Can we transform this if the high bit is set? 2366 2367 switch (LHS->getOpcode()) { 2368 default: return SDValue(); 2369 case ISD::OR: 2370 case ISD::XOR: 2371 HighBitSet = false; // We can only transform sra if the high bit is clear. 2372 break; 2373 case ISD::AND: 2374 HighBitSet = true; // We can only transform sra if the high bit is set. 2375 break; 2376 case ISD::ADD: 2377 if (N->getOpcode() != ISD::SHL) 2378 return SDValue(); // only shl(add) not sr[al](add). 2379 HighBitSet = false; // We can only transform sra if the high bit is clear. 2380 break; 2381 } 2382 2383 // We require the RHS of the binop to be a constant as well. 2384 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2385 if (!BinOpCst) return SDValue(); 2386 2387 // FIXME: disable this unless the input to the binop is a shift by a constant. 2388 // If it is not a shift, it pessimizes some common cases like: 2389 // 2390 // void foo(int *X, int i) { X[i & 1235] = 1; } 2391 // int bar(int *X, int i) { return X[i & 255]; } 2392 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2393 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2394 BinOpLHSVal->getOpcode() != ISD::SRA && 2395 BinOpLHSVal->getOpcode() != ISD::SRL) || 2396 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2397 return SDValue(); 2398 2399 EVT VT = N->getValueType(0); 2400 2401 // If this is a signed shift right, and the high bit is modified by the 2402 // logical operation, do not perform the transformation. The highBitSet 2403 // boolean indicates the value of the high bit of the constant which would 2404 // cause it to be modified for this operation. 2405 if (N->getOpcode() == ISD::SRA) { 2406 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2407 if (BinOpRHSSignSet != HighBitSet) 2408 return SDValue(); 2409 } 2410 2411 // Fold the constants, shifting the binop RHS by the shift amount. 2412 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2413 N->getValueType(0), 2414 LHS->getOperand(1), N->getOperand(1)); 2415 2416 // Create the new shift. 2417 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2418 VT, LHS->getOperand(0), N->getOperand(1)); 2419 2420 // Create the new binop. 2421 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2422} 2423 2424SDValue DAGCombiner::visitSHL(SDNode *N) { 2425 SDValue N0 = N->getOperand(0); 2426 SDValue N1 = N->getOperand(1); 2427 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2428 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2429 EVT VT = N0.getValueType(); 2430 unsigned OpSizeInBits = VT.getSizeInBits(); 2431 2432 // fold (shl c1, c2) -> c1<<c2 2433 if (N0C && N1C) 2434 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2435 // fold (shl 0, x) -> 0 2436 if (N0C && N0C->isNullValue()) 2437 return N0; 2438 // fold (shl x, c >= size(x)) -> undef 2439 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2440 return DAG.getUNDEF(VT); 2441 // fold (shl x, 0) -> x 2442 if (N1C && N1C->isNullValue()) 2443 return N0; 2444 // if (shl x, c) is known to be zero, return 0 2445 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2446 APInt::getAllOnesValue(VT.getSizeInBits()))) 2447 return DAG.getConstant(0, VT); 2448 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2449 if (N1.getOpcode() == ISD::TRUNCATE && 2450 N1.getOperand(0).getOpcode() == ISD::AND && 2451 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2452 SDValue N101 = N1.getOperand(0).getOperand(1); 2453 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2454 EVT TruncVT = N1.getValueType(); 2455 SDValue N100 = N1.getOperand(0).getOperand(0); 2456 APInt TruncC = N101C->getAPIntValue(); 2457 TruncC.trunc(TruncVT.getSizeInBits()); 2458 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2459 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2460 DAG.getNode(ISD::TRUNCATE, 2461 N->getDebugLoc(), 2462 TruncVT, N100), 2463 DAG.getConstant(TruncC, TruncVT))); 2464 } 2465 } 2466 2467 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2468 return SDValue(N, 0); 2469 2470 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2471 if (N1C && N0.getOpcode() == ISD::SHL && 2472 N0.getOperand(1).getOpcode() == ISD::Constant) { 2473 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2474 uint64_t c2 = N1C->getZExtValue(); 2475 if (c1 + c2 > OpSizeInBits) 2476 return DAG.getConstant(0, VT); 2477 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2478 DAG.getConstant(c1 + c2, N1.getValueType())); 2479 } 2480 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2481 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2482 if (N1C && N0.getOpcode() == ISD::SRL && 2483 N0.getOperand(1).getOpcode() == ISD::Constant) { 2484 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2485 if (c1 < VT.getSizeInBits()) { 2486 uint64_t c2 = N1C->getZExtValue(); 2487 SDValue HiBitsMask = 2488 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2489 VT.getSizeInBits() - c1), 2490 VT); 2491 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2492 N0.getOperand(0), 2493 HiBitsMask); 2494 if (c2 > c1) 2495 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2496 DAG.getConstant(c2-c1, N1.getValueType())); 2497 else 2498 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2499 DAG.getConstant(c1-c2, N1.getValueType())); 2500 } 2501 } 2502 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2503 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2504 SDValue HiBitsMask = 2505 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2506 VT.getSizeInBits() - 2507 N1C->getZExtValue()), 2508 VT); 2509 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2510 HiBitsMask); 2511 } 2512 2513 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2514} 2515 2516SDValue DAGCombiner::visitSRA(SDNode *N) { 2517 SDValue N0 = N->getOperand(0); 2518 SDValue N1 = N->getOperand(1); 2519 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2521 EVT VT = N0.getValueType(); 2522 2523 // fold (sra c1, c2) -> (sra c1, c2) 2524 if (N0C && N1C) 2525 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2526 // fold (sra 0, x) -> 0 2527 if (N0C && N0C->isNullValue()) 2528 return N0; 2529 // fold (sra -1, x) -> -1 2530 if (N0C && N0C->isAllOnesValue()) 2531 return N0; 2532 // fold (sra x, (setge c, size(x))) -> undef 2533 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2534 return DAG.getUNDEF(VT); 2535 // fold (sra x, 0) -> x 2536 if (N1C && N1C->isNullValue()) 2537 return N0; 2538 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2539 // sext_inreg. 2540 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2541 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2542 EVT EVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2543 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2544 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2545 N0.getOperand(0), DAG.getValueType(EVT)); 2546 } 2547 2548 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2549 if (N1C && N0.getOpcode() == ISD::SRA) { 2550 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2551 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2552 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2553 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2554 DAG.getConstant(Sum, N1C->getValueType(0))); 2555 } 2556 } 2557 2558 // fold (sra (shl X, m), (sub result_size, n)) 2559 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2560 // result_size - n != m. 2561 // If truncate is free for the target sext(shl) is likely to result in better 2562 // code. 2563 if (N0.getOpcode() == ISD::SHL) { 2564 // Get the two constanst of the shifts, CN0 = m, CN = n. 2565 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2566 if (N01C && N1C) { 2567 // Determine what the truncate's result bitsize and type would be. 2568 unsigned VTValSize = VT.getSizeInBits(); 2569 EVT TruncVT = 2570 EVT::getIntegerVT(*DAG.getContext(), VTValSize - N1C->getZExtValue()); 2571 // Determine the residual right-shift amount. 2572 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2573 2574 // If the shift is not a no-op (in which case this should be just a sign 2575 // extend already), the truncated to type is legal, sign_extend is legal 2576 // on that type, and the the truncate to that type is both legal and free, 2577 // perform the transform. 2578 if ((ShiftAmt > 0) && 2579 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2580 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2581 TLI.isTruncateFree(VT, TruncVT)) { 2582 2583 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2584 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2585 N0.getOperand(0), Amt); 2586 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2587 Shift); 2588 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2589 N->getValueType(0), Trunc); 2590 } 2591 } 2592 } 2593 2594 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2595 if (N1.getOpcode() == ISD::TRUNCATE && 2596 N1.getOperand(0).getOpcode() == ISD::AND && 2597 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2598 SDValue N101 = N1.getOperand(0).getOperand(1); 2599 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2600 EVT TruncVT = N1.getValueType(); 2601 SDValue N100 = N1.getOperand(0).getOperand(0); 2602 APInt TruncC = N101C->getAPIntValue(); 2603 TruncC.trunc(TruncVT.getSizeInBits()); 2604 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2605 DAG.getNode(ISD::AND, N->getDebugLoc(), 2606 TruncVT, 2607 DAG.getNode(ISD::TRUNCATE, 2608 N->getDebugLoc(), 2609 TruncVT, N100), 2610 DAG.getConstant(TruncC, TruncVT))); 2611 } 2612 } 2613 2614 // Simplify, based on bits shifted out of the LHS. 2615 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2616 return SDValue(N, 0); 2617 2618 2619 // If the sign bit is known to be zero, switch this to a SRL. 2620 if (DAG.SignBitIsZero(N0)) 2621 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2622 2623 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2624} 2625 2626SDValue DAGCombiner::visitSRL(SDNode *N) { 2627 SDValue N0 = N->getOperand(0); 2628 SDValue N1 = N->getOperand(1); 2629 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2630 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2631 EVT VT = N0.getValueType(); 2632 unsigned OpSizeInBits = VT.getSizeInBits(); 2633 2634 // fold (srl c1, c2) -> c1 >>u c2 2635 if (N0C && N1C) 2636 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2637 // fold (srl 0, x) -> 0 2638 if (N0C && N0C->isNullValue()) 2639 return N0; 2640 // fold (srl x, c >= size(x)) -> undef 2641 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2642 return DAG.getUNDEF(VT); 2643 // fold (srl x, 0) -> x 2644 if (N1C && N1C->isNullValue()) 2645 return N0; 2646 // if (srl x, c) is known to be zero, return 0 2647 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2648 APInt::getAllOnesValue(OpSizeInBits))) 2649 return DAG.getConstant(0, VT); 2650 2651 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2652 if (N1C && N0.getOpcode() == ISD::SRL && 2653 N0.getOperand(1).getOpcode() == ISD::Constant) { 2654 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2655 uint64_t c2 = N1C->getZExtValue(); 2656 if (c1 + c2 > OpSizeInBits) 2657 return DAG.getConstant(0, VT); 2658 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2659 DAG.getConstant(c1 + c2, N1.getValueType())); 2660 } 2661 2662 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2663 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2664 // Shifting in all undef bits? 2665 EVT SmallVT = N0.getOperand(0).getValueType(); 2666 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2667 return DAG.getUNDEF(VT); 2668 2669 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2670 N0.getOperand(0), N1); 2671 AddToWorkList(SmallShift.getNode()); 2672 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2673 } 2674 2675 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2676 // bit, which is unmodified by sra. 2677 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2678 if (N0.getOpcode() == ISD::SRA) 2679 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2680 } 2681 2682 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2683 if (N1C && N0.getOpcode() == ISD::CTLZ && 2684 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2685 APInt KnownZero, KnownOne; 2686 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2687 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2688 2689 // If any of the input bits are KnownOne, then the input couldn't be all 2690 // zeros, thus the result of the srl will always be zero. 2691 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2692 2693 // If all of the bits input the to ctlz node are known to be zero, then 2694 // the result of the ctlz is "32" and the result of the shift is one. 2695 APInt UnknownBits = ~KnownZero & Mask; 2696 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2697 2698 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2699 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2700 // Okay, we know that only that the single bit specified by UnknownBits 2701 // could be set on input to the CTLZ node. If this bit is set, the SRL 2702 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2703 // to an SRL/XOR pair, which is likely to simplify more. 2704 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2705 SDValue Op = N0.getOperand(0); 2706 2707 if (ShAmt) { 2708 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2709 DAG.getConstant(ShAmt, getShiftAmountTy())); 2710 AddToWorkList(Op.getNode()); 2711 } 2712 2713 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2714 Op, DAG.getConstant(1, VT)); 2715 } 2716 } 2717 2718 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2719 if (N1.getOpcode() == ISD::TRUNCATE && 2720 N1.getOperand(0).getOpcode() == ISD::AND && 2721 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2722 SDValue N101 = N1.getOperand(0).getOperand(1); 2723 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2724 EVT TruncVT = N1.getValueType(); 2725 SDValue N100 = N1.getOperand(0).getOperand(0); 2726 APInt TruncC = N101C->getAPIntValue(); 2727 TruncC.trunc(TruncVT.getSizeInBits()); 2728 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2729 DAG.getNode(ISD::AND, N->getDebugLoc(), 2730 TruncVT, 2731 DAG.getNode(ISD::TRUNCATE, 2732 N->getDebugLoc(), 2733 TruncVT, N100), 2734 DAG.getConstant(TruncC, TruncVT))); 2735 } 2736 } 2737 2738 // fold operands of srl based on knowledge that the low bits are not 2739 // demanded. 2740 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2741 return SDValue(N, 0); 2742 2743 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2744} 2745 2746SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2747 SDValue N0 = N->getOperand(0); 2748 EVT VT = N->getValueType(0); 2749 2750 // fold (ctlz c1) -> c2 2751 if (isa<ConstantSDNode>(N0)) 2752 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2753 return SDValue(); 2754} 2755 2756SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2757 SDValue N0 = N->getOperand(0); 2758 EVT VT = N->getValueType(0); 2759 2760 // fold (cttz c1) -> c2 2761 if (isa<ConstantSDNode>(N0)) 2762 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2763 return SDValue(); 2764} 2765 2766SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2767 SDValue N0 = N->getOperand(0); 2768 EVT VT = N->getValueType(0); 2769 2770 // fold (ctpop c1) -> c2 2771 if (isa<ConstantSDNode>(N0)) 2772 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2773 return SDValue(); 2774} 2775 2776SDValue DAGCombiner::visitSELECT(SDNode *N) { 2777 SDValue N0 = N->getOperand(0); 2778 SDValue N1 = N->getOperand(1); 2779 SDValue N2 = N->getOperand(2); 2780 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2781 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2782 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2783 EVT VT = N->getValueType(0); 2784 EVT VT0 = N0.getValueType(); 2785 2786 // fold (select C, X, X) -> X 2787 if (N1 == N2) 2788 return N1; 2789 // fold (select true, X, Y) -> X 2790 if (N0C && !N0C->isNullValue()) 2791 return N1; 2792 // fold (select false, X, Y) -> Y 2793 if (N0C && N0C->isNullValue()) 2794 return N2; 2795 // fold (select C, 1, X) -> (or C, X) 2796 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2797 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2798 // fold (select C, 0, 1) -> (xor C, 1) 2799 if (VT.isInteger() && 2800 (VT0 == MVT::i1 || 2801 (VT0.isInteger() && 2802 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2803 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2804 SDValue XORNode; 2805 if (VT == VT0) 2806 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2807 N0, DAG.getConstant(1, VT0)); 2808 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2809 N0, DAG.getConstant(1, VT0)); 2810 AddToWorkList(XORNode.getNode()); 2811 if (VT.bitsGT(VT0)) 2812 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2813 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2814 } 2815 // fold (select C, 0, X) -> (and (not C), X) 2816 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2817 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2818 AddToWorkList(NOTNode.getNode()); 2819 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2820 } 2821 // fold (select C, X, 1) -> (or (not C), X) 2822 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2823 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2824 AddToWorkList(NOTNode.getNode()); 2825 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2826 } 2827 // fold (select C, X, 0) -> (and C, X) 2828 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2829 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2830 // fold (select X, X, Y) -> (or X, Y) 2831 // fold (select X, 1, Y) -> (or X, Y) 2832 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2833 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2834 // fold (select X, Y, X) -> (and X, Y) 2835 // fold (select X, Y, 0) -> (and X, Y) 2836 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2837 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2838 2839 // If we can fold this based on the true/false value, do so. 2840 if (SimplifySelectOps(N, N1, N2)) 2841 return SDValue(N, 0); // Don't revisit N. 2842 2843 // fold selects based on a setcc into other things, such as min/max/abs 2844 if (N0.getOpcode() == ISD::SETCC) { 2845 // FIXME: 2846 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2847 // having to say they don't support SELECT_CC on every type the DAG knows 2848 // about, since there is no way to mark an opcode illegal at all value types 2849 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2850 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2851 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2852 N0.getOperand(0), N0.getOperand(1), 2853 N1, N2, N0.getOperand(2)); 2854 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2855 } 2856 2857 return SDValue(); 2858} 2859 2860SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2861 SDValue N0 = N->getOperand(0); 2862 SDValue N1 = N->getOperand(1); 2863 SDValue N2 = N->getOperand(2); 2864 SDValue N3 = N->getOperand(3); 2865 SDValue N4 = N->getOperand(4); 2866 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2867 2868 // fold select_cc lhs, rhs, x, x, cc -> x 2869 if (N2 == N3) 2870 return N2; 2871 2872 // Determine if the condition we're dealing with is constant 2873 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2874 N0, N1, CC, N->getDebugLoc(), false); 2875 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2876 2877 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2878 if (!SCCC->isNullValue()) 2879 return N2; // cond always true -> true val 2880 else 2881 return N3; // cond always false -> false val 2882 } 2883 2884 // Fold to a simpler select_cc 2885 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2886 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2887 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2888 SCC.getOperand(2)); 2889 2890 // If we can fold this based on the true/false value, do so. 2891 if (SimplifySelectOps(N, N2, N3)) 2892 return SDValue(N, 0); // Don't revisit N. 2893 2894 // fold select_cc into other things, such as min/max/abs 2895 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2896} 2897 2898SDValue DAGCombiner::visitSETCC(SDNode *N) { 2899 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2900 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2901 N->getDebugLoc()); 2902} 2903 2904// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2905// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2906// transformation. Returns true if extension are possible and the above 2907// mentioned transformation is profitable. 2908static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2909 unsigned ExtOpc, 2910 SmallVector<SDNode*, 4> &ExtendNodes, 2911 const TargetLowering &TLI) { 2912 bool HasCopyToRegUses = false; 2913 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2914 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2915 UE = N0.getNode()->use_end(); 2916 UI != UE; ++UI) { 2917 SDNode *User = *UI; 2918 if (User == N) 2919 continue; 2920 if (UI.getUse().getResNo() != N0.getResNo()) 2921 continue; 2922 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2923 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 2924 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2925 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2926 // Sign bits will be lost after a zext. 2927 return false; 2928 bool Add = false; 2929 for (unsigned i = 0; i != 2; ++i) { 2930 SDValue UseOp = User->getOperand(i); 2931 if (UseOp == N0) 2932 continue; 2933 if (!isa<ConstantSDNode>(UseOp)) 2934 return false; 2935 Add = true; 2936 } 2937 if (Add) 2938 ExtendNodes.push_back(User); 2939 continue; 2940 } 2941 // If truncates aren't free and there are users we can't 2942 // extend, it isn't worthwhile. 2943 if (!isTruncFree) 2944 return false; 2945 // Remember if this value is live-out. 2946 if (User->getOpcode() == ISD::CopyToReg) 2947 HasCopyToRegUses = true; 2948 } 2949 2950 if (HasCopyToRegUses) { 2951 bool BothLiveOut = false; 2952 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2953 UI != UE; ++UI) { 2954 SDUse &Use = UI.getUse(); 2955 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 2956 BothLiveOut = true; 2957 break; 2958 } 2959 } 2960 if (BothLiveOut) 2961 // Both unextended and extended values are live out. There had better be 2962 // good a reason for the transformation. 2963 return ExtendNodes.size(); 2964 } 2965 return true; 2966} 2967 2968SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2969 SDValue N0 = N->getOperand(0); 2970 EVT VT = N->getValueType(0); 2971 2972 // fold (sext c1) -> c1 2973 if (isa<ConstantSDNode>(N0)) 2974 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2975 2976 // fold (sext (sext x)) -> (sext x) 2977 // fold (sext (aext x)) -> (sext x) 2978 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2979 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2980 N0.getOperand(0)); 2981 2982 if (N0.getOpcode() == ISD::TRUNCATE) { 2983 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2984 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2985 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2986 if (NarrowLoad.getNode()) { 2987 if (NarrowLoad.getNode() != N0.getNode()) 2988 CombineTo(N0.getNode(), NarrowLoad); 2989 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2990 } 2991 2992 // See if the value being truncated is already sign extended. If so, just 2993 // eliminate the trunc/sext pair. 2994 SDValue Op = N0.getOperand(0); 2995 unsigned OpBits = Op.getValueType().getSizeInBits(); 2996 unsigned MidBits = N0.getValueType().getSizeInBits(); 2997 unsigned DestBits = VT.getSizeInBits(); 2998 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2999 3000 if (OpBits == DestBits) { 3001 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3002 // bits, it is already ready. 3003 if (NumSignBits > DestBits-MidBits) 3004 return Op; 3005 } else if (OpBits < DestBits) { 3006 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3007 // bits, just sext from i32. 3008 if (NumSignBits > OpBits-MidBits) 3009 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3010 } else { 3011 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3012 // bits, just truncate to i32. 3013 if (NumSignBits > OpBits-MidBits) 3014 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3015 } 3016 3017 // fold (sext (truncate x)) -> (sextinreg x). 3018 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3019 N0.getValueType())) { 3020 if (Op.getValueType().bitsLT(VT)) 3021 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3022 else if (Op.getValueType().bitsGT(VT)) 3023 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3024 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3025 DAG.getValueType(N0.getValueType())); 3026 } 3027 } 3028 3029 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3030 if (ISD::isNON_EXTLoad(N0.getNode()) && 3031 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3032 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3033 bool DoXform = true; 3034 SmallVector<SDNode*, 4> SetCCs; 3035 if (!N0.hasOneUse()) 3036 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3037 if (DoXform) { 3038 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3039 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3040 LN0->getChain(), 3041 LN0->getBasePtr(), LN0->getSrcValue(), 3042 LN0->getSrcValueOffset(), 3043 N0.getValueType(), 3044 LN0->isVolatile(), LN0->getAlignment()); 3045 CombineTo(N, ExtLoad); 3046 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3047 N0.getValueType(), ExtLoad); 3048 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3049 3050 // Extend SetCC uses if necessary. 3051 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3052 SDNode *SetCC = SetCCs[i]; 3053 SmallVector<SDValue, 4> Ops; 3054 3055 for (unsigned j = 0; j != 2; ++j) { 3056 SDValue SOp = SetCC->getOperand(j); 3057 if (SOp == Trunc) 3058 Ops.push_back(ExtLoad); 3059 else 3060 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3061 N->getDebugLoc(), VT, SOp)); 3062 } 3063 3064 Ops.push_back(SetCC->getOperand(2)); 3065 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3066 SetCC->getValueType(0), 3067 &Ops[0], Ops.size())); 3068 } 3069 3070 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3071 } 3072 } 3073 3074 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3075 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3076 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3077 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3078 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3079 EVT EVT = LN0->getMemoryVT(); 3080 if ((!LegalOperations && !LN0->isVolatile()) || 3081 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3082 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3083 LN0->getChain(), 3084 LN0->getBasePtr(), LN0->getSrcValue(), 3085 LN0->getSrcValueOffset(), EVT, 3086 LN0->isVolatile(), LN0->getAlignment()); 3087 CombineTo(N, ExtLoad); 3088 CombineTo(N0.getNode(), 3089 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3090 N0.getValueType(), ExtLoad), 3091 ExtLoad.getValue(1)); 3092 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3093 } 3094 } 3095 3096 if (N0.getOpcode() == ISD::SETCC) { 3097 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3098 if (VT.isVector() && 3099 // We know that the # elements of the results is the same as the 3100 // # elements of the compare (and the # elements of the compare result 3101 // for that matter). Check to see that they are the same size. If so, 3102 // we know that the element size of the sext'd result matches the 3103 // element size of the compare operands. 3104 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3105 3106 // Only do this before legalize for now. 3107 !LegalOperations) { 3108 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3109 N0.getOperand(1), 3110 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3111 } 3112 3113 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3114 SDValue NegOne = 3115 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3116 SDValue SCC = 3117 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3118 NegOne, DAG.getConstant(0, VT), 3119 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3120 if (SCC.getNode()) return SCC; 3121 } 3122 3123 3124 3125 // fold (sext x) -> (zext x) if the sign bit is known zero. 3126 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3127 DAG.SignBitIsZero(N0)) 3128 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3129 3130 return SDValue(); 3131} 3132 3133SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3134 SDValue N0 = N->getOperand(0); 3135 EVT VT = N->getValueType(0); 3136 3137 // fold (zext c1) -> c1 3138 if (isa<ConstantSDNode>(N0)) 3139 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3140 // fold (zext (zext x)) -> (zext x) 3141 // fold (zext (aext x)) -> (zext x) 3142 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3143 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3144 N0.getOperand(0)); 3145 3146 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3147 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3148 if (N0.getOpcode() == ISD::TRUNCATE) { 3149 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3150 if (NarrowLoad.getNode()) { 3151 if (NarrowLoad.getNode() != N0.getNode()) 3152 CombineTo(N0.getNode(), NarrowLoad); 3153 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3154 } 3155 } 3156 3157 // fold (zext (truncate x)) -> (and x, mask) 3158 if (N0.getOpcode() == ISD::TRUNCATE && 3159 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3160 SDValue Op = N0.getOperand(0); 3161 if (Op.getValueType().bitsLT(VT)) { 3162 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3163 } else if (Op.getValueType().bitsGT(VT)) { 3164 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3165 } 3166 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3167 } 3168 3169 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3170 // if either of the casts is not free. 3171 if (N0.getOpcode() == ISD::AND && 3172 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3173 N0.getOperand(1).getOpcode() == ISD::Constant && 3174 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3175 N0.getValueType()) || 3176 !TLI.isZExtFree(N0.getValueType(), VT))) { 3177 SDValue X = N0.getOperand(0).getOperand(0); 3178 if (X.getValueType().bitsLT(VT)) { 3179 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3180 } else if (X.getValueType().bitsGT(VT)) { 3181 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3182 } 3183 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3184 Mask.zext(VT.getSizeInBits()); 3185 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3186 X, DAG.getConstant(Mask, VT)); 3187 } 3188 3189 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3190 if (ISD::isNON_EXTLoad(N0.getNode()) && 3191 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3192 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3193 bool DoXform = true; 3194 SmallVector<SDNode*, 4> SetCCs; 3195 if (!N0.hasOneUse()) 3196 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3197 if (DoXform) { 3198 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3199 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3200 LN0->getChain(), 3201 LN0->getBasePtr(), LN0->getSrcValue(), 3202 LN0->getSrcValueOffset(), 3203 N0.getValueType(), 3204 LN0->isVolatile(), LN0->getAlignment()); 3205 CombineTo(N, ExtLoad); 3206 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3207 N0.getValueType(), ExtLoad); 3208 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3209 3210 // Extend SetCC uses if necessary. 3211 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3212 SDNode *SetCC = SetCCs[i]; 3213 SmallVector<SDValue, 4> Ops; 3214 3215 for (unsigned j = 0; j != 2; ++j) { 3216 SDValue SOp = SetCC->getOperand(j); 3217 if (SOp == Trunc) 3218 Ops.push_back(ExtLoad); 3219 else 3220 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3221 N->getDebugLoc(), VT, SOp)); 3222 } 3223 3224 Ops.push_back(SetCC->getOperand(2)); 3225 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3226 SetCC->getValueType(0), 3227 &Ops[0], Ops.size())); 3228 } 3229 3230 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3231 } 3232 } 3233 3234 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3235 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3236 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3237 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3238 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3239 EVT EVT = LN0->getMemoryVT(); 3240 if ((!LegalOperations && !LN0->isVolatile()) || 3241 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3242 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3243 LN0->getChain(), 3244 LN0->getBasePtr(), LN0->getSrcValue(), 3245 LN0->getSrcValueOffset(), EVT, 3246 LN0->isVolatile(), LN0->getAlignment()); 3247 CombineTo(N, ExtLoad); 3248 CombineTo(N0.getNode(), 3249 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3250 ExtLoad), 3251 ExtLoad.getValue(1)); 3252 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3253 } 3254 } 3255 3256 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3257 if (N0.getOpcode() == ISD::SETCC) { 3258 SDValue SCC = 3259 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3260 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3261 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3262 if (SCC.getNode()) return SCC; 3263 } 3264 3265 return SDValue(); 3266} 3267 3268SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3269 SDValue N0 = N->getOperand(0); 3270 EVT VT = N->getValueType(0); 3271 3272 // fold (aext c1) -> c1 3273 if (isa<ConstantSDNode>(N0)) 3274 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3275 // fold (aext (aext x)) -> (aext x) 3276 // fold (aext (zext x)) -> (zext x) 3277 // fold (aext (sext x)) -> (sext x) 3278 if (N0.getOpcode() == ISD::ANY_EXTEND || 3279 N0.getOpcode() == ISD::ZERO_EXTEND || 3280 N0.getOpcode() == ISD::SIGN_EXTEND) 3281 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3282 3283 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3284 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3285 if (N0.getOpcode() == ISD::TRUNCATE) { 3286 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3287 if (NarrowLoad.getNode()) { 3288 if (NarrowLoad.getNode() != N0.getNode()) 3289 CombineTo(N0.getNode(), NarrowLoad); 3290 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3291 } 3292 } 3293 3294 // fold (aext (truncate x)) 3295 if (N0.getOpcode() == ISD::TRUNCATE) { 3296 SDValue TruncOp = N0.getOperand(0); 3297 if (TruncOp.getValueType() == VT) 3298 return TruncOp; // x iff x size == zext size. 3299 if (TruncOp.getValueType().bitsGT(VT)) 3300 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3301 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3302 } 3303 3304 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3305 // if the trunc is not free. 3306 if (N0.getOpcode() == ISD::AND && 3307 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3308 N0.getOperand(1).getOpcode() == ISD::Constant && 3309 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3310 N0.getValueType())) { 3311 SDValue X = N0.getOperand(0).getOperand(0); 3312 if (X.getValueType().bitsLT(VT)) { 3313 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3314 } else if (X.getValueType().bitsGT(VT)) { 3315 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3316 } 3317 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3318 Mask.zext(VT.getSizeInBits()); 3319 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3320 X, DAG.getConstant(Mask, VT)); 3321 } 3322 3323 // fold (aext (load x)) -> (aext (truncate (extload x))) 3324 if (ISD::isNON_EXTLoad(N0.getNode()) && 3325 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3326 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3327 bool DoXform = true; 3328 SmallVector<SDNode*, 4> SetCCs; 3329 if (!N0.hasOneUse()) 3330 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3331 if (DoXform) { 3332 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3333 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3334 LN0->getChain(), 3335 LN0->getBasePtr(), LN0->getSrcValue(), 3336 LN0->getSrcValueOffset(), 3337 N0.getValueType(), 3338 LN0->isVolatile(), LN0->getAlignment()); 3339 CombineTo(N, ExtLoad); 3340 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3341 N0.getValueType(), ExtLoad); 3342 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3343 3344 // Extend SetCC uses if necessary. 3345 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3346 SDNode *SetCC = SetCCs[i]; 3347 SmallVector<SDValue, 4> Ops; 3348 3349 for (unsigned j = 0; j != 2; ++j) { 3350 SDValue SOp = SetCC->getOperand(j); 3351 if (SOp == Trunc) 3352 Ops.push_back(ExtLoad); 3353 else 3354 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3355 N->getDebugLoc(), VT, SOp)); 3356 } 3357 3358 Ops.push_back(SetCC->getOperand(2)); 3359 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3360 SetCC->getValueType(0), 3361 &Ops[0], Ops.size())); 3362 } 3363 3364 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3365 } 3366 } 3367 3368 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3369 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3370 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3371 if (N0.getOpcode() == ISD::LOAD && 3372 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3373 N0.hasOneUse()) { 3374 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3375 EVT EVT = LN0->getMemoryVT(); 3376 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3377 VT, LN0->getChain(), LN0->getBasePtr(), 3378 LN0->getSrcValue(), 3379 LN0->getSrcValueOffset(), EVT, 3380 LN0->isVolatile(), LN0->getAlignment()); 3381 CombineTo(N, ExtLoad); 3382 CombineTo(N0.getNode(), 3383 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3384 N0.getValueType(), ExtLoad), 3385 ExtLoad.getValue(1)); 3386 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3387 } 3388 3389 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3390 if (N0.getOpcode() == ISD::SETCC) { 3391 SDValue SCC = 3392 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3393 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3394 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3395 if (SCC.getNode()) 3396 return SCC; 3397 } 3398 3399 return SDValue(); 3400} 3401 3402/// GetDemandedBits - See if the specified operand can be simplified with the 3403/// knowledge that only the bits specified by Mask are used. If so, return the 3404/// simpler operand, otherwise return a null SDValue. 3405SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3406 switch (V.getOpcode()) { 3407 default: break; 3408 case ISD::OR: 3409 case ISD::XOR: 3410 // If the LHS or RHS don't contribute bits to the or, drop them. 3411 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3412 return V.getOperand(1); 3413 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3414 return V.getOperand(0); 3415 break; 3416 case ISD::SRL: 3417 // Only look at single-use SRLs. 3418 if (!V.getNode()->hasOneUse()) 3419 break; 3420 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3421 // See if we can recursively simplify the LHS. 3422 unsigned Amt = RHSC->getZExtValue(); 3423 3424 // Watch out for shift count overflow though. 3425 if (Amt >= Mask.getBitWidth()) break; 3426 APInt NewMask = Mask << Amt; 3427 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3428 if (SimplifyLHS.getNode()) 3429 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3430 SimplifyLHS, V.getOperand(1)); 3431 } 3432 } 3433 return SDValue(); 3434} 3435 3436/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3437/// bits and then truncated to a narrower type and where N is a multiple 3438/// of number of bits of the narrower type, transform it to a narrower load 3439/// from address + N / num of bits of new type. If the result is to be 3440/// extended, also fold the extension to form a extending load. 3441SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3442 unsigned Opc = N->getOpcode(); 3443 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3444 SDValue N0 = N->getOperand(0); 3445 EVT VT = N->getValueType(0); 3446 EVT ExtVT = VT; 3447 3448 // This transformation isn't valid for vector loads. 3449 if (VT.isVector()) 3450 return SDValue(); 3451 3452 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3453 // extended to VT. 3454 if (Opc == ISD::SIGN_EXTEND_INREG) { 3455 ExtType = ISD::SEXTLOAD; 3456 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3457 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 3458 return SDValue(); 3459 } 3460 3461 unsigned EVTBits = ExtVT.getSizeInBits(); 3462 unsigned ShAmt = 0; 3463 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3464 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3465 ShAmt = N01->getZExtValue(); 3466 // Is the shift amount a multiple of size of VT? 3467 if ((ShAmt & (EVTBits-1)) == 0) { 3468 N0 = N0.getOperand(0); 3469 if (N0.getValueType().getSizeInBits() <= EVTBits) 3470 return SDValue(); 3471 } 3472 } 3473 } 3474 3475 // Do not generate loads of non-round integer types since these can 3476 // be expensive (and would be wrong if the type is not byte sized). 3477 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 3478 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3479 // Do not change the width of a volatile load. 3480 !cast<LoadSDNode>(N0)->isVolatile()) { 3481 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3482 EVT PtrType = N0.getOperand(1).getValueType(); 3483 3484 // For big endian targets, we need to adjust the offset to the pointer to 3485 // load the correct bytes. 3486 if (TLI.isBigEndian()) { 3487 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3488 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 3489 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3490 } 3491 3492 uint64_t PtrOff = ShAmt / 8; 3493 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3494 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3495 PtrType, LN0->getBasePtr(), 3496 DAG.getConstant(PtrOff, PtrType)); 3497 AddToWorkList(NewPtr.getNode()); 3498 3499 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3500 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3501 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3502 LN0->isVolatile(), NewAlign) 3503 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3504 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3505 ExtVT, LN0->isVolatile(), NewAlign); 3506 3507 // Replace the old load's chain with the new load's chain. 3508 WorkListRemover DeadNodes(*this); 3509 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3510 &DeadNodes); 3511 3512 // Return the new loaded value. 3513 return Load; 3514 } 3515 3516 return SDValue(); 3517} 3518 3519SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3520 SDValue N0 = N->getOperand(0); 3521 SDValue N1 = N->getOperand(1); 3522 EVT VT = N->getValueType(0); 3523 EVT EVT = cast<VTSDNode>(N1)->getVT(); 3524 unsigned VTBits = VT.getSizeInBits(); 3525 unsigned EVTBits = EVT.getSizeInBits(); 3526 3527 // fold (sext_in_reg c1) -> c1 3528 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3529 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3530 3531 // If the input is already sign extended, just drop the extension. 3532 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3533 return N0; 3534 3535 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3536 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3537 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3538 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3539 N0.getOperand(0), N1); 3540 } 3541 3542 // fold (sext_in_reg (sext x)) -> (sext x) 3543 // fold (sext_in_reg (aext x)) -> (sext x) 3544 // if x is small enough. 3545 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3546 SDValue N00 = N0.getOperand(0); 3547 if (N00.getValueType().getSizeInBits() < EVTBits) 3548 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3549 } 3550 3551 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3552 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3553 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3554 3555 // fold operands of sext_in_reg based on knowledge that the top bits are not 3556 // demanded. 3557 if (SimplifyDemandedBits(SDValue(N, 0))) 3558 return SDValue(N, 0); 3559 3560 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3561 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3562 SDValue NarrowLoad = ReduceLoadWidth(N); 3563 if (NarrowLoad.getNode()) 3564 return NarrowLoad; 3565 3566 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3567 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3568 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3569 if (N0.getOpcode() == ISD::SRL) { 3570 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3571 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3572 // We can turn this into an SRA iff the input to the SRL is already sign 3573 // extended enough. 3574 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3575 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3576 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3577 N0.getOperand(0), N0.getOperand(1)); 3578 } 3579 } 3580 3581 // fold (sext_inreg (extload x)) -> (sextload x) 3582 if (ISD::isEXTLoad(N0.getNode()) && 3583 ISD::isUNINDEXEDLoad(N0.getNode()) && 3584 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3585 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3586 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3587 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3588 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3589 LN0->getChain(), 3590 LN0->getBasePtr(), LN0->getSrcValue(), 3591 LN0->getSrcValueOffset(), EVT, 3592 LN0->isVolatile(), LN0->getAlignment()); 3593 CombineTo(N, ExtLoad); 3594 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3595 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3596 } 3597 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3598 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3599 N0.hasOneUse() && 3600 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3601 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3602 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3603 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3604 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3605 LN0->getChain(), 3606 LN0->getBasePtr(), LN0->getSrcValue(), 3607 LN0->getSrcValueOffset(), EVT, 3608 LN0->isVolatile(), LN0->getAlignment()); 3609 CombineTo(N, ExtLoad); 3610 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3611 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3612 } 3613 return SDValue(); 3614} 3615 3616SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3617 SDValue N0 = N->getOperand(0); 3618 EVT VT = N->getValueType(0); 3619 3620 // noop truncate 3621 if (N0.getValueType() == N->getValueType(0)) 3622 return N0; 3623 // fold (truncate c1) -> c1 3624 if (isa<ConstantSDNode>(N0)) 3625 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3626 // fold (truncate (truncate x)) -> (truncate x) 3627 if (N0.getOpcode() == ISD::TRUNCATE) 3628 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3629 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3630 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3631 N0.getOpcode() == ISD::ANY_EXTEND) { 3632 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3633 // if the source is smaller than the dest, we still need an extend 3634 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3635 N0.getOperand(0)); 3636 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3637 // if the source is larger than the dest, than we just need the truncate 3638 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3639 else 3640 // if the source and dest are the same type, we can drop both the extend 3641 // and the truncate 3642 return N0.getOperand(0); 3643 } 3644 3645 // See if we can simplify the input to this truncate through knowledge that 3646 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3647 // -> trunc y 3648 SDValue Shorter = 3649 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3650 VT.getSizeInBits())); 3651 if (Shorter.getNode()) 3652 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3653 3654 // fold (truncate (load x)) -> (smaller load x) 3655 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3656 return ReduceLoadWidth(N); 3657} 3658 3659static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3660 SDValue Elt = N->getOperand(i); 3661 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3662 return Elt.getNode(); 3663 return Elt.getOperand(Elt.getResNo()).getNode(); 3664} 3665 3666/// CombineConsecutiveLoads - build_pair (load, load) -> load 3667/// if load locations are consecutive. 3668SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 3669 assert(N->getOpcode() == ISD::BUILD_PAIR); 3670 3671 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3672 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3673 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3674 return SDValue(); 3675 EVT LD1VT = LD1->getValueType(0); 3676 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3677 3678 if (ISD::isNON_EXTLoad(LD2) && 3679 LD2->hasOneUse() && 3680 // If both are volatile this would reduce the number of volatile loads. 3681 // If one is volatile it might be ok, but play conservative and bail out. 3682 !LD1->isVolatile() && 3683 !LD2->isVolatile() && 3684 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3685 unsigned Align = LD1->getAlignment(); 3686 unsigned NewAlign = TLI.getTargetData()-> 3687 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3688 3689 if (NewAlign <= Align && 3690 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3691 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3692 LD1->getBasePtr(), LD1->getSrcValue(), 3693 LD1->getSrcValueOffset(), false, Align); 3694 } 3695 3696 return SDValue(); 3697} 3698 3699SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3700 SDValue N0 = N->getOperand(0); 3701 EVT VT = N->getValueType(0); 3702 3703 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3704 // Only do this before legalize, since afterward the target may be depending 3705 // on the bitconvert. 3706 // First check to see if this is all constant. 3707 if (!LegalTypes && 3708 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3709 VT.isVector()) { 3710 bool isSimple = true; 3711 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3712 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3713 N0.getOperand(i).getOpcode() != ISD::Constant && 3714 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3715 isSimple = false; 3716 break; 3717 } 3718 3719 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 3720 assert(!DestEltVT.isVector() && 3721 "Element type of vector ValueType must not be vector!"); 3722 if (isSimple) 3723 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3724 } 3725 3726 // If the input is a constant, let getNode fold it. 3727 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3728 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3729 if (Res.getNode() != N) { 3730 if (!LegalOperations || 3731 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 3732 return Res; 3733 3734 // Folding it resulted in an illegal node, and it's too late to 3735 // do that. Clean up the old node and forego the transformation. 3736 // Ideally this won't happen very often, because instcombine 3737 // and the earlier dagcombine runs (where illegal nodes are 3738 // permitted) should have folded most of them already. 3739 DAG.DeleteNode(Res.getNode()); 3740 } 3741 } 3742 3743 // (conv (conv x, t1), t2) -> (conv x, t2) 3744 if (N0.getOpcode() == ISD::BIT_CONVERT) 3745 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3746 N0.getOperand(0)); 3747 3748 // fold (conv (load x)) -> (load (conv*)x) 3749 // If the resultant load doesn't need a higher alignment than the original! 3750 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3751 // Do not change the width of a volatile load. 3752 !cast<LoadSDNode>(N0)->isVolatile() && 3753 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3754 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3755 unsigned Align = TLI.getTargetData()-> 3756 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3757 unsigned OrigAlign = LN0->getAlignment(); 3758 3759 if (Align <= OrigAlign) { 3760 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3761 LN0->getBasePtr(), 3762 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3763 LN0->isVolatile(), OrigAlign); 3764 AddToWorkList(N); 3765 CombineTo(N0.getNode(), 3766 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3767 N0.getValueType(), Load), 3768 Load.getValue(1)); 3769 return Load; 3770 } 3771 } 3772 3773 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3774 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3775 // This often reduces constant pool loads. 3776 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3777 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3778 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3779 N0.getOperand(0)); 3780 AddToWorkList(NewConv.getNode()); 3781 3782 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3783 if (N0.getOpcode() == ISD::FNEG) 3784 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3785 NewConv, DAG.getConstant(SignBit, VT)); 3786 assert(N0.getOpcode() == ISD::FABS); 3787 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3788 NewConv, DAG.getConstant(~SignBit, VT)); 3789 } 3790 3791 // fold (bitconvert (fcopysign cst, x)) -> 3792 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3793 // Note that we don't handle (copysign x, cst) because this can always be 3794 // folded to an fneg or fabs. 3795 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3796 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3797 VT.isInteger() && !VT.isVector()) { 3798 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3799 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 3800 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3801 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3802 IntXVT, N0.getOperand(1)); 3803 AddToWorkList(X.getNode()); 3804 3805 // If X has a different width than the result/lhs, sext it or truncate it. 3806 unsigned VTWidth = VT.getSizeInBits(); 3807 if (OrigXWidth < VTWidth) { 3808 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3809 AddToWorkList(X.getNode()); 3810 } else if (OrigXWidth > VTWidth) { 3811 // To get the sign bit in the right place, we have to shift it right 3812 // before truncating. 3813 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3814 X.getValueType(), X, 3815 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3816 AddToWorkList(X.getNode()); 3817 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3818 AddToWorkList(X.getNode()); 3819 } 3820 3821 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3822 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3823 X, DAG.getConstant(SignBit, VT)); 3824 AddToWorkList(X.getNode()); 3825 3826 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3827 VT, N0.getOperand(0)); 3828 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3829 Cst, DAG.getConstant(~SignBit, VT)); 3830 AddToWorkList(Cst.getNode()); 3831 3832 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3833 } 3834 } 3835 3836 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3837 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3838 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3839 if (CombineLD.getNode()) 3840 return CombineLD; 3841 } 3842 3843 return SDValue(); 3844} 3845 3846SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3847 EVT VT = N->getValueType(0); 3848 return CombineConsecutiveLoads(N, VT); 3849} 3850 3851/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3852/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3853/// destination element value type. 3854SDValue DAGCombiner:: 3855ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 3856 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3857 3858 // If this is already the right type, we're done. 3859 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3860 3861 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3862 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3863 3864 // If this is a conversion of N elements of one type to N elements of another 3865 // type, convert each element. This handles FP<->INT cases. 3866 if (SrcBitSize == DstBitSize) { 3867 SmallVector<SDValue, 8> Ops; 3868 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3869 SDValue Op = BV->getOperand(i); 3870 // If the vector element type is not legal, the BUILD_VECTOR operands 3871 // are promoted and implicitly truncated. Make that explicit here. 3872 if (Op.getValueType() != SrcEltVT) 3873 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3874 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3875 DstEltVT, Op)); 3876 AddToWorkList(Ops.back().getNode()); 3877 } 3878 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 3879 BV->getValueType(0).getVectorNumElements()); 3880 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3881 &Ops[0], Ops.size()); 3882 } 3883 3884 // Otherwise, we're growing or shrinking the elements. To avoid having to 3885 // handle annoying details of growing/shrinking FP values, we convert them to 3886 // int first. 3887 if (SrcEltVT.isFloatingPoint()) { 3888 // Convert the input float vector to a int vector where the elements are the 3889 // same sizes. 3890 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3891 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 3892 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3893 SrcEltVT = IntVT; 3894 } 3895 3896 // Now we know the input is an integer vector. If the output is a FP type, 3897 // convert to integer first, then to FP of the right size. 3898 if (DstEltVT.isFloatingPoint()) { 3899 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3900 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 3901 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3902 3903 // Next, convert to FP elements of the same size. 3904 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3905 } 3906 3907 // Okay, we know the src/dst types are both integers of differing types. 3908 // Handling growing first. 3909 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3910 if (SrcBitSize < DstBitSize) { 3911 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3912 3913 SmallVector<SDValue, 8> Ops; 3914 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3915 i += NumInputsPerOutput) { 3916 bool isLE = TLI.isLittleEndian(); 3917 APInt NewBits = APInt(DstBitSize, 0); 3918 bool EltIsUndef = true; 3919 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3920 // Shift the previously computed bits over. 3921 NewBits <<= SrcBitSize; 3922 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3923 if (Op.getOpcode() == ISD::UNDEF) continue; 3924 EltIsUndef = false; 3925 3926 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 3927 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 3928 } 3929 3930 if (EltIsUndef) 3931 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3932 else 3933 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3934 } 3935 3936 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 3937 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3938 &Ops[0], Ops.size()); 3939 } 3940 3941 // Finally, this must be the case where we are shrinking elements: each input 3942 // turns into multiple outputs. 3943 bool isS2V = ISD::isScalarToVector(BV); 3944 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3945 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 3946 NumOutputsPerInput*BV->getNumOperands()); 3947 SmallVector<SDValue, 8> Ops; 3948 3949 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3950 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3951 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3952 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3953 continue; 3954 } 3955 3956 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 3957 getAPIntValue()).zextOrTrunc(SrcBitSize); 3958 3959 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3960 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3961 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3962 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3963 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3964 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3965 Ops[0]); 3966 OpVal = OpVal.lshr(DstBitSize); 3967 } 3968 3969 // For big endian targets, swap the order of the pieces of each element. 3970 if (TLI.isBigEndian()) 3971 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3972 } 3973 3974 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3975 &Ops[0], Ops.size()); 3976} 3977 3978SDValue DAGCombiner::visitFADD(SDNode *N) { 3979 SDValue N0 = N->getOperand(0); 3980 SDValue N1 = N->getOperand(1); 3981 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3982 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3983 EVT VT = N->getValueType(0); 3984 3985 // fold vector ops 3986 if (VT.isVector()) { 3987 SDValue FoldedVOp = SimplifyVBinOp(N); 3988 if (FoldedVOp.getNode()) return FoldedVOp; 3989 } 3990 3991 // fold (fadd c1, c2) -> (fadd c1, c2) 3992 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3993 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3994 // canonicalize constant to RHS 3995 if (N0CFP && !N1CFP) 3996 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3997 // fold (fadd A, 0) -> A 3998 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3999 return N0; 4000 // fold (fadd A, (fneg B)) -> (fsub A, B) 4001 if (isNegatibleForFree(N1, LegalOperations) == 2) 4002 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4003 GetNegatedExpression(N1, DAG, LegalOperations)); 4004 // fold (fadd (fneg A), B) -> (fsub B, A) 4005 if (isNegatibleForFree(N0, LegalOperations) == 2) 4006 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4007 GetNegatedExpression(N0, DAG, LegalOperations)); 4008 4009 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4010 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4011 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4012 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4013 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4014 N0.getOperand(1), N1)); 4015 4016 return SDValue(); 4017} 4018 4019SDValue DAGCombiner::visitFSUB(SDNode *N) { 4020 SDValue N0 = N->getOperand(0); 4021 SDValue N1 = N->getOperand(1); 4022 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4023 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4024 EVT VT = N->getValueType(0); 4025 4026 // fold vector ops 4027 if (VT.isVector()) { 4028 SDValue FoldedVOp = SimplifyVBinOp(N); 4029 if (FoldedVOp.getNode()) return FoldedVOp; 4030 } 4031 4032 // fold (fsub c1, c2) -> c1-c2 4033 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4034 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4035 // fold (fsub A, 0) -> A 4036 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4037 return N0; 4038 // fold (fsub 0, B) -> -B 4039 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4040 if (isNegatibleForFree(N1, LegalOperations)) 4041 return GetNegatedExpression(N1, DAG, LegalOperations); 4042 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4043 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4044 } 4045 // fold (fsub A, (fneg B)) -> (fadd A, B) 4046 if (isNegatibleForFree(N1, LegalOperations)) 4047 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4048 GetNegatedExpression(N1, DAG, LegalOperations)); 4049 4050 return SDValue(); 4051} 4052 4053SDValue DAGCombiner::visitFMUL(SDNode *N) { 4054 SDValue N0 = N->getOperand(0); 4055 SDValue N1 = N->getOperand(1); 4056 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4057 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4058 EVT VT = N->getValueType(0); 4059 4060 // fold vector ops 4061 if (VT.isVector()) { 4062 SDValue FoldedVOp = SimplifyVBinOp(N); 4063 if (FoldedVOp.getNode()) return FoldedVOp; 4064 } 4065 4066 // fold (fmul c1, c2) -> c1*c2 4067 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4068 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4069 // canonicalize constant to RHS 4070 if (N0CFP && !N1CFP) 4071 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4072 // fold (fmul A, 0) -> 0 4073 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4074 return N1; 4075 // fold (fmul A, 0) -> 0, vector edition. 4076 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4077 return N1; 4078 // fold (fmul X, 2.0) -> (fadd X, X) 4079 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4080 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4081 // fold (fmul X, -1.0) -> (fneg X) 4082 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4083 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4084 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4085 4086 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4087 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4088 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4089 // Both can be negated for free, check to see if at least one is cheaper 4090 // negated. 4091 if (LHSNeg == 2 || RHSNeg == 2) 4092 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4093 GetNegatedExpression(N0, DAG, LegalOperations), 4094 GetNegatedExpression(N1, DAG, LegalOperations)); 4095 } 4096 } 4097 4098 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4099 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4100 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4101 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4102 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4103 N0.getOperand(1), N1)); 4104 4105 return SDValue(); 4106} 4107 4108SDValue DAGCombiner::visitFDIV(SDNode *N) { 4109 SDValue N0 = N->getOperand(0); 4110 SDValue N1 = N->getOperand(1); 4111 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4112 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4113 EVT VT = N->getValueType(0); 4114 4115 // fold vector ops 4116 if (VT.isVector()) { 4117 SDValue FoldedVOp = SimplifyVBinOp(N); 4118 if (FoldedVOp.getNode()) return FoldedVOp; 4119 } 4120 4121 // fold (fdiv c1, c2) -> c1/c2 4122 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4123 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4124 4125 4126 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4127 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4128 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4129 // Both can be negated for free, check to see if at least one is cheaper 4130 // negated. 4131 if (LHSNeg == 2 || RHSNeg == 2) 4132 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4133 GetNegatedExpression(N0, DAG, LegalOperations), 4134 GetNegatedExpression(N1, DAG, LegalOperations)); 4135 } 4136 } 4137 4138 return SDValue(); 4139} 4140 4141SDValue DAGCombiner::visitFREM(SDNode *N) { 4142 SDValue N0 = N->getOperand(0); 4143 SDValue N1 = N->getOperand(1); 4144 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4145 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4146 EVT VT = N->getValueType(0); 4147 4148 // fold (frem c1, c2) -> fmod(c1,c2) 4149 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4150 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4151 4152 return SDValue(); 4153} 4154 4155SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4156 SDValue N0 = N->getOperand(0); 4157 SDValue N1 = N->getOperand(1); 4158 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4159 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4160 EVT VT = N->getValueType(0); 4161 4162 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4163 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4164 4165 if (N1CFP) { 4166 const APFloat& V = N1CFP->getValueAPF(); 4167 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4168 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4169 if (!V.isNegative()) { 4170 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4171 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4172 } else { 4173 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4174 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4175 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4176 } 4177 } 4178 4179 // copysign(fabs(x), y) -> copysign(x, y) 4180 // copysign(fneg(x), y) -> copysign(x, y) 4181 // copysign(copysign(x,z), y) -> copysign(x, y) 4182 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4183 N0.getOpcode() == ISD::FCOPYSIGN) 4184 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4185 N0.getOperand(0), N1); 4186 4187 // copysign(x, abs(y)) -> abs(x) 4188 if (N1.getOpcode() == ISD::FABS) 4189 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4190 4191 // copysign(x, copysign(y,z)) -> copysign(x, z) 4192 if (N1.getOpcode() == ISD::FCOPYSIGN) 4193 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4194 N0, N1.getOperand(1)); 4195 4196 // copysign(x, fp_extend(y)) -> copysign(x, y) 4197 // copysign(x, fp_round(y)) -> copysign(x, y) 4198 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4199 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4200 N0, N1.getOperand(0)); 4201 4202 return SDValue(); 4203} 4204 4205SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4206 SDValue N0 = N->getOperand(0); 4207 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4208 EVT VT = N->getValueType(0); 4209 EVT OpVT = N0.getValueType(); 4210 4211 // fold (sint_to_fp c1) -> c1fp 4212 if (N0C && OpVT != MVT::ppcf128) 4213 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4214 4215 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4216 // but UINT_TO_FP is legal on this target, try to convert. 4217 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4218 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4219 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4220 if (DAG.SignBitIsZero(N0)) 4221 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4222 } 4223 4224 return SDValue(); 4225} 4226 4227SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4228 SDValue N0 = N->getOperand(0); 4229 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4230 EVT VT = N->getValueType(0); 4231 EVT OpVT = N0.getValueType(); 4232 4233 // fold (uint_to_fp c1) -> c1fp 4234 if (N0C && OpVT != MVT::ppcf128) 4235 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4236 4237 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4238 // but SINT_TO_FP is legal on this target, try to convert. 4239 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4240 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4241 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4242 if (DAG.SignBitIsZero(N0)) 4243 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4244 } 4245 4246 return SDValue(); 4247} 4248 4249SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4250 SDValue N0 = N->getOperand(0); 4251 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4252 EVT VT = N->getValueType(0); 4253 4254 // fold (fp_to_sint c1fp) -> c1 4255 if (N0CFP) 4256 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4257 4258 return SDValue(); 4259} 4260 4261SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4262 SDValue N0 = N->getOperand(0); 4263 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4264 EVT VT = N->getValueType(0); 4265 4266 // fold (fp_to_uint c1fp) -> c1 4267 if (N0CFP && VT != MVT::ppcf128) 4268 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4269 4270 return SDValue(); 4271} 4272 4273SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4274 SDValue N0 = N->getOperand(0); 4275 SDValue N1 = N->getOperand(1); 4276 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4277 EVT VT = N->getValueType(0); 4278 4279 // fold (fp_round c1fp) -> c1fp 4280 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4281 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4282 4283 // fold (fp_round (fp_extend x)) -> x 4284 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4285 return N0.getOperand(0); 4286 4287 // fold (fp_round (fp_round x)) -> (fp_round x) 4288 if (N0.getOpcode() == ISD::FP_ROUND) { 4289 // This is a value preserving truncation if both round's are. 4290 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4291 N0.getNode()->getConstantOperandVal(1) == 1; 4292 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4293 DAG.getIntPtrConstant(IsTrunc)); 4294 } 4295 4296 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4297 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4298 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4299 N0.getOperand(0), N1); 4300 AddToWorkList(Tmp.getNode()); 4301 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4302 Tmp, N0.getOperand(1)); 4303 } 4304 4305 return SDValue(); 4306} 4307 4308SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4309 SDValue N0 = N->getOperand(0); 4310 EVT VT = N->getValueType(0); 4311 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4312 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4313 4314 // fold (fp_round_inreg c1fp) -> c1fp 4315 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4316 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4317 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4318 } 4319 4320 return SDValue(); 4321} 4322 4323SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4324 SDValue N0 = N->getOperand(0); 4325 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4326 EVT VT = N->getValueType(0); 4327 4328 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4329 if (N->hasOneUse() && 4330 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4331 return SDValue(); 4332 4333 // fold (fp_extend c1fp) -> c1fp 4334 if (N0CFP && VT != MVT::ppcf128) 4335 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4336 4337 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4338 // value of X. 4339 if (N0.getOpcode() == ISD::FP_ROUND 4340 && N0.getNode()->getConstantOperandVal(1) == 1) { 4341 SDValue In = N0.getOperand(0); 4342 if (In.getValueType() == VT) return In; 4343 if (VT.bitsLT(In.getValueType())) 4344 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4345 In, N0.getOperand(1)); 4346 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4347 } 4348 4349 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4350 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4351 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4352 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4353 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4354 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4355 LN0->getChain(), 4356 LN0->getBasePtr(), LN0->getSrcValue(), 4357 LN0->getSrcValueOffset(), 4358 N0.getValueType(), 4359 LN0->isVolatile(), LN0->getAlignment()); 4360 CombineTo(N, ExtLoad); 4361 CombineTo(N0.getNode(), 4362 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4363 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4364 ExtLoad.getValue(1)); 4365 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4366 } 4367 4368 return SDValue(); 4369} 4370 4371SDValue DAGCombiner::visitFNEG(SDNode *N) { 4372 SDValue N0 = N->getOperand(0); 4373 4374 if (isNegatibleForFree(N0, LegalOperations)) 4375 return GetNegatedExpression(N0, DAG, LegalOperations); 4376 4377 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4378 // constant pool values. 4379 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4380 N0.getOperand(0).getValueType().isInteger() && 4381 !N0.getOperand(0).getValueType().isVector()) { 4382 SDValue Int = N0.getOperand(0); 4383 EVT IntVT = Int.getValueType(); 4384 if (IntVT.isInteger() && !IntVT.isVector()) { 4385 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4386 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4387 AddToWorkList(Int.getNode()); 4388 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4389 N->getValueType(0), Int); 4390 } 4391 } 4392 4393 return SDValue(); 4394} 4395 4396SDValue DAGCombiner::visitFABS(SDNode *N) { 4397 SDValue N0 = N->getOperand(0); 4398 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4399 EVT VT = N->getValueType(0); 4400 4401 // fold (fabs c1) -> fabs(c1) 4402 if (N0CFP && VT != MVT::ppcf128) 4403 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4404 // fold (fabs (fabs x)) -> (fabs x) 4405 if (N0.getOpcode() == ISD::FABS) 4406 return N->getOperand(0); 4407 // fold (fabs (fneg x)) -> (fabs x) 4408 // fold (fabs (fcopysign x, y)) -> (fabs x) 4409 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4410 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4411 4412 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4413 // constant pool values. 4414 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4415 N0.getOperand(0).getValueType().isInteger() && 4416 !N0.getOperand(0).getValueType().isVector()) { 4417 SDValue Int = N0.getOperand(0); 4418 EVT IntVT = Int.getValueType(); 4419 if (IntVT.isInteger() && !IntVT.isVector()) { 4420 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4421 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4422 AddToWorkList(Int.getNode()); 4423 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4424 N->getValueType(0), Int); 4425 } 4426 } 4427 4428 return SDValue(); 4429} 4430 4431SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4432 SDValue Chain = N->getOperand(0); 4433 SDValue N1 = N->getOperand(1); 4434 SDValue N2 = N->getOperand(2); 4435 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4436 4437 // never taken branch, fold to chain 4438 if (N1C && N1C->isNullValue()) 4439 return Chain; 4440 // unconditional branch 4441 if (N1C && N1C->getAPIntValue() == 1) 4442 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4443 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4444 // on the target. 4445 if (N1.getOpcode() == ISD::SETCC && 4446 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4447 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4448 Chain, N1.getOperand(2), 4449 N1.getOperand(0), N1.getOperand(1), N2); 4450 } 4451 4452 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4453 // Match this pattern so that we can generate simpler code: 4454 // 4455 // %a = ... 4456 // %b = and i32 %a, 2 4457 // %c = srl i32 %b, 1 4458 // brcond i32 %c ... 4459 // 4460 // into 4461 // 4462 // %a = ... 4463 // %b = and %a, 2 4464 // %c = setcc eq %b, 0 4465 // brcond %c ... 4466 // 4467 // This applies only when the AND constant value has one bit set and the 4468 // SRL constant is equal to the log2 of the AND constant. The back-end is 4469 // smart enough to convert the result into a TEST/JMP sequence. 4470 SDValue Op0 = N1.getOperand(0); 4471 SDValue Op1 = N1.getOperand(1); 4472 4473 if (Op0.getOpcode() == ISD::AND && 4474 Op0.hasOneUse() && 4475 Op1.getOpcode() == ISD::Constant) { 4476 SDValue AndOp0 = Op0.getOperand(0); 4477 SDValue AndOp1 = Op0.getOperand(1); 4478 4479 if (AndOp1.getOpcode() == ISD::Constant) { 4480 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4481 4482 if (AndConst.isPowerOf2() && 4483 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4484 SDValue SetCC = 4485 DAG.getSetCC(N->getDebugLoc(), 4486 TLI.getSetCCResultType(Op0.getValueType()), 4487 Op0, DAG.getConstant(0, Op0.getValueType()), 4488 ISD::SETNE); 4489 4490 // Replace the uses of SRL with SETCC 4491 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4492 removeFromWorkList(N1.getNode()); 4493 DAG.DeleteNode(N1.getNode()); 4494 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4495 MVT::Other, Chain, SetCC, N2); 4496 } 4497 } 4498 } 4499 } 4500 4501 return SDValue(); 4502} 4503 4504// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4505// 4506SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4507 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4508 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4509 4510 // Use SimplifySetCC to simplify SETCC's. 4511 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4512 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4513 false); 4514 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4515 4516 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4517 4518 // fold br_cc true, dest -> br dest (unconditional branch) 4519 if (SCCC && !SCCC->isNullValue()) 4520 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4521 N->getOperand(0), N->getOperand(4)); 4522 // fold br_cc false, dest -> unconditional fall through 4523 if (SCCC && SCCC->isNullValue()) 4524 return N->getOperand(0); 4525 4526 // fold to a simpler setcc 4527 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4528 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4529 N->getOperand(0), Simp.getOperand(2), 4530 Simp.getOperand(0), Simp.getOperand(1), 4531 N->getOperand(4)); 4532 4533 return SDValue(); 4534} 4535 4536/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4537/// pre-indexed load / store when the base pointer is an add or subtract 4538/// and it has other uses besides the load / store. After the 4539/// transformation, the new indexed load / store has effectively folded 4540/// the add / subtract in and all of its other uses are redirected to the 4541/// new load / store. 4542bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4543 if (!LegalOperations) 4544 return false; 4545 4546 bool isLoad = true; 4547 SDValue Ptr; 4548 EVT VT; 4549 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4550 if (LD->isIndexed()) 4551 return false; 4552 VT = LD->getMemoryVT(); 4553 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4554 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4555 return false; 4556 Ptr = LD->getBasePtr(); 4557 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4558 if (ST->isIndexed()) 4559 return false; 4560 VT = ST->getMemoryVT(); 4561 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4562 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4563 return false; 4564 Ptr = ST->getBasePtr(); 4565 isLoad = false; 4566 } else { 4567 return false; 4568 } 4569 4570 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4571 // out. There is no reason to make this a preinc/predec. 4572 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4573 Ptr.getNode()->hasOneUse()) 4574 return false; 4575 4576 // Ask the target to do addressing mode selection. 4577 SDValue BasePtr; 4578 SDValue Offset; 4579 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4580 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4581 return false; 4582 // Don't create a indexed load / store with zero offset. 4583 if (isa<ConstantSDNode>(Offset) && 4584 cast<ConstantSDNode>(Offset)->isNullValue()) 4585 return false; 4586 4587 // Try turning it into a pre-indexed load / store except when: 4588 // 1) The new base ptr is a frame index. 4589 // 2) If N is a store and the new base ptr is either the same as or is a 4590 // predecessor of the value being stored. 4591 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4592 // that would create a cycle. 4593 // 4) All uses are load / store ops that use it as old base ptr. 4594 4595 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4596 // (plus the implicit offset) to a register to preinc anyway. 4597 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4598 return false; 4599 4600 // Check #2. 4601 if (!isLoad) { 4602 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4603 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4604 return false; 4605 } 4606 4607 // Now check for #3 and #4. 4608 bool RealUse = false; 4609 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4610 E = Ptr.getNode()->use_end(); I != E; ++I) { 4611 SDNode *Use = *I; 4612 if (Use == N) 4613 continue; 4614 if (Use->isPredecessorOf(N)) 4615 return false; 4616 4617 if (!((Use->getOpcode() == ISD::LOAD && 4618 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4619 (Use->getOpcode() == ISD::STORE && 4620 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4621 RealUse = true; 4622 } 4623 4624 if (!RealUse) 4625 return false; 4626 4627 SDValue Result; 4628 if (isLoad) 4629 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4630 BasePtr, Offset, AM); 4631 else 4632 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4633 BasePtr, Offset, AM); 4634 ++PreIndexedNodes; 4635 ++NodesCombined; 4636 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4637 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4638 DOUT << '\n'; 4639 WorkListRemover DeadNodes(*this); 4640 if (isLoad) { 4641 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4642 &DeadNodes); 4643 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4644 &DeadNodes); 4645 } else { 4646 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4647 &DeadNodes); 4648 } 4649 4650 // Finally, since the node is now dead, remove it from the graph. 4651 DAG.DeleteNode(N); 4652 4653 // Replace the uses of Ptr with uses of the updated base value. 4654 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4655 &DeadNodes); 4656 removeFromWorkList(Ptr.getNode()); 4657 DAG.DeleteNode(Ptr.getNode()); 4658 4659 return true; 4660} 4661 4662/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4663/// add / sub of the base pointer node into a post-indexed load / store. 4664/// The transformation folded the add / subtract into the new indexed 4665/// load / store effectively and all of its uses are redirected to the 4666/// new load / store. 4667bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4668 if (!LegalOperations) 4669 return false; 4670 4671 bool isLoad = true; 4672 SDValue Ptr; 4673 EVT VT; 4674 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4675 if (LD->isIndexed()) 4676 return false; 4677 VT = LD->getMemoryVT(); 4678 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4679 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4680 return false; 4681 Ptr = LD->getBasePtr(); 4682 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4683 if (ST->isIndexed()) 4684 return false; 4685 VT = ST->getMemoryVT(); 4686 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4687 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4688 return false; 4689 Ptr = ST->getBasePtr(); 4690 isLoad = false; 4691 } else { 4692 return false; 4693 } 4694 4695 if (Ptr.getNode()->hasOneUse()) 4696 return false; 4697 4698 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4699 E = Ptr.getNode()->use_end(); I != E; ++I) { 4700 SDNode *Op = *I; 4701 if (Op == N || 4702 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4703 continue; 4704 4705 SDValue BasePtr; 4706 SDValue Offset; 4707 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4708 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4709 if (Ptr == Offset) 4710 std::swap(BasePtr, Offset); 4711 if (Ptr != BasePtr) 4712 continue; 4713 // Don't create a indexed load / store with zero offset. 4714 if (isa<ConstantSDNode>(Offset) && 4715 cast<ConstantSDNode>(Offset)->isNullValue()) 4716 continue; 4717 4718 // Try turning it into a post-indexed load / store except when 4719 // 1) All uses are load / store ops that use it as base ptr. 4720 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4721 // nor a successor of N. Otherwise, if Op is folded that would 4722 // create a cycle. 4723 4724 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4725 continue; 4726 4727 // Check for #1. 4728 bool TryNext = false; 4729 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4730 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4731 SDNode *Use = *II; 4732 if (Use == Ptr.getNode()) 4733 continue; 4734 4735 // If all the uses are load / store addresses, then don't do the 4736 // transformation. 4737 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4738 bool RealUse = false; 4739 for (SDNode::use_iterator III = Use->use_begin(), 4740 EEE = Use->use_end(); III != EEE; ++III) { 4741 SDNode *UseUse = *III; 4742 if (!((UseUse->getOpcode() == ISD::LOAD && 4743 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4744 (UseUse->getOpcode() == ISD::STORE && 4745 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4746 RealUse = true; 4747 } 4748 4749 if (!RealUse) { 4750 TryNext = true; 4751 break; 4752 } 4753 } 4754 } 4755 4756 if (TryNext) 4757 continue; 4758 4759 // Check for #2 4760 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4761 SDValue Result = isLoad 4762 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4763 BasePtr, Offset, AM) 4764 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4765 BasePtr, Offset, AM); 4766 ++PostIndexedNodes; 4767 ++NodesCombined; 4768 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4769 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4770 DOUT << '\n'; 4771 WorkListRemover DeadNodes(*this); 4772 if (isLoad) { 4773 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4774 &DeadNodes); 4775 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4776 &DeadNodes); 4777 } else { 4778 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4779 &DeadNodes); 4780 } 4781 4782 // Finally, since the node is now dead, remove it from the graph. 4783 DAG.DeleteNode(N); 4784 4785 // Replace the uses of Use with uses of the updated base value. 4786 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4787 Result.getValue(isLoad ? 1 : 0), 4788 &DeadNodes); 4789 removeFromWorkList(Op); 4790 DAG.DeleteNode(Op); 4791 return true; 4792 } 4793 } 4794 } 4795 4796 return false; 4797} 4798 4799/// InferAlignment - If we can infer some alignment information from this 4800/// pointer, return it. 4801static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4802 // If this is a direct reference to a stack slot, use information about the 4803 // stack slot's alignment. 4804 int FrameIdx = 1 << 31; 4805 int64_t FrameOffset = 0; 4806 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4807 FrameIdx = FI->getIndex(); 4808 } else if (Ptr.getOpcode() == ISD::ADD && 4809 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4810 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4811 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4812 FrameOffset = Ptr.getConstantOperandVal(1); 4813 } 4814 4815 if (FrameIdx != (1 << 31)) { 4816 // FIXME: Handle FI+CST. 4817 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4818 if (MFI.isFixedObjectIndex(FrameIdx)) { 4819 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4820 4821 // The alignment of the frame index can be determined from its offset from 4822 // the incoming frame position. If the frame object is at offset 32 and 4823 // the stack is guaranteed to be 16-byte aligned, then we know that the 4824 // object is 16-byte aligned. 4825 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4826 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4827 4828 // Finally, the frame object itself may have a known alignment. Factor 4829 // the alignment + offset into a new alignment. For example, if we know 4830 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4831 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4832 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4833 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4834 FrameOffset); 4835 return std::max(Align, FIInfoAlign); 4836 } 4837 } 4838 4839 return 0; 4840} 4841 4842SDValue DAGCombiner::visitLOAD(SDNode *N) { 4843 LoadSDNode *LD = cast<LoadSDNode>(N); 4844 SDValue Chain = LD->getChain(); 4845 SDValue Ptr = LD->getBasePtr(); 4846 4847 // Try to infer better alignment information than the load already has. 4848 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4849 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4850 if (Align > LD->getAlignment()) 4851 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4852 LD->getValueType(0), 4853 Chain, Ptr, LD->getSrcValue(), 4854 LD->getSrcValueOffset(), LD->getMemoryVT(), 4855 LD->isVolatile(), Align); 4856 } 4857 } 4858 4859 // If load is not volatile and there are no uses of the loaded value (and 4860 // the updated indexed value in case of indexed loads), change uses of the 4861 // chain value into uses of the chain input (i.e. delete the dead load). 4862 if (!LD->isVolatile()) { 4863 if (N->getValueType(1) == MVT::Other) { 4864 // Unindexed loads. 4865 if (N->hasNUsesOfValue(0, 0)) { 4866 // It's not safe to use the two value CombineTo variant here. e.g. 4867 // v1, chain2 = load chain1, loc 4868 // v2, chain3 = load chain2, loc 4869 // v3 = add v2, c 4870 // Now we replace use of chain2 with chain1. This makes the second load 4871 // isomorphic to the one we are deleting, and thus makes this load live. 4872 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4873 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4874 DOUT << "\n"; 4875 WorkListRemover DeadNodes(*this); 4876 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4877 4878 if (N->use_empty()) { 4879 removeFromWorkList(N); 4880 DAG.DeleteNode(N); 4881 } 4882 4883 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4884 } 4885 } else { 4886 // Indexed loads. 4887 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4888 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4889 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4890 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4891 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4892 DOUT << " and 2 other values\n"; 4893 WorkListRemover DeadNodes(*this); 4894 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4895 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4896 DAG.getUNDEF(N->getValueType(1)), 4897 &DeadNodes); 4898 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4899 removeFromWorkList(N); 4900 DAG.DeleteNode(N); 4901 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4902 } 4903 } 4904 } 4905 4906 // If this load is directly stored, replace the load value with the stored 4907 // value. 4908 // TODO: Handle store large -> read small portion. 4909 // TODO: Handle TRUNCSTORE/LOADEXT 4910 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4911 !LD->isVolatile()) { 4912 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4913 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4914 if (PrevST->getBasePtr() == Ptr && 4915 PrevST->getValue().getValueType() == N->getValueType(0)) 4916 return CombineTo(N, Chain.getOperand(1), Chain); 4917 } 4918 } 4919 4920 if (CombinerAA) { 4921 // Walk up chain skipping non-aliasing memory nodes. 4922 SDValue BetterChain = FindBetterChain(N, Chain); 4923 4924 // If there is a better chain. 4925 if (Chain != BetterChain) { 4926 SDValue ReplLoad; 4927 4928 // Replace the chain to void dependency. 4929 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4930 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4931 BetterChain, Ptr, 4932 LD->getSrcValue(), LD->getSrcValueOffset(), 4933 LD->isVolatile(), LD->getAlignment()); 4934 } else { 4935 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4936 LD->getValueType(0), 4937 BetterChain, Ptr, LD->getSrcValue(), 4938 LD->getSrcValueOffset(), 4939 LD->getMemoryVT(), 4940 LD->isVolatile(), 4941 LD->getAlignment()); 4942 } 4943 4944 // Create token factor to keep old chain connected. 4945 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4946 MVT::Other, Chain, ReplLoad.getValue(1)); 4947 4948 // Replace uses with load result and token factor. Don't add users 4949 // to work list. 4950 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4951 } 4952 } 4953 4954 // Try transforming N to an indexed load. 4955 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4956 return SDValue(N, 0); 4957 4958 return SDValue(); 4959} 4960 4961 4962/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 4963/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 4964/// of the loaded bits, try narrowing the load and store if it would end up 4965/// being a win for performance or code size. 4966SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 4967 StoreSDNode *ST = cast<StoreSDNode>(N); 4968 if (ST->isVolatile()) 4969 return SDValue(); 4970 4971 SDValue Chain = ST->getChain(); 4972 SDValue Value = ST->getValue(); 4973 SDValue Ptr = ST->getBasePtr(); 4974 EVT VT = Value.getValueType(); 4975 4976 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 4977 return SDValue(); 4978 4979 unsigned Opc = Value.getOpcode(); 4980 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 4981 Value.getOperand(1).getOpcode() != ISD::Constant) 4982 return SDValue(); 4983 4984 SDValue N0 = Value.getOperand(0); 4985 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 4986 LoadSDNode *LD = cast<LoadSDNode>(N0); 4987 if (LD->getBasePtr() != Ptr) 4988 return SDValue(); 4989 4990 // Find the type to narrow it the load / op / store to. 4991 SDValue N1 = Value.getOperand(1); 4992 unsigned BitWidth = N1.getValueSizeInBits(); 4993 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 4994 if (Opc == ISD::AND) 4995 Imm ^= APInt::getAllOnesValue(BitWidth); 4996 if (Imm == 0 || Imm.isAllOnesValue()) 4997 return SDValue(); 4998 unsigned ShAmt = Imm.countTrailingZeros(); 4999 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5000 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5001 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5002 while (NewBW < BitWidth && 5003 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5004 TLI.isNarrowingProfitable(VT, NewVT))) { 5005 NewBW = NextPowerOf2(NewBW); 5006 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5007 } 5008 if (NewBW >= BitWidth) 5009 return SDValue(); 5010 5011 // If the lsb changed does not start at the type bitwidth boundary, 5012 // start at the previous one. 5013 if (ShAmt % NewBW) 5014 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5015 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5016 if ((Imm & Mask) == Imm) { 5017 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5018 if (Opc == ISD::AND) 5019 NewImm ^= APInt::getAllOnesValue(NewBW); 5020 uint64_t PtrOff = ShAmt / 8; 5021 // For big endian targets, we need to adjust the offset to the pointer to 5022 // load the correct bytes. 5023 if (TLI.isBigEndian()) 5024 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5025 5026 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5027 if (NewAlign < 5028 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext()))) 5029 return SDValue(); 5030 5031 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5032 Ptr.getValueType(), Ptr, 5033 DAG.getConstant(PtrOff, Ptr.getValueType())); 5034 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5035 LD->getChain(), NewPtr, 5036 LD->getSrcValue(), LD->getSrcValueOffset(), 5037 LD->isVolatile(), NewAlign); 5038 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5039 DAG.getConstant(NewImm, NewVT)); 5040 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5041 NewVal, NewPtr, 5042 ST->getSrcValue(), ST->getSrcValueOffset(), 5043 false, NewAlign); 5044 5045 AddToWorkList(NewPtr.getNode()); 5046 AddToWorkList(NewLD.getNode()); 5047 AddToWorkList(NewVal.getNode()); 5048 WorkListRemover DeadNodes(*this); 5049 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5050 &DeadNodes); 5051 ++OpsNarrowed; 5052 return NewST; 5053 } 5054 } 5055 5056 return SDValue(); 5057} 5058 5059SDValue DAGCombiner::visitSTORE(SDNode *N) { 5060 StoreSDNode *ST = cast<StoreSDNode>(N); 5061 SDValue Chain = ST->getChain(); 5062 SDValue Value = ST->getValue(); 5063 SDValue Ptr = ST->getBasePtr(); 5064 5065 // Try to infer better alignment information than the store already has. 5066 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5067 if (unsigned Align = InferAlignment(Ptr, DAG)) { 5068 if (Align > ST->getAlignment()) 5069 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5070 Ptr, ST->getSrcValue(), 5071 ST->getSrcValueOffset(), ST->getMemoryVT(), 5072 ST->isVolatile(), Align); 5073 } 5074 } 5075 5076 // If this is a store of a bit convert, store the input value if the 5077 // resultant store does not need a higher alignment than the original. 5078 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5079 ST->isUnindexed()) { 5080 unsigned OrigAlign = ST->getAlignment(); 5081 EVT SVT = Value.getOperand(0).getValueType(); 5082 unsigned Align = TLI.getTargetData()-> 5083 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5084 if (Align <= OrigAlign && 5085 ((!LegalOperations && !ST->isVolatile()) || 5086 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5087 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5088 Ptr, ST->getSrcValue(), 5089 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5090 } 5091 5092 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5093 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5094 // NOTE: If the original store is volatile, this transform must not increase 5095 // the number of stores. For example, on x86-32 an f64 can be stored in one 5096 // processor operation but an i64 (which is not legal) requires two. So the 5097 // transform should not be done in this case. 5098 if (Value.getOpcode() != ISD::TargetConstantFP) { 5099 SDValue Tmp; 5100 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5101 default: llvm_unreachable("Unknown FP type"); 5102 case MVT::f80: // We don't do this for these yet. 5103 case MVT::f128: 5104 case MVT::ppcf128: 5105 break; 5106 case MVT::f32: 5107 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5108 !ST->isVolatile()) || 5109 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5110 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5111 bitcastToAPInt().getZExtValue(), MVT::i32); 5112 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5113 Ptr, ST->getSrcValue(), 5114 ST->getSrcValueOffset(), ST->isVolatile(), 5115 ST->getAlignment()); 5116 } 5117 break; 5118 case MVT::f64: 5119 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5120 !ST->isVolatile()) || 5121 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5122 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5123 getZExtValue(), MVT::i64); 5124 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5125 Ptr, ST->getSrcValue(), 5126 ST->getSrcValueOffset(), ST->isVolatile(), 5127 ST->getAlignment()); 5128 } else if (!ST->isVolatile() && 5129 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5130 // Many FP stores are not made apparent until after legalize, e.g. for 5131 // argument passing. Since this is so common, custom legalize the 5132 // 64-bit integer store into two 32-bit stores. 5133 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5134 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5135 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5136 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5137 5138 int SVOffset = ST->getSrcValueOffset(); 5139 unsigned Alignment = ST->getAlignment(); 5140 bool isVolatile = ST->isVolatile(); 5141 5142 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5143 Ptr, ST->getSrcValue(), 5144 ST->getSrcValueOffset(), 5145 isVolatile, ST->getAlignment()); 5146 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5147 DAG.getConstant(4, Ptr.getValueType())); 5148 SVOffset += 4; 5149 Alignment = MinAlign(Alignment, 4U); 5150 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5151 Ptr, ST->getSrcValue(), 5152 SVOffset, isVolatile, Alignment); 5153 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5154 St0, St1); 5155 } 5156 5157 break; 5158 } 5159 } 5160 } 5161 5162 if (CombinerAA) { 5163 // Walk up chain skipping non-aliasing memory nodes. 5164 SDValue BetterChain = FindBetterChain(N, Chain); 5165 5166 // If there is a better chain. 5167 if (Chain != BetterChain) { 5168 // Replace the chain to avoid dependency. 5169 SDValue ReplStore; 5170 if (ST->isTruncatingStore()) { 5171 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5172 ST->getSrcValue(),ST->getSrcValueOffset(), 5173 ST->getMemoryVT(), 5174 ST->isVolatile(), ST->getAlignment()); 5175 } else { 5176 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5177 ST->getSrcValue(), ST->getSrcValueOffset(), 5178 ST->isVolatile(), ST->getAlignment()); 5179 } 5180 5181 // Create token to keep both nodes around. 5182 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5183 MVT::Other, Chain, ReplStore); 5184 5185 // Don't add users to work list. 5186 return CombineTo(N, Token, false); 5187 } 5188 } 5189 5190 // Try transforming N to an indexed store. 5191 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5192 return SDValue(N, 0); 5193 5194 // FIXME: is there such a thing as a truncating indexed store? 5195 if (ST->isTruncatingStore() && ST->isUnindexed() && 5196 Value.getValueType().isInteger()) { 5197 // See if we can simplify the input to this truncstore with knowledge that 5198 // only the low bits are being used. For example: 5199 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5200 SDValue Shorter = 5201 GetDemandedBits(Value, 5202 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5203 ST->getMemoryVT().getSizeInBits())); 5204 AddToWorkList(Value.getNode()); 5205 if (Shorter.getNode()) 5206 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5207 Ptr, ST->getSrcValue(), 5208 ST->getSrcValueOffset(), ST->getMemoryVT(), 5209 ST->isVolatile(), ST->getAlignment()); 5210 5211 // Otherwise, see if we can simplify the operation with 5212 // SimplifyDemandedBits, which only works if the value has a single use. 5213 if (SimplifyDemandedBits(Value, 5214 APInt::getLowBitsSet( 5215 Value.getValueSizeInBits(), 5216 ST->getMemoryVT().getSizeInBits()))) 5217 return SDValue(N, 0); 5218 } 5219 5220 // If this is a load followed by a store to the same location, then the store 5221 // is dead/noop. 5222 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5223 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5224 ST->isUnindexed() && !ST->isVolatile() && 5225 // There can't be any side effects between the load and store, such as 5226 // a call or store. 5227 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5228 // The store is dead, remove it. 5229 return Chain; 5230 } 5231 } 5232 5233 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5234 // truncating store. We can do this even if this is already a truncstore. 5235 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5236 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5237 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5238 ST->getMemoryVT())) { 5239 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5240 Ptr, ST->getSrcValue(), 5241 ST->getSrcValueOffset(), ST->getMemoryVT(), 5242 ST->isVolatile(), ST->getAlignment()); 5243 } 5244 5245 return ReduceLoadOpStoreWidth(N); 5246} 5247 5248SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5249 SDValue InVec = N->getOperand(0); 5250 SDValue InVal = N->getOperand(1); 5251 SDValue EltNo = N->getOperand(2); 5252 5253 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5254 // vector with the inserted element. 5255 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5256 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5257 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5258 InVec.getNode()->op_end()); 5259 if (Elt < Ops.size()) 5260 Ops[Elt] = InVal; 5261 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5262 InVec.getValueType(), &Ops[0], Ops.size()); 5263 } 5264 // If the invec is an UNDEF and if EltNo is a constant, create a new 5265 // BUILD_VECTOR with undef elements and the inserted element. 5266 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5267 isa<ConstantSDNode>(EltNo)) { 5268 EVT VT = InVec.getValueType(); 5269 EVT EVT = VT.getVectorElementType(); 5270 unsigned NElts = VT.getVectorNumElements(); 5271 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT)); 5272 5273 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5274 if (Elt < Ops.size()) 5275 Ops[Elt] = InVal; 5276 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5277 InVec.getValueType(), &Ops[0], Ops.size()); 5278 } 5279 return SDValue(); 5280} 5281 5282SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5283 // (vextract (scalar_to_vector val, 0) -> val 5284 SDValue InVec = N->getOperand(0); 5285 5286 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5287 // If the operand is wider than the vector element type then it is implicitly 5288 // truncated. Make that explicit here. 5289 EVT EltVT = InVec.getValueType().getVectorElementType(); 5290 SDValue InOp = InVec.getOperand(0); 5291 if (InOp.getValueType() != EltVT) 5292 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5293 return InOp; 5294 } 5295 5296 // Perform only after legalization to ensure build_vector / vector_shuffle 5297 // optimizations have already been done. 5298 if (!LegalOperations) return SDValue(); 5299 5300 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5301 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5302 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5303 SDValue EltNo = N->getOperand(1); 5304 5305 if (isa<ConstantSDNode>(EltNo)) { 5306 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5307 bool NewLoad = false; 5308 bool BCNumEltsChanged = false; 5309 EVT VT = InVec.getValueType(); 5310 EVT ExtVT = VT.getVectorElementType(); 5311 EVT LVT = ExtVT; 5312 5313 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5314 EVT BCVT = InVec.getOperand(0).getValueType(); 5315 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 5316 return SDValue(); 5317 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5318 BCNumEltsChanged = true; 5319 InVec = InVec.getOperand(0); 5320 ExtVT = BCVT.getVectorElementType(); 5321 NewLoad = true; 5322 } 5323 5324 LoadSDNode *LN0 = NULL; 5325 const ShuffleVectorSDNode *SVN = NULL; 5326 if (ISD::isNormalLoad(InVec.getNode())) { 5327 LN0 = cast<LoadSDNode>(InVec); 5328 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5329 InVec.getOperand(0).getValueType() == ExtVT && 5330 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5331 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5332 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5333 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5334 // => 5335 // (load $addr+1*size) 5336 5337 // If the bit convert changed the number of elements, it is unsafe 5338 // to examine the mask. 5339 if (BCNumEltsChanged) 5340 return SDValue(); 5341 5342 // Select the input vector, guarding against out of range extract vector. 5343 unsigned NumElems = VT.getVectorNumElements(); 5344 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5345 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5346 5347 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5348 InVec = InVec.getOperand(0); 5349 if (ISD::isNormalLoad(InVec.getNode())) { 5350 LN0 = cast<LoadSDNode>(InVec); 5351 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5352 } 5353 } 5354 5355 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5356 return SDValue(); 5357 5358 unsigned Align = LN0->getAlignment(); 5359 if (NewLoad) { 5360 // Check the resultant load doesn't need a higher alignment than the 5361 // original load. 5362 unsigned NewAlign = 5363 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 5364 5365 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5366 return SDValue(); 5367 5368 Align = NewAlign; 5369 } 5370 5371 SDValue NewPtr = LN0->getBasePtr(); 5372 if (Elt) { 5373 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5374 EVT PtrType = NewPtr.getValueType(); 5375 if (TLI.isBigEndian()) 5376 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5377 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5378 DAG.getConstant(PtrOff, PtrType)); 5379 } 5380 5381 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5382 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5383 LN0->isVolatile(), Align); 5384 } 5385 5386 return SDValue(); 5387} 5388 5389SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5390 unsigned NumInScalars = N->getNumOperands(); 5391 EVT VT = N->getValueType(0); 5392 EVT EltType = VT.getVectorElementType(); 5393 5394 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5395 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5396 // at most two distinct vectors, turn this into a shuffle node. 5397 SDValue VecIn1, VecIn2; 5398 for (unsigned i = 0; i != NumInScalars; ++i) { 5399 // Ignore undef inputs. 5400 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5401 5402 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5403 // constant index, bail out. 5404 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5405 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5406 VecIn1 = VecIn2 = SDValue(0, 0); 5407 break; 5408 } 5409 5410 // If the input vector type disagrees with the result of the build_vector, 5411 // we can't make a shuffle. 5412 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5413 if (ExtractedFromVec.getValueType() != VT) { 5414 VecIn1 = VecIn2 = SDValue(0, 0); 5415 break; 5416 } 5417 5418 // Otherwise, remember this. We allow up to two distinct input vectors. 5419 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5420 continue; 5421 5422 if (VecIn1.getNode() == 0) { 5423 VecIn1 = ExtractedFromVec; 5424 } else if (VecIn2.getNode() == 0) { 5425 VecIn2 = ExtractedFromVec; 5426 } else { 5427 // Too many inputs. 5428 VecIn1 = VecIn2 = SDValue(0, 0); 5429 break; 5430 } 5431 } 5432 5433 // If everything is good, we can make a shuffle operation. 5434 if (VecIn1.getNode()) { 5435 SmallVector<int, 8> Mask; 5436 for (unsigned i = 0; i != NumInScalars; ++i) { 5437 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5438 Mask.push_back(-1); 5439 continue; 5440 } 5441 5442 // If extracting from the first vector, just use the index directly. 5443 SDValue Extract = N->getOperand(i); 5444 SDValue ExtVal = Extract.getOperand(1); 5445 if (Extract.getOperand(0) == VecIn1) { 5446 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5447 if (ExtIndex > VT.getVectorNumElements()) 5448 return SDValue(); 5449 5450 Mask.push_back(ExtIndex); 5451 continue; 5452 } 5453 5454 // Otherwise, use InIdx + VecSize 5455 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5456 Mask.push_back(Idx+NumInScalars); 5457 } 5458 5459 // Add count and size info. 5460 if (!TLI.isTypeLegal(VT) && LegalTypes) 5461 return SDValue(); 5462 5463 // Return the new VECTOR_SHUFFLE node. 5464 SDValue Ops[2]; 5465 Ops[0] = VecIn1; 5466 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5467 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5468 } 5469 5470 return SDValue(); 5471} 5472 5473SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5474 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5475 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5476 // inputs come from at most two distinct vectors, turn this into a shuffle 5477 // node. 5478 5479 // If we only have one input vector, we don't need to do any concatenation. 5480 if (N->getNumOperands() == 1) 5481 return N->getOperand(0); 5482 5483 return SDValue(); 5484} 5485 5486SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5487 return SDValue(); 5488 5489 EVT VT = N->getValueType(0); 5490 unsigned NumElts = VT.getVectorNumElements(); 5491 5492 SDValue N0 = N->getOperand(0); 5493 SDValue N1 = N->getOperand(1); 5494 5495 assert(N0.getValueType().getVectorNumElements() == NumElts && 5496 "Vector shuffle must be normalized in DAG"); 5497 5498 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5499 5500 // If it is a splat, check if the argument vector is a build_vector with 5501 // all scalar elements the same. 5502 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5503 SDNode *V = N0.getNode(); 5504 5505 5506 // If this is a bit convert that changes the element type of the vector but 5507 // not the number of vector elements, look through it. Be careful not to 5508 // look though conversions that change things like v4f32 to v2f64. 5509 if (V->getOpcode() == ISD::BIT_CONVERT) { 5510 SDValue ConvInput = V->getOperand(0); 5511 if (ConvInput.getValueType().isVector() && 5512 ConvInput.getValueType().getVectorNumElements() == NumElts) 5513 V = ConvInput.getNode(); 5514 } 5515 5516 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5517 unsigned NumElems = V->getNumOperands(); 5518 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5519 if (NumElems > BaseIdx) { 5520 SDValue Base; 5521 bool AllSame = true; 5522 for (unsigned i = 0; i != NumElems; ++i) { 5523 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5524 Base = V->getOperand(i); 5525 break; 5526 } 5527 } 5528 // Splat of <u, u, u, u>, return <u, u, u, u> 5529 if (!Base.getNode()) 5530 return N0; 5531 for (unsigned i = 0; i != NumElems; ++i) { 5532 if (V->getOperand(i) != Base) { 5533 AllSame = false; 5534 break; 5535 } 5536 } 5537 // Splat of <x, x, x, x>, return <x, x, x, x> 5538 if (AllSame) 5539 return N0; 5540 } 5541 } 5542 } 5543 return SDValue(); 5544} 5545 5546/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5547/// an AND to a vector_shuffle with the destination vector and a zero vector. 5548/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5549/// vector_shuffle V, Zero, <0, 4, 2, 4> 5550SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5551 EVT VT = N->getValueType(0); 5552 DebugLoc dl = N->getDebugLoc(); 5553 SDValue LHS = N->getOperand(0); 5554 SDValue RHS = N->getOperand(1); 5555 if (N->getOpcode() == ISD::AND) { 5556 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5557 RHS = RHS.getOperand(0); 5558 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5559 SmallVector<int, 8> Indices; 5560 unsigned NumElts = RHS.getNumOperands(); 5561 for (unsigned i = 0; i != NumElts; ++i) { 5562 SDValue Elt = RHS.getOperand(i); 5563 if (!isa<ConstantSDNode>(Elt)) 5564 return SDValue(); 5565 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5566 Indices.push_back(i); 5567 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5568 Indices.push_back(NumElts); 5569 else 5570 return SDValue(); 5571 } 5572 5573 // Let's see if the target supports this vector_shuffle. 5574 EVT RVT = RHS.getValueType(); 5575 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5576 return SDValue(); 5577 5578 // Return the new VECTOR_SHUFFLE node. 5579 EVT EVT = RVT.getVectorElementType(); 5580 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5581 DAG.getConstant(0, EVT)); 5582 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5583 RVT, &ZeroOps[0], ZeroOps.size()); 5584 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5585 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5586 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5587 } 5588 } 5589 5590 return SDValue(); 5591} 5592 5593/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5594SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5595 // After legalize, the target may be depending on adds and other 5596 // binary ops to provide legal ways to construct constants or other 5597 // things. Simplifying them may result in a loss of legality. 5598 if (LegalOperations) return SDValue(); 5599 5600 EVT VT = N->getValueType(0); 5601 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5602 5603 EVT EltType = VT.getVectorElementType(); 5604 SDValue LHS = N->getOperand(0); 5605 SDValue RHS = N->getOperand(1); 5606 SDValue Shuffle = XformToShuffleWithZero(N); 5607 if (Shuffle.getNode()) return Shuffle; 5608 5609 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5610 // this operation. 5611 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5612 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5613 SmallVector<SDValue, 8> Ops; 5614 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5615 SDValue LHSOp = LHS.getOperand(i); 5616 SDValue RHSOp = RHS.getOperand(i); 5617 // If these two elements can't be folded, bail out. 5618 if ((LHSOp.getOpcode() != ISD::UNDEF && 5619 LHSOp.getOpcode() != ISD::Constant && 5620 LHSOp.getOpcode() != ISD::ConstantFP) || 5621 (RHSOp.getOpcode() != ISD::UNDEF && 5622 RHSOp.getOpcode() != ISD::Constant && 5623 RHSOp.getOpcode() != ISD::ConstantFP)) 5624 break; 5625 5626 // Can't fold divide by zero. 5627 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5628 N->getOpcode() == ISD::FDIV) { 5629 if ((RHSOp.getOpcode() == ISD::Constant && 5630 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5631 (RHSOp.getOpcode() == ISD::ConstantFP && 5632 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5633 break; 5634 } 5635 5636 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5637 EltType, LHSOp, RHSOp)); 5638 AddToWorkList(Ops.back().getNode()); 5639 assert((Ops.back().getOpcode() == ISD::UNDEF || 5640 Ops.back().getOpcode() == ISD::Constant || 5641 Ops.back().getOpcode() == ISD::ConstantFP) && 5642 "Scalar binop didn't fold!"); 5643 } 5644 5645 if (Ops.size() == LHS.getNumOperands()) { 5646 EVT VT = LHS.getValueType(); 5647 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5648 &Ops[0], Ops.size()); 5649 } 5650 } 5651 5652 return SDValue(); 5653} 5654 5655SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5656 SDValue N1, SDValue N2){ 5657 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5658 5659 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5660 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5661 5662 // If we got a simplified select_cc node back from SimplifySelectCC, then 5663 // break it down into a new SETCC node, and a new SELECT node, and then return 5664 // the SELECT node, since we were called with a SELECT node. 5665 if (SCC.getNode()) { 5666 // Check to see if we got a select_cc back (to turn into setcc/select). 5667 // Otherwise, just return whatever node we got back, like fabs. 5668 if (SCC.getOpcode() == ISD::SELECT_CC) { 5669 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5670 N0.getValueType(), 5671 SCC.getOperand(0), SCC.getOperand(1), 5672 SCC.getOperand(4)); 5673 AddToWorkList(SETCC.getNode()); 5674 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5675 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5676 } 5677 5678 return SCC; 5679 } 5680 return SDValue(); 5681} 5682 5683/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5684/// are the two values being selected between, see if we can simplify the 5685/// select. Callers of this should assume that TheSelect is deleted if this 5686/// returns true. As such, they should return the appropriate thing (e.g. the 5687/// node) back to the top-level of the DAG combiner loop to avoid it being 5688/// looked at. 5689bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5690 SDValue RHS) { 5691 5692 // If this is a select from two identical things, try to pull the operation 5693 // through the select. 5694 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5695 // If this is a load and the token chain is identical, replace the select 5696 // of two loads with a load through a select of the address to load from. 5697 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5698 // constants have been dropped into the constant pool. 5699 if (LHS.getOpcode() == ISD::LOAD && 5700 // Do not let this transformation reduce the number of volatile loads. 5701 !cast<LoadSDNode>(LHS)->isVolatile() && 5702 !cast<LoadSDNode>(RHS)->isVolatile() && 5703 // Token chains must be identical. 5704 LHS.getOperand(0) == RHS.getOperand(0)) { 5705 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5706 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5707 5708 // If this is an EXTLOAD, the VT's must match. 5709 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5710 // FIXME: this conflates two src values, discarding one. This is not 5711 // the right thing to do, but nothing uses srcvalues now. When they do, 5712 // turn SrcValue into a list of locations. 5713 SDValue Addr; 5714 if (TheSelect->getOpcode() == ISD::SELECT) { 5715 // Check that the condition doesn't reach either load. If so, folding 5716 // this will induce a cycle into the DAG. 5717 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5718 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5719 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5720 LLD->getBasePtr().getValueType(), 5721 TheSelect->getOperand(0), LLD->getBasePtr(), 5722 RLD->getBasePtr()); 5723 } 5724 } else { 5725 // Check that the condition doesn't reach either load. If so, folding 5726 // this will induce a cycle into the DAG. 5727 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5728 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5729 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5730 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5731 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5732 LLD->getBasePtr().getValueType(), 5733 TheSelect->getOperand(0), 5734 TheSelect->getOperand(1), 5735 LLD->getBasePtr(), RLD->getBasePtr(), 5736 TheSelect->getOperand(4)); 5737 } 5738 } 5739 5740 if (Addr.getNode()) { 5741 SDValue Load; 5742 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5743 Load = DAG.getLoad(TheSelect->getValueType(0), 5744 TheSelect->getDebugLoc(), 5745 LLD->getChain(), 5746 Addr,LLD->getSrcValue(), 5747 LLD->getSrcValueOffset(), 5748 LLD->isVolatile(), 5749 LLD->getAlignment()); 5750 } else { 5751 Load = DAG.getExtLoad(LLD->getExtensionType(), 5752 TheSelect->getDebugLoc(), 5753 TheSelect->getValueType(0), 5754 LLD->getChain(), Addr, LLD->getSrcValue(), 5755 LLD->getSrcValueOffset(), 5756 LLD->getMemoryVT(), 5757 LLD->isVolatile(), 5758 LLD->getAlignment()); 5759 } 5760 5761 // Users of the select now use the result of the load. 5762 CombineTo(TheSelect, Load); 5763 5764 // Users of the old loads now use the new load's chain. We know the 5765 // old-load value is dead now. 5766 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5767 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5768 return true; 5769 } 5770 } 5771 } 5772 } 5773 5774 return false; 5775} 5776 5777/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5778/// where 'cond' is the comparison specified by CC. 5779SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5780 SDValue N2, SDValue N3, 5781 ISD::CondCode CC, bool NotExtCompare) { 5782 // (x ? y : y) -> y. 5783 if (N2 == N3) return N2; 5784 5785 EVT VT = N2.getValueType(); 5786 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5787 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5788 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5789 5790 // Determine if the condition we're dealing with is constant 5791 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5792 N0, N1, CC, DL, false); 5793 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5794 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5795 5796 // fold select_cc true, x, y -> x 5797 if (SCCC && !SCCC->isNullValue()) 5798 return N2; 5799 // fold select_cc false, x, y -> y 5800 if (SCCC && SCCC->isNullValue()) 5801 return N3; 5802 5803 // Check to see if we can simplify the select into an fabs node 5804 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5805 // Allow either -0.0 or 0.0 5806 if (CFP->getValueAPF().isZero()) { 5807 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5808 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5809 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5810 N2 == N3.getOperand(0)) 5811 return DAG.getNode(ISD::FABS, DL, VT, N0); 5812 5813 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5814 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5815 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5816 N2.getOperand(0) == N3) 5817 return DAG.getNode(ISD::FABS, DL, VT, N3); 5818 } 5819 } 5820 5821 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5822 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5823 // in it. This is a win when the constant is not otherwise available because 5824 // it replaces two constant pool loads with one. We only do this if the FP 5825 // type is known to be legal, because if it isn't, then we are before legalize 5826 // types an we want the other legalization to happen first (e.g. to avoid 5827 // messing with soft float) and if the ConstantFP is not legal, because if 5828 // it is legal, we may not need to store the FP constant in a constant pool. 5829 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5830 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5831 if (TLI.isTypeLegal(N2.getValueType()) && 5832 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5833 TargetLowering::Legal) && 5834 // If both constants have multiple uses, then we won't need to do an 5835 // extra load, they are likely around in registers for other users. 5836 (TV->hasOneUse() || FV->hasOneUse())) { 5837 Constant *Elts[] = { 5838 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5839 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5840 }; 5841 const Type *FPTy = Elts[0]->getType(); 5842 const TargetData &TD = *TLI.getTargetData(); 5843 5844 // Create a ConstantArray of the two constants. 5845 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5846 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5847 TD.getPrefTypeAlignment(FPTy)); 5848 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5849 5850 // Get the offsets to the 0 and 1 element of the array so that we can 5851 // select between them. 5852 SDValue Zero = DAG.getIntPtrConstant(0); 5853 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5854 SDValue One = DAG.getIntPtrConstant(EltSize); 5855 5856 SDValue Cond = DAG.getSetCC(DL, 5857 TLI.getSetCCResultType(N0.getValueType()), 5858 N0, N1, CC); 5859 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5860 Cond, One, Zero); 5861 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5862 CstOffset); 5863 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5864 PseudoSourceValue::getConstantPool(), 0, false, 5865 Alignment); 5866 5867 } 5868 } 5869 5870 // Check to see if we can perform the "gzip trick", transforming 5871 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5872 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5873 N0.getValueType().isInteger() && 5874 N2.getValueType().isInteger() && 5875 (N1C->isNullValue() || // (a < 0) ? b : 0 5876 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5877 EVT XType = N0.getValueType(); 5878 EVT AType = N2.getValueType(); 5879 if (XType.bitsGE(AType)) { 5880 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5881 // single-bit constant. 5882 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5883 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5884 ShCtV = XType.getSizeInBits()-ShCtV-1; 5885 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5886 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5887 XType, N0, ShCt); 5888 AddToWorkList(Shift.getNode()); 5889 5890 if (XType.bitsGT(AType)) { 5891 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5892 AddToWorkList(Shift.getNode()); 5893 } 5894 5895 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5896 } 5897 5898 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5899 XType, N0, 5900 DAG.getConstant(XType.getSizeInBits()-1, 5901 getShiftAmountTy())); 5902 AddToWorkList(Shift.getNode()); 5903 5904 if (XType.bitsGT(AType)) { 5905 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5906 AddToWorkList(Shift.getNode()); 5907 } 5908 5909 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5910 } 5911 } 5912 5913 // fold select C, 16, 0 -> shl C, 4 5914 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5915 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5916 5917 // If the caller doesn't want us to simplify this into a zext of a compare, 5918 // don't do it. 5919 if (NotExtCompare && N2C->getAPIntValue() == 1) 5920 return SDValue(); 5921 5922 // Get a SetCC of the condition 5923 // FIXME: Should probably make sure that setcc is legal if we ever have a 5924 // target where it isn't. 5925 SDValue Temp, SCC; 5926 // cast from setcc result type to select result type 5927 if (LegalTypes) { 5928 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5929 N0, N1, CC); 5930 if (N2.getValueType().bitsLT(SCC.getValueType())) 5931 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5932 else 5933 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5934 N2.getValueType(), SCC); 5935 } else { 5936 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5937 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5938 N2.getValueType(), SCC); 5939 } 5940 5941 AddToWorkList(SCC.getNode()); 5942 AddToWorkList(Temp.getNode()); 5943 5944 if (N2C->getAPIntValue() == 1) 5945 return Temp; 5946 5947 // shl setcc result by log2 n2c 5948 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5949 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5950 getShiftAmountTy())); 5951 } 5952 5953 // Check to see if this is the equivalent of setcc 5954 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5955 // otherwise, go ahead with the folds. 5956 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5957 EVT XType = N0.getValueType(); 5958 if (!LegalOperations || 5959 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5960 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5961 if (Res.getValueType() != VT) 5962 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5963 return Res; 5964 } 5965 5966 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5967 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5968 (!LegalOperations || 5969 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5970 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5971 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5972 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5973 getShiftAmountTy())); 5974 } 5975 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5976 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5977 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5978 XType, DAG.getConstant(0, XType), N0); 5979 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5980 return DAG.getNode(ISD::SRL, DL, XType, 5981 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5982 DAG.getConstant(XType.getSizeInBits()-1, 5983 getShiftAmountTy())); 5984 } 5985 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5986 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5987 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5988 DAG.getConstant(XType.getSizeInBits()-1, 5989 getShiftAmountTy())); 5990 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5991 } 5992 } 5993 5994 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5995 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5996 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5997 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5998 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5999 EVT XType = N0.getValueType(); 6000 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6001 DAG.getConstant(XType.getSizeInBits()-1, 6002 getShiftAmountTy())); 6003 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6004 N0, Shift); 6005 AddToWorkList(Shift.getNode()); 6006 AddToWorkList(Add.getNode()); 6007 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6008 } 6009 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6010 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6011 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6012 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6013 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6014 EVT XType = N0.getValueType(); 6015 if (SubC->isNullValue() && XType.isInteger()) { 6016 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6017 N0, 6018 DAG.getConstant(XType.getSizeInBits()-1, 6019 getShiftAmountTy())); 6020 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6021 XType, N0, Shift); 6022 AddToWorkList(Shift.getNode()); 6023 AddToWorkList(Add.getNode()); 6024 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6025 } 6026 } 6027 } 6028 6029 return SDValue(); 6030} 6031 6032/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6033SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6034 SDValue N1, ISD::CondCode Cond, 6035 DebugLoc DL, bool foldBooleans) { 6036 TargetLowering::DAGCombinerInfo 6037 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6038 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6039} 6040 6041/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6042/// return a DAG expression to select that will generate the same value by 6043/// multiplying by a magic number. See: 6044/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6045SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6046 std::vector<SDNode*> Built; 6047 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6048 6049 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6050 ii != ee; ++ii) 6051 AddToWorkList(*ii); 6052 return S; 6053} 6054 6055/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6056/// return a DAG expression to select that will generate the same value by 6057/// multiplying by a magic number. See: 6058/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6059SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6060 std::vector<SDNode*> Built; 6061 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6062 6063 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6064 ii != ee; ++ii) 6065 AddToWorkList(*ii); 6066 return S; 6067} 6068 6069/// FindBaseOffset - Return true if base is known not to alias with anything 6070/// but itself. Provides base object and offset as results. 6071static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 6072 // Assume it is a primitive operation. 6073 Base = Ptr; Offset = 0; 6074 6075 // If it's an adding a simple constant then integrate the offset. 6076 if (Base.getOpcode() == ISD::ADD) { 6077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6078 Base = Base.getOperand(0); 6079 Offset += C->getZExtValue(); 6080 } 6081 } 6082 6083 // If it's any of the following then it can't alias with anything but itself. 6084 return isa<FrameIndexSDNode>(Base) || 6085 isa<ConstantPoolSDNode>(Base) || 6086 isa<GlobalAddressSDNode>(Base); 6087} 6088 6089/// isAlias - Return true if there is any possibility that the two addresses 6090/// overlap. 6091bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6092 const Value *SrcValue1, int SrcValueOffset1, 6093 SDValue Ptr2, int64_t Size2, 6094 const Value *SrcValue2, int SrcValueOffset2) const { 6095 // If they are the same then they must be aliases. 6096 if (Ptr1 == Ptr2) return true; 6097 6098 // Gather base node and offset information. 6099 SDValue Base1, Base2; 6100 int64_t Offset1, Offset2; 6101 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 6102 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 6103 6104 // If they have a same base address then... 6105 if (Base1 == Base2) 6106 // Check to see if the addresses overlap. 6107 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6108 6109 // If we know both bases then they can't alias. 6110 if (KnownBase1 && KnownBase2) return false; 6111 6112 if (CombinerGlobalAA) { 6113 // Use alias analysis information. 6114 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6115 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6116 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6117 AliasAnalysis::AliasResult AAResult = 6118 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6119 if (AAResult == AliasAnalysis::NoAlias) 6120 return false; 6121 } 6122 6123 // Otherwise we have to assume they alias. 6124 return true; 6125} 6126 6127/// FindAliasInfo - Extracts the relevant alias information from the memory 6128/// node. Returns true if the operand was a load. 6129bool DAGCombiner::FindAliasInfo(SDNode *N, 6130 SDValue &Ptr, int64_t &Size, 6131 const Value *&SrcValue, int &SrcValueOffset) const { 6132 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6133 Ptr = LD->getBasePtr(); 6134 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6135 SrcValue = LD->getSrcValue(); 6136 SrcValueOffset = LD->getSrcValueOffset(); 6137 return true; 6138 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6139 Ptr = ST->getBasePtr(); 6140 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6141 SrcValue = ST->getSrcValue(); 6142 SrcValueOffset = ST->getSrcValueOffset(); 6143 } else { 6144 llvm_unreachable("FindAliasInfo expected a memory operand"); 6145 } 6146 6147 return false; 6148} 6149 6150/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6151/// looking for aliasing nodes and adding them to the Aliases vector. 6152void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6153 SmallVector<SDValue, 8> &Aliases) { 6154 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6155 std::set<SDNode *> Visited; // Visited node set. 6156 6157 // Get alias information for node. 6158 SDValue Ptr; 6159 int64_t Size = 0; 6160 const Value *SrcValue = 0; 6161 int SrcValueOffset = 0; 6162 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6163 6164 // Starting off. 6165 Chains.push_back(OriginalChain); 6166 6167 // Look at each chain and determine if it is an alias. If so, add it to the 6168 // aliases list. If not, then continue up the chain looking for the next 6169 // candidate. 6170 while (!Chains.empty()) { 6171 SDValue Chain = Chains.back(); 6172 Chains.pop_back(); 6173 6174 // Don't bother if we've been before. 6175 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6176 Visited.insert(Chain.getNode()); 6177 6178 switch (Chain.getOpcode()) { 6179 case ISD::EntryToken: 6180 // Entry token is ideal chain operand, but handled in FindBetterChain. 6181 break; 6182 6183 case ISD::LOAD: 6184 case ISD::STORE: { 6185 // Get alias information for Chain. 6186 SDValue OpPtr; 6187 int64_t OpSize = 0; 6188 const Value *OpSrcValue = 0; 6189 int OpSrcValueOffset = 0; 6190 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6191 OpSrcValue, OpSrcValueOffset); 6192 6193 // If chain is alias then stop here. 6194 if (!(IsLoad && IsOpLoad) && 6195 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6196 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6197 Aliases.push_back(Chain); 6198 } else { 6199 // Look further up the chain. 6200 Chains.push_back(Chain.getOperand(0)); 6201 // Clean up old chain. 6202 AddToWorkList(Chain.getNode()); 6203 } 6204 break; 6205 } 6206 6207 case ISD::TokenFactor: 6208 // We have to check each of the operands of the token factor, so we queue 6209 // then up. Adding the operands to the queue (stack) in reverse order 6210 // maintains the original order and increases the likelihood that getNode 6211 // will find a matching token factor (CSE.) 6212 for (unsigned n = Chain.getNumOperands(); n;) 6213 Chains.push_back(Chain.getOperand(--n)); 6214 // Eliminate the token factor if we can. 6215 AddToWorkList(Chain.getNode()); 6216 break; 6217 6218 default: 6219 // For all other instructions we will just have to take what we can get. 6220 Aliases.push_back(Chain); 6221 break; 6222 } 6223 } 6224} 6225 6226/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6227/// for a better chain (aliasing node.) 6228SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6229 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6230 6231 // Accumulate all the aliases to this node. 6232 GatherAllAliases(N, OldChain, Aliases); 6233 6234 if (Aliases.size() == 0) { 6235 // If no operands then chain to entry token. 6236 return DAG.getEntryNode(); 6237 } else if (Aliases.size() == 1) { 6238 // If a single operand then chain to it. We don't need to revisit it. 6239 return Aliases[0]; 6240 } 6241 6242 // Construct a custom tailored token factor. 6243 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6244 &Aliases[0], Aliases.size()); 6245 6246 // Make sure the old chain gets cleaned up. 6247 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6248 6249 return NewChain; 6250} 6251 6252// SelectionDAG::Combine - This is the entry point for the file. 6253// 6254void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6255 CodeGenOpt::Level OptLevel) { 6256 /// run - This is the main entry point to this class. 6257 /// 6258 DAGCombiner(*this, AA, OptLevel).Run(Level); 6259} 6260