DAGCombiner.cpp revision 2b7a271c713ff1db83990f691126bc33d6c59b52
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetFrameInfo.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Support/Compiler.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include <algorithm> 38#include <set> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class VISIBILITY_HIDDEN DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 std::vector<SDNode*> WorkList; 67 68 // AA - Used for DAG load/store alias analysis. 69 AliasAnalysis &AA; 70 71 /// AddUsersToWorkList - When an instruction is simplified, add all users of 72 /// the instruction to the work lists because they might get more simplified 73 /// now. 74 /// 75 void AddUsersToWorkList(SDNode *N) { 76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 77 UI != UE; ++UI) 78 AddToWorkList(*UI); 79 } 80 81 /// visit - call the node-specific routine that knows how to fold each 82 /// particular type of node. 83 SDValue visit(SDNode *N); 84 85 public: 86 /// AddToWorkList - Add to the work list making sure it's instance is at the 87 /// the back (next to be processed.) 88 void AddToWorkList(SDNode *N) { 89 removeFromWorkList(N); 90 WorkList.push_back(N); 91 } 92 93 /// removeFromWorkList - remove all instances of N from the worklist. 94 /// 95 void removeFromWorkList(SDNode *N) { 96 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 97 WorkList.end()); 98 } 99 100 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 101 bool AddTo = true); 102 103 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 104 return CombineTo(N, &Res, 1, AddTo); 105 } 106 107 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 108 bool AddTo = true) { 109 SDValue To[] = { Res0, Res1 }; 110 return CombineTo(N, To, 2, AddTo); 111 } 112 113 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 114 115 private: 116 117 /// SimplifyDemandedBits - Check the specified integer node value to see if 118 /// it can be simplified or if things it uses can be simplified by bit 119 /// propagation. If so, return true. 120 bool SimplifyDemandedBits(SDValue Op) { 121 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 122 return SimplifyDemandedBits(Op, Demanded); 123 } 124 125 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 126 127 bool CombineToPreIndexedLoadStore(SDNode *N); 128 bool CombineToPostIndexedLoadStore(SDNode *N); 129 130 131 /// combine - call the node-specific routine that knows how to fold each 132 /// particular type of node. If that doesn't do anything, try the 133 /// target-specific DAG combines. 134 SDValue combine(SDNode *N); 135 136 // Visitation implementation - Implement dag node combining for different 137 // node types. The semantics are as follows: 138 // Return Value: 139 // SDValue.getNode() == 0 - No change was made 140 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 141 // otherwise - N should be replaced by the returned Operand. 142 // 143 SDValue visitTokenFactor(SDNode *N); 144 SDValue visitMERGE_VALUES(SDNode *N); 145 SDValue visitADD(SDNode *N); 146 SDValue visitSUB(SDNode *N); 147 SDValue visitADDC(SDNode *N); 148 SDValue visitADDE(SDNode *N); 149 SDValue visitMUL(SDNode *N); 150 SDValue visitSDIV(SDNode *N); 151 SDValue visitUDIV(SDNode *N); 152 SDValue visitSREM(SDNode *N); 153 SDValue visitUREM(SDNode *N); 154 SDValue visitMULHU(SDNode *N); 155 SDValue visitMULHS(SDNode *N); 156 SDValue visitSMUL_LOHI(SDNode *N); 157 SDValue visitUMUL_LOHI(SDNode *N); 158 SDValue visitSDIVREM(SDNode *N); 159 SDValue visitUDIVREM(SDNode *N); 160 SDValue visitAND(SDNode *N); 161 SDValue visitOR(SDNode *N); 162 SDValue visitXOR(SDNode *N); 163 SDValue SimplifyVBinOp(SDNode *N); 164 SDValue visitSHL(SDNode *N); 165 SDValue visitSRA(SDNode *N); 166 SDValue visitSRL(SDNode *N); 167 SDValue visitCTLZ(SDNode *N); 168 SDValue visitCTTZ(SDNode *N); 169 SDValue visitCTPOP(SDNode *N); 170 SDValue visitSELECT(SDNode *N); 171 SDValue visitSELECT_CC(SDNode *N); 172 SDValue visitSETCC(SDNode *N); 173 SDValue visitSIGN_EXTEND(SDNode *N); 174 SDValue visitZERO_EXTEND(SDNode *N); 175 SDValue visitANY_EXTEND(SDNode *N); 176 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 177 SDValue visitTRUNCATE(SDNode *N); 178 SDValue visitBIT_CONVERT(SDNode *N); 179 SDValue visitBUILD_PAIR(SDNode *N); 180 SDValue visitFADD(SDNode *N); 181 SDValue visitFSUB(SDNode *N); 182 SDValue visitFMUL(SDNode *N); 183 SDValue visitFDIV(SDNode *N); 184 SDValue visitFREM(SDNode *N); 185 SDValue visitFCOPYSIGN(SDNode *N); 186 SDValue visitSINT_TO_FP(SDNode *N); 187 SDValue visitUINT_TO_FP(SDNode *N); 188 SDValue visitFP_TO_SINT(SDNode *N); 189 SDValue visitFP_TO_UINT(SDNode *N); 190 SDValue visitFP_ROUND(SDNode *N); 191 SDValue visitFP_ROUND_INREG(SDNode *N); 192 SDValue visitFP_EXTEND(SDNode *N); 193 SDValue visitFNEG(SDNode *N); 194 SDValue visitFABS(SDNode *N); 195 SDValue visitBRCOND(SDNode *N); 196 SDValue visitBR_CC(SDNode *N); 197 SDValue visitLOAD(SDNode *N); 198 SDValue visitSTORE(SDNode *N); 199 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 200 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 201 SDValue visitBUILD_VECTOR(SDNode *N); 202 SDValue visitCONCAT_VECTORS(SDNode *N); 203 SDValue visitVECTOR_SHUFFLE(SDNode *N); 204 205 SDValue XformToShuffleWithZero(SDNode *N); 206 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 207 208 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 209 210 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 211 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 212 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 213 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 214 SDValue N3, ISD::CondCode CC, 215 bool NotExtCompare = false); 216 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 217 DebugLoc DL, bool foldBooleans = true); 218 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 219 unsigned HiOp); 220 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 221 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 222 SDValue BuildSDIV(SDNode *N); 223 SDValue BuildUDIV(SDNode *N); 224 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 225 SDValue ReduceLoadWidth(SDNode *N); 226 SDValue ReduceLoadOpStoreWidth(SDNode *N); 227 228 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 229 230 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 231 /// looking for aliasing nodes and adding them to the Aliases vector. 232 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 233 SmallVector<SDValue, 8> &Aliases); 234 235 /// isAlias - Return true if there is any possibility that the two addresses 236 /// overlap. 237 bool isAlias(SDValue Ptr1, int64_t Size1, 238 const Value *SrcValue1, int SrcValueOffset1, 239 SDValue Ptr2, int64_t Size2, 240 const Value *SrcValue2, int SrcValueOffset2) const; 241 242 /// FindAliasInfo - Extracts the relevant alias information from the memory 243 /// node. Returns true if the operand was a load. 244 bool FindAliasInfo(SDNode *N, 245 SDValue &Ptr, int64_t &Size, 246 const Value *&SrcValue, int &SrcValueOffset) const; 247 248 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 249 /// looking for a better chain (aliasing node.) 250 SDValue FindBetterChain(SDNode *N, SDValue Chain); 251 252 /// getShiftAmountTy - Returns a type large enough to hold any valid 253 /// shift amount - before type legalization these can be huge. 254 MVT getShiftAmountTy() { 255 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 256 } 257 258public: 259 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 260 : DAG(D), 261 TLI(D.getTargetLoweringInfo()), 262 Level(Unrestricted), 263 OptLevel(OL), 264 LegalOperations(false), 265 LegalTypes(false), 266 AA(A) {} 267 268 /// Run - runs the dag combiner on all nodes in the work list 269 void Run(CombineLevel AtLevel); 270 }; 271} 272 273 274namespace { 275/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 276/// nodes from the worklist. 277class VISIBILITY_HIDDEN WorkListRemover : 278 public SelectionDAG::DAGUpdateListener { 279 DAGCombiner &DC; 280public: 281 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 282 283 virtual void NodeDeleted(SDNode *N, SDNode *E) { 284 DC.removeFromWorkList(N); 285 } 286 287 virtual void NodeUpdated(SDNode *N) { 288 // Ignore updates. 289 } 290}; 291} 292 293//===----------------------------------------------------------------------===// 294// TargetLowering::DAGCombinerInfo implementation 295//===----------------------------------------------------------------------===// 296 297void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 298 ((DAGCombiner*)DC)->AddToWorkList(N); 299} 300 301SDValue TargetLowering::DAGCombinerInfo:: 302CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 303 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 304} 305 306SDValue TargetLowering::DAGCombinerInfo:: 307CombineTo(SDNode *N, SDValue Res, bool AddTo) { 308 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 309} 310 311 312SDValue TargetLowering::DAGCombinerInfo:: 313CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 314 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 315} 316 317void TargetLowering::DAGCombinerInfo:: 318CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 319 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 320} 321 322//===----------------------------------------------------------------------===// 323// Helper Functions 324//===----------------------------------------------------------------------===// 325 326/// isNegatibleForFree - Return 1 if we can compute the negated form of the 327/// specified expression for the same cost as the expression itself, or 2 if we 328/// can compute the negated form more cheaply than the expression itself. 329static char isNegatibleForFree(SDValue Op, bool LegalOperations, 330 unsigned Depth = 0) { 331 // No compile time optimizations on this type. 332 if (Op.getValueType() == MVT::ppcf128) 333 return 0; 334 335 // fneg is removable even if it has multiple uses. 336 if (Op.getOpcode() == ISD::FNEG) return 2; 337 338 // Don't allow anything with multiple uses. 339 if (!Op.hasOneUse()) return 0; 340 341 // Don't recurse exponentially. 342 if (Depth > 6) return 0; 343 344 switch (Op.getOpcode()) { 345 default: return false; 346 case ISD::ConstantFP: 347 // Don't invert constant FP values after legalize. The negated constant 348 // isn't necessarily legal. 349 return LegalOperations ? 0 : 1; 350 case ISD::FADD: 351 // FIXME: determine better conditions for this xform. 352 if (!UnsafeFPMath) return 0; 353 354 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 355 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 356 return V; 357 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 358 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 359 case ISD::FSUB: 360 // We can't turn -(A-B) into B-A when we honor signed zeros. 361 if (!UnsafeFPMath) return 0; 362 363 // fold (fneg (fsub A, B)) -> (fsub B, A) 364 return 1; 365 366 case ISD::FMUL: 367 case ISD::FDIV: 368 if (HonorSignDependentRoundingFPMath()) return 0; 369 370 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 371 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 372 return V; 373 374 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 375 376 case ISD::FP_EXTEND: 377 case ISD::FP_ROUND: 378 case ISD::FSIN: 379 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 380 } 381} 382 383/// GetNegatedExpression - If isNegatibleForFree returns true, this function 384/// returns the newly negated expression. 385static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 386 bool LegalOperations, unsigned Depth = 0) { 387 // fneg is removable even if it has multiple uses. 388 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 389 390 // Don't allow anything with multiple uses. 391 assert(Op.hasOneUse() && "Unknown reuse!"); 392 393 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 394 switch (Op.getOpcode()) { 395 default: assert(0 && "Unknown code"); 396 case ISD::ConstantFP: { 397 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 398 V.changeSign(); 399 return DAG.getConstantFP(V, Op.getValueType()); 400 } 401 case ISD::FADD: 402 // FIXME: determine better conditions for this xform. 403 assert(UnsafeFPMath); 404 405 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 406 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 407 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 408 GetNegatedExpression(Op.getOperand(0), DAG, 409 LegalOperations, Depth+1), 410 Op.getOperand(1)); 411 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 412 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 413 GetNegatedExpression(Op.getOperand(1), DAG, 414 LegalOperations, Depth+1), 415 Op.getOperand(0)); 416 case ISD::FSUB: 417 // We can't turn -(A-B) into B-A when we honor signed zeros. 418 assert(UnsafeFPMath); 419 420 // fold (fneg (fsub 0, B)) -> B 421 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 422 if (N0CFP->getValueAPF().isZero()) 423 return Op.getOperand(1); 424 425 // fold (fneg (fsub A, B)) -> (fsub B, A) 426 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 427 Op.getOperand(1), Op.getOperand(0)); 428 429 case ISD::FMUL: 430 case ISD::FDIV: 431 assert(!HonorSignDependentRoundingFPMath()); 432 433 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 434 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 435 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 436 GetNegatedExpression(Op.getOperand(0), DAG, 437 LegalOperations, Depth+1), 438 Op.getOperand(1)); 439 440 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 441 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 442 Op.getOperand(0), 443 GetNegatedExpression(Op.getOperand(1), DAG, 444 LegalOperations, Depth+1)); 445 446 case ISD::FP_EXTEND: 447 case ISD::FSIN: 448 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 449 GetNegatedExpression(Op.getOperand(0), DAG, 450 LegalOperations, Depth+1)); 451 case ISD::FP_ROUND: 452 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1), 455 Op.getOperand(1)); 456 } 457} 458 459 460// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 461// that selects between the values 1 and 0, making it equivalent to a setcc. 462// Also, set the incoming LHS, RHS, and CC references to the appropriate 463// nodes based on the type of node we are checking. This simplifies life a 464// bit for the callers. 465static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 466 SDValue &CC) { 467 if (N.getOpcode() == ISD::SETCC) { 468 LHS = N.getOperand(0); 469 RHS = N.getOperand(1); 470 CC = N.getOperand(2); 471 return true; 472 } 473 if (N.getOpcode() == ISD::SELECT_CC && 474 N.getOperand(2).getOpcode() == ISD::Constant && 475 N.getOperand(3).getOpcode() == ISD::Constant && 476 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 477 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 478 LHS = N.getOperand(0); 479 RHS = N.getOperand(1); 480 CC = N.getOperand(4); 481 return true; 482 } 483 return false; 484} 485 486// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 487// one use. If this is true, it allows the users to invert the operation for 488// free when it is profitable to do so. 489static bool isOneUseSetCC(SDValue N) { 490 SDValue N0, N1, N2; 491 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 492 return true; 493 return false; 494} 495 496SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 497 SDValue N0, SDValue N1) { 498 MVT VT = N0.getValueType(); 499 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 500 if (isa<ConstantSDNode>(N1)) { 501 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 502 SDValue OpNode = 503 DAG.FoldConstantArithmetic(Opc, VT, 504 cast<ConstantSDNode>(N0.getOperand(1)), 505 cast<ConstantSDNode>(N1)); 506 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 507 } else if (N0.hasOneUse()) { 508 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 509 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 510 N0.getOperand(0), N1); 511 AddToWorkList(OpNode.getNode()); 512 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 513 } 514 } 515 516 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 517 if (isa<ConstantSDNode>(N0)) { 518 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 519 SDValue OpNode = 520 DAG.FoldConstantArithmetic(Opc, VT, 521 cast<ConstantSDNode>(N1.getOperand(1)), 522 cast<ConstantSDNode>(N0)); 523 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 524 } else if (N1.hasOneUse()) { 525 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 526 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 527 N1.getOperand(0), N0); 528 AddToWorkList(OpNode.getNode()); 529 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 530 } 531 } 532 533 return SDValue(); 534} 535 536SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 537 bool AddTo) { 538 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 539 ++NodesCombined; 540 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 541 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 542 DOUT << " and " << NumTo-1 << " other values\n"; 543 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 544 assert(N->getValueType(i) == To[i].getValueType() && 545 "Cannot combine value to value of different type!")); 546 WorkListRemover DeadNodes(*this); 547 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 548 549 if (AddTo) { 550 // Push the new nodes and any users onto the worklist 551 for (unsigned i = 0, e = NumTo; i != e; ++i) { 552 if (To[i].getNode()) { 553 AddToWorkList(To[i].getNode()); 554 AddUsersToWorkList(To[i].getNode()); 555 } 556 } 557 } 558 559 // Finally, if the node is now dead, remove it from the graph. The node 560 // may not be dead if the replacement process recursively simplified to 561 // something else needing this node. 562 if (N->use_empty()) { 563 // Nodes can be reintroduced into the worklist. Make sure we do not 564 // process a node that has been replaced. 565 removeFromWorkList(N); 566 567 // Finally, since the node is now dead, remove it from the graph. 568 DAG.DeleteNode(N); 569 } 570 return SDValue(N, 0); 571} 572 573void 574DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 575 TLO) { 576 // Replace all uses. If any nodes become isomorphic to other nodes and 577 // are deleted, make sure to remove them from our worklist. 578 WorkListRemover DeadNodes(*this); 579 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 580 581 // Push the new node and any (possibly new) users onto the worklist. 582 AddToWorkList(TLO.New.getNode()); 583 AddUsersToWorkList(TLO.New.getNode()); 584 585 // Finally, if the node is now dead, remove it from the graph. The node 586 // may not be dead if the replacement process recursively simplified to 587 // something else needing this node. 588 if (TLO.Old.getNode()->use_empty()) { 589 removeFromWorkList(TLO.Old.getNode()); 590 591 // If the operands of this node are only used by the node, they will now 592 // be dead. Make sure to visit them first to delete dead nodes early. 593 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 594 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 595 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 596 597 DAG.DeleteNode(TLO.Old.getNode()); 598 } 599} 600 601/// SimplifyDemandedBits - Check the specified integer node value to see if 602/// it can be simplified or if things it uses can be simplified by bit 603/// propagation. If so, return true. 604bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 605 TargetLowering::TargetLoweringOpt TLO(DAG); 606 APInt KnownZero, KnownOne; 607 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 608 return false; 609 610 // Revisit the node. 611 AddToWorkList(Op.getNode()); 612 613 // Replace the old value with the new one. 614 ++NodesCombined; 615 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 616 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 617 DOUT << '\n'; 618 619 CommitTargetLoweringOpt(TLO); 620 return true; 621} 622 623//===----------------------------------------------------------------------===// 624// Main DAG Combiner implementation 625//===----------------------------------------------------------------------===// 626 627void DAGCombiner::Run(CombineLevel AtLevel) { 628 // set the instance variables, so that the various visit routines may use it. 629 Level = AtLevel; 630 LegalOperations = Level >= NoIllegalOperations; 631 LegalTypes = Level >= NoIllegalTypes; 632 633 // Add all the dag nodes to the worklist. 634 WorkList.reserve(DAG.allnodes_size()); 635 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 636 E = DAG.allnodes_end(); I != E; ++I) 637 WorkList.push_back(I); 638 639 // Create a dummy node (which is not added to allnodes), that adds a reference 640 // to the root node, preventing it from being deleted, and tracking any 641 // changes of the root. 642 HandleSDNode Dummy(DAG.getRoot()); 643 644 // The root of the dag may dangle to deleted nodes until the dag combiner is 645 // done. Set it to null to avoid confusion. 646 DAG.setRoot(SDValue()); 647 648 // while the worklist isn't empty, inspect the node on the end of it and 649 // try and combine it. 650 while (!WorkList.empty()) { 651 SDNode *N = WorkList.back(); 652 WorkList.pop_back(); 653 654 // If N has no uses, it is dead. Make sure to revisit all N's operands once 655 // N is deleted from the DAG, since they too may now be dead or may have a 656 // reduced number of uses, allowing other xforms. 657 if (N->use_empty() && N != &Dummy) { 658 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 659 AddToWorkList(N->getOperand(i).getNode()); 660 661 DAG.DeleteNode(N); 662 continue; 663 } 664 665 SDValue RV = combine(N); 666 667 if (RV.getNode() == 0) 668 continue; 669 670 ++NodesCombined; 671 672 // If we get back the same node we passed in, rather than a new node or 673 // zero, we know that the node must have defined multiple values and 674 // CombineTo was used. Since CombineTo takes care of the worklist 675 // mechanics for us, we have no work to do in this case. 676 if (RV.getNode() == N) 677 continue; 678 679 assert(N->getOpcode() != ISD::DELETED_NODE && 680 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 681 "Node was deleted but visit returned new node!"); 682 683 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 684 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 685 DOUT << '\n'; 686 WorkListRemover DeadNodes(*this); 687 if (N->getNumValues() == RV.getNode()->getNumValues()) 688 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 689 else { 690 assert(N->getValueType(0) == RV.getValueType() && 691 N->getNumValues() == 1 && "Type mismatch"); 692 SDValue OpV = RV; 693 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 694 } 695 696 // Push the new node and any users onto the worklist 697 AddToWorkList(RV.getNode()); 698 AddUsersToWorkList(RV.getNode()); 699 700 // Add any uses of the old node to the worklist in case this node is the 701 // last one that uses them. They may become dead after this node is 702 // deleted. 703 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 704 AddToWorkList(N->getOperand(i).getNode()); 705 706 // Finally, if the node is now dead, remove it from the graph. The node 707 // may not be dead if the replacement process recursively simplified to 708 // something else needing this node. 709 if (N->use_empty()) { 710 // Nodes can be reintroduced into the worklist. Make sure we do not 711 // process a node that has been replaced. 712 removeFromWorkList(N); 713 714 // Finally, since the node is now dead, remove it from the graph. 715 DAG.DeleteNode(N); 716 } 717 } 718 719 // If the root changed (e.g. it was a dead load, update the root). 720 DAG.setRoot(Dummy.getValue()); 721} 722 723SDValue DAGCombiner::visit(SDNode *N) { 724 switch(N->getOpcode()) { 725 default: break; 726 case ISD::TokenFactor: return visitTokenFactor(N); 727 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 728 case ISD::ADD: return visitADD(N); 729 case ISD::SUB: return visitSUB(N); 730 case ISD::ADDC: return visitADDC(N); 731 case ISD::ADDE: return visitADDE(N); 732 case ISD::MUL: return visitMUL(N); 733 case ISD::SDIV: return visitSDIV(N); 734 case ISD::UDIV: return visitUDIV(N); 735 case ISD::SREM: return visitSREM(N); 736 case ISD::UREM: return visitUREM(N); 737 case ISD::MULHU: return visitMULHU(N); 738 case ISD::MULHS: return visitMULHS(N); 739 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 740 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 741 case ISD::SDIVREM: return visitSDIVREM(N); 742 case ISD::UDIVREM: return visitUDIVREM(N); 743 case ISD::AND: return visitAND(N); 744 case ISD::OR: return visitOR(N); 745 case ISD::XOR: return visitXOR(N); 746 case ISD::SHL: return visitSHL(N); 747 case ISD::SRA: return visitSRA(N); 748 case ISD::SRL: return visitSRL(N); 749 case ISD::CTLZ: return visitCTLZ(N); 750 case ISD::CTTZ: return visitCTTZ(N); 751 case ISD::CTPOP: return visitCTPOP(N); 752 case ISD::SELECT: return visitSELECT(N); 753 case ISD::SELECT_CC: return visitSELECT_CC(N); 754 case ISD::SETCC: return visitSETCC(N); 755 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 756 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 757 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 758 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 759 case ISD::TRUNCATE: return visitTRUNCATE(N); 760 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 761 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 762 case ISD::FADD: return visitFADD(N); 763 case ISD::FSUB: return visitFSUB(N); 764 case ISD::FMUL: return visitFMUL(N); 765 case ISD::FDIV: return visitFDIV(N); 766 case ISD::FREM: return visitFREM(N); 767 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 768 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 769 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 770 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 771 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 772 case ISD::FP_ROUND: return visitFP_ROUND(N); 773 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 774 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 775 case ISD::FNEG: return visitFNEG(N); 776 case ISD::FABS: return visitFABS(N); 777 case ISD::BRCOND: return visitBRCOND(N); 778 case ISD::BR_CC: return visitBR_CC(N); 779 case ISD::LOAD: return visitLOAD(N); 780 case ISD::STORE: return visitSTORE(N); 781 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 782 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 783 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 784 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 785 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 786 } 787 return SDValue(); 788} 789 790SDValue DAGCombiner::combine(SDNode *N) { 791 SDValue RV = visit(N); 792 793 // If nothing happened, try a target-specific DAG combine. 794 if (RV.getNode() == 0) { 795 assert(N->getOpcode() != ISD::DELETED_NODE && 796 "Node was deleted but visit returned NULL!"); 797 798 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 799 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 800 801 // Expose the DAG combiner to the target combiner impls. 802 TargetLowering::DAGCombinerInfo 803 DagCombineInfo(DAG, Level == Unrestricted, false, this); 804 805 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 806 } 807 } 808 809 // If N is a commutative binary node, try commuting it to enable more 810 // sdisel CSE. 811 if (RV.getNode() == 0 && 812 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 813 N->getNumValues() == 1) { 814 SDValue N0 = N->getOperand(0); 815 SDValue N1 = N->getOperand(1); 816 817 // Constant operands are canonicalized to RHS. 818 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 819 SDValue Ops[] = { N1, N0 }; 820 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 821 Ops, 2); 822 if (CSENode) 823 return SDValue(CSENode, 0); 824 } 825 } 826 827 return RV; 828} 829 830/// getInputChainForNode - Given a node, return its input chain if it has one, 831/// otherwise return a null sd operand. 832static SDValue getInputChainForNode(SDNode *N) { 833 if (unsigned NumOps = N->getNumOperands()) { 834 if (N->getOperand(0).getValueType() == MVT::Other) 835 return N->getOperand(0); 836 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 837 return N->getOperand(NumOps-1); 838 for (unsigned i = 1; i < NumOps-1; ++i) 839 if (N->getOperand(i).getValueType() == MVT::Other) 840 return N->getOperand(i); 841 } 842 return SDValue(); 843} 844 845SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 846 // If N has two operands, where one has an input chain equal to the other, 847 // the 'other' chain is redundant. 848 if (N->getNumOperands() == 2) { 849 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 850 return N->getOperand(0); 851 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 852 return N->getOperand(1); 853 } 854 855 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 856 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 857 SmallPtrSet<SDNode*, 16> SeenOps; 858 bool Changed = false; // If we should replace this token factor. 859 860 // Start out with this token factor. 861 TFs.push_back(N); 862 863 // Iterate through token factors. The TFs grows when new token factors are 864 // encountered. 865 for (unsigned i = 0; i < TFs.size(); ++i) { 866 SDNode *TF = TFs[i]; 867 868 // Check each of the operands. 869 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 870 SDValue Op = TF->getOperand(i); 871 872 switch (Op.getOpcode()) { 873 case ISD::EntryToken: 874 // Entry tokens don't need to be added to the list. They are 875 // rededundant. 876 Changed = true; 877 break; 878 879 case ISD::TokenFactor: 880 if ((CombinerAA || Op.hasOneUse()) && 881 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 882 // Queue up for processing. 883 TFs.push_back(Op.getNode()); 884 // Clean up in case the token factor is removed. 885 AddToWorkList(Op.getNode()); 886 Changed = true; 887 break; 888 } 889 // Fall thru 890 891 default: 892 // Only add if it isn't already in the list. 893 if (SeenOps.insert(Op.getNode())) 894 Ops.push_back(Op); 895 else 896 Changed = true; 897 break; 898 } 899 } 900 } 901 902 SDValue Result; 903 904 // If we've change things around then replace token factor. 905 if (Changed) { 906 if (Ops.empty()) { 907 // The entry token is the only possible outcome. 908 Result = DAG.getEntryNode(); 909 } else { 910 // New and improved token factor. 911 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 912 MVT::Other, &Ops[0], Ops.size()); 913 } 914 915 // Don't add users to work list. 916 return CombineTo(N, Result, false); 917 } 918 919 return Result; 920} 921 922/// MERGE_VALUES can always be eliminated. 923SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 924 WorkListRemover DeadNodes(*this); 925 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 926 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 927 &DeadNodes); 928 removeFromWorkList(N); 929 DAG.DeleteNode(N); 930 return SDValue(N, 0); // Return N so it doesn't get rechecked! 931} 932 933static 934SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 935 SelectionDAG &DAG) { 936 MVT VT = N0.getValueType(); 937 SDValue N00 = N0.getOperand(0); 938 SDValue N01 = N0.getOperand(1); 939 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 940 941 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 942 isa<ConstantSDNode>(N00.getOperand(1))) { 943 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 944 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 945 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 946 N00.getOperand(0), N01), 947 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 948 N00.getOperand(1), N01)); 949 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 950 } 951 952 return SDValue(); 953} 954 955SDValue DAGCombiner::visitADD(SDNode *N) { 956 SDValue N0 = N->getOperand(0); 957 SDValue N1 = N->getOperand(1); 958 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 959 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 960 MVT VT = N0.getValueType(); 961 962 // fold vector ops 963 if (VT.isVector()) { 964 SDValue FoldedVOp = SimplifyVBinOp(N); 965 if (FoldedVOp.getNode()) return FoldedVOp; 966 } 967 968 // fold (add x, undef) -> undef 969 if (N0.getOpcode() == ISD::UNDEF) 970 return N0; 971 if (N1.getOpcode() == ISD::UNDEF) 972 return N1; 973 // fold (add c1, c2) -> c1+c2 974 if (N0C && N1C) 975 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 976 // canonicalize constant to RHS 977 if (N0C && !N1C) 978 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 979 // fold (add x, 0) -> x 980 if (N1C && N1C->isNullValue()) 981 return N0; 982 // fold (add Sym, c) -> Sym+c 983 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 984 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 985 GA->getOpcode() == ISD::GlobalAddress) 986 return DAG.getGlobalAddress(GA->getGlobal(), VT, 987 GA->getOffset() + 988 (uint64_t)N1C->getSExtValue()); 989 // fold ((c1-A)+c2) -> (c1+c2)-A 990 if (N1C && N0.getOpcode() == ISD::SUB) 991 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 992 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 993 DAG.getConstant(N1C->getAPIntValue()+ 994 N0C->getAPIntValue(), VT), 995 N0.getOperand(1)); 996 // reassociate add 997 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 998 if (RADD.getNode() != 0) 999 return RADD; 1000 // fold ((0-A) + B) -> B-A 1001 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1002 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1003 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1004 // fold (A + (0-B)) -> A-B 1005 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1006 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1007 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1008 // fold (A+(B-A)) -> B 1009 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1010 return N1.getOperand(0); 1011 // fold ((B-A)+A) -> B 1012 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1013 return N0.getOperand(0); 1014 // fold (A+(B-(A+C))) to (B-C) 1015 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1016 N0 == N1.getOperand(1).getOperand(0)) 1017 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1018 N1.getOperand(1).getOperand(1)); 1019 // fold (A+(B-(C+A))) to (B-C) 1020 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1021 N0 == N1.getOperand(1).getOperand(1)) 1022 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1023 N1.getOperand(1).getOperand(0)); 1024 // fold (A+((B-A)+or-C)) to (B+or-C) 1025 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1026 N1.getOperand(0).getOpcode() == ISD::SUB && 1027 N0 == N1.getOperand(0).getOperand(1)) 1028 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1029 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1030 1031 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1032 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1033 SDValue N00 = N0.getOperand(0); 1034 SDValue N01 = N0.getOperand(1); 1035 SDValue N10 = N1.getOperand(0); 1036 SDValue N11 = N1.getOperand(1); 1037 1038 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1039 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1040 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1041 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1042 } 1043 1044 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1045 return SDValue(N, 0); 1046 1047 // fold (a+b) -> (a|b) iff a and b share no bits. 1048 if (VT.isInteger() && !VT.isVector()) { 1049 APInt LHSZero, LHSOne; 1050 APInt RHSZero, RHSOne; 1051 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1052 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1053 1054 if (LHSZero.getBoolValue()) { 1055 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1056 1057 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1058 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1059 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1060 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1061 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1062 } 1063 } 1064 1065 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1066 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1067 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1068 if (Result.getNode()) return Result; 1069 } 1070 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1071 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1072 if (Result.getNode()) return Result; 1073 } 1074 1075 return SDValue(); 1076} 1077 1078SDValue DAGCombiner::visitADDC(SDNode *N) { 1079 SDValue N0 = N->getOperand(0); 1080 SDValue N1 = N->getOperand(1); 1081 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1082 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1083 MVT VT = N0.getValueType(); 1084 1085 // If the flag result is dead, turn this into an ADD. 1086 if (N->hasNUsesOfValue(0, 1)) 1087 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1088 DAG.getNode(ISD::CARRY_FALSE, 1089 N->getDebugLoc(), MVT::Flag)); 1090 1091 // canonicalize constant to RHS. 1092 if (N0C && !N1C) 1093 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1094 1095 // fold (addc x, 0) -> x + no carry out 1096 if (N1C && N1C->isNullValue()) 1097 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1098 N->getDebugLoc(), MVT::Flag)); 1099 1100 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1101 APInt LHSZero, LHSOne; 1102 APInt RHSZero, RHSOne; 1103 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1104 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1105 1106 if (LHSZero.getBoolValue()) { 1107 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1108 1109 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1110 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1111 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1112 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1113 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1114 DAG.getNode(ISD::CARRY_FALSE, 1115 N->getDebugLoc(), MVT::Flag)); 1116 } 1117 1118 return SDValue(); 1119} 1120 1121SDValue DAGCombiner::visitADDE(SDNode *N) { 1122 SDValue N0 = N->getOperand(0); 1123 SDValue N1 = N->getOperand(1); 1124 SDValue CarryIn = N->getOperand(2); 1125 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1126 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1127 1128 // canonicalize constant to RHS 1129 if (N0C && !N1C) 1130 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1131 N1, N0, CarryIn); 1132 1133 // fold (adde x, y, false) -> (addc x, y) 1134 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1135 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1136 1137 return SDValue(); 1138} 1139 1140SDValue DAGCombiner::visitSUB(SDNode *N) { 1141 SDValue N0 = N->getOperand(0); 1142 SDValue N1 = N->getOperand(1); 1143 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1144 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1145 MVT VT = N0.getValueType(); 1146 1147 // fold vector ops 1148 if (VT.isVector()) { 1149 SDValue FoldedVOp = SimplifyVBinOp(N); 1150 if (FoldedVOp.getNode()) return FoldedVOp; 1151 } 1152 1153 // fold (sub x, x) -> 0 1154 if (N0 == N1) 1155 return DAG.getConstant(0, N->getValueType(0)); 1156 // fold (sub c1, c2) -> c1-c2 1157 if (N0C && N1C) 1158 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1159 // fold (sub x, c) -> (add x, -c) 1160 if (N1C) 1161 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1162 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1163 // fold (A+B)-A -> B 1164 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1165 return N0.getOperand(1); 1166 // fold (A+B)-B -> A 1167 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1168 return N0.getOperand(0); 1169 // fold ((A+(B+or-C))-B) -> A+or-C 1170 if (N0.getOpcode() == ISD::ADD && 1171 (N0.getOperand(1).getOpcode() == ISD::SUB || 1172 N0.getOperand(1).getOpcode() == ISD::ADD) && 1173 N0.getOperand(1).getOperand(0) == N1) 1174 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1175 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1176 // fold ((A+(C+B))-B) -> A+C 1177 if (N0.getOpcode() == ISD::ADD && 1178 N0.getOperand(1).getOpcode() == ISD::ADD && 1179 N0.getOperand(1).getOperand(1) == N1) 1180 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1181 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1182 // fold ((A-(B-C))-C) -> A-B 1183 if (N0.getOpcode() == ISD::SUB && 1184 N0.getOperand(1).getOpcode() == ISD::SUB && 1185 N0.getOperand(1).getOperand(1) == N1) 1186 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1187 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1188 1189 // If either operand of a sub is undef, the result is undef 1190 if (N0.getOpcode() == ISD::UNDEF) 1191 return N0; 1192 if (N1.getOpcode() == ISD::UNDEF) 1193 return N1; 1194 1195 // If the relocation model supports it, consider symbol offsets. 1196 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1197 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1198 // fold (sub Sym, c) -> Sym-c 1199 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1200 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1201 GA->getOffset() - 1202 (uint64_t)N1C->getSExtValue()); 1203 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1204 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1205 if (GA->getGlobal() == GB->getGlobal()) 1206 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1207 VT); 1208 } 1209 1210 return SDValue(); 1211} 1212 1213SDValue DAGCombiner::visitMUL(SDNode *N) { 1214 SDValue N0 = N->getOperand(0); 1215 SDValue N1 = N->getOperand(1); 1216 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1217 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1218 MVT VT = N0.getValueType(); 1219 1220 // fold vector ops 1221 if (VT.isVector()) { 1222 SDValue FoldedVOp = SimplifyVBinOp(N); 1223 if (FoldedVOp.getNode()) return FoldedVOp; 1224 } 1225 1226 // fold (mul x, undef) -> 0 1227 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1228 return DAG.getConstant(0, VT); 1229 // fold (mul c1, c2) -> c1*c2 1230 if (N0C && N1C) 1231 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1232 // canonicalize constant to RHS 1233 if (N0C && !N1C) 1234 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1235 // fold (mul x, 0) -> 0 1236 if (N1C && N1C->isNullValue()) 1237 return N1; 1238 // fold (mul x, -1) -> 0-x 1239 if (N1C && N1C->isAllOnesValue()) 1240 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1241 DAG.getConstant(0, VT), N0); 1242 // fold (mul x, (1 << c)) -> x << c 1243 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1244 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1245 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1246 getShiftAmountTy())); 1247 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1248 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1249 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1250 // FIXME: If the input is something that is easily negated (e.g. a 1251 // single-use add), we should put the negate there. 1252 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1253 DAG.getConstant(0, VT), 1254 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1255 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1256 } 1257 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1258 if (N1C && N0.getOpcode() == ISD::SHL && 1259 isa<ConstantSDNode>(N0.getOperand(1))) { 1260 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1261 N1, N0.getOperand(1)); 1262 AddToWorkList(C3.getNode()); 1263 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1264 N0.getOperand(0), C3); 1265 } 1266 1267 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1268 // use. 1269 { 1270 SDValue Sh(0,0), Y(0,0); 1271 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1272 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1273 N0.getNode()->hasOneUse()) { 1274 Sh = N0; Y = N1; 1275 } else if (N1.getOpcode() == ISD::SHL && 1276 isa<ConstantSDNode>(N1.getOperand(1)) && 1277 N1.getNode()->hasOneUse()) { 1278 Sh = N1; Y = N0; 1279 } 1280 1281 if (Sh.getNode()) { 1282 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1283 Sh.getOperand(0), Y); 1284 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1285 Mul, Sh.getOperand(1)); 1286 } 1287 } 1288 1289 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1290 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1291 isa<ConstantSDNode>(N0.getOperand(1))) 1292 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1293 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1294 N0.getOperand(0), N1), 1295 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1296 N0.getOperand(1), N1)); 1297 1298 // reassociate mul 1299 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1300 if (RMUL.getNode() != 0) 1301 return RMUL; 1302 1303 return SDValue(); 1304} 1305 1306SDValue DAGCombiner::visitSDIV(SDNode *N) { 1307 SDValue N0 = N->getOperand(0); 1308 SDValue N1 = N->getOperand(1); 1309 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1310 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1311 MVT VT = N->getValueType(0); 1312 1313 // fold vector ops 1314 if (VT.isVector()) { 1315 SDValue FoldedVOp = SimplifyVBinOp(N); 1316 if (FoldedVOp.getNode()) return FoldedVOp; 1317 } 1318 1319 // fold (sdiv c1, c2) -> c1/c2 1320 if (N0C && N1C && !N1C->isNullValue()) 1321 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1322 // fold (sdiv X, 1) -> X 1323 if (N1C && N1C->getSExtValue() == 1LL) 1324 return N0; 1325 // fold (sdiv X, -1) -> 0-X 1326 if (N1C && N1C->isAllOnesValue()) 1327 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1328 DAG.getConstant(0, VT), N0); 1329 // If we know the sign bits of both operands are zero, strength reduce to a 1330 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1331 if (!VT.isVector()) { 1332 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1333 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1334 N0, N1); 1335 } 1336 // fold (sdiv X, pow2) -> simple ops after legalize 1337 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1338 (isPowerOf2_64(N1C->getSExtValue()) || 1339 isPowerOf2_64(-N1C->getSExtValue()))) { 1340 // If dividing by powers of two is cheap, then don't perform the following 1341 // fold. 1342 if (TLI.isPow2DivCheap()) 1343 return SDValue(); 1344 1345 int64_t pow2 = N1C->getSExtValue(); 1346 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1347 unsigned lg2 = Log2_64(abs2); 1348 1349 // Splat the sign bit into the register 1350 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1351 DAG.getConstant(VT.getSizeInBits()-1, 1352 getShiftAmountTy())); 1353 AddToWorkList(SGN.getNode()); 1354 1355 // Add (N0 < 0) ? abs2 - 1 : 0; 1356 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1357 DAG.getConstant(VT.getSizeInBits() - lg2, 1358 getShiftAmountTy())); 1359 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1360 AddToWorkList(SRL.getNode()); 1361 AddToWorkList(ADD.getNode()); // Divide by pow2 1362 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1363 DAG.getConstant(lg2, getShiftAmountTy())); 1364 1365 // If we're dividing by a positive value, we're done. Otherwise, we must 1366 // negate the result. 1367 if (pow2 > 0) 1368 return SRA; 1369 1370 AddToWorkList(SRA.getNode()); 1371 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1372 DAG.getConstant(0, VT), SRA); 1373 } 1374 1375 // if integer divide is expensive and we satisfy the requirements, emit an 1376 // alternate sequence. 1377 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1378 !TLI.isIntDivCheap()) { 1379 SDValue Op = BuildSDIV(N); 1380 if (Op.getNode()) return Op; 1381 } 1382 1383 // undef / X -> 0 1384 if (N0.getOpcode() == ISD::UNDEF) 1385 return DAG.getConstant(0, VT); 1386 // X / undef -> undef 1387 if (N1.getOpcode() == ISD::UNDEF) 1388 return N1; 1389 1390 return SDValue(); 1391} 1392 1393SDValue DAGCombiner::visitUDIV(SDNode *N) { 1394 SDValue N0 = N->getOperand(0); 1395 SDValue N1 = N->getOperand(1); 1396 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1397 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1398 MVT VT = N->getValueType(0); 1399 1400 // fold vector ops 1401 if (VT.isVector()) { 1402 SDValue FoldedVOp = SimplifyVBinOp(N); 1403 if (FoldedVOp.getNode()) return FoldedVOp; 1404 } 1405 1406 // fold (udiv c1, c2) -> c1/c2 1407 if (N0C && N1C && !N1C->isNullValue()) 1408 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1409 // fold (udiv x, (1 << c)) -> x >>u c 1410 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1411 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1412 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1413 getShiftAmountTy())); 1414 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1415 if (N1.getOpcode() == ISD::SHL) { 1416 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1417 if (SHC->getAPIntValue().isPowerOf2()) { 1418 MVT ADDVT = N1.getOperand(1).getValueType(); 1419 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1420 N1.getOperand(1), 1421 DAG.getConstant(SHC->getAPIntValue() 1422 .logBase2(), 1423 ADDVT)); 1424 AddToWorkList(Add.getNode()); 1425 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1426 } 1427 } 1428 } 1429 // fold (udiv x, c) -> alternate 1430 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1431 SDValue Op = BuildUDIV(N); 1432 if (Op.getNode()) return Op; 1433 } 1434 1435 // undef / X -> 0 1436 if (N0.getOpcode() == ISD::UNDEF) 1437 return DAG.getConstant(0, VT); 1438 // X / undef -> undef 1439 if (N1.getOpcode() == ISD::UNDEF) 1440 return N1; 1441 1442 return SDValue(); 1443} 1444 1445SDValue DAGCombiner::visitSREM(SDNode *N) { 1446 SDValue N0 = N->getOperand(0); 1447 SDValue N1 = N->getOperand(1); 1448 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1449 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1450 MVT VT = N->getValueType(0); 1451 1452 // fold (srem c1, c2) -> c1%c2 1453 if (N0C && N1C && !N1C->isNullValue()) 1454 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1455 // If we know the sign bits of both operands are zero, strength reduce to a 1456 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1457 if (!VT.isVector()) { 1458 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1459 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1460 } 1461 1462 // If X/C can be simplified by the division-by-constant logic, lower 1463 // X%C to the equivalent of X-X/C*C. 1464 if (N1C && !N1C->isNullValue()) { 1465 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1466 AddToWorkList(Div.getNode()); 1467 SDValue OptimizedDiv = combine(Div.getNode()); 1468 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1469 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1470 OptimizedDiv, N1); 1471 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1472 AddToWorkList(Mul.getNode()); 1473 return Sub; 1474 } 1475 } 1476 1477 // undef % X -> 0 1478 if (N0.getOpcode() == ISD::UNDEF) 1479 return DAG.getConstant(0, VT); 1480 // X % undef -> undef 1481 if (N1.getOpcode() == ISD::UNDEF) 1482 return N1; 1483 1484 return SDValue(); 1485} 1486 1487SDValue DAGCombiner::visitUREM(SDNode *N) { 1488 SDValue N0 = N->getOperand(0); 1489 SDValue N1 = N->getOperand(1); 1490 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1491 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1492 MVT VT = N->getValueType(0); 1493 1494 // fold (urem c1, c2) -> c1%c2 1495 if (N0C && N1C && !N1C->isNullValue()) 1496 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1497 // fold (urem x, pow2) -> (and x, pow2-1) 1498 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1499 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1500 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1501 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1502 if (N1.getOpcode() == ISD::SHL) { 1503 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1504 if (SHC->getAPIntValue().isPowerOf2()) { 1505 SDValue Add = 1506 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1507 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1508 VT)); 1509 AddToWorkList(Add.getNode()); 1510 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1511 } 1512 } 1513 } 1514 1515 // If X/C can be simplified by the division-by-constant logic, lower 1516 // X%C to the equivalent of X-X/C*C. 1517 if (N1C && !N1C->isNullValue()) { 1518 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1519 AddToWorkList(Div.getNode()); 1520 SDValue OptimizedDiv = combine(Div.getNode()); 1521 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1522 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1523 OptimizedDiv, N1); 1524 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1525 AddToWorkList(Mul.getNode()); 1526 return Sub; 1527 } 1528 } 1529 1530 // undef % X -> 0 1531 if (N0.getOpcode() == ISD::UNDEF) 1532 return DAG.getConstant(0, VT); 1533 // X % undef -> undef 1534 if (N1.getOpcode() == ISD::UNDEF) 1535 return N1; 1536 1537 return SDValue(); 1538} 1539 1540SDValue DAGCombiner::visitMULHS(SDNode *N) { 1541 SDValue N0 = N->getOperand(0); 1542 SDValue N1 = N->getOperand(1); 1543 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1544 MVT VT = N->getValueType(0); 1545 1546 // fold (mulhs x, 0) -> 0 1547 if (N1C && N1C->isNullValue()) 1548 return N1; 1549 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1550 if (N1C && N1C->getAPIntValue() == 1) 1551 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1552 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1553 getShiftAmountTy())); 1554 // fold (mulhs x, undef) -> 0 1555 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1556 return DAG.getConstant(0, VT); 1557 1558 return SDValue(); 1559} 1560 1561SDValue DAGCombiner::visitMULHU(SDNode *N) { 1562 SDValue N0 = N->getOperand(0); 1563 SDValue N1 = N->getOperand(1); 1564 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1565 MVT VT = N->getValueType(0); 1566 1567 // fold (mulhu x, 0) -> 0 1568 if (N1C && N1C->isNullValue()) 1569 return N1; 1570 // fold (mulhu x, 1) -> 0 1571 if (N1C && N1C->getAPIntValue() == 1) 1572 return DAG.getConstant(0, N0.getValueType()); 1573 // fold (mulhu x, undef) -> 0 1574 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1575 return DAG.getConstant(0, VT); 1576 1577 return SDValue(); 1578} 1579 1580/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1581/// compute two values. LoOp and HiOp give the opcodes for the two computations 1582/// that are being performed. Return true if a simplification was made. 1583/// 1584SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1585 unsigned HiOp) { 1586 // If the high half is not needed, just compute the low half. 1587 bool HiExists = N->hasAnyUseOfValue(1); 1588 if (!HiExists && 1589 (!LegalOperations || 1590 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1591 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1592 N->op_begin(), N->getNumOperands()); 1593 return CombineTo(N, Res, Res); 1594 } 1595 1596 // If the low half is not needed, just compute the high half. 1597 bool LoExists = N->hasAnyUseOfValue(0); 1598 if (!LoExists && 1599 (!LegalOperations || 1600 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1601 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1602 N->op_begin(), N->getNumOperands()); 1603 return CombineTo(N, Res, Res); 1604 } 1605 1606 // If both halves are used, return as it is. 1607 if (LoExists && HiExists) 1608 return SDValue(); 1609 1610 // If the two computed results can be simplified separately, separate them. 1611 if (LoExists) { 1612 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1613 N->op_begin(), N->getNumOperands()); 1614 AddToWorkList(Lo.getNode()); 1615 SDValue LoOpt = combine(Lo.getNode()); 1616 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1617 (!LegalOperations || 1618 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1619 return CombineTo(N, LoOpt, LoOpt); 1620 } 1621 1622 if (HiExists) { 1623 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1624 N->op_begin(), N->getNumOperands()); 1625 AddToWorkList(Hi.getNode()); 1626 SDValue HiOpt = combine(Hi.getNode()); 1627 if (HiOpt.getNode() && HiOpt != Hi && 1628 (!LegalOperations || 1629 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1630 return CombineTo(N, HiOpt, HiOpt); 1631 } 1632 1633 return SDValue(); 1634} 1635 1636SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1637 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1638 if (Res.getNode()) return Res; 1639 1640 return SDValue(); 1641} 1642 1643SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1644 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1645 if (Res.getNode()) return Res; 1646 1647 return SDValue(); 1648} 1649 1650SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1651 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1652 if (Res.getNode()) return Res; 1653 1654 return SDValue(); 1655} 1656 1657SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1658 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1659 if (Res.getNode()) return Res; 1660 1661 return SDValue(); 1662} 1663 1664/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1665/// two operands of the same opcode, try to simplify it. 1666SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1667 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1668 MVT VT = N0.getValueType(); 1669 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1670 1671 // For each of OP in AND/OR/XOR: 1672 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1673 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1674 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1675 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1676 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1677 N0.getOpcode() == ISD::SIGN_EXTEND || 1678 (N0.getOpcode() == ISD::TRUNCATE && 1679 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1680 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1681 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1682 N0.getOperand(0).getValueType(), 1683 N0.getOperand(0), N1.getOperand(0)); 1684 AddToWorkList(ORNode.getNode()); 1685 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1686 } 1687 1688 // For each of OP in SHL/SRL/SRA/AND... 1689 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1690 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1691 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1692 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1693 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1694 N0.getOperand(1) == N1.getOperand(1)) { 1695 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1696 N0.getOperand(0).getValueType(), 1697 N0.getOperand(0), N1.getOperand(0)); 1698 AddToWorkList(ORNode.getNode()); 1699 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1700 ORNode, N0.getOperand(1)); 1701 } 1702 1703 return SDValue(); 1704} 1705 1706SDValue DAGCombiner::visitAND(SDNode *N) { 1707 SDValue N0 = N->getOperand(0); 1708 SDValue N1 = N->getOperand(1); 1709 SDValue LL, LR, RL, RR, CC0, CC1; 1710 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1711 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1712 MVT VT = N1.getValueType(); 1713 unsigned BitWidth = VT.getSizeInBits(); 1714 1715 // fold vector ops 1716 if (VT.isVector()) { 1717 SDValue FoldedVOp = SimplifyVBinOp(N); 1718 if (FoldedVOp.getNode()) return FoldedVOp; 1719 } 1720 1721 // fold (and x, undef) -> 0 1722 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1723 return DAG.getConstant(0, VT); 1724 // fold (and c1, c2) -> c1&c2 1725 if (N0C && N1C) 1726 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1727 // canonicalize constant to RHS 1728 if (N0C && !N1C) 1729 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1730 // fold (and x, -1) -> x 1731 if (N1C && N1C->isAllOnesValue()) 1732 return N0; 1733 // if (and x, c) is known to be zero, return 0 1734 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1735 APInt::getAllOnesValue(BitWidth))) 1736 return DAG.getConstant(0, VT); 1737 // reassociate and 1738 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1739 if (RAND.getNode() != 0) 1740 return RAND; 1741 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1742 if (N1C && N0.getOpcode() == ISD::OR) 1743 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1744 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1745 return N1; 1746 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1747 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1748 SDValue N0Op0 = N0.getOperand(0); 1749 APInt Mask = ~N1C->getAPIntValue(); 1750 Mask.trunc(N0Op0.getValueSizeInBits()); 1751 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1752 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1753 N0.getValueType(), N0Op0); 1754 1755 // Replace uses of the AND with uses of the Zero extend node. 1756 CombineTo(N, Zext); 1757 1758 // We actually want to replace all uses of the any_extend with the 1759 // zero_extend, to avoid duplicating things. This will later cause this 1760 // AND to be folded. 1761 CombineTo(N0.getNode(), Zext); 1762 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1763 } 1764 } 1765 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1766 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1767 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1768 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1769 1770 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1771 LL.getValueType().isInteger()) { 1772 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1773 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1774 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1775 LR.getValueType(), LL, RL); 1776 AddToWorkList(ORNode.getNode()); 1777 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1778 } 1779 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1780 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1781 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1782 LR.getValueType(), LL, RL); 1783 AddToWorkList(ANDNode.getNode()); 1784 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1785 } 1786 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1787 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1788 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1789 LR.getValueType(), LL, RL); 1790 AddToWorkList(ORNode.getNode()); 1791 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1792 } 1793 } 1794 // canonicalize equivalent to ll == rl 1795 if (LL == RR && LR == RL) { 1796 Op1 = ISD::getSetCCSwappedOperands(Op1); 1797 std::swap(RL, RR); 1798 } 1799 if (LL == RL && LR == RR) { 1800 bool isInteger = LL.getValueType().isInteger(); 1801 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1802 if (Result != ISD::SETCC_INVALID && 1803 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1804 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1805 LL, LR, Result); 1806 } 1807 } 1808 1809 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1810 if (N0.getOpcode() == N1.getOpcode()) { 1811 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1812 if (Tmp.getNode()) return Tmp; 1813 } 1814 1815 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1816 // fold (and (sra)) -> (and (srl)) when possible. 1817 if (!VT.isVector() && 1818 SimplifyDemandedBits(SDValue(N, 0))) 1819 return SDValue(N, 0); 1820 // fold (zext_inreg (extload x)) -> (zextload x) 1821 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1822 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1823 MVT EVT = LN0->getMemoryVT(); 1824 // If we zero all the possible extended bits, then we can turn this into 1825 // a zextload if we are running before legalize or the operation is legal. 1826 unsigned BitWidth = N1.getValueSizeInBits(); 1827 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1828 BitWidth - EVT.getSizeInBits())) && 1829 ((!LegalOperations && !LN0->isVolatile()) || 1830 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1831 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1832 LN0->getChain(), LN0->getBasePtr(), 1833 LN0->getSrcValue(), 1834 LN0->getSrcValueOffset(), EVT, 1835 LN0->isVolatile(), LN0->getAlignment()); 1836 AddToWorkList(N); 1837 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1838 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1839 } 1840 } 1841 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1842 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1843 N0.hasOneUse()) { 1844 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1845 MVT EVT = LN0->getMemoryVT(); 1846 // If we zero all the possible extended bits, then we can turn this into 1847 // a zextload if we are running before legalize or the operation is legal. 1848 unsigned BitWidth = N1.getValueSizeInBits(); 1849 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1850 BitWidth - EVT.getSizeInBits())) && 1851 ((!LegalOperations && !LN0->isVolatile()) || 1852 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1853 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1854 LN0->getChain(), 1855 LN0->getBasePtr(), LN0->getSrcValue(), 1856 LN0->getSrcValueOffset(), EVT, 1857 LN0->isVolatile(), LN0->getAlignment()); 1858 AddToWorkList(N); 1859 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1860 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1861 } 1862 } 1863 1864 // fold (and (load x), 255) -> (zextload x, i8) 1865 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1866 if (N1C && N0.getOpcode() == ISD::LOAD) { 1867 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1868 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1869 LN0->isUnindexed() && N0.hasOneUse() && 1870 // Do not change the width of a volatile load. 1871 !LN0->isVolatile()) { 1872 MVT EVT = MVT::Other; 1873 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1874 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1875 EVT = MVT::getIntegerVT(ActiveBits); 1876 1877 MVT LoadedVT = LN0->getMemoryVT(); 1878 1879 // Do not generate loads of non-round integer types since these can 1880 // be expensive (and would be wrong if the type is not byte sized). 1881 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1882 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1883 MVT PtrType = N0.getOperand(1).getValueType(); 1884 1885 // For big endian targets, we need to add an offset to the pointer to 1886 // load the correct bytes. For little endian systems, we merely need to 1887 // read fewer bytes from the same pointer. 1888 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1889 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1890 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1891 unsigned Alignment = LN0->getAlignment(); 1892 SDValue NewPtr = LN0->getBasePtr(); 1893 1894 if (TLI.isBigEndian()) { 1895 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1896 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1897 Alignment = MinAlign(Alignment, PtrOff); 1898 } 1899 1900 AddToWorkList(NewPtr.getNode()); 1901 SDValue Load = 1902 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1903 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1904 EVT, LN0->isVolatile(), Alignment); 1905 AddToWorkList(N); 1906 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1907 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1908 } 1909 } 1910 } 1911 1912 return SDValue(); 1913} 1914 1915SDValue DAGCombiner::visitOR(SDNode *N) { 1916 SDValue N0 = N->getOperand(0); 1917 SDValue N1 = N->getOperand(1); 1918 SDValue LL, LR, RL, RR, CC0, CC1; 1919 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1920 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1921 MVT VT = N1.getValueType(); 1922 1923 // fold vector ops 1924 if (VT.isVector()) { 1925 SDValue FoldedVOp = SimplifyVBinOp(N); 1926 if (FoldedVOp.getNode()) return FoldedVOp; 1927 } 1928 1929 // fold (or x, undef) -> -1 1930 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1931 return DAG.getConstant(~0ULL, VT); 1932 // fold (or c1, c2) -> c1|c2 1933 if (N0C && N1C) 1934 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1935 // canonicalize constant to RHS 1936 if (N0C && !N1C) 1937 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1938 // fold (or x, 0) -> x 1939 if (N1C && N1C->isNullValue()) 1940 return N0; 1941 // fold (or x, -1) -> -1 1942 if (N1C && N1C->isAllOnesValue()) 1943 return N1; 1944 // fold (or x, c) -> c iff (x & ~c) == 0 1945 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1946 return N1; 1947 // reassociate or 1948 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1949 if (ROR.getNode() != 0) 1950 return ROR; 1951 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1952 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1953 isa<ConstantSDNode>(N0.getOperand(1))) { 1954 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1955 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1956 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1957 N0.getOperand(0), N1), 1958 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1959 } 1960 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1961 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1962 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1963 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1964 1965 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1966 LL.getValueType().isInteger()) { 1967 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1968 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1969 if (cast<ConstantSDNode>(LR)->isNullValue() && 1970 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1971 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1972 LR.getValueType(), LL, RL); 1973 AddToWorkList(ORNode.getNode()); 1974 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1975 } 1976 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 1977 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 1978 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1979 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1980 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 1981 LR.getValueType(), LL, RL); 1982 AddToWorkList(ANDNode.getNode()); 1983 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1984 } 1985 } 1986 // canonicalize equivalent to ll == rl 1987 if (LL == RR && LR == RL) { 1988 Op1 = ISD::getSetCCSwappedOperands(Op1); 1989 std::swap(RL, RR); 1990 } 1991 if (LL == RL && LR == RR) { 1992 bool isInteger = LL.getValueType().isInteger(); 1993 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1994 if (Result != ISD::SETCC_INVALID && 1995 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1996 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1997 LL, LR, Result); 1998 } 1999 } 2000 2001 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2002 if (N0.getOpcode() == N1.getOpcode()) { 2003 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2004 if (Tmp.getNode()) return Tmp; 2005 } 2006 2007 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2008 if (N0.getOpcode() == ISD::AND && 2009 N1.getOpcode() == ISD::AND && 2010 N0.getOperand(1).getOpcode() == ISD::Constant && 2011 N1.getOperand(1).getOpcode() == ISD::Constant && 2012 // Don't increase # computations. 2013 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2014 // We can only do this xform if we know that bits from X that are set in C2 2015 // but not in C1 are already zero. Likewise for Y. 2016 const APInt &LHSMask = 2017 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2018 const APInt &RHSMask = 2019 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2020 2021 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2022 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2023 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2024 N0.getOperand(0), N1.getOperand(0)); 2025 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2026 DAG.getConstant(LHSMask | RHSMask, VT)); 2027 } 2028 } 2029 2030 // See if this is some rotate idiom. 2031 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2032 return SDValue(Rot, 0); 2033 2034 return SDValue(); 2035} 2036 2037/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2038static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2039 if (Op.getOpcode() == ISD::AND) { 2040 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2041 Mask = Op.getOperand(1); 2042 Op = Op.getOperand(0); 2043 } else { 2044 return false; 2045 } 2046 } 2047 2048 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2049 Shift = Op; 2050 return true; 2051 } 2052 2053 return false; 2054} 2055 2056// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2057// idioms for rotate, and if the target supports rotation instructions, generate 2058// a rot[lr]. 2059SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2060 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2061 MVT VT = LHS.getValueType(); 2062 if (!TLI.isTypeLegal(VT)) return 0; 2063 2064 // The target must have at least one rotate flavor. 2065 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2066 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2067 if (!HasROTL && !HasROTR) return 0; 2068 2069 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2070 SDValue LHSShift; // The shift. 2071 SDValue LHSMask; // AND value if any. 2072 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2073 return 0; // Not part of a rotate. 2074 2075 SDValue RHSShift; // The shift. 2076 SDValue RHSMask; // AND value if any. 2077 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2078 return 0; // Not part of a rotate. 2079 2080 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2081 return 0; // Not shifting the same value. 2082 2083 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2084 return 0; // Shifts must disagree. 2085 2086 // Canonicalize shl to left side in a shl/srl pair. 2087 if (RHSShift.getOpcode() == ISD::SHL) { 2088 std::swap(LHS, RHS); 2089 std::swap(LHSShift, RHSShift); 2090 std::swap(LHSMask , RHSMask ); 2091 } 2092 2093 unsigned OpSizeInBits = VT.getSizeInBits(); 2094 SDValue LHSShiftArg = LHSShift.getOperand(0); 2095 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2096 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2097 2098 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2099 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2100 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2101 RHSShiftAmt.getOpcode() == ISD::Constant) { 2102 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2103 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2104 if ((LShVal + RShVal) != OpSizeInBits) 2105 return 0; 2106 2107 SDValue Rot; 2108 if (HasROTL) 2109 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2110 else 2111 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2112 2113 // If there is an AND of either shifted operand, apply it to the result. 2114 if (LHSMask.getNode() || RHSMask.getNode()) { 2115 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2116 2117 if (LHSMask.getNode()) { 2118 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2119 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2120 } 2121 if (RHSMask.getNode()) { 2122 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2123 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2124 } 2125 2126 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2127 } 2128 2129 return Rot.getNode(); 2130 } 2131 2132 // If there is a mask here, and we have a variable shift, we can't be sure 2133 // that we're masking out the right stuff. 2134 if (LHSMask.getNode() || RHSMask.getNode()) 2135 return 0; 2136 2137 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2138 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2139 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2140 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2141 if (ConstantSDNode *SUBC = 2142 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2143 if (SUBC->getAPIntValue() == OpSizeInBits) { 2144 if (HasROTL) 2145 return DAG.getNode(ISD::ROTL, DL, VT, 2146 LHSShiftArg, LHSShiftAmt).getNode(); 2147 else 2148 return DAG.getNode(ISD::ROTR, DL, VT, 2149 LHSShiftArg, RHSShiftAmt).getNode(); 2150 } 2151 } 2152 } 2153 2154 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2155 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2156 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2157 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2158 if (ConstantSDNode *SUBC = 2159 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2160 if (SUBC->getAPIntValue() == OpSizeInBits) { 2161 if (HasROTR) 2162 return DAG.getNode(ISD::ROTR, DL, VT, 2163 LHSShiftArg, RHSShiftAmt).getNode(); 2164 else 2165 return DAG.getNode(ISD::ROTL, DL, VT, 2166 LHSShiftArg, LHSShiftAmt).getNode(); 2167 } 2168 } 2169 } 2170 2171 // Look for sign/zext/any-extended or truncate cases: 2172 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2173 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2174 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2175 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2176 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2177 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2178 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2179 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2180 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2181 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2182 if (RExtOp0.getOpcode() == ISD::SUB && 2183 RExtOp0.getOperand(1) == LExtOp0) { 2184 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2185 // (rotl x, y) 2186 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2187 // (rotr x, (sub 32, y)) 2188 if (ConstantSDNode *SUBC = 2189 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2190 if (SUBC->getAPIntValue() == OpSizeInBits) { 2191 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2192 LHSShiftArg, 2193 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2194 } 2195 } 2196 } else if (LExtOp0.getOpcode() == ISD::SUB && 2197 RExtOp0 == LExtOp0.getOperand(1)) { 2198 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2199 // (rotr x, y) 2200 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2201 // (rotl x, (sub 32, y)) 2202 if (ConstantSDNode *SUBC = 2203 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2204 if (SUBC->getAPIntValue() == OpSizeInBits) { 2205 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2206 LHSShiftArg, 2207 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2208 } 2209 } 2210 } 2211 } 2212 2213 return 0; 2214} 2215 2216SDValue DAGCombiner::visitXOR(SDNode *N) { 2217 SDValue N0 = N->getOperand(0); 2218 SDValue N1 = N->getOperand(1); 2219 SDValue LHS, RHS, CC; 2220 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2221 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2222 MVT VT = N0.getValueType(); 2223 2224 // fold vector ops 2225 if (VT.isVector()) { 2226 SDValue FoldedVOp = SimplifyVBinOp(N); 2227 if (FoldedVOp.getNode()) return FoldedVOp; 2228 } 2229 2230 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2231 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2232 return DAG.getConstant(0, VT); 2233 // fold (xor x, undef) -> undef 2234 if (N0.getOpcode() == ISD::UNDEF) 2235 return N0; 2236 if (N1.getOpcode() == ISD::UNDEF) 2237 return N1; 2238 // fold (xor c1, c2) -> c1^c2 2239 if (N0C && N1C) 2240 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2241 // canonicalize constant to RHS 2242 if (N0C && !N1C) 2243 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2244 // fold (xor x, 0) -> x 2245 if (N1C && N1C->isNullValue()) 2246 return N0; 2247 // reassociate xor 2248 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2249 if (RXOR.getNode() != 0) 2250 return RXOR; 2251 2252 // fold !(x cc y) -> (x !cc y) 2253 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2254 bool isInt = LHS.getValueType().isInteger(); 2255 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2256 isInt); 2257 2258 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2259 switch (N0.getOpcode()) { 2260 default: 2261 assert(0 && "Unhandled SetCC Equivalent!"); 2262 abort(); 2263 case ISD::SETCC: 2264 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2265 case ISD::SELECT_CC: 2266 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2267 N0.getOperand(3), NotCC); 2268 } 2269 } 2270 } 2271 2272 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2273 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2274 N0.getNode()->hasOneUse() && 2275 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2276 SDValue V = N0.getOperand(0); 2277 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2278 DAG.getConstant(1, V.getValueType())); 2279 AddToWorkList(V.getNode()); 2280 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2281 } 2282 2283 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2284 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2285 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2286 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2287 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2288 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2289 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2290 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2291 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2292 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2293 } 2294 } 2295 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2296 if (N1C && N1C->isAllOnesValue() && 2297 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2298 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2299 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2300 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2301 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2302 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2303 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2304 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2305 } 2306 } 2307 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2308 if (N1C && N0.getOpcode() == ISD::XOR) { 2309 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2310 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2311 if (N00C) 2312 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2313 DAG.getConstant(N1C->getAPIntValue() ^ 2314 N00C->getAPIntValue(), VT)); 2315 if (N01C) 2316 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2317 DAG.getConstant(N1C->getAPIntValue() ^ 2318 N01C->getAPIntValue(), VT)); 2319 } 2320 // fold (xor x, x) -> 0 2321 if (N0 == N1) { 2322 if (!VT.isVector()) { 2323 return DAG.getConstant(0, VT); 2324 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2325 // Produce a vector of zeros. 2326 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2327 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2328 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2329 &Ops[0], Ops.size()); 2330 } 2331 } 2332 2333 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2334 if (N0.getOpcode() == N1.getOpcode()) { 2335 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2336 if (Tmp.getNode()) return Tmp; 2337 } 2338 2339 // Simplify the expression using non-local knowledge. 2340 if (!VT.isVector() && 2341 SimplifyDemandedBits(SDValue(N, 0))) 2342 return SDValue(N, 0); 2343 2344 return SDValue(); 2345} 2346 2347/// visitShiftByConstant - Handle transforms common to the three shifts, when 2348/// the shift amount is a constant. 2349SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2350 SDNode *LHS = N->getOperand(0).getNode(); 2351 if (!LHS->hasOneUse()) return SDValue(); 2352 2353 // We want to pull some binops through shifts, so that we have (and (shift)) 2354 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2355 // thing happens with address calculations, so it's important to canonicalize 2356 // it. 2357 bool HighBitSet = false; // Can we transform this if the high bit is set? 2358 2359 switch (LHS->getOpcode()) { 2360 default: return SDValue(); 2361 case ISD::OR: 2362 case ISD::XOR: 2363 HighBitSet = false; // We can only transform sra if the high bit is clear. 2364 break; 2365 case ISD::AND: 2366 HighBitSet = true; // We can only transform sra if the high bit is set. 2367 break; 2368 case ISD::ADD: 2369 if (N->getOpcode() != ISD::SHL) 2370 return SDValue(); // only shl(add) not sr[al](add). 2371 HighBitSet = false; // We can only transform sra if the high bit is clear. 2372 break; 2373 } 2374 2375 // We require the RHS of the binop to be a constant as well. 2376 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2377 if (!BinOpCst) return SDValue(); 2378 2379 // FIXME: disable this unless the input to the binop is a shift by a constant. 2380 // If it is not a shift, it pessimizes some common cases like: 2381 // 2382 // void foo(int *X, int i) { X[i & 1235] = 1; } 2383 // int bar(int *X, int i) { return X[i & 255]; } 2384 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2385 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2386 BinOpLHSVal->getOpcode() != ISD::SRA && 2387 BinOpLHSVal->getOpcode() != ISD::SRL) || 2388 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2389 return SDValue(); 2390 2391 MVT VT = N->getValueType(0); 2392 2393 // If this is a signed shift right, and the high bit is modified by the 2394 // logical operation, do not perform the transformation. The highBitSet 2395 // boolean indicates the value of the high bit of the constant which would 2396 // cause it to be modified for this operation. 2397 if (N->getOpcode() == ISD::SRA) { 2398 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2399 if (BinOpRHSSignSet != HighBitSet) 2400 return SDValue(); 2401 } 2402 2403 // Fold the constants, shifting the binop RHS by the shift amount. 2404 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2405 N->getValueType(0), 2406 LHS->getOperand(1), N->getOperand(1)); 2407 2408 // Create the new shift. 2409 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2410 VT, LHS->getOperand(0), N->getOperand(1)); 2411 2412 // Create the new binop. 2413 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2414} 2415 2416SDValue DAGCombiner::visitSHL(SDNode *N) { 2417 SDValue N0 = N->getOperand(0); 2418 SDValue N1 = N->getOperand(1); 2419 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2420 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2421 MVT VT = N0.getValueType(); 2422 unsigned OpSizeInBits = VT.getSizeInBits(); 2423 2424 // fold (shl c1, c2) -> c1<<c2 2425 if (N0C && N1C) 2426 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2427 // fold (shl 0, x) -> 0 2428 if (N0C && N0C->isNullValue()) 2429 return N0; 2430 // fold (shl x, c >= size(x)) -> undef 2431 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2432 return DAG.getUNDEF(VT); 2433 // fold (shl x, 0) -> x 2434 if (N1C && N1C->isNullValue()) 2435 return N0; 2436 // if (shl x, c) is known to be zero, return 0 2437 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2438 APInt::getAllOnesValue(VT.getSizeInBits()))) 2439 return DAG.getConstant(0, VT); 2440 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2441 if (N1.getOpcode() == ISD::TRUNCATE && 2442 N1.getOperand(0).getOpcode() == ISD::AND && 2443 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2444 SDValue N101 = N1.getOperand(0).getOperand(1); 2445 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2446 MVT TruncVT = N1.getValueType(); 2447 SDValue N100 = N1.getOperand(0).getOperand(0); 2448 APInt TruncC = N101C->getAPIntValue(); 2449 TruncC.trunc(TruncVT.getSizeInBits()); 2450 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2451 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2452 DAG.getNode(ISD::TRUNCATE, 2453 N->getDebugLoc(), 2454 TruncVT, N100), 2455 DAG.getConstant(TruncC, TruncVT))); 2456 } 2457 } 2458 2459 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2460 return SDValue(N, 0); 2461 2462 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2463 if (N1C && N0.getOpcode() == ISD::SHL && 2464 N0.getOperand(1).getOpcode() == ISD::Constant) { 2465 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2466 uint64_t c2 = N1C->getZExtValue(); 2467 if (c1 + c2 > OpSizeInBits) 2468 return DAG.getConstant(0, VT); 2469 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2470 DAG.getConstant(c1 + c2, N1.getValueType())); 2471 } 2472 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2473 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2474 if (N1C && N0.getOpcode() == ISD::SRL && 2475 N0.getOperand(1).getOpcode() == ISD::Constant) { 2476 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2477 uint64_t c2 = N1C->getZExtValue(); 2478 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), 2479 DAG.getConstant(~0ULL << c1, VT)); 2480 if (c2 > c1) 2481 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2482 DAG.getConstant(c2-c1, N1.getValueType())); 2483 else 2484 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2485 DAG.getConstant(c1-c2, N1.getValueType())); 2486 } 2487 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2488 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2489 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2490 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2491 2492 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2493} 2494 2495SDValue DAGCombiner::visitSRA(SDNode *N) { 2496 SDValue N0 = N->getOperand(0); 2497 SDValue N1 = N->getOperand(1); 2498 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2499 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2500 MVT VT = N0.getValueType(); 2501 2502 // fold (sra c1, c2) -> (sra c1, c2) 2503 if (N0C && N1C) 2504 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2505 // fold (sra 0, x) -> 0 2506 if (N0C && N0C->isNullValue()) 2507 return N0; 2508 // fold (sra -1, x) -> -1 2509 if (N0C && N0C->isAllOnesValue()) 2510 return N0; 2511 // fold (sra x, (setge c, size(x))) -> undef 2512 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2513 return DAG.getUNDEF(VT); 2514 // fold (sra x, 0) -> x 2515 if (N1C && N1C->isNullValue()) 2516 return N0; 2517 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2518 // sext_inreg. 2519 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2520 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2521 MVT EVT = MVT::getIntegerVT(LowBits); 2522 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2523 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2524 N0.getOperand(0), DAG.getValueType(EVT)); 2525 } 2526 2527 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2528 if (N1C && N0.getOpcode() == ISD::SRA) { 2529 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2530 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2531 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2532 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2533 DAG.getConstant(Sum, N1C->getValueType(0))); 2534 } 2535 } 2536 2537 // fold (sra (shl X, m), (sub result_size, n)) 2538 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2539 // result_size - n != m. 2540 // If truncate is free for the target sext(shl) is likely to result in better 2541 // code. 2542 if (N0.getOpcode() == ISD::SHL) { 2543 // Get the two constanst of the shifts, CN0 = m, CN = n. 2544 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2545 if (N01C && N1C) { 2546 // Determine what the truncate's result bitsize and type would be. 2547 unsigned VTValSize = VT.getSizeInBits(); 2548 MVT TruncVT = 2549 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2550 // Determine the residual right-shift amount. 2551 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2552 2553 // If the shift is not a no-op (in which case this should be just a sign 2554 // extend already), the truncated to type is legal, sign_extend is legal 2555 // on that type, and the the truncate to that type is both legal and free, 2556 // perform the transform. 2557 if ((ShiftAmt > 0) && 2558 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2559 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2560 TLI.isTruncateFree(VT, TruncVT)) { 2561 2562 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2563 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2564 N0.getOperand(0), Amt); 2565 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2566 Shift); 2567 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2568 N->getValueType(0), Trunc); 2569 } 2570 } 2571 } 2572 2573 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2574 if (N1.getOpcode() == ISD::TRUNCATE && 2575 N1.getOperand(0).getOpcode() == ISD::AND && 2576 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2577 SDValue N101 = N1.getOperand(0).getOperand(1); 2578 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2579 MVT TruncVT = N1.getValueType(); 2580 SDValue N100 = N1.getOperand(0).getOperand(0); 2581 APInt TruncC = N101C->getAPIntValue(); 2582 TruncC.trunc(TruncVT.getSizeInBits()); 2583 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2584 DAG.getNode(ISD::AND, N->getDebugLoc(), 2585 TruncVT, 2586 DAG.getNode(ISD::TRUNCATE, 2587 N->getDebugLoc(), 2588 TruncVT, N100), 2589 DAG.getConstant(TruncC, TruncVT))); 2590 } 2591 } 2592 2593 // Simplify, based on bits shifted out of the LHS. 2594 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2595 return SDValue(N, 0); 2596 2597 2598 // If the sign bit is known to be zero, switch this to a SRL. 2599 if (DAG.SignBitIsZero(N0)) 2600 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2601 2602 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2603} 2604 2605SDValue DAGCombiner::visitSRL(SDNode *N) { 2606 SDValue N0 = N->getOperand(0); 2607 SDValue N1 = N->getOperand(1); 2608 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2609 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2610 MVT VT = N0.getValueType(); 2611 unsigned OpSizeInBits = VT.getSizeInBits(); 2612 2613 // fold (srl c1, c2) -> c1 >>u c2 2614 if (N0C && N1C) 2615 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2616 // fold (srl 0, x) -> 0 2617 if (N0C && N0C->isNullValue()) 2618 return N0; 2619 // fold (srl x, c >= size(x)) -> undef 2620 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2621 return DAG.getUNDEF(VT); 2622 // fold (srl x, 0) -> x 2623 if (N1C && N1C->isNullValue()) 2624 return N0; 2625 // if (srl x, c) is known to be zero, return 0 2626 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2627 APInt::getAllOnesValue(OpSizeInBits))) 2628 return DAG.getConstant(0, VT); 2629 2630 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2631 if (N1C && N0.getOpcode() == ISD::SRL && 2632 N0.getOperand(1).getOpcode() == ISD::Constant) { 2633 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2634 uint64_t c2 = N1C->getZExtValue(); 2635 if (c1 + c2 > OpSizeInBits) 2636 return DAG.getConstant(0, VT); 2637 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2638 DAG.getConstant(c1 + c2, N1.getValueType())); 2639 } 2640 2641 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2642 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2643 // Shifting in all undef bits? 2644 MVT SmallVT = N0.getOperand(0).getValueType(); 2645 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2646 return DAG.getUNDEF(VT); 2647 2648 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2649 N0.getOperand(0), N1); 2650 AddToWorkList(SmallShift.getNode()); 2651 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2652 } 2653 2654 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2655 // bit, which is unmodified by sra. 2656 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2657 if (N0.getOpcode() == ISD::SRA) 2658 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2659 } 2660 2661 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2662 if (N1C && N0.getOpcode() == ISD::CTLZ && 2663 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2664 APInt KnownZero, KnownOne; 2665 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2666 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2667 2668 // If any of the input bits are KnownOne, then the input couldn't be all 2669 // zeros, thus the result of the srl will always be zero. 2670 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2671 2672 // If all of the bits input the to ctlz node are known to be zero, then 2673 // the result of the ctlz is "32" and the result of the shift is one. 2674 APInt UnknownBits = ~KnownZero & Mask; 2675 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2676 2677 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2678 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2679 // Okay, we know that only that the single bit specified by UnknownBits 2680 // could be set on input to the CTLZ node. If this bit is set, the SRL 2681 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2682 // to an SRL/XOR pair, which is likely to simplify more. 2683 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2684 SDValue Op = N0.getOperand(0); 2685 2686 if (ShAmt) { 2687 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2688 DAG.getConstant(ShAmt, getShiftAmountTy())); 2689 AddToWorkList(Op.getNode()); 2690 } 2691 2692 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2693 Op, DAG.getConstant(1, VT)); 2694 } 2695 } 2696 2697 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2698 if (N1.getOpcode() == ISD::TRUNCATE && 2699 N1.getOperand(0).getOpcode() == ISD::AND && 2700 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2701 SDValue N101 = N1.getOperand(0).getOperand(1); 2702 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2703 MVT TruncVT = N1.getValueType(); 2704 SDValue N100 = N1.getOperand(0).getOperand(0); 2705 APInt TruncC = N101C->getAPIntValue(); 2706 TruncC.trunc(TruncVT.getSizeInBits()); 2707 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2708 DAG.getNode(ISD::AND, N->getDebugLoc(), 2709 TruncVT, 2710 DAG.getNode(ISD::TRUNCATE, 2711 N->getDebugLoc(), 2712 TruncVT, N100), 2713 DAG.getConstant(TruncC, TruncVT))); 2714 } 2715 } 2716 2717 // fold operands of srl based on knowledge that the low bits are not 2718 // demanded. 2719 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2720 return SDValue(N, 0); 2721 2722 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2723} 2724 2725SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2726 SDValue N0 = N->getOperand(0); 2727 MVT VT = N->getValueType(0); 2728 2729 // fold (ctlz c1) -> c2 2730 if (isa<ConstantSDNode>(N0)) 2731 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2732 return SDValue(); 2733} 2734 2735SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2736 SDValue N0 = N->getOperand(0); 2737 MVT VT = N->getValueType(0); 2738 2739 // fold (cttz c1) -> c2 2740 if (isa<ConstantSDNode>(N0)) 2741 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2742 return SDValue(); 2743} 2744 2745SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2746 SDValue N0 = N->getOperand(0); 2747 MVT VT = N->getValueType(0); 2748 2749 // fold (ctpop c1) -> c2 2750 if (isa<ConstantSDNode>(N0)) 2751 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2752 return SDValue(); 2753} 2754 2755SDValue DAGCombiner::visitSELECT(SDNode *N) { 2756 SDValue N0 = N->getOperand(0); 2757 SDValue N1 = N->getOperand(1); 2758 SDValue N2 = N->getOperand(2); 2759 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2760 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2761 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2762 MVT VT = N->getValueType(0); 2763 MVT VT0 = N0.getValueType(); 2764 2765 // fold (select C, X, X) -> X 2766 if (N1 == N2) 2767 return N1; 2768 // fold (select true, X, Y) -> X 2769 if (N0C && !N0C->isNullValue()) 2770 return N1; 2771 // fold (select false, X, Y) -> Y 2772 if (N0C && N0C->isNullValue()) 2773 return N2; 2774 // fold (select C, 1, X) -> (or C, X) 2775 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2776 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2777 // fold (select C, 0, 1) -> (xor C, 1) 2778 if (VT.isInteger() && 2779 (VT0 == MVT::i1 || 2780 (VT0.isInteger() && 2781 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2782 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2783 SDValue XORNode; 2784 if (VT == VT0) 2785 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2786 N0, DAG.getConstant(1, VT0)); 2787 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2788 N0, DAG.getConstant(1, VT0)); 2789 AddToWorkList(XORNode.getNode()); 2790 if (VT.bitsGT(VT0)) 2791 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2792 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2793 } 2794 // fold (select C, 0, X) -> (and (not C), X) 2795 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2796 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2797 AddToWorkList(NOTNode.getNode()); 2798 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2799 } 2800 // fold (select C, X, 1) -> (or (not C), X) 2801 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2802 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2803 AddToWorkList(NOTNode.getNode()); 2804 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2805 } 2806 // fold (select C, X, 0) -> (and C, X) 2807 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2808 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2809 // fold (select X, X, Y) -> (or X, Y) 2810 // fold (select X, 1, Y) -> (or X, Y) 2811 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2812 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2813 // fold (select X, Y, X) -> (and X, Y) 2814 // fold (select X, Y, 0) -> (and X, Y) 2815 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2816 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2817 2818 // If we can fold this based on the true/false value, do so. 2819 if (SimplifySelectOps(N, N1, N2)) 2820 return SDValue(N, 0); // Don't revisit N. 2821 2822 // fold selects based on a setcc into other things, such as min/max/abs 2823 if (N0.getOpcode() == ISD::SETCC) { 2824 // FIXME: 2825 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2826 // having to say they don't support SELECT_CC on every type the DAG knows 2827 // about, since there is no way to mark an opcode illegal at all value types 2828 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2829 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2830 N0.getOperand(0), N0.getOperand(1), 2831 N1, N2, N0.getOperand(2)); 2832 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2833 } 2834 2835 return SDValue(); 2836} 2837 2838SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2839 SDValue N0 = N->getOperand(0); 2840 SDValue N1 = N->getOperand(1); 2841 SDValue N2 = N->getOperand(2); 2842 SDValue N3 = N->getOperand(3); 2843 SDValue N4 = N->getOperand(4); 2844 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2845 2846 // fold select_cc lhs, rhs, x, x, cc -> x 2847 if (N2 == N3) 2848 return N2; 2849 2850 // Determine if the condition we're dealing with is constant 2851 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2852 N0, N1, CC, N->getDebugLoc(), false); 2853 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2854 2855 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2856 if (!SCCC->isNullValue()) 2857 return N2; // cond always true -> true val 2858 else 2859 return N3; // cond always false -> false val 2860 } 2861 2862 // Fold to a simpler select_cc 2863 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2864 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2865 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2866 SCC.getOperand(2)); 2867 2868 // If we can fold this based on the true/false value, do so. 2869 if (SimplifySelectOps(N, N2, N3)) 2870 return SDValue(N, 0); // Don't revisit N. 2871 2872 // fold select_cc into other things, such as min/max/abs 2873 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2874} 2875 2876SDValue DAGCombiner::visitSETCC(SDNode *N) { 2877 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2878 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2879 N->getDebugLoc()); 2880} 2881 2882// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2883// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2884// transformation. Returns true if extension are possible and the above 2885// mentioned transformation is profitable. 2886static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2887 unsigned ExtOpc, 2888 SmallVector<SDNode*, 4> &ExtendNodes, 2889 const TargetLowering &TLI) { 2890 bool HasCopyToRegUses = false; 2891 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2892 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2893 UE = N0.getNode()->use_end(); 2894 UI != UE; ++UI) { 2895 SDNode *User = *UI; 2896 if (User == N) 2897 continue; 2898 if (UI.getUse().getResNo() != N0.getResNo()) 2899 continue; 2900 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2901 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 2902 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2903 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2904 // Sign bits will be lost after a zext. 2905 return false; 2906 bool Add = false; 2907 for (unsigned i = 0; i != 2; ++i) { 2908 SDValue UseOp = User->getOperand(i); 2909 if (UseOp == N0) 2910 continue; 2911 if (!isa<ConstantSDNode>(UseOp)) 2912 return false; 2913 Add = true; 2914 } 2915 if (Add) 2916 ExtendNodes.push_back(User); 2917 continue; 2918 } 2919 // If truncates aren't free and there are users we can't 2920 // extend, it isn't worthwhile. 2921 if (!isTruncFree) 2922 return false; 2923 // Remember if this value is live-out. 2924 if (User->getOpcode() == ISD::CopyToReg) 2925 HasCopyToRegUses = true; 2926 } 2927 2928 if (HasCopyToRegUses) { 2929 bool BothLiveOut = false; 2930 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2931 UI != UE; ++UI) { 2932 SDUse &Use = UI.getUse(); 2933 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 2934 BothLiveOut = true; 2935 break; 2936 } 2937 } 2938 if (BothLiveOut) 2939 // Both unextended and extended values are live out. There had better be 2940 // good a reason for the transformation. 2941 return ExtendNodes.size(); 2942 } 2943 return true; 2944} 2945 2946SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2947 SDValue N0 = N->getOperand(0); 2948 MVT VT = N->getValueType(0); 2949 2950 // fold (sext c1) -> c1 2951 if (isa<ConstantSDNode>(N0)) 2952 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2953 2954 // fold (sext (sext x)) -> (sext x) 2955 // fold (sext (aext x)) -> (sext x) 2956 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2957 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2958 N0.getOperand(0)); 2959 2960 if (N0.getOpcode() == ISD::TRUNCATE) { 2961 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2962 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2963 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2964 if (NarrowLoad.getNode()) { 2965 if (NarrowLoad.getNode() != N0.getNode()) 2966 CombineTo(N0.getNode(), NarrowLoad); 2967 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2968 } 2969 2970 // See if the value being truncated is already sign extended. If so, just 2971 // eliminate the trunc/sext pair. 2972 SDValue Op = N0.getOperand(0); 2973 unsigned OpBits = Op.getValueType().getSizeInBits(); 2974 unsigned MidBits = N0.getValueType().getSizeInBits(); 2975 unsigned DestBits = VT.getSizeInBits(); 2976 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2977 2978 if (OpBits == DestBits) { 2979 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2980 // bits, it is already ready. 2981 if (NumSignBits > DestBits-MidBits) 2982 return Op; 2983 } else if (OpBits < DestBits) { 2984 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2985 // bits, just sext from i32. 2986 if (NumSignBits > OpBits-MidBits) 2987 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 2988 } else { 2989 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2990 // bits, just truncate to i32. 2991 if (NumSignBits > OpBits-MidBits) 2992 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 2993 } 2994 2995 // fold (sext (truncate x)) -> (sextinreg x). 2996 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2997 N0.getValueType())) { 2998 if (Op.getValueType().bitsLT(VT)) 2999 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3000 else if (Op.getValueType().bitsGT(VT)) 3001 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3002 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3003 DAG.getValueType(N0.getValueType())); 3004 } 3005 } 3006 3007 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3008 if (ISD::isNON_EXTLoad(N0.getNode()) && 3009 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3010 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3011 bool DoXform = true; 3012 SmallVector<SDNode*, 4> SetCCs; 3013 if (!N0.hasOneUse()) 3014 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3015 if (DoXform) { 3016 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3017 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3018 LN0->getChain(), 3019 LN0->getBasePtr(), LN0->getSrcValue(), 3020 LN0->getSrcValueOffset(), 3021 N0.getValueType(), 3022 LN0->isVolatile(), LN0->getAlignment()); 3023 CombineTo(N, ExtLoad); 3024 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3025 N0.getValueType(), ExtLoad); 3026 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3027 3028 // Extend SetCC uses if necessary. 3029 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3030 SDNode *SetCC = SetCCs[i]; 3031 SmallVector<SDValue, 4> Ops; 3032 3033 for (unsigned j = 0; j != 2; ++j) { 3034 SDValue SOp = SetCC->getOperand(j); 3035 if (SOp == Trunc) 3036 Ops.push_back(ExtLoad); 3037 else 3038 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3039 N->getDebugLoc(), VT, SOp)); 3040 } 3041 3042 Ops.push_back(SetCC->getOperand(2)); 3043 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3044 SetCC->getValueType(0), 3045 &Ops[0], Ops.size())); 3046 } 3047 3048 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3049 } 3050 } 3051 3052 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3053 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3054 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3055 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3056 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3057 MVT EVT = LN0->getMemoryVT(); 3058 if ((!LegalOperations && !LN0->isVolatile()) || 3059 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3060 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3061 LN0->getChain(), 3062 LN0->getBasePtr(), LN0->getSrcValue(), 3063 LN0->getSrcValueOffset(), EVT, 3064 LN0->isVolatile(), LN0->getAlignment()); 3065 CombineTo(N, ExtLoad); 3066 CombineTo(N0.getNode(), 3067 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3068 N0.getValueType(), ExtLoad), 3069 ExtLoad.getValue(1)); 3070 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3071 } 3072 } 3073 3074 if (N0.getOpcode() == ISD::SETCC) { 3075 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3076 if (VT.isVector() && 3077 // We know that the # elements of the results is the same as the 3078 // # elements of the compare (and the # elements of the compare result 3079 // for that matter). Check to see that they are the same size. If so, 3080 // we know that the element size of the sext'd result matches the 3081 // element size of the compare operands. 3082 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3083 3084 // Only do this before legalize for now. 3085 !LegalOperations) { 3086 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3087 N0.getOperand(1), 3088 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3089 } 3090 3091 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3092 SDValue SCC = 3093 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3094 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3095 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3096 if (SCC.getNode()) return SCC; 3097 } 3098 3099 3100 3101 // fold (sext x) -> (zext x) if the sign bit is known zero. 3102 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3103 DAG.SignBitIsZero(N0)) 3104 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3105 3106 return SDValue(); 3107} 3108 3109SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3110 SDValue N0 = N->getOperand(0); 3111 MVT VT = N->getValueType(0); 3112 3113 // fold (zext c1) -> c1 3114 if (isa<ConstantSDNode>(N0)) 3115 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3116 // fold (zext (zext x)) -> (zext x) 3117 // fold (zext (aext x)) -> (zext x) 3118 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3119 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3120 N0.getOperand(0)); 3121 3122 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3123 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3124 if (N0.getOpcode() == ISD::TRUNCATE) { 3125 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3126 if (NarrowLoad.getNode()) { 3127 if (NarrowLoad.getNode() != N0.getNode()) 3128 CombineTo(N0.getNode(), NarrowLoad); 3129 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3130 } 3131 } 3132 3133 // fold (zext (truncate x)) -> (and x, mask) 3134 if (N0.getOpcode() == ISD::TRUNCATE && 3135 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3136 SDValue Op = N0.getOperand(0); 3137 if (Op.getValueType().bitsLT(VT)) { 3138 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3139 } else if (Op.getValueType().bitsGT(VT)) { 3140 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3141 } 3142 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3143 } 3144 3145 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3146 // if either of the casts is not free. 3147 if (N0.getOpcode() == ISD::AND && 3148 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3149 N0.getOperand(1).getOpcode() == ISD::Constant && 3150 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3151 N0.getValueType()) || 3152 !TLI.isZExtFree(N0.getValueType(), VT))) { 3153 SDValue X = N0.getOperand(0).getOperand(0); 3154 if (X.getValueType().bitsLT(VT)) { 3155 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3156 } else if (X.getValueType().bitsGT(VT)) { 3157 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3158 } 3159 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3160 Mask.zext(VT.getSizeInBits()); 3161 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3162 X, DAG.getConstant(Mask, VT)); 3163 } 3164 3165 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3166 if (ISD::isNON_EXTLoad(N0.getNode()) && 3167 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3168 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3169 bool DoXform = true; 3170 SmallVector<SDNode*, 4> SetCCs; 3171 if (!N0.hasOneUse()) 3172 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3173 if (DoXform) { 3174 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3175 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3176 LN0->getChain(), 3177 LN0->getBasePtr(), LN0->getSrcValue(), 3178 LN0->getSrcValueOffset(), 3179 N0.getValueType(), 3180 LN0->isVolatile(), LN0->getAlignment()); 3181 CombineTo(N, ExtLoad); 3182 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3183 N0.getValueType(), ExtLoad); 3184 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3185 3186 // Extend SetCC uses if necessary. 3187 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3188 SDNode *SetCC = SetCCs[i]; 3189 SmallVector<SDValue, 4> Ops; 3190 3191 for (unsigned j = 0; j != 2; ++j) { 3192 SDValue SOp = SetCC->getOperand(j); 3193 if (SOp == Trunc) 3194 Ops.push_back(ExtLoad); 3195 else 3196 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3197 N->getDebugLoc(), VT, SOp)); 3198 } 3199 3200 Ops.push_back(SetCC->getOperand(2)); 3201 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3202 SetCC->getValueType(0), 3203 &Ops[0], Ops.size())); 3204 } 3205 3206 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3207 } 3208 } 3209 3210 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3211 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3212 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3213 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3214 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3215 MVT EVT = LN0->getMemoryVT(); 3216 if ((!LegalOperations && !LN0->isVolatile()) || 3217 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3218 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3219 LN0->getChain(), 3220 LN0->getBasePtr(), LN0->getSrcValue(), 3221 LN0->getSrcValueOffset(), EVT, 3222 LN0->isVolatile(), LN0->getAlignment()); 3223 CombineTo(N, ExtLoad); 3224 CombineTo(N0.getNode(), 3225 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3226 ExtLoad), 3227 ExtLoad.getValue(1)); 3228 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3229 } 3230 } 3231 3232 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3233 if (N0.getOpcode() == ISD::SETCC) { 3234 SDValue SCC = 3235 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3236 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3237 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3238 if (SCC.getNode()) return SCC; 3239 } 3240 3241 return SDValue(); 3242} 3243 3244SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3245 SDValue N0 = N->getOperand(0); 3246 MVT VT = N->getValueType(0); 3247 3248 // fold (aext c1) -> c1 3249 if (isa<ConstantSDNode>(N0)) 3250 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3251 // fold (aext (aext x)) -> (aext x) 3252 // fold (aext (zext x)) -> (zext x) 3253 // fold (aext (sext x)) -> (sext x) 3254 if (N0.getOpcode() == ISD::ANY_EXTEND || 3255 N0.getOpcode() == ISD::ZERO_EXTEND || 3256 N0.getOpcode() == ISD::SIGN_EXTEND) 3257 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3258 3259 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3260 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3261 if (N0.getOpcode() == ISD::TRUNCATE) { 3262 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3263 if (NarrowLoad.getNode()) { 3264 if (NarrowLoad.getNode() != N0.getNode()) 3265 CombineTo(N0.getNode(), NarrowLoad); 3266 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3267 } 3268 } 3269 3270 // fold (aext (truncate x)) 3271 if (N0.getOpcode() == ISD::TRUNCATE) { 3272 SDValue TruncOp = N0.getOperand(0); 3273 if (TruncOp.getValueType() == VT) 3274 return TruncOp; // x iff x size == zext size. 3275 if (TruncOp.getValueType().bitsGT(VT)) 3276 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3277 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3278 } 3279 3280 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3281 // if the trunc is not free. 3282 if (N0.getOpcode() == ISD::AND && 3283 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3284 N0.getOperand(1).getOpcode() == ISD::Constant && 3285 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3286 N0.getValueType())) { 3287 SDValue X = N0.getOperand(0).getOperand(0); 3288 if (X.getValueType().bitsLT(VT)) { 3289 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3290 } else if (X.getValueType().bitsGT(VT)) { 3291 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3292 } 3293 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3294 Mask.zext(VT.getSizeInBits()); 3295 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3296 X, DAG.getConstant(Mask, VT)); 3297 } 3298 3299 // fold (aext (load x)) -> (aext (truncate (extload x))) 3300 if (ISD::isNON_EXTLoad(N0.getNode()) && 3301 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3302 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3303 bool DoXform = true; 3304 SmallVector<SDNode*, 4> SetCCs; 3305 if (!N0.hasOneUse()) 3306 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3307 if (DoXform) { 3308 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3309 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3310 LN0->getChain(), 3311 LN0->getBasePtr(), LN0->getSrcValue(), 3312 LN0->getSrcValueOffset(), 3313 N0.getValueType(), 3314 LN0->isVolatile(), LN0->getAlignment()); 3315 CombineTo(N, ExtLoad); 3316 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3317 N0.getValueType(), ExtLoad); 3318 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3319 3320 // Extend SetCC uses if necessary. 3321 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3322 SDNode *SetCC = SetCCs[i]; 3323 SmallVector<SDValue, 4> Ops; 3324 3325 for (unsigned j = 0; j != 2; ++j) { 3326 SDValue SOp = SetCC->getOperand(j); 3327 if (SOp == Trunc) 3328 Ops.push_back(ExtLoad); 3329 else 3330 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3331 N->getDebugLoc(), VT, SOp)); 3332 } 3333 3334 Ops.push_back(SetCC->getOperand(2)); 3335 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3336 SetCC->getValueType(0), 3337 &Ops[0], Ops.size())); 3338 } 3339 3340 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3341 } 3342 } 3343 3344 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3345 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3346 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3347 if (N0.getOpcode() == ISD::LOAD && 3348 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3349 N0.hasOneUse()) { 3350 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3351 MVT EVT = LN0->getMemoryVT(); 3352 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3353 VT, LN0->getChain(), LN0->getBasePtr(), 3354 LN0->getSrcValue(), 3355 LN0->getSrcValueOffset(), EVT, 3356 LN0->isVolatile(), LN0->getAlignment()); 3357 CombineTo(N, ExtLoad); 3358 CombineTo(N0.getNode(), 3359 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3360 N0.getValueType(), ExtLoad), 3361 ExtLoad.getValue(1)); 3362 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3363 } 3364 3365 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3366 if (N0.getOpcode() == ISD::SETCC) { 3367 SDValue SCC = 3368 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3369 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3370 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3371 if (SCC.getNode()) 3372 return SCC; 3373 } 3374 3375 return SDValue(); 3376} 3377 3378/// GetDemandedBits - See if the specified operand can be simplified with the 3379/// knowledge that only the bits specified by Mask are used. If so, return the 3380/// simpler operand, otherwise return a null SDValue. 3381SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3382 switch (V.getOpcode()) { 3383 default: break; 3384 case ISD::OR: 3385 case ISD::XOR: 3386 // If the LHS or RHS don't contribute bits to the or, drop them. 3387 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3388 return V.getOperand(1); 3389 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3390 return V.getOperand(0); 3391 break; 3392 case ISD::SRL: 3393 // Only look at single-use SRLs. 3394 if (!V.getNode()->hasOneUse()) 3395 break; 3396 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3397 // See if we can recursively simplify the LHS. 3398 unsigned Amt = RHSC->getZExtValue(); 3399 3400 // Watch out for shift count overflow though. 3401 if (Amt >= Mask.getBitWidth()) break; 3402 APInt NewMask = Mask << Amt; 3403 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3404 if (SimplifyLHS.getNode()) 3405 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3406 SimplifyLHS, V.getOperand(1)); 3407 } 3408 } 3409 return SDValue(); 3410} 3411 3412/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3413/// bits and then truncated to a narrower type and where N is a multiple 3414/// of number of bits of the narrower type, transform it to a narrower load 3415/// from address + N / num of bits of new type. If the result is to be 3416/// extended, also fold the extension to form a extending load. 3417SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3418 unsigned Opc = N->getOpcode(); 3419 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3420 SDValue N0 = N->getOperand(0); 3421 MVT VT = N->getValueType(0); 3422 MVT EVT = VT; 3423 3424 // This transformation isn't valid for vector loads. 3425 if (VT.isVector()) 3426 return SDValue(); 3427 3428 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3429 // extended to VT. 3430 if (Opc == ISD::SIGN_EXTEND_INREG) { 3431 ExtType = ISD::SEXTLOAD; 3432 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3433 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3434 return SDValue(); 3435 } 3436 3437 unsigned EVTBits = EVT.getSizeInBits(); 3438 unsigned ShAmt = 0; 3439 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3440 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3441 ShAmt = N01->getZExtValue(); 3442 // Is the shift amount a multiple of size of VT? 3443 if ((ShAmt & (EVTBits-1)) == 0) { 3444 N0 = N0.getOperand(0); 3445 if (N0.getValueType().getSizeInBits() <= EVTBits) 3446 return SDValue(); 3447 } 3448 } 3449 } 3450 3451 // Do not generate loads of non-round integer types since these can 3452 // be expensive (and would be wrong if the type is not byte sized). 3453 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3454 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3455 // Do not change the width of a volatile load. 3456 !cast<LoadSDNode>(N0)->isVolatile()) { 3457 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3458 MVT PtrType = N0.getOperand(1).getValueType(); 3459 3460 // For big endian targets, we need to adjust the offset to the pointer to 3461 // load the correct bytes. 3462 if (TLI.isBigEndian()) { 3463 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3464 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3465 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3466 } 3467 3468 uint64_t PtrOff = ShAmt / 8; 3469 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3470 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3471 PtrType, LN0->getBasePtr(), 3472 DAG.getConstant(PtrOff, PtrType)); 3473 AddToWorkList(NewPtr.getNode()); 3474 3475 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3476 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3477 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3478 LN0->isVolatile(), NewAlign) 3479 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3480 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3481 EVT, LN0->isVolatile(), NewAlign); 3482 3483 // Replace the old load's chain with the new load's chain. 3484 WorkListRemover DeadNodes(*this); 3485 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3486 &DeadNodes); 3487 3488 // Return the new loaded value. 3489 return Load; 3490 } 3491 3492 return SDValue(); 3493} 3494 3495SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3496 SDValue N0 = N->getOperand(0); 3497 SDValue N1 = N->getOperand(1); 3498 MVT VT = N->getValueType(0); 3499 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3500 unsigned VTBits = VT.getSizeInBits(); 3501 unsigned EVTBits = EVT.getSizeInBits(); 3502 3503 // fold (sext_in_reg c1) -> c1 3504 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3505 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3506 3507 // If the input is already sign extended, just drop the extension. 3508 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3509 return N0; 3510 3511 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3512 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3513 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3514 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3515 N0.getOperand(0), N1); 3516 } 3517 3518 // fold (sext_in_reg (sext x)) -> (sext x) 3519 // fold (sext_in_reg (aext x)) -> (sext x) 3520 // if x is small enough. 3521 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3522 SDValue N00 = N0.getOperand(0); 3523 if (N00.getValueType().getSizeInBits() < EVTBits) 3524 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3525 } 3526 3527 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3528 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3529 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3530 3531 // fold operands of sext_in_reg based on knowledge that the top bits are not 3532 // demanded. 3533 if (SimplifyDemandedBits(SDValue(N, 0))) 3534 return SDValue(N, 0); 3535 3536 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3537 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3538 SDValue NarrowLoad = ReduceLoadWidth(N); 3539 if (NarrowLoad.getNode()) 3540 return NarrowLoad; 3541 3542 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3543 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3544 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3545 if (N0.getOpcode() == ISD::SRL) { 3546 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3547 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3548 // We can turn this into an SRA iff the input to the SRL is already sign 3549 // extended enough. 3550 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3551 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3552 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3553 N0.getOperand(0), N0.getOperand(1)); 3554 } 3555 } 3556 3557 // fold (sext_inreg (extload x)) -> (sextload x) 3558 if (ISD::isEXTLoad(N0.getNode()) && 3559 ISD::isUNINDEXEDLoad(N0.getNode()) && 3560 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3561 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3562 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3563 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3564 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3565 LN0->getChain(), 3566 LN0->getBasePtr(), LN0->getSrcValue(), 3567 LN0->getSrcValueOffset(), EVT, 3568 LN0->isVolatile(), LN0->getAlignment()); 3569 CombineTo(N, ExtLoad); 3570 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3571 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3572 } 3573 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3574 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3575 N0.hasOneUse() && 3576 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3577 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3578 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3579 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3580 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3581 LN0->getChain(), 3582 LN0->getBasePtr(), LN0->getSrcValue(), 3583 LN0->getSrcValueOffset(), EVT, 3584 LN0->isVolatile(), LN0->getAlignment()); 3585 CombineTo(N, ExtLoad); 3586 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3587 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3588 } 3589 return SDValue(); 3590} 3591 3592SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3593 SDValue N0 = N->getOperand(0); 3594 MVT VT = N->getValueType(0); 3595 3596 // noop truncate 3597 if (N0.getValueType() == N->getValueType(0)) 3598 return N0; 3599 // fold (truncate c1) -> c1 3600 if (isa<ConstantSDNode>(N0)) 3601 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3602 // fold (truncate (truncate x)) -> (truncate x) 3603 if (N0.getOpcode() == ISD::TRUNCATE) 3604 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3605 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3606 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3607 N0.getOpcode() == ISD::ANY_EXTEND) { 3608 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3609 // if the source is smaller than the dest, we still need an extend 3610 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3611 N0.getOperand(0)); 3612 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3613 // if the source is larger than the dest, than we just need the truncate 3614 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3615 else 3616 // if the source and dest are the same type, we can drop both the extend 3617 // and the truncate 3618 return N0.getOperand(0); 3619 } 3620 3621 // See if we can simplify the input to this truncate through knowledge that 3622 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3623 // -> trunc y 3624 SDValue Shorter = 3625 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3626 VT.getSizeInBits())); 3627 if (Shorter.getNode()) 3628 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3629 3630 // fold (truncate (load x)) -> (smaller load x) 3631 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3632 return ReduceLoadWidth(N); 3633} 3634 3635static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3636 SDValue Elt = N->getOperand(i); 3637 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3638 return Elt.getNode(); 3639 return Elt.getOperand(Elt.getResNo()).getNode(); 3640} 3641 3642/// CombineConsecutiveLoads - build_pair (load, load) -> load 3643/// if load locations are consecutive. 3644SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3645 assert(N->getOpcode() == ISD::BUILD_PAIR); 3646 3647 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3648 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3649 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3650 return SDValue(); 3651 MVT LD1VT = LD1->getValueType(0); 3652 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3653 3654 if (ISD::isNON_EXTLoad(LD2) && 3655 LD2->hasOneUse() && 3656 // If both are volatile this would reduce the number of volatile loads. 3657 // If one is volatile it might be ok, but play conservative and bail out. 3658 !LD1->isVolatile() && 3659 !LD2->isVolatile() && 3660 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3661 unsigned Align = LD1->getAlignment(); 3662 unsigned NewAlign = TLI.getTargetData()-> 3663 getABITypeAlignment(VT.getTypeForMVT()); 3664 3665 if (NewAlign <= Align && 3666 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3667 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3668 LD1->getBasePtr(), LD1->getSrcValue(), 3669 LD1->getSrcValueOffset(), false, Align); 3670 } 3671 3672 return SDValue(); 3673} 3674 3675SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3676 SDValue N0 = N->getOperand(0); 3677 MVT VT = N->getValueType(0); 3678 3679 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3680 // Only do this before legalize, since afterward the target may be depending 3681 // on the bitconvert. 3682 // First check to see if this is all constant. 3683 if (!LegalTypes && 3684 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3685 VT.isVector()) { 3686 bool isSimple = true; 3687 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3688 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3689 N0.getOperand(i).getOpcode() != ISD::Constant && 3690 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3691 isSimple = false; 3692 break; 3693 } 3694 3695 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3696 assert(!DestEltVT.isVector() && 3697 "Element type of vector ValueType must not be vector!"); 3698 if (isSimple) 3699 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3700 } 3701 3702 // If the input is a constant, let getNode fold it. 3703 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3704 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3705 if (Res.getNode() != N) return Res; 3706 } 3707 3708 // (conv (conv x, t1), t2) -> (conv x, t2) 3709 if (N0.getOpcode() == ISD::BIT_CONVERT) 3710 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3711 N0.getOperand(0)); 3712 3713 // fold (conv (load x)) -> (load (conv*)x) 3714 // If the resultant load doesn't need a higher alignment than the original! 3715 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3716 // Do not change the width of a volatile load. 3717 !cast<LoadSDNode>(N0)->isVolatile() && 3718 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3719 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3720 unsigned Align = TLI.getTargetData()-> 3721 getABITypeAlignment(VT.getTypeForMVT()); 3722 unsigned OrigAlign = LN0->getAlignment(); 3723 3724 if (Align <= OrigAlign) { 3725 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3726 LN0->getBasePtr(), 3727 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3728 LN0->isVolatile(), OrigAlign); 3729 AddToWorkList(N); 3730 CombineTo(N0.getNode(), 3731 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3732 N0.getValueType(), Load), 3733 Load.getValue(1)); 3734 return Load; 3735 } 3736 } 3737 3738 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3739 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3740 // This often reduces constant pool loads. 3741 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3742 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3743 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3744 N0.getOperand(0)); 3745 AddToWorkList(NewConv.getNode()); 3746 3747 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3748 if (N0.getOpcode() == ISD::FNEG) 3749 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3750 NewConv, DAG.getConstant(SignBit, VT)); 3751 assert(N0.getOpcode() == ISD::FABS); 3752 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3753 NewConv, DAG.getConstant(~SignBit, VT)); 3754 } 3755 3756 // fold (bitconvert (fcopysign cst, x)) -> 3757 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3758 // Note that we don't handle (copysign x, cst) because this can always be 3759 // folded to an fneg or fabs. 3760 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3761 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3762 VT.isInteger() && !VT.isVector()) { 3763 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3764 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3765 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3766 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3767 IntXVT, N0.getOperand(1)); 3768 AddToWorkList(X.getNode()); 3769 3770 // If X has a different width than the result/lhs, sext it or truncate it. 3771 unsigned VTWidth = VT.getSizeInBits(); 3772 if (OrigXWidth < VTWidth) { 3773 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3774 AddToWorkList(X.getNode()); 3775 } else if (OrigXWidth > VTWidth) { 3776 // To get the sign bit in the right place, we have to shift it right 3777 // before truncating. 3778 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3779 X.getValueType(), X, 3780 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3781 AddToWorkList(X.getNode()); 3782 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3783 AddToWorkList(X.getNode()); 3784 } 3785 3786 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3787 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3788 X, DAG.getConstant(SignBit, VT)); 3789 AddToWorkList(X.getNode()); 3790 3791 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3792 VT, N0.getOperand(0)); 3793 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3794 Cst, DAG.getConstant(~SignBit, VT)); 3795 AddToWorkList(Cst.getNode()); 3796 3797 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3798 } 3799 } 3800 3801 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3802 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3803 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3804 if (CombineLD.getNode()) 3805 return CombineLD; 3806 } 3807 3808 return SDValue(); 3809} 3810 3811SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3812 MVT VT = N->getValueType(0); 3813 return CombineConsecutiveLoads(N, VT); 3814} 3815 3816/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3817/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3818/// destination element value type. 3819SDValue DAGCombiner:: 3820ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3821 MVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3822 3823 // If this is already the right type, we're done. 3824 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3825 3826 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3827 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3828 3829 // If this is a conversion of N elements of one type to N elements of another 3830 // type, convert each element. This handles FP<->INT cases. 3831 if (SrcBitSize == DstBitSize) { 3832 SmallVector<SDValue, 8> Ops; 3833 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3834 SDValue Op = BV->getOperand(i); 3835 // If the vector element type is not legal, the BUILD_VECTOR operands 3836 // are promoted and implicitly truncated. Make that explicit here. 3837 if (Op.getValueType() != SrcEltVT) 3838 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3839 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3840 DstEltVT, Op)); 3841 AddToWorkList(Ops.back().getNode()); 3842 } 3843 MVT VT = MVT::getVectorVT(DstEltVT, 3844 BV->getValueType(0).getVectorNumElements()); 3845 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3846 &Ops[0], Ops.size()); 3847 } 3848 3849 // Otherwise, we're growing or shrinking the elements. To avoid having to 3850 // handle annoying details of growing/shrinking FP values, we convert them to 3851 // int first. 3852 if (SrcEltVT.isFloatingPoint()) { 3853 // Convert the input float vector to a int vector where the elements are the 3854 // same sizes. 3855 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3856 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3857 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3858 SrcEltVT = IntVT; 3859 } 3860 3861 // Now we know the input is an integer vector. If the output is a FP type, 3862 // convert to integer first, then to FP of the right size. 3863 if (DstEltVT.isFloatingPoint()) { 3864 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3865 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3866 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3867 3868 // Next, convert to FP elements of the same size. 3869 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3870 } 3871 3872 // Okay, we know the src/dst types are both integers of differing types. 3873 // Handling growing first. 3874 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3875 if (SrcBitSize < DstBitSize) { 3876 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3877 3878 SmallVector<SDValue, 8> Ops; 3879 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3880 i += NumInputsPerOutput) { 3881 bool isLE = TLI.isLittleEndian(); 3882 APInt NewBits = APInt(DstBitSize, 0); 3883 bool EltIsUndef = true; 3884 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3885 // Shift the previously computed bits over. 3886 NewBits <<= SrcBitSize; 3887 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3888 if (Op.getOpcode() == ISD::UNDEF) continue; 3889 EltIsUndef = false; 3890 3891 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 3892 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 3893 } 3894 3895 if (EltIsUndef) 3896 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3897 else 3898 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3899 } 3900 3901 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3902 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3903 &Ops[0], Ops.size()); 3904 } 3905 3906 // Finally, this must be the case where we are shrinking elements: each input 3907 // turns into multiple outputs. 3908 bool isS2V = ISD::isScalarToVector(BV); 3909 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3910 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3911 SmallVector<SDValue, 8> Ops; 3912 3913 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3914 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3915 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3916 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3917 continue; 3918 } 3919 3920 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 3921 getAPIntValue()).zextOrTrunc(SrcBitSize); 3922 3923 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3924 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3925 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3926 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3927 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3928 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3929 Ops[0]); 3930 OpVal = OpVal.lshr(DstBitSize); 3931 } 3932 3933 // For big endian targets, swap the order of the pieces of each element. 3934 if (TLI.isBigEndian()) 3935 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3936 } 3937 3938 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3939 &Ops[0], Ops.size()); 3940} 3941 3942SDValue DAGCombiner::visitFADD(SDNode *N) { 3943 SDValue N0 = N->getOperand(0); 3944 SDValue N1 = N->getOperand(1); 3945 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3946 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3947 MVT VT = N->getValueType(0); 3948 3949 // fold vector ops 3950 if (VT.isVector()) { 3951 SDValue FoldedVOp = SimplifyVBinOp(N); 3952 if (FoldedVOp.getNode()) return FoldedVOp; 3953 } 3954 3955 // fold (fadd c1, c2) -> (fadd c1, c2) 3956 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3957 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3958 // canonicalize constant to RHS 3959 if (N0CFP && !N1CFP) 3960 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3961 // fold (fadd A, 0) -> A 3962 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3963 return N0; 3964 // fold (fadd A, (fneg B)) -> (fsub A, B) 3965 if (isNegatibleForFree(N1, LegalOperations) == 2) 3966 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3967 GetNegatedExpression(N1, DAG, LegalOperations)); 3968 // fold (fadd (fneg A), B) -> (fsub B, A) 3969 if (isNegatibleForFree(N0, LegalOperations) == 2) 3970 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3971 GetNegatedExpression(N0, DAG, LegalOperations)); 3972 3973 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3974 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3975 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3976 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3977 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3978 N0.getOperand(1), N1)); 3979 3980 return SDValue(); 3981} 3982 3983SDValue DAGCombiner::visitFSUB(SDNode *N) { 3984 SDValue N0 = N->getOperand(0); 3985 SDValue N1 = N->getOperand(1); 3986 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3987 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3988 MVT VT = N->getValueType(0); 3989 3990 // fold vector ops 3991 if (VT.isVector()) { 3992 SDValue FoldedVOp = SimplifyVBinOp(N); 3993 if (FoldedVOp.getNode()) return FoldedVOp; 3994 } 3995 3996 // fold (fsub c1, c2) -> c1-c2 3997 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3998 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 3999 // fold (fsub A, 0) -> A 4000 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4001 return N0; 4002 // fold (fsub 0, B) -> -B 4003 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4004 if (isNegatibleForFree(N1, LegalOperations)) 4005 return GetNegatedExpression(N1, DAG, LegalOperations); 4006 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4007 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4008 } 4009 // fold (fsub A, (fneg B)) -> (fadd A, B) 4010 if (isNegatibleForFree(N1, LegalOperations)) 4011 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4012 GetNegatedExpression(N1, DAG, LegalOperations)); 4013 4014 return SDValue(); 4015} 4016 4017SDValue DAGCombiner::visitFMUL(SDNode *N) { 4018 SDValue N0 = N->getOperand(0); 4019 SDValue N1 = N->getOperand(1); 4020 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4021 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4022 MVT VT = N->getValueType(0); 4023 4024 // fold vector ops 4025 if (VT.isVector()) { 4026 SDValue FoldedVOp = SimplifyVBinOp(N); 4027 if (FoldedVOp.getNode()) return FoldedVOp; 4028 } 4029 4030 // fold (fmul c1, c2) -> c1*c2 4031 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4032 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4033 // canonicalize constant to RHS 4034 if (N0CFP && !N1CFP) 4035 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4036 // fold (fmul A, 0) -> 0 4037 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4038 return N1; 4039 // fold (fmul A, 0) -> 0, vector edition. 4040 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4041 return N1; 4042 // fold (fmul X, 2.0) -> (fadd X, X) 4043 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4044 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4045 // fold (fmul X, (fneg 1.0)) -> (fneg X) 4046 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4047 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4048 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4049 4050 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4051 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4052 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4053 // Both can be negated for free, check to see if at least one is cheaper 4054 // negated. 4055 if (LHSNeg == 2 || RHSNeg == 2) 4056 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4057 GetNegatedExpression(N0, DAG, LegalOperations), 4058 GetNegatedExpression(N1, DAG, LegalOperations)); 4059 } 4060 } 4061 4062 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4063 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4064 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4065 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4066 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4067 N0.getOperand(1), N1)); 4068 4069 return SDValue(); 4070} 4071 4072SDValue DAGCombiner::visitFDIV(SDNode *N) { 4073 SDValue N0 = N->getOperand(0); 4074 SDValue N1 = N->getOperand(1); 4075 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4076 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4077 MVT VT = N->getValueType(0); 4078 4079 // fold vector ops 4080 if (VT.isVector()) { 4081 SDValue FoldedVOp = SimplifyVBinOp(N); 4082 if (FoldedVOp.getNode()) return FoldedVOp; 4083 } 4084 4085 // fold (fdiv c1, c2) -> c1/c2 4086 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4087 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4088 4089 4090 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4091 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4092 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4093 // Both can be negated for free, check to see if at least one is cheaper 4094 // negated. 4095 if (LHSNeg == 2 || RHSNeg == 2) 4096 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4097 GetNegatedExpression(N0, DAG, LegalOperations), 4098 GetNegatedExpression(N1, DAG, LegalOperations)); 4099 } 4100 } 4101 4102 return SDValue(); 4103} 4104 4105SDValue DAGCombiner::visitFREM(SDNode *N) { 4106 SDValue N0 = N->getOperand(0); 4107 SDValue N1 = N->getOperand(1); 4108 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4109 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4110 MVT VT = N->getValueType(0); 4111 4112 // fold (frem c1, c2) -> fmod(c1,c2) 4113 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4114 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4115 4116 return SDValue(); 4117} 4118 4119SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4120 SDValue N0 = N->getOperand(0); 4121 SDValue N1 = N->getOperand(1); 4122 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4123 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4124 MVT VT = N->getValueType(0); 4125 4126 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4127 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4128 4129 if (N1CFP) { 4130 const APFloat& V = N1CFP->getValueAPF(); 4131 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4132 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4133 if (!V.isNegative()) { 4134 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4135 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4136 } else { 4137 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4138 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4139 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4140 } 4141 } 4142 4143 // copysign(fabs(x), y) -> copysign(x, y) 4144 // copysign(fneg(x), y) -> copysign(x, y) 4145 // copysign(copysign(x,z), y) -> copysign(x, y) 4146 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4147 N0.getOpcode() == ISD::FCOPYSIGN) 4148 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4149 N0.getOperand(0), N1); 4150 4151 // copysign(x, abs(y)) -> abs(x) 4152 if (N1.getOpcode() == ISD::FABS) 4153 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4154 4155 // copysign(x, copysign(y,z)) -> copysign(x, z) 4156 if (N1.getOpcode() == ISD::FCOPYSIGN) 4157 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4158 N0, N1.getOperand(1)); 4159 4160 // copysign(x, fp_extend(y)) -> copysign(x, y) 4161 // copysign(x, fp_round(y)) -> copysign(x, y) 4162 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4163 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4164 N0, N1.getOperand(0)); 4165 4166 return SDValue(); 4167} 4168 4169SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4170 SDValue N0 = N->getOperand(0); 4171 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4172 MVT VT = N->getValueType(0); 4173 MVT OpVT = N0.getValueType(); 4174 4175 // fold (sint_to_fp c1) -> c1fp 4176 if (N0C && OpVT != MVT::ppcf128) 4177 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4178 4179 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4180 // but UINT_TO_FP is legal on this target, try to convert. 4181 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4182 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4183 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4184 if (DAG.SignBitIsZero(N0)) 4185 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4186 } 4187 4188 return SDValue(); 4189} 4190 4191SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4192 SDValue N0 = N->getOperand(0); 4193 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4194 MVT VT = N->getValueType(0); 4195 MVT OpVT = N0.getValueType(); 4196 4197 // fold (uint_to_fp c1) -> c1fp 4198 if (N0C && OpVT != MVT::ppcf128) 4199 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4200 4201 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4202 // but SINT_TO_FP is legal on this target, try to convert. 4203 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4204 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4205 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4206 if (DAG.SignBitIsZero(N0)) 4207 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4208 } 4209 4210 return SDValue(); 4211} 4212 4213SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4214 SDValue N0 = N->getOperand(0); 4215 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4216 MVT VT = N->getValueType(0); 4217 4218 // fold (fp_to_sint c1fp) -> c1 4219 if (N0CFP) 4220 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4221 4222 return SDValue(); 4223} 4224 4225SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4226 SDValue N0 = N->getOperand(0); 4227 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4228 MVT VT = N->getValueType(0); 4229 4230 // fold (fp_to_uint c1fp) -> c1 4231 if (N0CFP && VT != MVT::ppcf128) 4232 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4233 4234 return SDValue(); 4235} 4236 4237SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4238 SDValue N0 = N->getOperand(0); 4239 SDValue N1 = N->getOperand(1); 4240 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4241 MVT VT = N->getValueType(0); 4242 4243 // fold (fp_round c1fp) -> c1fp 4244 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4245 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4246 4247 // fold (fp_round (fp_extend x)) -> x 4248 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4249 return N0.getOperand(0); 4250 4251 // fold (fp_round (fp_round x)) -> (fp_round x) 4252 if (N0.getOpcode() == ISD::FP_ROUND) { 4253 // This is a value preserving truncation if both round's are. 4254 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4255 N0.getNode()->getConstantOperandVal(1) == 1; 4256 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4257 DAG.getIntPtrConstant(IsTrunc)); 4258 } 4259 4260 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4261 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4262 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4263 N0.getOperand(0), N1); 4264 AddToWorkList(Tmp.getNode()); 4265 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4266 Tmp, N0.getOperand(1)); 4267 } 4268 4269 return SDValue(); 4270} 4271 4272SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4273 SDValue N0 = N->getOperand(0); 4274 MVT VT = N->getValueType(0); 4275 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4276 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4277 4278 // fold (fp_round_inreg c1fp) -> c1fp 4279 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4280 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4281 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4282 } 4283 4284 return SDValue(); 4285} 4286 4287SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4288 SDValue N0 = N->getOperand(0); 4289 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4290 MVT VT = N->getValueType(0); 4291 4292 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4293 if (N->hasOneUse() && 4294 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4295 return SDValue(); 4296 4297 // fold (fp_extend c1fp) -> c1fp 4298 if (N0CFP && VT != MVT::ppcf128) 4299 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4300 4301 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4302 // value of X. 4303 if (N0.getOpcode() == ISD::FP_ROUND 4304 && N0.getNode()->getConstantOperandVal(1) == 1) { 4305 SDValue In = N0.getOperand(0); 4306 if (In.getValueType() == VT) return In; 4307 if (VT.bitsLT(In.getValueType())) 4308 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4309 In, N0.getOperand(1)); 4310 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4311 } 4312 4313 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4314 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4315 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4316 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4317 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4318 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4319 LN0->getChain(), 4320 LN0->getBasePtr(), LN0->getSrcValue(), 4321 LN0->getSrcValueOffset(), 4322 N0.getValueType(), 4323 LN0->isVolatile(), LN0->getAlignment()); 4324 CombineTo(N, ExtLoad); 4325 CombineTo(N0.getNode(), 4326 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4327 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4328 ExtLoad.getValue(1)); 4329 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4330 } 4331 4332 return SDValue(); 4333} 4334 4335SDValue DAGCombiner::visitFNEG(SDNode *N) { 4336 SDValue N0 = N->getOperand(0); 4337 4338 if (isNegatibleForFree(N0, LegalOperations)) 4339 return GetNegatedExpression(N0, DAG, LegalOperations); 4340 4341 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4342 // constant pool values. 4343 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4344 N0.getOperand(0).getValueType().isInteger() && 4345 !N0.getOperand(0).getValueType().isVector()) { 4346 SDValue Int = N0.getOperand(0); 4347 MVT IntVT = Int.getValueType(); 4348 if (IntVT.isInteger() && !IntVT.isVector()) { 4349 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4350 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4351 AddToWorkList(Int.getNode()); 4352 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4353 N->getValueType(0), Int); 4354 } 4355 } 4356 4357 return SDValue(); 4358} 4359 4360SDValue DAGCombiner::visitFABS(SDNode *N) { 4361 SDValue N0 = N->getOperand(0); 4362 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4363 MVT VT = N->getValueType(0); 4364 4365 // fold (fabs c1) -> fabs(c1) 4366 if (N0CFP && VT != MVT::ppcf128) 4367 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4368 // fold (fabs (fabs x)) -> (fabs x) 4369 if (N0.getOpcode() == ISD::FABS) 4370 return N->getOperand(0); 4371 // fold (fabs (fneg x)) -> (fabs x) 4372 // fold (fabs (fcopysign x, y)) -> (fabs x) 4373 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4374 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4375 4376 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4377 // constant pool values. 4378 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4379 N0.getOperand(0).getValueType().isInteger() && 4380 !N0.getOperand(0).getValueType().isVector()) { 4381 SDValue Int = N0.getOperand(0); 4382 MVT IntVT = Int.getValueType(); 4383 if (IntVT.isInteger() && !IntVT.isVector()) { 4384 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4385 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4386 AddToWorkList(Int.getNode()); 4387 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4388 N->getValueType(0), Int); 4389 } 4390 } 4391 4392 return SDValue(); 4393} 4394 4395SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4396 SDValue Chain = N->getOperand(0); 4397 SDValue N1 = N->getOperand(1); 4398 SDValue N2 = N->getOperand(2); 4399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4400 4401 // never taken branch, fold to chain 4402 if (N1C && N1C->isNullValue()) 4403 return Chain; 4404 // unconditional branch 4405 if (N1C && N1C->getAPIntValue() == 1) 4406 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4407 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4408 // on the target. 4409 if (N1.getOpcode() == ISD::SETCC && 4410 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4411 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4412 Chain, N1.getOperand(2), 4413 N1.getOperand(0), N1.getOperand(1), N2); 4414 } 4415 4416 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4417 // Match this pattern so that we can generate simpler code: 4418 // 4419 // %a = ... 4420 // %b = and i32 %a, 2 4421 // %c = srl i32 %b, 1 4422 // brcond i32 %c ... 4423 // 4424 // into 4425 // 4426 // %a = ... 4427 // %b = and %a, 2 4428 // %c = setcc eq %b, 0 4429 // brcond %c ... 4430 // 4431 // This applies only when the AND constant value has one bit set and the 4432 // SRL constant is equal to the log2 of the AND constant. The back-end is 4433 // smart enough to convert the result into a TEST/JMP sequence. 4434 SDValue Op0 = N1.getOperand(0); 4435 SDValue Op1 = N1.getOperand(1); 4436 4437 if (Op0.getOpcode() == ISD::AND && 4438 Op0.hasOneUse() && 4439 Op1.getOpcode() == ISD::Constant) { 4440 SDValue AndOp0 = Op0.getOperand(0); 4441 SDValue AndOp1 = Op0.getOperand(1); 4442 4443 if (AndOp1.getOpcode() == ISD::Constant) { 4444 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4445 4446 if (AndConst.isPowerOf2() && 4447 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4448 SDValue SetCC = 4449 DAG.getSetCC(N->getDebugLoc(), 4450 TLI.getSetCCResultType(Op0.getValueType()), 4451 Op0, DAG.getConstant(0, Op0.getValueType()), 4452 ISD::SETNE); 4453 4454 // Replace the uses of SRL with SETCC 4455 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4456 removeFromWorkList(N1.getNode()); 4457 DAG.DeleteNode(N1.getNode()); 4458 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4459 MVT::Other, Chain, SetCC, N2); 4460 } 4461 } 4462 } 4463 } 4464 4465 return SDValue(); 4466} 4467 4468// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4469// 4470SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4471 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4472 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4473 4474 // Use SimplifySetCC to simplify SETCC's. 4475 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4476 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4477 false); 4478 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4479 4480 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4481 4482 // fold br_cc true, dest -> br dest (unconditional branch) 4483 if (SCCC && !SCCC->isNullValue()) 4484 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4485 N->getOperand(0), N->getOperand(4)); 4486 // fold br_cc false, dest -> unconditional fall through 4487 if (SCCC && SCCC->isNullValue()) 4488 return N->getOperand(0); 4489 4490 // fold to a simpler setcc 4491 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4492 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4493 N->getOperand(0), Simp.getOperand(2), 4494 Simp.getOperand(0), Simp.getOperand(1), 4495 N->getOperand(4)); 4496 4497 return SDValue(); 4498} 4499 4500/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4501/// pre-indexed load / store when the base pointer is an add or subtract 4502/// and it has other uses besides the load / store. After the 4503/// transformation, the new indexed load / store has effectively folded 4504/// the add / subtract in and all of its other uses are redirected to the 4505/// new load / store. 4506bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4507 if (!LegalOperations) 4508 return false; 4509 4510 bool isLoad = true; 4511 SDValue Ptr; 4512 MVT VT; 4513 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4514 if (LD->isIndexed()) 4515 return false; 4516 VT = LD->getMemoryVT(); 4517 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4518 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4519 return false; 4520 Ptr = LD->getBasePtr(); 4521 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4522 if (ST->isIndexed()) 4523 return false; 4524 VT = ST->getMemoryVT(); 4525 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4526 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4527 return false; 4528 Ptr = ST->getBasePtr(); 4529 isLoad = false; 4530 } else { 4531 return false; 4532 } 4533 4534 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4535 // out. There is no reason to make this a preinc/predec. 4536 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4537 Ptr.getNode()->hasOneUse()) 4538 return false; 4539 4540 // Ask the target to do addressing mode selection. 4541 SDValue BasePtr; 4542 SDValue Offset; 4543 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4544 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4545 return false; 4546 // Don't create a indexed load / store with zero offset. 4547 if (isa<ConstantSDNode>(Offset) && 4548 cast<ConstantSDNode>(Offset)->isNullValue()) 4549 return false; 4550 4551 // Try turning it into a pre-indexed load / store except when: 4552 // 1) The new base ptr is a frame index. 4553 // 2) If N is a store and the new base ptr is either the same as or is a 4554 // predecessor of the value being stored. 4555 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4556 // that would create a cycle. 4557 // 4) All uses are load / store ops that use it as old base ptr. 4558 4559 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4560 // (plus the implicit offset) to a register to preinc anyway. 4561 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4562 return false; 4563 4564 // Check #2. 4565 if (!isLoad) { 4566 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4567 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4568 return false; 4569 } 4570 4571 // Now check for #3 and #4. 4572 bool RealUse = false; 4573 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4574 E = Ptr.getNode()->use_end(); I != E; ++I) { 4575 SDNode *Use = *I; 4576 if (Use == N) 4577 continue; 4578 if (Use->isPredecessorOf(N)) 4579 return false; 4580 4581 if (!((Use->getOpcode() == ISD::LOAD && 4582 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4583 (Use->getOpcode() == ISD::STORE && 4584 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4585 RealUse = true; 4586 } 4587 4588 if (!RealUse) 4589 return false; 4590 4591 SDValue Result; 4592 if (isLoad) 4593 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4594 BasePtr, Offset, AM); 4595 else 4596 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4597 BasePtr, Offset, AM); 4598 ++PreIndexedNodes; 4599 ++NodesCombined; 4600 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4601 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4602 DOUT << '\n'; 4603 WorkListRemover DeadNodes(*this); 4604 if (isLoad) { 4605 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4606 &DeadNodes); 4607 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4608 &DeadNodes); 4609 } else { 4610 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4611 &DeadNodes); 4612 } 4613 4614 // Finally, since the node is now dead, remove it from the graph. 4615 DAG.DeleteNode(N); 4616 4617 // Replace the uses of Ptr with uses of the updated base value. 4618 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4619 &DeadNodes); 4620 removeFromWorkList(Ptr.getNode()); 4621 DAG.DeleteNode(Ptr.getNode()); 4622 4623 return true; 4624} 4625 4626/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4627/// add / sub of the base pointer node into a post-indexed load / store. 4628/// The transformation folded the add / subtract into the new indexed 4629/// load / store effectively and all of its uses are redirected to the 4630/// new load / store. 4631bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4632 if (!LegalOperations) 4633 return false; 4634 4635 bool isLoad = true; 4636 SDValue Ptr; 4637 MVT VT; 4638 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4639 if (LD->isIndexed()) 4640 return false; 4641 VT = LD->getMemoryVT(); 4642 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4643 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4644 return false; 4645 Ptr = LD->getBasePtr(); 4646 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4647 if (ST->isIndexed()) 4648 return false; 4649 VT = ST->getMemoryVT(); 4650 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4651 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4652 return false; 4653 Ptr = ST->getBasePtr(); 4654 isLoad = false; 4655 } else { 4656 return false; 4657 } 4658 4659 if (Ptr.getNode()->hasOneUse()) 4660 return false; 4661 4662 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4663 E = Ptr.getNode()->use_end(); I != E; ++I) { 4664 SDNode *Op = *I; 4665 if (Op == N || 4666 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4667 continue; 4668 4669 SDValue BasePtr; 4670 SDValue Offset; 4671 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4672 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4673 if (Ptr == Offset) 4674 std::swap(BasePtr, Offset); 4675 if (Ptr != BasePtr) 4676 continue; 4677 // Don't create a indexed load / store with zero offset. 4678 if (isa<ConstantSDNode>(Offset) && 4679 cast<ConstantSDNode>(Offset)->isNullValue()) 4680 continue; 4681 4682 // Try turning it into a post-indexed load / store except when 4683 // 1) All uses are load / store ops that use it as base ptr. 4684 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4685 // nor a successor of N. Otherwise, if Op is folded that would 4686 // create a cycle. 4687 4688 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4689 continue; 4690 4691 // Check for #1. 4692 bool TryNext = false; 4693 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4694 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4695 SDNode *Use = *II; 4696 if (Use == Ptr.getNode()) 4697 continue; 4698 4699 // If all the uses are load / store addresses, then don't do the 4700 // transformation. 4701 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4702 bool RealUse = false; 4703 for (SDNode::use_iterator III = Use->use_begin(), 4704 EEE = Use->use_end(); III != EEE; ++III) { 4705 SDNode *UseUse = *III; 4706 if (!((UseUse->getOpcode() == ISD::LOAD && 4707 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4708 (UseUse->getOpcode() == ISD::STORE && 4709 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4710 RealUse = true; 4711 } 4712 4713 if (!RealUse) { 4714 TryNext = true; 4715 break; 4716 } 4717 } 4718 } 4719 4720 if (TryNext) 4721 continue; 4722 4723 // Check for #2 4724 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4725 SDValue Result = isLoad 4726 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4727 BasePtr, Offset, AM) 4728 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4729 BasePtr, Offset, AM); 4730 ++PostIndexedNodes; 4731 ++NodesCombined; 4732 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4733 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4734 DOUT << '\n'; 4735 WorkListRemover DeadNodes(*this); 4736 if (isLoad) { 4737 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4738 &DeadNodes); 4739 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4740 &DeadNodes); 4741 } else { 4742 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4743 &DeadNodes); 4744 } 4745 4746 // Finally, since the node is now dead, remove it from the graph. 4747 DAG.DeleteNode(N); 4748 4749 // Replace the uses of Use with uses of the updated base value. 4750 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4751 Result.getValue(isLoad ? 1 : 0), 4752 &DeadNodes); 4753 removeFromWorkList(Op); 4754 DAG.DeleteNode(Op); 4755 return true; 4756 } 4757 } 4758 } 4759 4760 return false; 4761} 4762 4763/// InferAlignment - If we can infer some alignment information from this 4764/// pointer, return it. 4765static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4766 // If this is a direct reference to a stack slot, use information about the 4767 // stack slot's alignment. 4768 int FrameIdx = 1 << 31; 4769 int64_t FrameOffset = 0; 4770 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4771 FrameIdx = FI->getIndex(); 4772 } else if (Ptr.getOpcode() == ISD::ADD && 4773 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4774 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4775 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4776 FrameOffset = Ptr.getConstantOperandVal(1); 4777 } 4778 4779 if (FrameIdx != (1 << 31)) { 4780 // FIXME: Handle FI+CST. 4781 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4782 if (MFI.isFixedObjectIndex(FrameIdx)) { 4783 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4784 4785 // The alignment of the frame index can be determined from its offset from 4786 // the incoming frame position. If the frame object is at offset 32 and 4787 // the stack is guaranteed to be 16-byte aligned, then we know that the 4788 // object is 16-byte aligned. 4789 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4790 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4791 4792 // Finally, the frame object itself may have a known alignment. Factor 4793 // the alignment + offset into a new alignment. For example, if we know 4794 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4795 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4796 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4797 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4798 FrameOffset); 4799 return std::max(Align, FIInfoAlign); 4800 } 4801 } 4802 4803 return 0; 4804} 4805 4806SDValue DAGCombiner::visitLOAD(SDNode *N) { 4807 LoadSDNode *LD = cast<LoadSDNode>(N); 4808 SDValue Chain = LD->getChain(); 4809 SDValue Ptr = LD->getBasePtr(); 4810 4811 // Try to infer better alignment information than the load already has. 4812 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4813 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4814 if (Align > LD->getAlignment()) 4815 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4816 LD->getValueType(0), 4817 Chain, Ptr, LD->getSrcValue(), 4818 LD->getSrcValueOffset(), LD->getMemoryVT(), 4819 LD->isVolatile(), Align); 4820 } 4821 } 4822 4823 // If load is not volatile and there are no uses of the loaded value (and 4824 // the updated indexed value in case of indexed loads), change uses of the 4825 // chain value into uses of the chain input (i.e. delete the dead load). 4826 if (!LD->isVolatile()) { 4827 if (N->getValueType(1) == MVT::Other) { 4828 // Unindexed loads. 4829 if (N->hasNUsesOfValue(0, 0)) { 4830 // It's not safe to use the two value CombineTo variant here. e.g. 4831 // v1, chain2 = load chain1, loc 4832 // v2, chain3 = load chain2, loc 4833 // v3 = add v2, c 4834 // Now we replace use of chain2 with chain1. This makes the second load 4835 // isomorphic to the one we are deleting, and thus makes this load live. 4836 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4837 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4838 DOUT << "\n"; 4839 WorkListRemover DeadNodes(*this); 4840 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4841 4842 if (N->use_empty()) { 4843 removeFromWorkList(N); 4844 DAG.DeleteNode(N); 4845 } 4846 4847 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4848 } 4849 } else { 4850 // Indexed loads. 4851 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4852 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4853 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4854 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4855 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4856 DOUT << " and 2 other values\n"; 4857 WorkListRemover DeadNodes(*this); 4858 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4859 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4860 DAG.getUNDEF(N->getValueType(1)), 4861 &DeadNodes); 4862 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4863 removeFromWorkList(N); 4864 DAG.DeleteNode(N); 4865 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4866 } 4867 } 4868 } 4869 4870 // If this load is directly stored, replace the load value with the stored 4871 // value. 4872 // TODO: Handle store large -> read small portion. 4873 // TODO: Handle TRUNCSTORE/LOADEXT 4874 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4875 !LD->isVolatile()) { 4876 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4877 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4878 if (PrevST->getBasePtr() == Ptr && 4879 PrevST->getValue().getValueType() == N->getValueType(0)) 4880 return CombineTo(N, Chain.getOperand(1), Chain); 4881 } 4882 } 4883 4884 if (CombinerAA) { 4885 // Walk up chain skipping non-aliasing memory nodes. 4886 SDValue BetterChain = FindBetterChain(N, Chain); 4887 4888 // If there is a better chain. 4889 if (Chain != BetterChain) { 4890 SDValue ReplLoad; 4891 4892 // Replace the chain to void dependency. 4893 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4894 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4895 BetterChain, Ptr, 4896 LD->getSrcValue(), LD->getSrcValueOffset(), 4897 LD->isVolatile(), LD->getAlignment()); 4898 } else { 4899 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4900 LD->getValueType(0), 4901 BetterChain, Ptr, LD->getSrcValue(), 4902 LD->getSrcValueOffset(), 4903 LD->getMemoryVT(), 4904 LD->isVolatile(), 4905 LD->getAlignment()); 4906 } 4907 4908 // Create token factor to keep old chain connected. 4909 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4910 MVT::Other, Chain, ReplLoad.getValue(1)); 4911 4912 // Replace uses with load result and token factor. Don't add users 4913 // to work list. 4914 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4915 } 4916 } 4917 4918 // Try transforming N to an indexed load. 4919 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4920 return SDValue(N, 0); 4921 4922 return SDValue(); 4923} 4924 4925 4926/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 4927/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 4928/// of the loaded bits, try narrowing the load and store if it would end up 4929/// being a win for performance or code size. 4930SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 4931 StoreSDNode *ST = cast<StoreSDNode>(N); 4932 if (ST->isVolatile()) 4933 return SDValue(); 4934 4935 SDValue Chain = ST->getChain(); 4936 SDValue Value = ST->getValue(); 4937 SDValue Ptr = ST->getBasePtr(); 4938 MVT VT = Value.getValueType(); 4939 4940 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 4941 return SDValue(); 4942 4943 unsigned Opc = Value.getOpcode(); 4944 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 4945 Value.getOperand(1).getOpcode() != ISD::Constant) 4946 return SDValue(); 4947 4948 SDValue N0 = Value.getOperand(0); 4949 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 4950 LoadSDNode *LD = cast<LoadSDNode>(N0); 4951 if (LD->getBasePtr() != Ptr) 4952 return SDValue(); 4953 4954 // Find the type to narrow it the load / op / store to. 4955 SDValue N1 = Value.getOperand(1); 4956 unsigned BitWidth = N1.getValueSizeInBits(); 4957 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 4958 if (Opc == ISD::AND) 4959 Imm ^= APInt::getAllOnesValue(BitWidth); 4960 if (Imm == 0 || Imm.isAllOnesValue()) 4961 return SDValue(); 4962 unsigned ShAmt = Imm.countTrailingZeros(); 4963 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 4964 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 4965 MVT NewVT = MVT::getIntegerVT(NewBW); 4966 while (NewBW < BitWidth && 4967 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 4968 TLI.isNarrowingProfitable(VT, NewVT))) { 4969 NewBW = NextPowerOf2(NewBW); 4970 NewVT = MVT::getIntegerVT(NewBW); 4971 } 4972 if (NewBW >= BitWidth) 4973 return SDValue(); 4974 4975 // If the lsb changed does not start at the type bitwidth boundary, 4976 // start at the previous one. 4977 if (ShAmt % NewBW) 4978 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 4979 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 4980 if ((Imm & Mask) == Imm) { 4981 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 4982 if (Opc == ISD::AND) 4983 NewImm ^= APInt::getAllOnesValue(NewBW); 4984 uint64_t PtrOff = ShAmt / 8; 4985 // For big endian targets, we need to adjust the offset to the pointer to 4986 // load the correct bytes. 4987 if (TLI.isBigEndian()) 4988 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 4989 4990 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 4991 if (NewAlign < 4992 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT())) 4993 return SDValue(); 4994 4995 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 4996 Ptr.getValueType(), Ptr, 4997 DAG.getConstant(PtrOff, Ptr.getValueType())); 4998 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 4999 LD->getChain(), NewPtr, 5000 LD->getSrcValue(), LD->getSrcValueOffset(), 5001 LD->isVolatile(), NewAlign); 5002 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5003 DAG.getConstant(NewImm, NewVT)); 5004 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5005 NewVal, NewPtr, 5006 ST->getSrcValue(), ST->getSrcValueOffset(), 5007 false, NewAlign); 5008 5009 AddToWorkList(NewPtr.getNode()); 5010 AddToWorkList(NewLD.getNode()); 5011 AddToWorkList(NewVal.getNode()); 5012 WorkListRemover DeadNodes(*this); 5013 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5014 &DeadNodes); 5015 ++OpsNarrowed; 5016 return NewST; 5017 } 5018 } 5019 5020 return SDValue(); 5021} 5022 5023SDValue DAGCombiner::visitSTORE(SDNode *N) { 5024 StoreSDNode *ST = cast<StoreSDNode>(N); 5025 SDValue Chain = ST->getChain(); 5026 SDValue Value = ST->getValue(); 5027 SDValue Ptr = ST->getBasePtr(); 5028 5029 // Try to infer better alignment information than the store already has. 5030 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5031 if (unsigned Align = InferAlignment(Ptr, DAG)) { 5032 if (Align > ST->getAlignment()) 5033 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5034 Ptr, ST->getSrcValue(), 5035 ST->getSrcValueOffset(), ST->getMemoryVT(), 5036 ST->isVolatile(), Align); 5037 } 5038 } 5039 5040 // If this is a store of a bit convert, store the input value if the 5041 // resultant store does not need a higher alignment than the original. 5042 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5043 ST->isUnindexed()) { 5044 unsigned OrigAlign = ST->getAlignment(); 5045 MVT SVT = Value.getOperand(0).getValueType(); 5046 unsigned Align = TLI.getTargetData()-> 5047 getABITypeAlignment(SVT.getTypeForMVT()); 5048 if (Align <= OrigAlign && 5049 ((!LegalOperations && !ST->isVolatile()) || 5050 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5051 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5052 Ptr, ST->getSrcValue(), 5053 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5054 } 5055 5056 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5057 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5058 // NOTE: If the original store is volatile, this transform must not increase 5059 // the number of stores. For example, on x86-32 an f64 can be stored in one 5060 // processor operation but an i64 (which is not legal) requires two. So the 5061 // transform should not be done in this case. 5062 if (Value.getOpcode() != ISD::TargetConstantFP) { 5063 SDValue Tmp; 5064 switch (CFP->getValueType(0).getSimpleVT()) { 5065 default: assert(0 && "Unknown FP type"); 5066 case MVT::f80: // We don't do this for these yet. 5067 case MVT::f128: 5068 case MVT::ppcf128: 5069 break; 5070 case MVT::f32: 5071 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5072 !ST->isVolatile()) || 5073 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5074 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5075 bitcastToAPInt().getZExtValue(), MVT::i32); 5076 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5077 Ptr, ST->getSrcValue(), 5078 ST->getSrcValueOffset(), ST->isVolatile(), 5079 ST->getAlignment()); 5080 } 5081 break; 5082 case MVT::f64: 5083 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5084 !ST->isVolatile()) || 5085 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5086 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5087 getZExtValue(), MVT::i64); 5088 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5089 Ptr, ST->getSrcValue(), 5090 ST->getSrcValueOffset(), ST->isVolatile(), 5091 ST->getAlignment()); 5092 } else if (!ST->isVolatile() && 5093 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5094 // Many FP stores are not made apparent until after legalize, e.g. for 5095 // argument passing. Since this is so common, custom legalize the 5096 // 64-bit integer store into two 32-bit stores. 5097 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5098 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5099 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5100 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5101 5102 int SVOffset = ST->getSrcValueOffset(); 5103 unsigned Alignment = ST->getAlignment(); 5104 bool isVolatile = ST->isVolatile(); 5105 5106 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5107 Ptr, ST->getSrcValue(), 5108 ST->getSrcValueOffset(), 5109 isVolatile, ST->getAlignment()); 5110 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5111 DAG.getConstant(4, Ptr.getValueType())); 5112 SVOffset += 4; 5113 Alignment = MinAlign(Alignment, 4U); 5114 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5115 Ptr, ST->getSrcValue(), 5116 SVOffset, isVolatile, Alignment); 5117 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5118 St0, St1); 5119 } 5120 5121 break; 5122 } 5123 } 5124 } 5125 5126 if (CombinerAA) { 5127 // Walk up chain skipping non-aliasing memory nodes. 5128 SDValue BetterChain = FindBetterChain(N, Chain); 5129 5130 // If there is a better chain. 5131 if (Chain != BetterChain) { 5132 // Replace the chain to avoid dependency. 5133 SDValue ReplStore; 5134 if (ST->isTruncatingStore()) { 5135 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5136 ST->getSrcValue(),ST->getSrcValueOffset(), 5137 ST->getMemoryVT(), 5138 ST->isVolatile(), ST->getAlignment()); 5139 } else { 5140 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5141 ST->getSrcValue(), ST->getSrcValueOffset(), 5142 ST->isVolatile(), ST->getAlignment()); 5143 } 5144 5145 // Create token to keep both nodes around. 5146 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5147 MVT::Other, Chain, ReplStore); 5148 5149 // Don't add users to work list. 5150 return CombineTo(N, Token, false); 5151 } 5152 } 5153 5154 // Try transforming N to an indexed store. 5155 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5156 return SDValue(N, 0); 5157 5158 // FIXME: is there such a thing as a truncating indexed store? 5159 if (ST->isTruncatingStore() && ST->isUnindexed() && 5160 Value.getValueType().isInteger()) { 5161 // See if we can simplify the input to this truncstore with knowledge that 5162 // only the low bits are being used. For example: 5163 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5164 SDValue Shorter = 5165 GetDemandedBits(Value, 5166 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5167 ST->getMemoryVT().getSizeInBits())); 5168 AddToWorkList(Value.getNode()); 5169 if (Shorter.getNode()) 5170 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5171 Ptr, ST->getSrcValue(), 5172 ST->getSrcValueOffset(), ST->getMemoryVT(), 5173 ST->isVolatile(), ST->getAlignment()); 5174 5175 // Otherwise, see if we can simplify the operation with 5176 // SimplifyDemandedBits, which only works if the value has a single use. 5177 if (SimplifyDemandedBits(Value, 5178 APInt::getLowBitsSet( 5179 Value.getValueSizeInBits(), 5180 ST->getMemoryVT().getSizeInBits()))) 5181 return SDValue(N, 0); 5182 } 5183 5184 // If this is a load followed by a store to the same location, then the store 5185 // is dead/noop. 5186 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5187 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5188 ST->isUnindexed() && !ST->isVolatile() && 5189 // There can't be any side effects between the load and store, such as 5190 // a call or store. 5191 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5192 // The store is dead, remove it. 5193 return Chain; 5194 } 5195 } 5196 5197 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5198 // truncating store. We can do this even if this is already a truncstore. 5199 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5200 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5201 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5202 ST->getMemoryVT())) { 5203 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5204 Ptr, ST->getSrcValue(), 5205 ST->getSrcValueOffset(), ST->getMemoryVT(), 5206 ST->isVolatile(), ST->getAlignment()); 5207 } 5208 5209 return ReduceLoadOpStoreWidth(N); 5210} 5211 5212SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5213 SDValue InVec = N->getOperand(0); 5214 SDValue InVal = N->getOperand(1); 5215 SDValue EltNo = N->getOperand(2); 5216 5217 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5218 // vector with the inserted element. 5219 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5220 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5221 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5222 InVec.getNode()->op_end()); 5223 if (Elt < Ops.size()) 5224 Ops[Elt] = InVal; 5225 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5226 InVec.getValueType(), &Ops[0], Ops.size()); 5227 } 5228 // If the invec is an UNDEF and if EltNo is a constant, create a new 5229 // BUILD_VECTOR with undef elements and the inserted element. 5230 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5231 isa<ConstantSDNode>(EltNo)) { 5232 MVT VT = InVec.getValueType(); 5233 MVT EVT = VT.getVectorElementType(); 5234 unsigned NElts = VT.getVectorNumElements(); 5235 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT)); 5236 5237 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5238 if (Elt < Ops.size()) 5239 Ops[Elt] = InVal; 5240 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5241 InVec.getValueType(), &Ops[0], Ops.size()); 5242 } 5243 return SDValue(); 5244} 5245 5246SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5247 // (vextract (scalar_to_vector val, 0) -> val 5248 SDValue InVec = N->getOperand(0); 5249 5250 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5251 // If the operand is wider than the vector element type then it is implicitly 5252 // truncated. Make that explicit here. 5253 MVT EltVT = InVec.getValueType().getVectorElementType(); 5254 SDValue InOp = InVec.getOperand(0); 5255 if (InOp.getValueType() != EltVT) 5256 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5257 return InOp; 5258 } 5259 5260 // Perform only after legalization to ensure build_vector / vector_shuffle 5261 // optimizations have already been done. 5262 if (!LegalOperations) return SDValue(); 5263 5264 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5265 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5266 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5267 SDValue EltNo = N->getOperand(1); 5268 5269 if (isa<ConstantSDNode>(EltNo)) { 5270 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5271 bool NewLoad = false; 5272 bool BCNumEltsChanged = false; 5273 MVT VT = InVec.getValueType(); 5274 MVT EVT = VT.getVectorElementType(); 5275 MVT LVT = EVT; 5276 5277 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5278 MVT BCVT = InVec.getOperand(0).getValueType(); 5279 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5280 return SDValue(); 5281 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5282 BCNumEltsChanged = true; 5283 InVec = InVec.getOperand(0); 5284 EVT = BCVT.getVectorElementType(); 5285 NewLoad = true; 5286 } 5287 5288 LoadSDNode *LN0 = NULL; 5289 const ShuffleVectorSDNode *SVN = NULL; 5290 if (ISD::isNormalLoad(InVec.getNode())) { 5291 LN0 = cast<LoadSDNode>(InVec); 5292 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5293 InVec.getOperand(0).getValueType() == EVT && 5294 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5295 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5296 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5297 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5298 // => 5299 // (load $addr+1*size) 5300 5301 // If the bit convert changed the number of elements, it is unsafe 5302 // to examine the mask. 5303 if (BCNumEltsChanged) 5304 return SDValue(); 5305 5306 // Select the input vector, guarding against out of range extract vector. 5307 unsigned NumElems = VT.getVectorNumElements(); 5308 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5309 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5310 5311 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5312 InVec = InVec.getOperand(0); 5313 if (ISD::isNormalLoad(InVec.getNode())) { 5314 LN0 = cast<LoadSDNode>(InVec); 5315 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5316 } 5317 } 5318 5319 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5320 return SDValue(); 5321 5322 unsigned Align = LN0->getAlignment(); 5323 if (NewLoad) { 5324 // Check the resultant load doesn't need a higher alignment than the 5325 // original load. 5326 unsigned NewAlign = 5327 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); 5328 5329 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5330 return SDValue(); 5331 5332 Align = NewAlign; 5333 } 5334 5335 SDValue NewPtr = LN0->getBasePtr(); 5336 if (Elt) { 5337 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5338 MVT PtrType = NewPtr.getValueType(); 5339 if (TLI.isBigEndian()) 5340 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5341 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5342 DAG.getConstant(PtrOff, PtrType)); 5343 } 5344 5345 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5346 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5347 LN0->isVolatile(), Align); 5348 } 5349 5350 return SDValue(); 5351} 5352 5353SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5354 unsigned NumInScalars = N->getNumOperands(); 5355 MVT VT = N->getValueType(0); 5356 MVT EltType = VT.getVectorElementType(); 5357 5358 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5359 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5360 // at most two distinct vectors, turn this into a shuffle node. 5361 SDValue VecIn1, VecIn2; 5362 for (unsigned i = 0; i != NumInScalars; ++i) { 5363 // Ignore undef inputs. 5364 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5365 5366 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5367 // constant index, bail out. 5368 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5369 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5370 VecIn1 = VecIn2 = SDValue(0, 0); 5371 break; 5372 } 5373 5374 // If the input vector type disagrees with the result of the build_vector, 5375 // we can't make a shuffle. 5376 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5377 if (ExtractedFromVec.getValueType() != VT) { 5378 VecIn1 = VecIn2 = SDValue(0, 0); 5379 break; 5380 } 5381 5382 // Otherwise, remember this. We allow up to two distinct input vectors. 5383 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5384 continue; 5385 5386 if (VecIn1.getNode() == 0) { 5387 VecIn1 = ExtractedFromVec; 5388 } else if (VecIn2.getNode() == 0) { 5389 VecIn2 = ExtractedFromVec; 5390 } else { 5391 // Too many inputs. 5392 VecIn1 = VecIn2 = SDValue(0, 0); 5393 break; 5394 } 5395 } 5396 5397 // If everything is good, we can make a shuffle operation. 5398 if (VecIn1.getNode()) { 5399 SmallVector<int, 8> Mask; 5400 for (unsigned i = 0; i != NumInScalars; ++i) { 5401 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5402 Mask.push_back(-1); 5403 continue; 5404 } 5405 5406 // If extracting from the first vector, just use the index directly. 5407 SDValue Extract = N->getOperand(i); 5408 SDValue ExtVal = Extract.getOperand(1); 5409 if (Extract.getOperand(0) == VecIn1) { 5410 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5411 if (ExtIndex > VT.getVectorNumElements()) 5412 return SDValue(); 5413 5414 Mask.push_back(ExtIndex); 5415 continue; 5416 } 5417 5418 // Otherwise, use InIdx + VecSize 5419 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5420 Mask.push_back(Idx+NumInScalars); 5421 } 5422 5423 // Add count and size info. 5424 if (!TLI.isTypeLegal(VT) && LegalTypes) 5425 return SDValue(); 5426 5427 // Return the new VECTOR_SHUFFLE node. 5428 SDValue Ops[2]; 5429 Ops[0] = VecIn1; 5430 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5431 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5432 } 5433 5434 return SDValue(); 5435} 5436 5437SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5438 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5439 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5440 // inputs come from at most two distinct vectors, turn this into a shuffle 5441 // node. 5442 5443 // If we only have one input vector, we don't need to do any concatenation. 5444 if (N->getNumOperands() == 1) 5445 return N->getOperand(0); 5446 5447 return SDValue(); 5448} 5449 5450SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5451 return SDValue(); 5452 5453 MVT VT = N->getValueType(0); 5454 unsigned NumElts = VT.getVectorNumElements(); 5455 5456 SDValue N0 = N->getOperand(0); 5457 SDValue N1 = N->getOperand(1); 5458 5459 assert(N0.getValueType().getVectorNumElements() == NumElts && 5460 "Vector shuffle must be normalized in DAG"); 5461 5462 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5463 5464 // If it is a splat, check if the argument vector is a build_vector with 5465 // all scalar elements the same. 5466 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5467 SDNode *V = N0.getNode(); 5468 5469 5470 // If this is a bit convert that changes the element type of the vector but 5471 // not the number of vector elements, look through it. Be careful not to 5472 // look though conversions that change things like v4f32 to v2f64. 5473 if (V->getOpcode() == ISD::BIT_CONVERT) { 5474 SDValue ConvInput = V->getOperand(0); 5475 if (ConvInput.getValueType().isVector() && 5476 ConvInput.getValueType().getVectorNumElements() == NumElts) 5477 V = ConvInput.getNode(); 5478 } 5479 5480 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5481 unsigned NumElems = V->getNumOperands(); 5482 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5483 if (NumElems > BaseIdx) { 5484 SDValue Base; 5485 bool AllSame = true; 5486 for (unsigned i = 0; i != NumElems; ++i) { 5487 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5488 Base = V->getOperand(i); 5489 break; 5490 } 5491 } 5492 // Splat of <u, u, u, u>, return <u, u, u, u> 5493 if (!Base.getNode()) 5494 return N0; 5495 for (unsigned i = 0; i != NumElems; ++i) { 5496 if (V->getOperand(i) != Base) { 5497 AllSame = false; 5498 break; 5499 } 5500 } 5501 // Splat of <x, x, x, x>, return <x, x, x, x> 5502 if (AllSame) 5503 return N0; 5504 } 5505 } 5506 } 5507 return SDValue(); 5508} 5509 5510/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5511/// an AND to a vector_shuffle with the destination vector and a zero vector. 5512/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5513/// vector_shuffle V, Zero, <0, 4, 2, 4> 5514SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5515 MVT VT = N->getValueType(0); 5516 DebugLoc dl = N->getDebugLoc(); 5517 SDValue LHS = N->getOperand(0); 5518 SDValue RHS = N->getOperand(1); 5519 if (N->getOpcode() == ISD::AND) { 5520 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5521 RHS = RHS.getOperand(0); 5522 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5523 SmallVector<int, 8> Indices; 5524 unsigned NumElts = RHS.getNumOperands(); 5525 for (unsigned i = 0; i != NumElts; ++i) { 5526 SDValue Elt = RHS.getOperand(i); 5527 if (!isa<ConstantSDNode>(Elt)) 5528 return SDValue(); 5529 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5530 Indices.push_back(i); 5531 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5532 Indices.push_back(NumElts); 5533 else 5534 return SDValue(); 5535 } 5536 5537 // Let's see if the target supports this vector_shuffle. 5538 MVT RVT = RHS.getValueType(); 5539 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5540 return SDValue(); 5541 5542 // Return the new VECTOR_SHUFFLE node. 5543 MVT EVT = RVT.getVectorElementType(); 5544 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5545 DAG.getConstant(0, EVT)); 5546 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5547 RVT, &ZeroOps[0], ZeroOps.size()); 5548 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5549 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5550 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5551 } 5552 } 5553 5554 return SDValue(); 5555} 5556 5557/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5558SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5559 // After legalize, the target may be depending on adds and other 5560 // binary ops to provide legal ways to construct constants or other 5561 // things. Simplifying them may result in a loss of legality. 5562 if (LegalOperations) return SDValue(); 5563 5564 MVT VT = N->getValueType(0); 5565 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5566 5567 MVT EltType = VT.getVectorElementType(); 5568 SDValue LHS = N->getOperand(0); 5569 SDValue RHS = N->getOperand(1); 5570 SDValue Shuffle = XformToShuffleWithZero(N); 5571 if (Shuffle.getNode()) return Shuffle; 5572 5573 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5574 // this operation. 5575 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5576 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5577 SmallVector<SDValue, 8> Ops; 5578 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5579 SDValue LHSOp = LHS.getOperand(i); 5580 SDValue RHSOp = RHS.getOperand(i); 5581 // If these two elements can't be folded, bail out. 5582 if ((LHSOp.getOpcode() != ISD::UNDEF && 5583 LHSOp.getOpcode() != ISD::Constant && 5584 LHSOp.getOpcode() != ISD::ConstantFP) || 5585 (RHSOp.getOpcode() != ISD::UNDEF && 5586 RHSOp.getOpcode() != ISD::Constant && 5587 RHSOp.getOpcode() != ISD::ConstantFP)) 5588 break; 5589 5590 // Can't fold divide by zero. 5591 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5592 N->getOpcode() == ISD::FDIV) { 5593 if ((RHSOp.getOpcode() == ISD::Constant && 5594 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5595 (RHSOp.getOpcode() == ISD::ConstantFP && 5596 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5597 break; 5598 } 5599 5600 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5601 EltType, LHSOp, RHSOp)); 5602 AddToWorkList(Ops.back().getNode()); 5603 assert((Ops.back().getOpcode() == ISD::UNDEF || 5604 Ops.back().getOpcode() == ISD::Constant || 5605 Ops.back().getOpcode() == ISD::ConstantFP) && 5606 "Scalar binop didn't fold!"); 5607 } 5608 5609 if (Ops.size() == LHS.getNumOperands()) { 5610 MVT VT = LHS.getValueType(); 5611 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5612 &Ops[0], Ops.size()); 5613 } 5614 } 5615 5616 return SDValue(); 5617} 5618 5619SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5620 SDValue N1, SDValue N2){ 5621 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5622 5623 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5624 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5625 5626 // If we got a simplified select_cc node back from SimplifySelectCC, then 5627 // break it down into a new SETCC node, and a new SELECT node, and then return 5628 // the SELECT node, since we were called with a SELECT node. 5629 if (SCC.getNode()) { 5630 // Check to see if we got a select_cc back (to turn into setcc/select). 5631 // Otherwise, just return whatever node we got back, like fabs. 5632 if (SCC.getOpcode() == ISD::SELECT_CC) { 5633 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5634 N0.getValueType(), 5635 SCC.getOperand(0), SCC.getOperand(1), 5636 SCC.getOperand(4)); 5637 AddToWorkList(SETCC.getNode()); 5638 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5639 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5640 } 5641 5642 return SCC; 5643 } 5644 return SDValue(); 5645} 5646 5647/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5648/// are the two values being selected between, see if we can simplify the 5649/// select. Callers of this should assume that TheSelect is deleted if this 5650/// returns true. As such, they should return the appropriate thing (e.g. the 5651/// node) back to the top-level of the DAG combiner loop to avoid it being 5652/// looked at. 5653bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5654 SDValue RHS) { 5655 5656 // If this is a select from two identical things, try to pull the operation 5657 // through the select. 5658 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5659 // If this is a load and the token chain is identical, replace the select 5660 // of two loads with a load through a select of the address to load from. 5661 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5662 // constants have been dropped into the constant pool. 5663 if (LHS.getOpcode() == ISD::LOAD && 5664 // Do not let this transformation reduce the number of volatile loads. 5665 !cast<LoadSDNode>(LHS)->isVolatile() && 5666 !cast<LoadSDNode>(RHS)->isVolatile() && 5667 // Token chains must be identical. 5668 LHS.getOperand(0) == RHS.getOperand(0)) { 5669 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5670 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5671 5672 // If this is an EXTLOAD, the VT's must match. 5673 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5674 // FIXME: this conflates two src values, discarding one. This is not 5675 // the right thing to do, but nothing uses srcvalues now. When they do, 5676 // turn SrcValue into a list of locations. 5677 SDValue Addr; 5678 if (TheSelect->getOpcode() == ISD::SELECT) { 5679 // Check that the condition doesn't reach either load. If so, folding 5680 // this will induce a cycle into the DAG. 5681 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5682 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5683 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5684 LLD->getBasePtr().getValueType(), 5685 TheSelect->getOperand(0), LLD->getBasePtr(), 5686 RLD->getBasePtr()); 5687 } 5688 } else { 5689 // Check that the condition doesn't reach either load. If so, folding 5690 // this will induce a cycle into the DAG. 5691 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5692 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5693 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5694 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5695 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5696 LLD->getBasePtr().getValueType(), 5697 TheSelect->getOperand(0), 5698 TheSelect->getOperand(1), 5699 LLD->getBasePtr(), RLD->getBasePtr(), 5700 TheSelect->getOperand(4)); 5701 } 5702 } 5703 5704 if (Addr.getNode()) { 5705 SDValue Load; 5706 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5707 Load = DAG.getLoad(TheSelect->getValueType(0), 5708 TheSelect->getDebugLoc(), 5709 LLD->getChain(), 5710 Addr,LLD->getSrcValue(), 5711 LLD->getSrcValueOffset(), 5712 LLD->isVolatile(), 5713 LLD->getAlignment()); 5714 } else { 5715 Load = DAG.getExtLoad(LLD->getExtensionType(), 5716 TheSelect->getDebugLoc(), 5717 TheSelect->getValueType(0), 5718 LLD->getChain(), Addr, LLD->getSrcValue(), 5719 LLD->getSrcValueOffset(), 5720 LLD->getMemoryVT(), 5721 LLD->isVolatile(), 5722 LLD->getAlignment()); 5723 } 5724 5725 // Users of the select now use the result of the load. 5726 CombineTo(TheSelect, Load); 5727 5728 // Users of the old loads now use the new load's chain. We know the 5729 // old-load value is dead now. 5730 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5731 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5732 return true; 5733 } 5734 } 5735 } 5736 } 5737 5738 return false; 5739} 5740 5741/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5742/// where 'cond' is the comparison specified by CC. 5743SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5744 SDValue N2, SDValue N3, 5745 ISD::CondCode CC, bool NotExtCompare) { 5746 // (x ? y : y) -> y. 5747 if (N2 == N3) return N2; 5748 5749 MVT VT = N2.getValueType(); 5750 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5751 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5752 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5753 5754 // Determine if the condition we're dealing with is constant 5755 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5756 N0, N1, CC, DL, false); 5757 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5758 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5759 5760 // fold select_cc true, x, y -> x 5761 if (SCCC && !SCCC->isNullValue()) 5762 return N2; 5763 // fold select_cc false, x, y -> y 5764 if (SCCC && SCCC->isNullValue()) 5765 return N3; 5766 5767 // Check to see if we can simplify the select into an fabs node 5768 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5769 // Allow either -0.0 or 0.0 5770 if (CFP->getValueAPF().isZero()) { 5771 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5772 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5773 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5774 N2 == N3.getOperand(0)) 5775 return DAG.getNode(ISD::FABS, DL, VT, N0); 5776 5777 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5778 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5779 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5780 N2.getOperand(0) == N3) 5781 return DAG.getNode(ISD::FABS, DL, VT, N3); 5782 } 5783 } 5784 5785 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5786 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5787 // in it. This is a win when the constant is not otherwise available because 5788 // it replaces two constant pool loads with one. We only do this if the FP 5789 // type is known to be legal, because if it isn't, then we are before legalize 5790 // types an we want the other legalization to happen first (e.g. to avoid 5791 // messing with soft float) and if the ConstantFP is not legal, because if 5792 // it is legal, we may not need to store the FP constant in a constant pool. 5793 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5794 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5795 if (TLI.isTypeLegal(N2.getValueType()) && 5796 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5797 TargetLowering::Legal) && 5798 // If both constants have multiple uses, then we won't need to do an 5799 // extra load, they are likely around in registers for other users. 5800 (TV->hasOneUse() || FV->hasOneUse())) { 5801 Constant *Elts[] = { 5802 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5803 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5804 }; 5805 const Type *FPTy = Elts[0]->getType(); 5806 const TargetData &TD = *TLI.getTargetData(); 5807 5808 // Create a ConstantArray of the two constants. 5809 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5810 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5811 TD.getPrefTypeAlignment(FPTy)); 5812 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5813 5814 // Get the offsets to the 0 and 1 element of the array so that we can 5815 // select between them. 5816 SDValue Zero = DAG.getIntPtrConstant(0); 5817 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5818 SDValue One = DAG.getIntPtrConstant(EltSize); 5819 5820 SDValue Cond = DAG.getSetCC(DL, 5821 TLI.getSetCCResultType(N0.getValueType()), 5822 N0, N1, CC); 5823 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5824 Cond, One, Zero); 5825 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5826 CstOffset); 5827 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5828 PseudoSourceValue::getConstantPool(), 0, false, 5829 Alignment); 5830 5831 } 5832 } 5833 5834 // Check to see if we can perform the "gzip trick", transforming 5835 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5836 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5837 N0.getValueType().isInteger() && 5838 N2.getValueType().isInteger() && 5839 (N1C->isNullValue() || // (a < 0) ? b : 0 5840 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5841 MVT XType = N0.getValueType(); 5842 MVT AType = N2.getValueType(); 5843 if (XType.bitsGE(AType)) { 5844 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5845 // single-bit constant. 5846 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5847 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5848 ShCtV = XType.getSizeInBits()-ShCtV-1; 5849 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5850 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5851 XType, N0, ShCt); 5852 AddToWorkList(Shift.getNode()); 5853 5854 if (XType.bitsGT(AType)) { 5855 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5856 AddToWorkList(Shift.getNode()); 5857 } 5858 5859 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5860 } 5861 5862 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5863 XType, N0, 5864 DAG.getConstant(XType.getSizeInBits()-1, 5865 getShiftAmountTy())); 5866 AddToWorkList(Shift.getNode()); 5867 5868 if (XType.bitsGT(AType)) { 5869 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5870 AddToWorkList(Shift.getNode()); 5871 } 5872 5873 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5874 } 5875 } 5876 5877 // fold select C, 16, 0 -> shl C, 4 5878 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5879 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5880 5881 // If the caller doesn't want us to simplify this into a zext of a compare, 5882 // don't do it. 5883 if (NotExtCompare && N2C->getAPIntValue() == 1) 5884 return SDValue(); 5885 5886 // Get a SetCC of the condition 5887 // FIXME: Should probably make sure that setcc is legal if we ever have a 5888 // target where it isn't. 5889 SDValue Temp, SCC; 5890 // cast from setcc result type to select result type 5891 if (LegalTypes) { 5892 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5893 N0, N1, CC); 5894 if (N2.getValueType().bitsLT(SCC.getValueType())) 5895 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5896 else 5897 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5898 N2.getValueType(), SCC); 5899 } else { 5900 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5901 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5902 N2.getValueType(), SCC); 5903 } 5904 5905 AddToWorkList(SCC.getNode()); 5906 AddToWorkList(Temp.getNode()); 5907 5908 if (N2C->getAPIntValue() == 1) 5909 return Temp; 5910 5911 // shl setcc result by log2 n2c 5912 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5913 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5914 getShiftAmountTy())); 5915 } 5916 5917 // Check to see if this is the equivalent of setcc 5918 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5919 // otherwise, go ahead with the folds. 5920 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5921 MVT XType = N0.getValueType(); 5922 if (!LegalOperations || 5923 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5924 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5925 if (Res.getValueType() != VT) 5926 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5927 return Res; 5928 } 5929 5930 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5931 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5932 (!LegalOperations || 5933 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5934 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5935 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5936 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5937 getShiftAmountTy())); 5938 } 5939 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5940 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5941 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5942 XType, DAG.getConstant(0, XType), N0); 5943 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5944 return DAG.getNode(ISD::SRL, DL, XType, 5945 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5946 DAG.getConstant(XType.getSizeInBits()-1, 5947 getShiftAmountTy())); 5948 } 5949 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5950 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5951 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5952 DAG.getConstant(XType.getSizeInBits()-1, 5953 getShiftAmountTy())); 5954 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5955 } 5956 } 5957 5958 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5959 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5960 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5961 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5962 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5963 MVT XType = N0.getValueType(); 5964 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5965 DAG.getConstant(XType.getSizeInBits()-1, 5966 getShiftAmountTy())); 5967 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5968 N0, Shift); 5969 AddToWorkList(Shift.getNode()); 5970 AddToWorkList(Add.getNode()); 5971 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5972 } 5973 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5974 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5975 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5976 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5977 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5978 MVT XType = N0.getValueType(); 5979 if (SubC->isNullValue() && XType.isInteger()) { 5980 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5981 N0, 5982 DAG.getConstant(XType.getSizeInBits()-1, 5983 getShiftAmountTy())); 5984 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 5985 XType, N0, Shift); 5986 AddToWorkList(Shift.getNode()); 5987 AddToWorkList(Add.getNode()); 5988 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5989 } 5990 } 5991 } 5992 5993 return SDValue(); 5994} 5995 5996/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5997SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5998 SDValue N1, ISD::CondCode Cond, 5999 DebugLoc DL, bool foldBooleans) { 6000 TargetLowering::DAGCombinerInfo 6001 DagCombineInfo(DAG, Level == Unrestricted, false, this); 6002 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6003} 6004 6005/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6006/// return a DAG expression to select that will generate the same value by 6007/// multiplying by a magic number. See: 6008/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6009SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6010 std::vector<SDNode*> Built; 6011 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6012 6013 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6014 ii != ee; ++ii) 6015 AddToWorkList(*ii); 6016 return S; 6017} 6018 6019/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6020/// return a DAG expression to select that will generate the same value by 6021/// multiplying by a magic number. See: 6022/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6023SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6024 std::vector<SDNode*> Built; 6025 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6026 6027 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6028 ii != ee; ++ii) 6029 AddToWorkList(*ii); 6030 return S; 6031} 6032 6033/// FindBaseOffset - Return true if base is known not to alias with anything 6034/// but itself. Provides base object and offset as results. 6035static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 6036 // Assume it is a primitive operation. 6037 Base = Ptr; Offset = 0; 6038 6039 // If it's an adding a simple constant then integrate the offset. 6040 if (Base.getOpcode() == ISD::ADD) { 6041 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6042 Base = Base.getOperand(0); 6043 Offset += C->getZExtValue(); 6044 } 6045 } 6046 6047 // If it's any of the following then it can't alias with anything but itself. 6048 return isa<FrameIndexSDNode>(Base) || 6049 isa<ConstantPoolSDNode>(Base) || 6050 isa<GlobalAddressSDNode>(Base); 6051} 6052 6053/// isAlias - Return true if there is any possibility that the two addresses 6054/// overlap. 6055bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6056 const Value *SrcValue1, int SrcValueOffset1, 6057 SDValue Ptr2, int64_t Size2, 6058 const Value *SrcValue2, int SrcValueOffset2) const { 6059 // If they are the same then they must be aliases. 6060 if (Ptr1 == Ptr2) return true; 6061 6062 // Gather base node and offset information. 6063 SDValue Base1, Base2; 6064 int64_t Offset1, Offset2; 6065 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 6066 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 6067 6068 // If they have a same base address then... 6069 if (Base1 == Base2) 6070 // Check to see if the addresses overlap. 6071 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6072 6073 // If we know both bases then they can't alias. 6074 if (KnownBase1 && KnownBase2) return false; 6075 6076 if (CombinerGlobalAA) { 6077 // Use alias analysis information. 6078 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6079 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6080 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6081 AliasAnalysis::AliasResult AAResult = 6082 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6083 if (AAResult == AliasAnalysis::NoAlias) 6084 return false; 6085 } 6086 6087 // Otherwise we have to assume they alias. 6088 return true; 6089} 6090 6091/// FindAliasInfo - Extracts the relevant alias information from the memory 6092/// node. Returns true if the operand was a load. 6093bool DAGCombiner::FindAliasInfo(SDNode *N, 6094 SDValue &Ptr, int64_t &Size, 6095 const Value *&SrcValue, int &SrcValueOffset) const { 6096 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6097 Ptr = LD->getBasePtr(); 6098 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6099 SrcValue = LD->getSrcValue(); 6100 SrcValueOffset = LD->getSrcValueOffset(); 6101 return true; 6102 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6103 Ptr = ST->getBasePtr(); 6104 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6105 SrcValue = ST->getSrcValue(); 6106 SrcValueOffset = ST->getSrcValueOffset(); 6107 } else { 6108 assert(0 && "FindAliasInfo expected a memory operand"); 6109 } 6110 6111 return false; 6112} 6113 6114/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6115/// looking for aliasing nodes and adding them to the Aliases vector. 6116void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6117 SmallVector<SDValue, 8> &Aliases) { 6118 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6119 std::set<SDNode *> Visited; // Visited node set. 6120 6121 // Get alias information for node. 6122 SDValue Ptr; 6123 int64_t Size = 0; 6124 const Value *SrcValue = 0; 6125 int SrcValueOffset = 0; 6126 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6127 6128 // Starting off. 6129 Chains.push_back(OriginalChain); 6130 6131 // Look at each chain and determine if it is an alias. If so, add it to the 6132 // aliases list. If not, then continue up the chain looking for the next 6133 // candidate. 6134 while (!Chains.empty()) { 6135 SDValue Chain = Chains.back(); 6136 Chains.pop_back(); 6137 6138 // Don't bother if we've been before. 6139 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6140 Visited.insert(Chain.getNode()); 6141 6142 switch (Chain.getOpcode()) { 6143 case ISD::EntryToken: 6144 // Entry token is ideal chain operand, but handled in FindBetterChain. 6145 break; 6146 6147 case ISD::LOAD: 6148 case ISD::STORE: { 6149 // Get alias information for Chain. 6150 SDValue OpPtr; 6151 int64_t OpSize = 0; 6152 const Value *OpSrcValue = 0; 6153 int OpSrcValueOffset = 0; 6154 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6155 OpSrcValue, OpSrcValueOffset); 6156 6157 // If chain is alias then stop here. 6158 if (!(IsLoad && IsOpLoad) && 6159 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6160 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6161 Aliases.push_back(Chain); 6162 } else { 6163 // Look further up the chain. 6164 Chains.push_back(Chain.getOperand(0)); 6165 // Clean up old chain. 6166 AddToWorkList(Chain.getNode()); 6167 } 6168 break; 6169 } 6170 6171 case ISD::TokenFactor: 6172 // We have to check each of the operands of the token factor, so we queue 6173 // then up. Adding the operands to the queue (stack) in reverse order 6174 // maintains the original order and increases the likelihood that getNode 6175 // will find a matching token factor (CSE.) 6176 for (unsigned n = Chain.getNumOperands(); n;) 6177 Chains.push_back(Chain.getOperand(--n)); 6178 // Eliminate the token factor if we can. 6179 AddToWorkList(Chain.getNode()); 6180 break; 6181 6182 default: 6183 // For all other instructions we will just have to take what we can get. 6184 Aliases.push_back(Chain); 6185 break; 6186 } 6187 } 6188} 6189 6190/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6191/// for a better chain (aliasing node.) 6192SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6193 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6194 6195 // Accumulate all the aliases to this node. 6196 GatherAllAliases(N, OldChain, Aliases); 6197 6198 if (Aliases.size() == 0) { 6199 // If no operands then chain to entry token. 6200 return DAG.getEntryNode(); 6201 } else if (Aliases.size() == 1) { 6202 // If a single operand then chain to it. We don't need to revisit it. 6203 return Aliases[0]; 6204 } 6205 6206 // Construct a custom tailored token factor. 6207 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6208 &Aliases[0], Aliases.size()); 6209 6210 // Make sure the old chain gets cleaned up. 6211 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6212 6213 return NewChain; 6214} 6215 6216// SelectionDAG::Combine - This is the entry point for the file. 6217// 6218void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6219 CodeGenOpt::Level OptLevel) { 6220 /// run - This is the main entry point to this class. 6221 /// 6222 DAGCombiner(*this, AA, OptLevel).Run(Level); 6223} 6224