DAGCombiner.cpp revision 2c94b4201beccbd061fd679ea7e9db1381fe8357
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include <algorithm> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 std::vector<SDNode*> WorkList; 67 68 // AA - Used for DAG load/store alias analysis. 69 AliasAnalysis &AA; 70 71 /// AddUsersToWorkList - When an instruction is simplified, add all users of 72 /// the instruction to the work lists because they might get more simplified 73 /// now. 74 /// 75 void AddUsersToWorkList(SDNode *N) { 76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 77 UI != UE; ++UI) 78 AddToWorkList(*UI); 79 } 80 81 /// visit - call the node-specific routine that knows how to fold each 82 /// particular type of node. 83 SDValue visit(SDNode *N); 84 85 public: 86 /// AddToWorkList - Add to the work list making sure it's instance is at the 87 /// the back (next to be processed.) 88 void AddToWorkList(SDNode *N) { 89 removeFromWorkList(N); 90 WorkList.push_back(N); 91 } 92 93 /// removeFromWorkList - remove all instances of N from the worklist. 94 /// 95 void removeFromWorkList(SDNode *N) { 96 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 97 WorkList.end()); 98 } 99 100 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 101 bool AddTo = true); 102 103 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 104 return CombineTo(N, &Res, 1, AddTo); 105 } 106 107 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 108 bool AddTo = true) { 109 SDValue To[] = { Res0, Res1 }; 110 return CombineTo(N, To, 2, AddTo); 111 } 112 113 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 114 115 private: 116 117 /// SimplifyDemandedBits - Check the specified integer node value to see if 118 /// it can be simplified or if things it uses can be simplified by bit 119 /// propagation. If so, return true. 120 bool SimplifyDemandedBits(SDValue Op) { 121 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 122 APInt Demanded = APInt::getAllOnesValue(BitWidth); 123 return SimplifyDemandedBits(Op, Demanded); 124 } 125 126 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 127 128 bool CombineToPreIndexedLoadStore(SDNode *N); 129 bool CombineToPostIndexedLoadStore(SDNode *N); 130 131 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 132 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 133 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 134 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue PromoteIntBinOp(SDValue Op); 136 SDValue PromoteIntShiftOp(SDValue Op); 137 SDValue PromoteExtend(SDValue Op); 138 bool PromoteLoad(SDValue Op); 139 140 /// combine - call the node-specific routine that knows how to fold each 141 /// particular type of node. If that doesn't do anything, try the 142 /// target-specific DAG combines. 143 SDValue combine(SDNode *N); 144 145 // Visitation implementation - Implement dag node combining for different 146 // node types. The semantics are as follows: 147 // Return Value: 148 // SDValue.getNode() == 0 - No change was made 149 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 150 // otherwise - N should be replaced by the returned Operand. 151 // 152 SDValue visitTokenFactor(SDNode *N); 153 SDValue visitMERGE_VALUES(SDNode *N); 154 SDValue visitADD(SDNode *N); 155 SDValue visitSUB(SDNode *N); 156 SDValue visitADDC(SDNode *N); 157 SDValue visitADDE(SDNode *N); 158 SDValue visitMUL(SDNode *N); 159 SDValue visitSDIV(SDNode *N); 160 SDValue visitUDIV(SDNode *N); 161 SDValue visitSREM(SDNode *N); 162 SDValue visitUREM(SDNode *N); 163 SDValue visitMULHU(SDNode *N); 164 SDValue visitMULHS(SDNode *N); 165 SDValue visitSMUL_LOHI(SDNode *N); 166 SDValue visitUMUL_LOHI(SDNode *N); 167 SDValue visitSDIVREM(SDNode *N); 168 SDValue visitUDIVREM(SDNode *N); 169 SDValue visitAND(SDNode *N); 170 SDValue visitOR(SDNode *N); 171 SDValue visitXOR(SDNode *N); 172 SDValue SimplifyVBinOp(SDNode *N); 173 SDValue visitSHL(SDNode *N); 174 SDValue visitSRA(SDNode *N); 175 SDValue visitSRL(SDNode *N); 176 SDValue visitCTLZ(SDNode *N); 177 SDValue visitCTTZ(SDNode *N); 178 SDValue visitCTPOP(SDNode *N); 179 SDValue visitSELECT(SDNode *N); 180 SDValue visitSELECT_CC(SDNode *N); 181 SDValue visitSETCC(SDNode *N); 182 SDValue visitSIGN_EXTEND(SDNode *N); 183 SDValue visitZERO_EXTEND(SDNode *N); 184 SDValue visitANY_EXTEND(SDNode *N); 185 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 186 SDValue visitTRUNCATE(SDNode *N); 187 SDValue visitBITCAST(SDNode *N); 188 SDValue visitBUILD_PAIR(SDNode *N); 189 SDValue visitFADD(SDNode *N); 190 SDValue visitFSUB(SDNode *N); 191 SDValue visitFMUL(SDNode *N); 192 SDValue visitFDIV(SDNode *N); 193 SDValue visitFREM(SDNode *N); 194 SDValue visitFCOPYSIGN(SDNode *N); 195 SDValue visitSINT_TO_FP(SDNode *N); 196 SDValue visitUINT_TO_FP(SDNode *N); 197 SDValue visitFP_TO_SINT(SDNode *N); 198 SDValue visitFP_TO_UINT(SDNode *N); 199 SDValue visitFP_ROUND(SDNode *N); 200 SDValue visitFP_ROUND_INREG(SDNode *N); 201 SDValue visitFP_EXTEND(SDNode *N); 202 SDValue visitFNEG(SDNode *N); 203 SDValue visitFABS(SDNode *N); 204 SDValue visitBRCOND(SDNode *N); 205 SDValue visitBR_CC(SDNode *N); 206 SDValue visitLOAD(SDNode *N); 207 SDValue visitSTORE(SDNode *N); 208 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 209 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 210 SDValue visitBUILD_VECTOR(SDNode *N); 211 SDValue visitCONCAT_VECTORS(SDNode *N); 212 SDValue visitVECTOR_SHUFFLE(SDNode *N); 213 SDValue visitMEMBARRIER(SDNode *N); 214 215 SDValue XformToShuffleWithZero(SDNode *N); 216 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 217 218 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 219 220 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 221 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 222 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 223 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 224 SDValue N3, ISD::CondCode CC, 225 bool NotExtCompare = false); 226 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 227 DebugLoc DL, bool foldBooleans = true); 228 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 229 unsigned HiOp); 230 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 231 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 232 SDValue BuildSDIV(SDNode *N); 233 SDValue BuildUDIV(SDNode *N); 234 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 235 SDValue ReduceLoadWidth(SDNode *N); 236 SDValue ReduceLoadOpStoreWidth(SDNode *N); 237 238 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 239 240 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 241 /// looking for aliasing nodes and adding them to the Aliases vector. 242 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 243 SmallVector<SDValue, 8> &Aliases); 244 245 /// isAlias - Return true if there is any possibility that the two addresses 246 /// overlap. 247 bool isAlias(SDValue Ptr1, int64_t Size1, 248 const Value *SrcValue1, int SrcValueOffset1, 249 unsigned SrcValueAlign1, 250 const MDNode *TBAAInfo1, 251 SDValue Ptr2, int64_t Size2, 252 const Value *SrcValue2, int SrcValueOffset2, 253 unsigned SrcValueAlign2, 254 const MDNode *TBAAInfo2) const; 255 256 /// FindAliasInfo - Extracts the relevant alias information from the memory 257 /// node. Returns true if the operand was a load. 258 bool FindAliasInfo(SDNode *N, 259 SDValue &Ptr, int64_t &Size, 260 const Value *&SrcValue, int &SrcValueOffset, 261 unsigned &SrcValueAlignment, 262 const MDNode *&TBAAInfo) const; 263 264 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 265 /// looking for a better chain (aliasing node.) 266 SDValue FindBetterChain(SDNode *N, SDValue Chain); 267 268 public: 269 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 270 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 271 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 272 273 /// Run - runs the dag combiner on all nodes in the work list 274 void Run(CombineLevel AtLevel); 275 276 SelectionDAG &getDAG() const { return DAG; } 277 278 /// getShiftAmountTy - Returns a type large enough to hold any valid 279 /// shift amount - before type legalization these can be huge. 280 EVT getShiftAmountTy() { 281 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 282 } 283 284 /// isTypeLegal - This method returns true if we are running before type 285 /// legalization or if the specified VT is legal. 286 bool isTypeLegal(const EVT &VT) { 287 if (!LegalTypes) return true; 288 return TLI.isTypeLegal(VT); 289 } 290 }; 291} 292 293 294namespace { 295/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 296/// nodes from the worklist. 297class WorkListRemover : public SelectionDAG::DAGUpdateListener { 298 DAGCombiner &DC; 299public: 300 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 301 302 virtual void NodeDeleted(SDNode *N, SDNode *E) { 303 DC.removeFromWorkList(N); 304 } 305 306 virtual void NodeUpdated(SDNode *N) { 307 // Ignore updates. 308 } 309}; 310} 311 312//===----------------------------------------------------------------------===// 313// TargetLowering::DAGCombinerInfo implementation 314//===----------------------------------------------------------------------===// 315 316void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 317 ((DAGCombiner*)DC)->AddToWorkList(N); 318} 319 320SDValue TargetLowering::DAGCombinerInfo:: 321CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 322 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 323} 324 325SDValue TargetLowering::DAGCombinerInfo:: 326CombineTo(SDNode *N, SDValue Res, bool AddTo) { 327 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 328} 329 330 331SDValue TargetLowering::DAGCombinerInfo:: 332CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 333 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 334} 335 336void TargetLowering::DAGCombinerInfo:: 337CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 338 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 339} 340 341//===----------------------------------------------------------------------===// 342// Helper Functions 343//===----------------------------------------------------------------------===// 344 345/// isNegatibleForFree - Return 1 if we can compute the negated form of the 346/// specified expression for the same cost as the expression itself, or 2 if we 347/// can compute the negated form more cheaply than the expression itself. 348static char isNegatibleForFree(SDValue Op, bool LegalOperations, 349 unsigned Depth = 0) { 350 // No compile time optimizations on this type. 351 if (Op.getValueType() == MVT::ppcf128) 352 return 0; 353 354 // fneg is removable even if it has multiple uses. 355 if (Op.getOpcode() == ISD::FNEG) return 2; 356 357 // Don't allow anything with multiple uses. 358 if (!Op.hasOneUse()) return 0; 359 360 // Don't recurse exponentially. 361 if (Depth > 6) return 0; 362 363 switch (Op.getOpcode()) { 364 default: return false; 365 case ISD::ConstantFP: 366 // Don't invert constant FP values after legalize. The negated constant 367 // isn't necessarily legal. 368 return LegalOperations ? 0 : 1; 369 case ISD::FADD: 370 // FIXME: determine better conditions for this xform. 371 if (!UnsafeFPMath) return 0; 372 373 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 374 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 375 return V; 376 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 377 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 378 case ISD::FSUB: 379 // We can't turn -(A-B) into B-A when we honor signed zeros. 380 if (!UnsafeFPMath) return 0; 381 382 // fold (fneg (fsub A, B)) -> (fsub B, A) 383 return 1; 384 385 case ISD::FMUL: 386 case ISD::FDIV: 387 if (HonorSignDependentRoundingFPMath()) return 0; 388 389 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 390 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 391 return V; 392 393 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 394 395 case ISD::FP_EXTEND: 396 case ISD::FP_ROUND: 397 case ISD::FSIN: 398 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 399 } 400} 401 402/// GetNegatedExpression - If isNegatibleForFree returns true, this function 403/// returns the newly negated expression. 404static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 405 bool LegalOperations, unsigned Depth = 0) { 406 // fneg is removable even if it has multiple uses. 407 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 408 409 // Don't allow anything with multiple uses. 410 assert(Op.hasOneUse() && "Unknown reuse!"); 411 412 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 413 switch (Op.getOpcode()) { 414 default: llvm_unreachable("Unknown code"); 415 case ISD::ConstantFP: { 416 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 417 V.changeSign(); 418 return DAG.getConstantFP(V, Op.getValueType()); 419 } 420 case ISD::FADD: 421 // FIXME: determine better conditions for this xform. 422 assert(UnsafeFPMath); 423 424 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 425 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 426 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 427 GetNegatedExpression(Op.getOperand(0), DAG, 428 LegalOperations, Depth+1), 429 Op.getOperand(1)); 430 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 431 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 432 GetNegatedExpression(Op.getOperand(1), DAG, 433 LegalOperations, Depth+1), 434 Op.getOperand(0)); 435 case ISD::FSUB: 436 // We can't turn -(A-B) into B-A when we honor signed zeros. 437 assert(UnsafeFPMath); 438 439 // fold (fneg (fsub 0, B)) -> B 440 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 441 if (N0CFP->getValueAPF().isZero()) 442 return Op.getOperand(1); 443 444 // fold (fneg (fsub A, B)) -> (fsub B, A) 445 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 446 Op.getOperand(1), Op.getOperand(0)); 447 448 case ISD::FMUL: 449 case ISD::FDIV: 450 assert(!HonorSignDependentRoundingFPMath()); 451 452 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 453 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 454 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 455 GetNegatedExpression(Op.getOperand(0), DAG, 456 LegalOperations, Depth+1), 457 Op.getOperand(1)); 458 459 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 460 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 461 Op.getOperand(0), 462 GetNegatedExpression(Op.getOperand(1), DAG, 463 LegalOperations, Depth+1)); 464 465 case ISD::FP_EXTEND: 466 case ISD::FSIN: 467 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 468 GetNegatedExpression(Op.getOperand(0), DAG, 469 LegalOperations, Depth+1)); 470 case ISD::FP_ROUND: 471 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 472 GetNegatedExpression(Op.getOperand(0), DAG, 473 LegalOperations, Depth+1), 474 Op.getOperand(1)); 475 } 476} 477 478 479// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 480// that selects between the values 1 and 0, making it equivalent to a setcc. 481// Also, set the incoming LHS, RHS, and CC references to the appropriate 482// nodes based on the type of node we are checking. This simplifies life a 483// bit for the callers. 484static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 485 SDValue &CC) { 486 if (N.getOpcode() == ISD::SETCC) { 487 LHS = N.getOperand(0); 488 RHS = N.getOperand(1); 489 CC = N.getOperand(2); 490 return true; 491 } 492 if (N.getOpcode() == ISD::SELECT_CC && 493 N.getOperand(2).getOpcode() == ISD::Constant && 494 N.getOperand(3).getOpcode() == ISD::Constant && 495 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 496 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 497 LHS = N.getOperand(0); 498 RHS = N.getOperand(1); 499 CC = N.getOperand(4); 500 return true; 501 } 502 return false; 503} 504 505// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 506// one use. If this is true, it allows the users to invert the operation for 507// free when it is profitable to do so. 508static bool isOneUseSetCC(SDValue N) { 509 SDValue N0, N1, N2; 510 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 511 return true; 512 return false; 513} 514 515SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 516 SDValue N0, SDValue N1) { 517 EVT VT = N0.getValueType(); 518 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 519 if (isa<ConstantSDNode>(N1)) { 520 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 521 SDValue OpNode = 522 DAG.FoldConstantArithmetic(Opc, VT, 523 cast<ConstantSDNode>(N0.getOperand(1)), 524 cast<ConstantSDNode>(N1)); 525 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 526 } else if (N0.hasOneUse()) { 527 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 528 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 529 N0.getOperand(0), N1); 530 AddToWorkList(OpNode.getNode()); 531 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 532 } 533 } 534 535 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 536 if (isa<ConstantSDNode>(N0)) { 537 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 538 SDValue OpNode = 539 DAG.FoldConstantArithmetic(Opc, VT, 540 cast<ConstantSDNode>(N1.getOperand(1)), 541 cast<ConstantSDNode>(N0)); 542 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 543 } else if (N1.hasOneUse()) { 544 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 545 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 546 N1.getOperand(0), N0); 547 AddToWorkList(OpNode.getNode()); 548 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 549 } 550 } 551 552 return SDValue(); 553} 554 555SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 556 bool AddTo) { 557 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 558 ++NodesCombined; 559 DEBUG(dbgs() << "\nReplacing.1 "; 560 N->dump(&DAG); 561 dbgs() << "\nWith: "; 562 To[0].getNode()->dump(&DAG); 563 dbgs() << " and " << NumTo-1 << " other values\n"; 564 for (unsigned i = 0, e = NumTo; i != e; ++i) 565 assert((!To[i].getNode() || 566 N->getValueType(i) == To[i].getValueType()) && 567 "Cannot combine value to value of different type!")); 568 WorkListRemover DeadNodes(*this); 569 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 570 571 if (AddTo) { 572 // Push the new nodes and any users onto the worklist 573 for (unsigned i = 0, e = NumTo; i != e; ++i) { 574 if (To[i].getNode()) { 575 AddToWorkList(To[i].getNode()); 576 AddUsersToWorkList(To[i].getNode()); 577 } 578 } 579 } 580 581 // Finally, if the node is now dead, remove it from the graph. The node 582 // may not be dead if the replacement process recursively simplified to 583 // something else needing this node. 584 if (N->use_empty()) { 585 // Nodes can be reintroduced into the worklist. Make sure we do not 586 // process a node that has been replaced. 587 removeFromWorkList(N); 588 589 // Finally, since the node is now dead, remove it from the graph. 590 DAG.DeleteNode(N); 591 } 592 return SDValue(N, 0); 593} 594 595void DAGCombiner:: 596CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 597 // Replace all uses. If any nodes become isomorphic to other nodes and 598 // are deleted, make sure to remove them from our worklist. 599 WorkListRemover DeadNodes(*this); 600 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 601 602 // Push the new node and any (possibly new) users onto the worklist. 603 AddToWorkList(TLO.New.getNode()); 604 AddUsersToWorkList(TLO.New.getNode()); 605 606 // Finally, if the node is now dead, remove it from the graph. The node 607 // may not be dead if the replacement process recursively simplified to 608 // something else needing this node. 609 if (TLO.Old.getNode()->use_empty()) { 610 removeFromWorkList(TLO.Old.getNode()); 611 612 // If the operands of this node are only used by the node, they will now 613 // be dead. Make sure to visit them first to delete dead nodes early. 614 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 615 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 616 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 617 618 DAG.DeleteNode(TLO.Old.getNode()); 619 } 620} 621 622/// SimplifyDemandedBits - Check the specified integer node value to see if 623/// it can be simplified or if things it uses can be simplified by bit 624/// propagation. If so, return true. 625bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 626 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 627 APInt KnownZero, KnownOne; 628 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 629 return false; 630 631 // Revisit the node. 632 AddToWorkList(Op.getNode()); 633 634 // Replace the old value with the new one. 635 ++NodesCombined; 636 DEBUG(dbgs() << "\nReplacing.2 "; 637 TLO.Old.getNode()->dump(&DAG); 638 dbgs() << "\nWith: "; 639 TLO.New.getNode()->dump(&DAG); 640 dbgs() << '\n'); 641 642 CommitTargetLoweringOpt(TLO); 643 return true; 644} 645 646void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 647 DebugLoc dl = Load->getDebugLoc(); 648 EVT VT = Load->getValueType(0); 649 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 650 651 DEBUG(dbgs() << "\nReplacing.9 "; 652 Load->dump(&DAG); 653 dbgs() << "\nWith: "; 654 Trunc.getNode()->dump(&DAG); 655 dbgs() << '\n'); 656 WorkListRemover DeadNodes(*this); 657 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 658 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 659 &DeadNodes); 660 removeFromWorkList(Load); 661 DAG.DeleteNode(Load); 662 AddToWorkList(Trunc.getNode()); 663} 664 665SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 666 Replace = false; 667 DebugLoc dl = Op.getDebugLoc(); 668 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 669 EVT MemVT = LD->getMemoryVT(); 670 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 671 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 672 : ISD::EXTLOAD) 673 : LD->getExtensionType(); 674 Replace = true; 675 return DAG.getExtLoad(ExtType, PVT, dl, 676 LD->getChain(), LD->getBasePtr(), 677 LD->getPointerInfo(), 678 MemVT, LD->isVolatile(), 679 LD->isNonTemporal(), LD->getAlignment()); 680 } 681 682 unsigned Opc = Op.getOpcode(); 683 switch (Opc) { 684 default: break; 685 case ISD::AssertSext: 686 return DAG.getNode(ISD::AssertSext, dl, PVT, 687 SExtPromoteOperand(Op.getOperand(0), PVT), 688 Op.getOperand(1)); 689 case ISD::AssertZext: 690 return DAG.getNode(ISD::AssertZext, dl, PVT, 691 ZExtPromoteOperand(Op.getOperand(0), PVT), 692 Op.getOperand(1)); 693 case ISD::Constant: { 694 unsigned ExtOpc = 695 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 696 return DAG.getNode(ExtOpc, dl, PVT, Op); 697 } 698 } 699 700 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 701 return SDValue(); 702 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 703} 704 705SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 706 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 707 return SDValue(); 708 EVT OldVT = Op.getValueType(); 709 DebugLoc dl = Op.getDebugLoc(); 710 bool Replace = false; 711 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 712 if (NewOp.getNode() == 0) 713 return SDValue(); 714 AddToWorkList(NewOp.getNode()); 715 716 if (Replace) 717 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 718 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 719 DAG.getValueType(OldVT)); 720} 721 722SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 723 EVT OldVT = Op.getValueType(); 724 DebugLoc dl = Op.getDebugLoc(); 725 bool Replace = false; 726 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 727 if (NewOp.getNode() == 0) 728 return SDValue(); 729 AddToWorkList(NewOp.getNode()); 730 731 if (Replace) 732 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 733 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 734} 735 736/// PromoteIntBinOp - Promote the specified integer binary operation if the 737/// target indicates it is beneficial. e.g. On x86, it's usually better to 738/// promote i16 operations to i32 since i16 instructions are longer. 739SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 740 if (!LegalOperations) 741 return SDValue(); 742 743 EVT VT = Op.getValueType(); 744 if (VT.isVector() || !VT.isInteger()) 745 return SDValue(); 746 747 // If operation type is 'undesirable', e.g. i16 on x86, consider 748 // promoting it. 749 unsigned Opc = Op.getOpcode(); 750 if (TLI.isTypeDesirableForOp(Opc, VT)) 751 return SDValue(); 752 753 EVT PVT = VT; 754 // Consult target whether it is a good idea to promote this operation and 755 // what's the right type to promote it to. 756 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 757 assert(PVT != VT && "Don't know what type to promote to!"); 758 759 bool Replace0 = false; 760 SDValue N0 = Op.getOperand(0); 761 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 762 if (NN0.getNode() == 0) 763 return SDValue(); 764 765 bool Replace1 = false; 766 SDValue N1 = Op.getOperand(1); 767 SDValue NN1; 768 if (N0 == N1) 769 NN1 = NN0; 770 else { 771 NN1 = PromoteOperand(N1, PVT, Replace1); 772 if (NN1.getNode() == 0) 773 return SDValue(); 774 } 775 776 AddToWorkList(NN0.getNode()); 777 if (NN1.getNode()) 778 AddToWorkList(NN1.getNode()); 779 780 if (Replace0) 781 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 782 if (Replace1) 783 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 784 785 DEBUG(dbgs() << "\nPromoting "; 786 Op.getNode()->dump(&DAG)); 787 DebugLoc dl = Op.getDebugLoc(); 788 return DAG.getNode(ISD::TRUNCATE, dl, VT, 789 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 790 } 791 return SDValue(); 792} 793 794/// PromoteIntShiftOp - Promote the specified integer shift operation if the 795/// target indicates it is beneficial. e.g. On x86, it's usually better to 796/// promote i16 operations to i32 since i16 instructions are longer. 797SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 798 if (!LegalOperations) 799 return SDValue(); 800 801 EVT VT = Op.getValueType(); 802 if (VT.isVector() || !VT.isInteger()) 803 return SDValue(); 804 805 // If operation type is 'undesirable', e.g. i16 on x86, consider 806 // promoting it. 807 unsigned Opc = Op.getOpcode(); 808 if (TLI.isTypeDesirableForOp(Opc, VT)) 809 return SDValue(); 810 811 EVT PVT = VT; 812 // Consult target whether it is a good idea to promote this operation and 813 // what's the right type to promote it to. 814 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 815 assert(PVT != VT && "Don't know what type to promote to!"); 816 817 bool Replace = false; 818 SDValue N0 = Op.getOperand(0); 819 if (Opc == ISD::SRA) 820 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 821 else if (Opc == ISD::SRL) 822 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 823 else 824 N0 = PromoteOperand(N0, PVT, Replace); 825 if (N0.getNode() == 0) 826 return SDValue(); 827 828 AddToWorkList(N0.getNode()); 829 if (Replace) 830 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 831 832 DEBUG(dbgs() << "\nPromoting "; 833 Op.getNode()->dump(&DAG)); 834 DebugLoc dl = Op.getDebugLoc(); 835 return DAG.getNode(ISD::TRUNCATE, dl, VT, 836 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 837 } 838 return SDValue(); 839} 840 841SDValue DAGCombiner::PromoteExtend(SDValue Op) { 842 if (!LegalOperations) 843 return SDValue(); 844 845 EVT VT = Op.getValueType(); 846 if (VT.isVector() || !VT.isInteger()) 847 return SDValue(); 848 849 // If operation type is 'undesirable', e.g. i16 on x86, consider 850 // promoting it. 851 unsigned Opc = Op.getOpcode(); 852 if (TLI.isTypeDesirableForOp(Opc, VT)) 853 return SDValue(); 854 855 EVT PVT = VT; 856 // Consult target whether it is a good idea to promote this operation and 857 // what's the right type to promote it to. 858 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 859 assert(PVT != VT && "Don't know what type to promote to!"); 860 // fold (aext (aext x)) -> (aext x) 861 // fold (aext (zext x)) -> (zext x) 862 // fold (aext (sext x)) -> (sext x) 863 DEBUG(dbgs() << "\nPromoting "; 864 Op.getNode()->dump(&DAG)); 865 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 866 } 867 return SDValue(); 868} 869 870bool DAGCombiner::PromoteLoad(SDValue Op) { 871 if (!LegalOperations) 872 return false; 873 874 EVT VT = Op.getValueType(); 875 if (VT.isVector() || !VT.isInteger()) 876 return false; 877 878 // If operation type is 'undesirable', e.g. i16 on x86, consider 879 // promoting it. 880 unsigned Opc = Op.getOpcode(); 881 if (TLI.isTypeDesirableForOp(Opc, VT)) 882 return false; 883 884 EVT PVT = VT; 885 // Consult target whether it is a good idea to promote this operation and 886 // what's the right type to promote it to. 887 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 888 assert(PVT != VT && "Don't know what type to promote to!"); 889 890 DebugLoc dl = Op.getDebugLoc(); 891 SDNode *N = Op.getNode(); 892 LoadSDNode *LD = cast<LoadSDNode>(N); 893 EVT MemVT = LD->getMemoryVT(); 894 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 895 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 896 : ISD::EXTLOAD) 897 : LD->getExtensionType(); 898 SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl, 899 LD->getChain(), LD->getBasePtr(), 900 LD->getPointerInfo(), 901 MemVT, LD->isVolatile(), 902 LD->isNonTemporal(), LD->getAlignment()); 903 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 904 905 DEBUG(dbgs() << "\nPromoting "; 906 N->dump(&DAG); 907 dbgs() << "\nTo: "; 908 Result.getNode()->dump(&DAG); 909 dbgs() << '\n'); 910 WorkListRemover DeadNodes(*this); 911 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 912 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 913 removeFromWorkList(N); 914 DAG.DeleteNode(N); 915 AddToWorkList(Result.getNode()); 916 return true; 917 } 918 return false; 919} 920 921 922//===----------------------------------------------------------------------===// 923// Main DAG Combiner implementation 924//===----------------------------------------------------------------------===// 925 926void DAGCombiner::Run(CombineLevel AtLevel) { 927 // set the instance variables, so that the various visit routines may use it. 928 Level = AtLevel; 929 LegalOperations = Level >= NoIllegalOperations; 930 LegalTypes = Level >= NoIllegalTypes; 931 932 // Add all the dag nodes to the worklist. 933 WorkList.reserve(DAG.allnodes_size()); 934 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 935 E = DAG.allnodes_end(); I != E; ++I) 936 WorkList.push_back(I); 937 938 // Create a dummy node (which is not added to allnodes), that adds a reference 939 // to the root node, preventing it from being deleted, and tracking any 940 // changes of the root. 941 HandleSDNode Dummy(DAG.getRoot()); 942 943 // The root of the dag may dangle to deleted nodes until the dag combiner is 944 // done. Set it to null to avoid confusion. 945 DAG.setRoot(SDValue()); 946 947 // while the worklist isn't empty, inspect the node on the end of it and 948 // try and combine it. 949 while (!WorkList.empty()) { 950 SDNode *N = WorkList.back(); 951 WorkList.pop_back(); 952 953 // If N has no uses, it is dead. Make sure to revisit all N's operands once 954 // N is deleted from the DAG, since they too may now be dead or may have a 955 // reduced number of uses, allowing other xforms. 956 if (N->use_empty() && N != &Dummy) { 957 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 958 AddToWorkList(N->getOperand(i).getNode()); 959 960 DAG.DeleteNode(N); 961 continue; 962 } 963 964 SDValue RV = combine(N); 965 966 if (RV.getNode() == 0) 967 continue; 968 969 ++NodesCombined; 970 971 // If we get back the same node we passed in, rather than a new node or 972 // zero, we know that the node must have defined multiple values and 973 // CombineTo was used. Since CombineTo takes care of the worklist 974 // mechanics for us, we have no work to do in this case. 975 if (RV.getNode() == N) 976 continue; 977 978 assert(N->getOpcode() != ISD::DELETED_NODE && 979 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 980 "Node was deleted but visit returned new node!"); 981 982 DEBUG(dbgs() << "\nReplacing.3 "; 983 N->dump(&DAG); 984 dbgs() << "\nWith: "; 985 RV.getNode()->dump(&DAG); 986 dbgs() << '\n'); 987 WorkListRemover DeadNodes(*this); 988 if (N->getNumValues() == RV.getNode()->getNumValues()) 989 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 990 else { 991 assert(N->getValueType(0) == RV.getValueType() && 992 N->getNumValues() == 1 && "Type mismatch"); 993 SDValue OpV = RV; 994 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 995 } 996 997 // Push the new node and any users onto the worklist 998 AddToWorkList(RV.getNode()); 999 AddUsersToWorkList(RV.getNode()); 1000 1001 // Add any uses of the old node to the worklist in case this node is the 1002 // last one that uses them. They may become dead after this node is 1003 // deleted. 1004 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1005 AddToWorkList(N->getOperand(i).getNode()); 1006 1007 // Finally, if the node is now dead, remove it from the graph. The node 1008 // may not be dead if the replacement process recursively simplified to 1009 // something else needing this node. 1010 if (N->use_empty()) { 1011 // Nodes can be reintroduced into the worklist. Make sure we do not 1012 // process a node that has been replaced. 1013 removeFromWorkList(N); 1014 1015 // Finally, since the node is now dead, remove it from the graph. 1016 DAG.DeleteNode(N); 1017 } 1018 } 1019 1020 // If the root changed (e.g. it was a dead load, update the root). 1021 DAG.setRoot(Dummy.getValue()); 1022} 1023 1024SDValue DAGCombiner::visit(SDNode *N) { 1025 switch (N->getOpcode()) { 1026 default: break; 1027 case ISD::TokenFactor: return visitTokenFactor(N); 1028 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1029 case ISD::ADD: return visitADD(N); 1030 case ISD::SUB: return visitSUB(N); 1031 case ISD::ADDC: return visitADDC(N); 1032 case ISD::ADDE: return visitADDE(N); 1033 case ISD::MUL: return visitMUL(N); 1034 case ISD::SDIV: return visitSDIV(N); 1035 case ISD::UDIV: return visitUDIV(N); 1036 case ISD::SREM: return visitSREM(N); 1037 case ISD::UREM: return visitUREM(N); 1038 case ISD::MULHU: return visitMULHU(N); 1039 case ISD::MULHS: return visitMULHS(N); 1040 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1041 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1042 case ISD::SDIVREM: return visitSDIVREM(N); 1043 case ISD::UDIVREM: return visitUDIVREM(N); 1044 case ISD::AND: return visitAND(N); 1045 case ISD::OR: return visitOR(N); 1046 case ISD::XOR: return visitXOR(N); 1047 case ISD::SHL: return visitSHL(N); 1048 case ISD::SRA: return visitSRA(N); 1049 case ISD::SRL: return visitSRL(N); 1050 case ISD::CTLZ: return visitCTLZ(N); 1051 case ISD::CTTZ: return visitCTTZ(N); 1052 case ISD::CTPOP: return visitCTPOP(N); 1053 case ISD::SELECT: return visitSELECT(N); 1054 case ISD::SELECT_CC: return visitSELECT_CC(N); 1055 case ISD::SETCC: return visitSETCC(N); 1056 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1057 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1058 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1059 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1060 case ISD::TRUNCATE: return visitTRUNCATE(N); 1061 case ISD::BITCAST: return visitBITCAST(N); 1062 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1063 case ISD::FADD: return visitFADD(N); 1064 case ISD::FSUB: return visitFSUB(N); 1065 case ISD::FMUL: return visitFMUL(N); 1066 case ISD::FDIV: return visitFDIV(N); 1067 case ISD::FREM: return visitFREM(N); 1068 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1069 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1070 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1071 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1072 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1073 case ISD::FP_ROUND: return visitFP_ROUND(N); 1074 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1075 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1076 case ISD::FNEG: return visitFNEG(N); 1077 case ISD::FABS: return visitFABS(N); 1078 case ISD::BRCOND: return visitBRCOND(N); 1079 case ISD::BR_CC: return visitBR_CC(N); 1080 case ISD::LOAD: return visitLOAD(N); 1081 case ISD::STORE: return visitSTORE(N); 1082 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1083 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1084 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1085 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1086 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1087 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1088 } 1089 return SDValue(); 1090} 1091 1092SDValue DAGCombiner::combine(SDNode *N) { 1093 SDValue RV = visit(N); 1094 1095 // If nothing happened, try a target-specific DAG combine. 1096 if (RV.getNode() == 0) { 1097 assert(N->getOpcode() != ISD::DELETED_NODE && 1098 "Node was deleted but visit returned NULL!"); 1099 1100 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1101 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1102 1103 // Expose the DAG combiner to the target combiner impls. 1104 TargetLowering::DAGCombinerInfo 1105 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1106 1107 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1108 } 1109 } 1110 1111 // If nothing happened still, try promoting the operation. 1112 if (RV.getNode() == 0) { 1113 switch (N->getOpcode()) { 1114 default: break; 1115 case ISD::ADD: 1116 case ISD::SUB: 1117 case ISD::MUL: 1118 case ISD::AND: 1119 case ISD::OR: 1120 case ISD::XOR: 1121 RV = PromoteIntBinOp(SDValue(N, 0)); 1122 break; 1123 case ISD::SHL: 1124 case ISD::SRA: 1125 case ISD::SRL: 1126 RV = PromoteIntShiftOp(SDValue(N, 0)); 1127 break; 1128 case ISD::SIGN_EXTEND: 1129 case ISD::ZERO_EXTEND: 1130 case ISD::ANY_EXTEND: 1131 RV = PromoteExtend(SDValue(N, 0)); 1132 break; 1133 case ISD::LOAD: 1134 if (PromoteLoad(SDValue(N, 0))) 1135 RV = SDValue(N, 0); 1136 break; 1137 } 1138 } 1139 1140 // If N is a commutative binary node, try commuting it to enable more 1141 // sdisel CSE. 1142 if (RV.getNode() == 0 && 1143 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1144 N->getNumValues() == 1) { 1145 SDValue N0 = N->getOperand(0); 1146 SDValue N1 = N->getOperand(1); 1147 1148 // Constant operands are canonicalized to RHS. 1149 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1150 SDValue Ops[] = { N1, N0 }; 1151 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1152 Ops, 2); 1153 if (CSENode) 1154 return SDValue(CSENode, 0); 1155 } 1156 } 1157 1158 return RV; 1159} 1160 1161/// getInputChainForNode - Given a node, return its input chain if it has one, 1162/// otherwise return a null sd operand. 1163static SDValue getInputChainForNode(SDNode *N) { 1164 if (unsigned NumOps = N->getNumOperands()) { 1165 if (N->getOperand(0).getValueType() == MVT::Other) 1166 return N->getOperand(0); 1167 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1168 return N->getOperand(NumOps-1); 1169 for (unsigned i = 1; i < NumOps-1; ++i) 1170 if (N->getOperand(i).getValueType() == MVT::Other) 1171 return N->getOperand(i); 1172 } 1173 return SDValue(); 1174} 1175 1176SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1177 // If N has two operands, where one has an input chain equal to the other, 1178 // the 'other' chain is redundant. 1179 if (N->getNumOperands() == 2) { 1180 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1181 return N->getOperand(0); 1182 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1183 return N->getOperand(1); 1184 } 1185 1186 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1187 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1188 SmallPtrSet<SDNode*, 16> SeenOps; 1189 bool Changed = false; // If we should replace this token factor. 1190 1191 // Start out with this token factor. 1192 TFs.push_back(N); 1193 1194 // Iterate through token factors. The TFs grows when new token factors are 1195 // encountered. 1196 for (unsigned i = 0; i < TFs.size(); ++i) { 1197 SDNode *TF = TFs[i]; 1198 1199 // Check each of the operands. 1200 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1201 SDValue Op = TF->getOperand(i); 1202 1203 switch (Op.getOpcode()) { 1204 case ISD::EntryToken: 1205 // Entry tokens don't need to be added to the list. They are 1206 // rededundant. 1207 Changed = true; 1208 break; 1209 1210 case ISD::TokenFactor: 1211 if (Op.hasOneUse() && 1212 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1213 // Queue up for processing. 1214 TFs.push_back(Op.getNode()); 1215 // Clean up in case the token factor is removed. 1216 AddToWorkList(Op.getNode()); 1217 Changed = true; 1218 break; 1219 } 1220 // Fall thru 1221 1222 default: 1223 // Only add if it isn't already in the list. 1224 if (SeenOps.insert(Op.getNode())) 1225 Ops.push_back(Op); 1226 else 1227 Changed = true; 1228 break; 1229 } 1230 } 1231 } 1232 1233 SDValue Result; 1234 1235 // If we've change things around then replace token factor. 1236 if (Changed) { 1237 if (Ops.empty()) { 1238 // The entry token is the only possible outcome. 1239 Result = DAG.getEntryNode(); 1240 } else { 1241 // New and improved token factor. 1242 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1243 MVT::Other, &Ops[0], Ops.size()); 1244 } 1245 1246 // Don't add users to work list. 1247 return CombineTo(N, Result, false); 1248 } 1249 1250 return Result; 1251} 1252 1253/// MERGE_VALUES can always be eliminated. 1254SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1255 WorkListRemover DeadNodes(*this); 1256 // Replacing results may cause a different MERGE_VALUES to suddenly 1257 // be CSE'd with N, and carry its uses with it. Iterate until no 1258 // uses remain, to ensure that the node can be safely deleted. 1259 do { 1260 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1261 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1262 &DeadNodes); 1263 } while (!N->use_empty()); 1264 removeFromWorkList(N); 1265 DAG.DeleteNode(N); 1266 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1267} 1268 1269static 1270SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1271 SelectionDAG &DAG) { 1272 EVT VT = N0.getValueType(); 1273 SDValue N00 = N0.getOperand(0); 1274 SDValue N01 = N0.getOperand(1); 1275 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1276 1277 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1278 isa<ConstantSDNode>(N00.getOperand(1))) { 1279 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1280 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1281 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1282 N00.getOperand(0), N01), 1283 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1284 N00.getOperand(1), N01)); 1285 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1286 } 1287 1288 return SDValue(); 1289} 1290 1291SDValue DAGCombiner::visitADD(SDNode *N) { 1292 SDValue N0 = N->getOperand(0); 1293 SDValue N1 = N->getOperand(1); 1294 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1295 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1296 EVT VT = N0.getValueType(); 1297 1298 // fold vector ops 1299 if (VT.isVector()) { 1300 SDValue FoldedVOp = SimplifyVBinOp(N); 1301 if (FoldedVOp.getNode()) return FoldedVOp; 1302 } 1303 1304 // fold (add x, undef) -> undef 1305 if (N0.getOpcode() == ISD::UNDEF) 1306 return N0; 1307 if (N1.getOpcode() == ISD::UNDEF) 1308 return N1; 1309 // fold (add c1, c2) -> c1+c2 1310 if (N0C && N1C) 1311 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1312 // canonicalize constant to RHS 1313 if (N0C && !N1C) 1314 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1315 // fold (add x, 0) -> x 1316 if (N1C && N1C->isNullValue()) 1317 return N0; 1318 // fold (add Sym, c) -> Sym+c 1319 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1320 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1321 GA->getOpcode() == ISD::GlobalAddress) 1322 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1323 GA->getOffset() + 1324 (uint64_t)N1C->getSExtValue()); 1325 // fold ((c1-A)+c2) -> (c1+c2)-A 1326 if (N1C && N0.getOpcode() == ISD::SUB) 1327 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1328 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1329 DAG.getConstant(N1C->getAPIntValue()+ 1330 N0C->getAPIntValue(), VT), 1331 N0.getOperand(1)); 1332 // reassociate add 1333 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1334 if (RADD.getNode() != 0) 1335 return RADD; 1336 // fold ((0-A) + B) -> B-A 1337 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1338 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1339 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1340 // fold (A + (0-B)) -> A-B 1341 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1342 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1343 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1344 // fold (A+(B-A)) -> B 1345 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1346 return N1.getOperand(0); 1347 // fold ((B-A)+A) -> B 1348 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1349 return N0.getOperand(0); 1350 // fold (A+(B-(A+C))) to (B-C) 1351 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1352 N0 == N1.getOperand(1).getOperand(0)) 1353 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1354 N1.getOperand(1).getOperand(1)); 1355 // fold (A+(B-(C+A))) to (B-C) 1356 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1357 N0 == N1.getOperand(1).getOperand(1)) 1358 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1359 N1.getOperand(1).getOperand(0)); 1360 // fold (A+((B-A)+or-C)) to (B+or-C) 1361 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1362 N1.getOperand(0).getOpcode() == ISD::SUB && 1363 N0 == N1.getOperand(0).getOperand(1)) 1364 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1365 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1366 1367 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1368 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1369 SDValue N00 = N0.getOperand(0); 1370 SDValue N01 = N0.getOperand(1); 1371 SDValue N10 = N1.getOperand(0); 1372 SDValue N11 = N1.getOperand(1); 1373 1374 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1375 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1376 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1377 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1378 } 1379 1380 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1381 return SDValue(N, 0); 1382 1383 // fold (a+b) -> (a|b) iff a and b share no bits. 1384 if (VT.isInteger() && !VT.isVector()) { 1385 APInt LHSZero, LHSOne; 1386 APInt RHSZero, RHSOne; 1387 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1388 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1389 1390 if (LHSZero.getBoolValue()) { 1391 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1392 1393 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1394 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1395 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1396 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1397 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1398 } 1399 } 1400 1401 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1402 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1403 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1404 if (Result.getNode()) return Result; 1405 } 1406 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1407 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1408 if (Result.getNode()) return Result; 1409 } 1410 1411 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1412 if (N1.getOpcode() == ISD::SHL && 1413 N1.getOperand(0).getOpcode() == ISD::SUB) 1414 if (ConstantSDNode *C = 1415 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1416 if (C->getAPIntValue() == 0) 1417 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1418 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1419 N1.getOperand(0).getOperand(1), 1420 N1.getOperand(1))); 1421 if (N0.getOpcode() == ISD::SHL && 1422 N0.getOperand(0).getOpcode() == ISD::SUB) 1423 if (ConstantSDNode *C = 1424 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1425 if (C->getAPIntValue() == 0) 1426 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1427 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1428 N0.getOperand(0).getOperand(1), 1429 N0.getOperand(1))); 1430 1431 if (N1.getOpcode() == ISD::AND) { 1432 SDValue AndOp0 = N1.getOperand(0); 1433 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1434 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1435 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1436 1437 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1438 // and similar xforms where the inner op is either ~0 or 0. 1439 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1440 DebugLoc DL = N->getDebugLoc(); 1441 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1442 } 1443 } 1444 1445 // add (sext i1), X -> sub X, (zext i1) 1446 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1447 N0.getOperand(0).getValueType() == MVT::i1 && 1448 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1449 DebugLoc DL = N->getDebugLoc(); 1450 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1451 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1452 } 1453 1454 return SDValue(); 1455} 1456 1457SDValue DAGCombiner::visitADDC(SDNode *N) { 1458 SDValue N0 = N->getOperand(0); 1459 SDValue N1 = N->getOperand(1); 1460 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1461 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1462 EVT VT = N0.getValueType(); 1463 1464 // If the flag result is dead, turn this into an ADD. 1465 if (N->hasNUsesOfValue(0, 1)) 1466 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1467 DAG.getNode(ISD::CARRY_FALSE, 1468 N->getDebugLoc(), MVT::Glue)); 1469 1470 // canonicalize constant to RHS. 1471 if (N0C && !N1C) 1472 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1473 1474 // fold (addc x, 0) -> x + no carry out 1475 if (N1C && N1C->isNullValue()) 1476 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1477 N->getDebugLoc(), MVT::Glue)); 1478 1479 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1480 APInt LHSZero, LHSOne; 1481 APInt RHSZero, RHSOne; 1482 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1483 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1484 1485 if (LHSZero.getBoolValue()) { 1486 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1487 1488 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1489 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1490 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1491 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1492 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1493 DAG.getNode(ISD::CARRY_FALSE, 1494 N->getDebugLoc(), MVT::Glue)); 1495 } 1496 1497 return SDValue(); 1498} 1499 1500SDValue DAGCombiner::visitADDE(SDNode *N) { 1501 SDValue N0 = N->getOperand(0); 1502 SDValue N1 = N->getOperand(1); 1503 SDValue CarryIn = N->getOperand(2); 1504 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1505 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1506 1507 // canonicalize constant to RHS 1508 if (N0C && !N1C) 1509 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1510 N1, N0, CarryIn); 1511 1512 // fold (adde x, y, false) -> (addc x, y) 1513 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1514 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1515 1516 return SDValue(); 1517} 1518 1519SDValue DAGCombiner::visitSUB(SDNode *N) { 1520 SDValue N0 = N->getOperand(0); 1521 SDValue N1 = N->getOperand(1); 1522 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1523 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1524 EVT VT = N0.getValueType(); 1525 1526 // fold vector ops 1527 if (VT.isVector()) { 1528 SDValue FoldedVOp = SimplifyVBinOp(N); 1529 if (FoldedVOp.getNode()) return FoldedVOp; 1530 } 1531 1532 // fold (sub x, x) -> 0 1533 if (N0 == N1) 1534 return DAG.getConstant(0, N->getValueType(0)); 1535 // fold (sub c1, c2) -> c1-c2 1536 if (N0C && N1C) 1537 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1538 // fold (sub x, c) -> (add x, -c) 1539 if (N1C) 1540 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1541 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1542 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1543 if (N0C && N0C->isAllOnesValue()) 1544 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1545 // fold A-(A-B) -> B 1546 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1547 return N1.getOperand(1); 1548 // fold (A+B)-A -> B 1549 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1550 return N0.getOperand(1); 1551 // fold (A+B)-B -> A 1552 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1553 return N0.getOperand(0); 1554 // fold ((A+(B+or-C))-B) -> A+or-C 1555 if (N0.getOpcode() == ISD::ADD && 1556 (N0.getOperand(1).getOpcode() == ISD::SUB || 1557 N0.getOperand(1).getOpcode() == ISD::ADD) && 1558 N0.getOperand(1).getOperand(0) == N1) 1559 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1560 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1561 // fold ((A+(C+B))-B) -> A+C 1562 if (N0.getOpcode() == ISD::ADD && 1563 N0.getOperand(1).getOpcode() == ISD::ADD && 1564 N0.getOperand(1).getOperand(1) == N1) 1565 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1566 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1567 // fold ((A-(B-C))-C) -> A-B 1568 if (N0.getOpcode() == ISD::SUB && 1569 N0.getOperand(1).getOpcode() == ISD::SUB && 1570 N0.getOperand(1).getOperand(1) == N1) 1571 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1572 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1573 1574 // If either operand of a sub is undef, the result is undef 1575 if (N0.getOpcode() == ISD::UNDEF) 1576 return N0; 1577 if (N1.getOpcode() == ISD::UNDEF) 1578 return N1; 1579 1580 // If the relocation model supports it, consider symbol offsets. 1581 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1582 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1583 // fold (sub Sym, c) -> Sym-c 1584 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1585 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1586 GA->getOffset() - 1587 (uint64_t)N1C->getSExtValue()); 1588 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1589 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1590 if (GA->getGlobal() == GB->getGlobal()) 1591 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1592 VT); 1593 } 1594 1595 return SDValue(); 1596} 1597 1598SDValue DAGCombiner::visitMUL(SDNode *N) { 1599 SDValue N0 = N->getOperand(0); 1600 SDValue N1 = N->getOperand(1); 1601 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1602 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1603 EVT VT = N0.getValueType(); 1604 1605 // fold vector ops 1606 if (VT.isVector()) { 1607 SDValue FoldedVOp = SimplifyVBinOp(N); 1608 if (FoldedVOp.getNode()) return FoldedVOp; 1609 } 1610 1611 // fold (mul x, undef) -> 0 1612 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1613 return DAG.getConstant(0, VT); 1614 // fold (mul c1, c2) -> c1*c2 1615 if (N0C && N1C) 1616 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1617 // canonicalize constant to RHS 1618 if (N0C && !N1C) 1619 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1620 // fold (mul x, 0) -> 0 1621 if (N1C && N1C->isNullValue()) 1622 return N1; 1623 // fold (mul x, -1) -> 0-x 1624 if (N1C && N1C->isAllOnesValue()) 1625 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1626 DAG.getConstant(0, VT), N0); 1627 // fold (mul x, (1 << c)) -> x << c 1628 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1629 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1630 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1631 getShiftAmountTy())); 1632 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1633 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1634 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1635 // FIXME: If the input is something that is easily negated (e.g. a 1636 // single-use add), we should put the negate there. 1637 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1638 DAG.getConstant(0, VT), 1639 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1640 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1641 } 1642 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1643 if (N1C && N0.getOpcode() == ISD::SHL && 1644 isa<ConstantSDNode>(N0.getOperand(1))) { 1645 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1646 N1, N0.getOperand(1)); 1647 AddToWorkList(C3.getNode()); 1648 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1649 N0.getOperand(0), C3); 1650 } 1651 1652 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1653 // use. 1654 { 1655 SDValue Sh(0,0), Y(0,0); 1656 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1657 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1658 N0.getNode()->hasOneUse()) { 1659 Sh = N0; Y = N1; 1660 } else if (N1.getOpcode() == ISD::SHL && 1661 isa<ConstantSDNode>(N1.getOperand(1)) && 1662 N1.getNode()->hasOneUse()) { 1663 Sh = N1; Y = N0; 1664 } 1665 1666 if (Sh.getNode()) { 1667 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1668 Sh.getOperand(0), Y); 1669 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1670 Mul, Sh.getOperand(1)); 1671 } 1672 } 1673 1674 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1675 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1676 isa<ConstantSDNode>(N0.getOperand(1))) 1677 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1678 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1679 N0.getOperand(0), N1), 1680 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1681 N0.getOperand(1), N1)); 1682 1683 // reassociate mul 1684 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1685 if (RMUL.getNode() != 0) 1686 return RMUL; 1687 1688 return SDValue(); 1689} 1690 1691SDValue DAGCombiner::visitSDIV(SDNode *N) { 1692 SDValue N0 = N->getOperand(0); 1693 SDValue N1 = N->getOperand(1); 1694 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1695 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1696 EVT VT = N->getValueType(0); 1697 1698 // fold vector ops 1699 if (VT.isVector()) { 1700 SDValue FoldedVOp = SimplifyVBinOp(N); 1701 if (FoldedVOp.getNode()) return FoldedVOp; 1702 } 1703 1704 // fold (sdiv c1, c2) -> c1/c2 1705 if (N0C && N1C && !N1C->isNullValue()) 1706 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1707 // fold (sdiv X, 1) -> X 1708 if (N1C && N1C->getSExtValue() == 1LL) 1709 return N0; 1710 // fold (sdiv X, -1) -> 0-X 1711 if (N1C && N1C->isAllOnesValue()) 1712 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1713 DAG.getConstant(0, VT), N0); 1714 // If we know the sign bits of both operands are zero, strength reduce to a 1715 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1716 if (!VT.isVector()) { 1717 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1718 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1719 N0, N1); 1720 } 1721 // fold (sdiv X, pow2) -> simple ops after legalize 1722 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1723 (isPowerOf2_64(N1C->getSExtValue()) || 1724 isPowerOf2_64(-N1C->getSExtValue()))) { 1725 // If dividing by powers of two is cheap, then don't perform the following 1726 // fold. 1727 if (TLI.isPow2DivCheap()) 1728 return SDValue(); 1729 1730 int64_t pow2 = N1C->getSExtValue(); 1731 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1732 unsigned lg2 = Log2_64(abs2); 1733 1734 // Splat the sign bit into the register 1735 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1736 DAG.getConstant(VT.getSizeInBits()-1, 1737 getShiftAmountTy())); 1738 AddToWorkList(SGN.getNode()); 1739 1740 // Add (N0 < 0) ? abs2 - 1 : 0; 1741 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1742 DAG.getConstant(VT.getSizeInBits() - lg2, 1743 getShiftAmountTy())); 1744 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1745 AddToWorkList(SRL.getNode()); 1746 AddToWorkList(ADD.getNode()); // Divide by pow2 1747 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1748 DAG.getConstant(lg2, getShiftAmountTy())); 1749 1750 // If we're dividing by a positive value, we're done. Otherwise, we must 1751 // negate the result. 1752 if (pow2 > 0) 1753 return SRA; 1754 1755 AddToWorkList(SRA.getNode()); 1756 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1757 DAG.getConstant(0, VT), SRA); 1758 } 1759 1760 // if integer divide is expensive and we satisfy the requirements, emit an 1761 // alternate sequence. 1762 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1763 !TLI.isIntDivCheap()) { 1764 SDValue Op = BuildSDIV(N); 1765 if (Op.getNode()) return Op; 1766 } 1767 1768 // undef / X -> 0 1769 if (N0.getOpcode() == ISD::UNDEF) 1770 return DAG.getConstant(0, VT); 1771 // X / undef -> undef 1772 if (N1.getOpcode() == ISD::UNDEF) 1773 return N1; 1774 1775 return SDValue(); 1776} 1777 1778SDValue DAGCombiner::visitUDIV(SDNode *N) { 1779 SDValue N0 = N->getOperand(0); 1780 SDValue N1 = N->getOperand(1); 1781 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1782 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1783 EVT VT = N->getValueType(0); 1784 1785 // fold vector ops 1786 if (VT.isVector()) { 1787 SDValue FoldedVOp = SimplifyVBinOp(N); 1788 if (FoldedVOp.getNode()) return FoldedVOp; 1789 } 1790 1791 // fold (udiv c1, c2) -> c1/c2 1792 if (N0C && N1C && !N1C->isNullValue()) 1793 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1794 // fold (udiv x, (1 << c)) -> x >>u c 1795 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1796 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1797 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1798 getShiftAmountTy())); 1799 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1800 if (N1.getOpcode() == ISD::SHL) { 1801 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1802 if (SHC->getAPIntValue().isPowerOf2()) { 1803 EVT ADDVT = N1.getOperand(1).getValueType(); 1804 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1805 N1.getOperand(1), 1806 DAG.getConstant(SHC->getAPIntValue() 1807 .logBase2(), 1808 ADDVT)); 1809 AddToWorkList(Add.getNode()); 1810 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1811 } 1812 } 1813 } 1814 // fold (udiv x, c) -> alternate 1815 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1816 SDValue Op = BuildUDIV(N); 1817 if (Op.getNode()) return Op; 1818 } 1819 1820 // undef / X -> 0 1821 if (N0.getOpcode() == ISD::UNDEF) 1822 return DAG.getConstant(0, VT); 1823 // X / undef -> undef 1824 if (N1.getOpcode() == ISD::UNDEF) 1825 return N1; 1826 1827 return SDValue(); 1828} 1829 1830SDValue DAGCombiner::visitSREM(SDNode *N) { 1831 SDValue N0 = N->getOperand(0); 1832 SDValue N1 = N->getOperand(1); 1833 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1834 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1835 EVT VT = N->getValueType(0); 1836 1837 // fold (srem c1, c2) -> c1%c2 1838 if (N0C && N1C && !N1C->isNullValue()) 1839 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1840 // If we know the sign bits of both operands are zero, strength reduce to a 1841 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1842 if (!VT.isVector()) { 1843 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1844 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1845 } 1846 1847 // If X/C can be simplified by the division-by-constant logic, lower 1848 // X%C to the equivalent of X-X/C*C. 1849 if (N1C && !N1C->isNullValue()) { 1850 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1851 AddToWorkList(Div.getNode()); 1852 SDValue OptimizedDiv = combine(Div.getNode()); 1853 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1854 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1855 OptimizedDiv, N1); 1856 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1857 AddToWorkList(Mul.getNode()); 1858 return Sub; 1859 } 1860 } 1861 1862 // undef % X -> 0 1863 if (N0.getOpcode() == ISD::UNDEF) 1864 return DAG.getConstant(0, VT); 1865 // X % undef -> undef 1866 if (N1.getOpcode() == ISD::UNDEF) 1867 return N1; 1868 1869 return SDValue(); 1870} 1871 1872SDValue DAGCombiner::visitUREM(SDNode *N) { 1873 SDValue N0 = N->getOperand(0); 1874 SDValue N1 = N->getOperand(1); 1875 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1876 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1877 EVT VT = N->getValueType(0); 1878 1879 // fold (urem c1, c2) -> c1%c2 1880 if (N0C && N1C && !N1C->isNullValue()) 1881 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1882 // fold (urem x, pow2) -> (and x, pow2-1) 1883 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1884 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1885 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1886 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1887 if (N1.getOpcode() == ISD::SHL) { 1888 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1889 if (SHC->getAPIntValue().isPowerOf2()) { 1890 SDValue Add = 1891 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1892 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1893 VT)); 1894 AddToWorkList(Add.getNode()); 1895 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1896 } 1897 } 1898 } 1899 1900 // If X/C can be simplified by the division-by-constant logic, lower 1901 // X%C to the equivalent of X-X/C*C. 1902 if (N1C && !N1C->isNullValue()) { 1903 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1904 AddToWorkList(Div.getNode()); 1905 SDValue OptimizedDiv = combine(Div.getNode()); 1906 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1907 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1908 OptimizedDiv, N1); 1909 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1910 AddToWorkList(Mul.getNode()); 1911 return Sub; 1912 } 1913 } 1914 1915 // undef % X -> 0 1916 if (N0.getOpcode() == ISD::UNDEF) 1917 return DAG.getConstant(0, VT); 1918 // X % undef -> undef 1919 if (N1.getOpcode() == ISD::UNDEF) 1920 return N1; 1921 1922 return SDValue(); 1923} 1924 1925SDValue DAGCombiner::visitMULHS(SDNode *N) { 1926 SDValue N0 = N->getOperand(0); 1927 SDValue N1 = N->getOperand(1); 1928 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1929 EVT VT = N->getValueType(0); 1930 DebugLoc DL = N->getDebugLoc(); 1931 1932 // fold (mulhs x, 0) -> 0 1933 if (N1C && N1C->isNullValue()) 1934 return N1; 1935 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1936 if (N1C && N1C->getAPIntValue() == 1) 1937 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1938 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1939 getShiftAmountTy())); 1940 // fold (mulhs x, undef) -> 0 1941 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1942 return DAG.getConstant(0, VT); 1943 1944 // If the type twice as wide is legal, transform the mulhs to a wider multiply 1945 // plus a shift. 1946 if (VT.isSimple() && !VT.isVector()) { 1947 MVT Simple = VT.getSimpleVT(); 1948 unsigned SimpleSize = Simple.getSizeInBits(); 1949 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 1950 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 1951 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 1952 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 1953 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 1954 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 1955 DAG.getConstant(SimpleSize, getShiftAmountTy())); 1956 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 1957 } 1958 } 1959 1960 return SDValue(); 1961} 1962 1963SDValue DAGCombiner::visitMULHU(SDNode *N) { 1964 SDValue N0 = N->getOperand(0); 1965 SDValue N1 = N->getOperand(1); 1966 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1967 EVT VT = N->getValueType(0); 1968 DebugLoc DL = N->getDebugLoc(); 1969 1970 // fold (mulhu x, 0) -> 0 1971 if (N1C && N1C->isNullValue()) 1972 return N1; 1973 // fold (mulhu x, 1) -> 0 1974 if (N1C && N1C->getAPIntValue() == 1) 1975 return DAG.getConstant(0, N0.getValueType()); 1976 // fold (mulhu x, undef) -> 0 1977 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1978 return DAG.getConstant(0, VT); 1979 1980 // If the type twice as wide is legal, transform the mulhu to a wider multiply 1981 // plus a shift. 1982 if (VT.isSimple() && !VT.isVector()) { 1983 MVT Simple = VT.getSimpleVT(); 1984 unsigned SimpleSize = Simple.getSizeInBits(); 1985 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 1986 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 1987 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 1988 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 1989 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 1990 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 1991 DAG.getConstant(SimpleSize, getShiftAmountTy())); 1992 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 1993 } 1994 } 1995 1996 return SDValue(); 1997} 1998 1999/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2000/// compute two values. LoOp and HiOp give the opcodes for the two computations 2001/// that are being performed. Return true if a simplification was made. 2002/// 2003SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2004 unsigned HiOp) { 2005 // If the high half is not needed, just compute the low half. 2006 bool HiExists = N->hasAnyUseOfValue(1); 2007 if (!HiExists && 2008 (!LegalOperations || 2009 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2010 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2011 N->op_begin(), N->getNumOperands()); 2012 return CombineTo(N, Res, Res); 2013 } 2014 2015 // If the low half is not needed, just compute the high half. 2016 bool LoExists = N->hasAnyUseOfValue(0); 2017 if (!LoExists && 2018 (!LegalOperations || 2019 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2020 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2021 N->op_begin(), N->getNumOperands()); 2022 return CombineTo(N, Res, Res); 2023 } 2024 2025 // If both halves are used, return as it is. 2026 if (LoExists && HiExists) 2027 return SDValue(); 2028 2029 // If the two computed results can be simplified separately, separate them. 2030 if (LoExists) { 2031 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2032 N->op_begin(), N->getNumOperands()); 2033 AddToWorkList(Lo.getNode()); 2034 SDValue LoOpt = combine(Lo.getNode()); 2035 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2036 (!LegalOperations || 2037 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2038 return CombineTo(N, LoOpt, LoOpt); 2039 } 2040 2041 if (HiExists) { 2042 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2043 N->op_begin(), N->getNumOperands()); 2044 AddToWorkList(Hi.getNode()); 2045 SDValue HiOpt = combine(Hi.getNode()); 2046 if (HiOpt.getNode() && HiOpt != Hi && 2047 (!LegalOperations || 2048 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2049 return CombineTo(N, HiOpt, HiOpt); 2050 } 2051 2052 return SDValue(); 2053} 2054 2055SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2056 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2057 if (Res.getNode()) return Res; 2058 2059 EVT VT = N->getValueType(0); 2060 DebugLoc DL = N->getDebugLoc(); 2061 2062 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2063 // plus a shift. 2064 if (VT.isSimple() && !VT.isVector()) { 2065 MVT Simple = VT.getSimpleVT(); 2066 unsigned SimpleSize = Simple.getSizeInBits(); 2067 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2068 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2069 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2070 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2071 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2072 // Compute the high part as N1. 2073 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2074 DAG.getConstant(SimpleSize, getShiftAmountTy())); 2075 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2076 // Compute the low part as N0. 2077 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2078 return CombineTo(N, Lo, Hi); 2079 } 2080 } 2081 2082 return SDValue(); 2083} 2084 2085SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2086 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2087 if (Res.getNode()) return Res; 2088 2089 EVT VT = N->getValueType(0); 2090 DebugLoc DL = N->getDebugLoc(); 2091 2092 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2093 // plus a shift. 2094 if (VT.isSimple() && !VT.isVector()) { 2095 MVT Simple = VT.getSimpleVT(); 2096 unsigned SimpleSize = Simple.getSizeInBits(); 2097 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2098 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2099 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2100 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2101 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2102 // Compute the high part as N1. 2103 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2104 DAG.getConstant(SimpleSize, getShiftAmountTy())); 2105 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2106 // Compute the low part as N0. 2107 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2108 return CombineTo(N, Lo, Hi); 2109 } 2110 } 2111 2112 return SDValue(); 2113} 2114 2115SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2116 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2117 if (Res.getNode()) return Res; 2118 2119 return SDValue(); 2120} 2121 2122SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2123 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2124 if (Res.getNode()) return Res; 2125 2126 return SDValue(); 2127} 2128 2129/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2130/// two operands of the same opcode, try to simplify it. 2131SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2132 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2133 EVT VT = N0.getValueType(); 2134 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2135 2136 // Bail early if none of these transforms apply. 2137 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2138 2139 // For each of OP in AND/OR/XOR: 2140 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2141 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2142 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2143 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2144 // 2145 // do not sink logical op inside of a vector extend, since it may combine 2146 // into a vsetcc. 2147 EVT Op0VT = N0.getOperand(0).getValueType(); 2148 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2149 N0.getOpcode() == ISD::SIGN_EXTEND || 2150 // Avoid infinite looping with PromoteIntBinOp. 2151 (N0.getOpcode() == ISD::ANY_EXTEND && 2152 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2153 (N0.getOpcode() == ISD::TRUNCATE && 2154 (!TLI.isZExtFree(VT, Op0VT) || 2155 !TLI.isTruncateFree(Op0VT, VT)) && 2156 TLI.isTypeLegal(Op0VT))) && 2157 !VT.isVector() && 2158 Op0VT == N1.getOperand(0).getValueType() && 2159 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2160 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2161 N0.getOperand(0).getValueType(), 2162 N0.getOperand(0), N1.getOperand(0)); 2163 AddToWorkList(ORNode.getNode()); 2164 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2165 } 2166 2167 // For each of OP in SHL/SRL/SRA/AND... 2168 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2169 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2170 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2171 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2172 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2173 N0.getOperand(1) == N1.getOperand(1)) { 2174 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2175 N0.getOperand(0).getValueType(), 2176 N0.getOperand(0), N1.getOperand(0)); 2177 AddToWorkList(ORNode.getNode()); 2178 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2179 ORNode, N0.getOperand(1)); 2180 } 2181 2182 return SDValue(); 2183} 2184 2185SDValue DAGCombiner::visitAND(SDNode *N) { 2186 SDValue N0 = N->getOperand(0); 2187 SDValue N1 = N->getOperand(1); 2188 SDValue LL, LR, RL, RR, CC0, CC1; 2189 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2190 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2191 EVT VT = N1.getValueType(); 2192 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2193 2194 // fold vector ops 2195 if (VT.isVector()) { 2196 SDValue FoldedVOp = SimplifyVBinOp(N); 2197 if (FoldedVOp.getNode()) return FoldedVOp; 2198 } 2199 2200 // fold (and x, undef) -> 0 2201 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2202 return DAG.getConstant(0, VT); 2203 // fold (and c1, c2) -> c1&c2 2204 if (N0C && N1C) 2205 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2206 // canonicalize constant to RHS 2207 if (N0C && !N1C) 2208 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2209 // fold (and x, -1) -> x 2210 if (N1C && N1C->isAllOnesValue()) 2211 return N0; 2212 // if (and x, c) is known to be zero, return 0 2213 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2214 APInt::getAllOnesValue(BitWidth))) 2215 return DAG.getConstant(0, VT); 2216 // reassociate and 2217 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2218 if (RAND.getNode() != 0) 2219 return RAND; 2220 // fold (and (or x, C), D) -> D if (C & D) == D 2221 if (N1C && N0.getOpcode() == ISD::OR) 2222 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2223 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2224 return N1; 2225 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2226 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2227 SDValue N0Op0 = N0.getOperand(0); 2228 APInt Mask = ~N1C->getAPIntValue(); 2229 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2230 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2231 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2232 N0.getValueType(), N0Op0); 2233 2234 // Replace uses of the AND with uses of the Zero extend node. 2235 CombineTo(N, Zext); 2236 2237 // We actually want to replace all uses of the any_extend with the 2238 // zero_extend, to avoid duplicating things. This will later cause this 2239 // AND to be folded. 2240 CombineTo(N0.getNode(), Zext); 2241 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2242 } 2243 } 2244 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2245 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2246 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2247 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2248 2249 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2250 LL.getValueType().isInteger()) { 2251 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2252 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2253 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2254 LR.getValueType(), LL, RL); 2255 AddToWorkList(ORNode.getNode()); 2256 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2257 } 2258 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2259 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2260 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2261 LR.getValueType(), LL, RL); 2262 AddToWorkList(ANDNode.getNode()); 2263 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2264 } 2265 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2266 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2267 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2268 LR.getValueType(), LL, RL); 2269 AddToWorkList(ORNode.getNode()); 2270 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2271 } 2272 } 2273 // canonicalize equivalent to ll == rl 2274 if (LL == RR && LR == RL) { 2275 Op1 = ISD::getSetCCSwappedOperands(Op1); 2276 std::swap(RL, RR); 2277 } 2278 if (LL == RL && LR == RR) { 2279 bool isInteger = LL.getValueType().isInteger(); 2280 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2281 if (Result != ISD::SETCC_INVALID && 2282 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2283 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2284 LL, LR, Result); 2285 } 2286 } 2287 2288 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2289 if (N0.getOpcode() == N1.getOpcode()) { 2290 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2291 if (Tmp.getNode()) return Tmp; 2292 } 2293 2294 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2295 // fold (and (sra)) -> (and (srl)) when possible. 2296 if (!VT.isVector() && 2297 SimplifyDemandedBits(SDValue(N, 0))) 2298 return SDValue(N, 0); 2299 2300 // fold (zext_inreg (extload x)) -> (zextload x) 2301 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2302 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2303 EVT MemVT = LN0->getMemoryVT(); 2304 // If we zero all the possible extended bits, then we can turn this into 2305 // a zextload if we are running before legalize or the operation is legal. 2306 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2307 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2308 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2309 ((!LegalOperations && !LN0->isVolatile()) || 2310 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2311 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(), 2312 LN0->getChain(), LN0->getBasePtr(), 2313 LN0->getPointerInfo(), MemVT, 2314 LN0->isVolatile(), LN0->isNonTemporal(), 2315 LN0->getAlignment()); 2316 AddToWorkList(N); 2317 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2318 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2319 } 2320 } 2321 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2322 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2323 N0.hasOneUse()) { 2324 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2325 EVT MemVT = LN0->getMemoryVT(); 2326 // If we zero all the possible extended bits, then we can turn this into 2327 // a zextload if we are running before legalize or the operation is legal. 2328 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2329 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2330 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2331 ((!LegalOperations && !LN0->isVolatile()) || 2332 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2333 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(), 2334 LN0->getChain(), 2335 LN0->getBasePtr(), LN0->getPointerInfo(), 2336 MemVT, 2337 LN0->isVolatile(), LN0->isNonTemporal(), 2338 LN0->getAlignment()); 2339 AddToWorkList(N); 2340 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2341 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2342 } 2343 } 2344 2345 // fold (and (load x), 255) -> (zextload x, i8) 2346 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2347 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2348 if (N1C && (N0.getOpcode() == ISD::LOAD || 2349 (N0.getOpcode() == ISD::ANY_EXTEND && 2350 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2351 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2352 LoadSDNode *LN0 = HasAnyExt 2353 ? cast<LoadSDNode>(N0.getOperand(0)) 2354 : cast<LoadSDNode>(N0); 2355 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2356 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2357 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2358 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2359 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2360 EVT LoadedVT = LN0->getMemoryVT(); 2361 2362 if (ExtVT == LoadedVT && 2363 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2364 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2365 2366 SDValue NewLoad = 2367 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(), 2368 LN0->getChain(), LN0->getBasePtr(), 2369 LN0->getPointerInfo(), 2370 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2371 LN0->getAlignment()); 2372 AddToWorkList(N); 2373 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2374 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2375 } 2376 2377 // Do not change the width of a volatile load. 2378 // Do not generate loads of non-round integer types since these can 2379 // be expensive (and would be wrong if the type is not byte sized). 2380 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2381 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2382 EVT PtrType = LN0->getOperand(1).getValueType(); 2383 2384 unsigned Alignment = LN0->getAlignment(); 2385 SDValue NewPtr = LN0->getBasePtr(); 2386 2387 // For big endian targets, we need to add an offset to the pointer 2388 // to load the correct bytes. For little endian systems, we merely 2389 // need to read fewer bytes from the same pointer. 2390 if (TLI.isBigEndian()) { 2391 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2392 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2393 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2394 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2395 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2396 Alignment = MinAlign(Alignment, PtrOff); 2397 } 2398 2399 AddToWorkList(NewPtr.getNode()); 2400 2401 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2402 SDValue Load = 2403 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(), 2404 LN0->getChain(), NewPtr, 2405 LN0->getPointerInfo(), 2406 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2407 Alignment); 2408 AddToWorkList(N); 2409 CombineTo(LN0, Load, Load.getValue(1)); 2410 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2411 } 2412 } 2413 } 2414 } 2415 2416 return SDValue(); 2417} 2418 2419SDValue DAGCombiner::visitOR(SDNode *N) { 2420 SDValue N0 = N->getOperand(0); 2421 SDValue N1 = N->getOperand(1); 2422 SDValue LL, LR, RL, RR, CC0, CC1; 2423 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2424 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2425 EVT VT = N1.getValueType(); 2426 2427 // fold vector ops 2428 if (VT.isVector()) { 2429 SDValue FoldedVOp = SimplifyVBinOp(N); 2430 if (FoldedVOp.getNode()) return FoldedVOp; 2431 } 2432 2433 // fold (or x, undef) -> -1 2434 if (!LegalOperations && 2435 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2436 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2437 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2438 } 2439 // fold (or c1, c2) -> c1|c2 2440 if (N0C && N1C) 2441 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2442 // canonicalize constant to RHS 2443 if (N0C && !N1C) 2444 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2445 // fold (or x, 0) -> x 2446 if (N1C && N1C->isNullValue()) 2447 return N0; 2448 // fold (or x, -1) -> -1 2449 if (N1C && N1C->isAllOnesValue()) 2450 return N1; 2451 // fold (or x, c) -> c iff (x & ~c) == 0 2452 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2453 return N1; 2454 // reassociate or 2455 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2456 if (ROR.getNode() != 0) 2457 return ROR; 2458 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2459 // iff (c1 & c2) == 0. 2460 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2461 isa<ConstantSDNode>(N0.getOperand(1))) { 2462 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2463 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2464 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2465 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2466 N0.getOperand(0), N1), 2467 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2468 } 2469 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2470 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2471 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2472 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2473 2474 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2475 LL.getValueType().isInteger()) { 2476 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2477 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2478 if (cast<ConstantSDNode>(LR)->isNullValue() && 2479 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2480 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2481 LR.getValueType(), LL, RL); 2482 AddToWorkList(ORNode.getNode()); 2483 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2484 } 2485 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2486 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2487 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2488 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2489 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2490 LR.getValueType(), LL, RL); 2491 AddToWorkList(ANDNode.getNode()); 2492 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2493 } 2494 } 2495 // canonicalize equivalent to ll == rl 2496 if (LL == RR && LR == RL) { 2497 Op1 = ISD::getSetCCSwappedOperands(Op1); 2498 std::swap(RL, RR); 2499 } 2500 if (LL == RL && LR == RR) { 2501 bool isInteger = LL.getValueType().isInteger(); 2502 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2503 if (Result != ISD::SETCC_INVALID && 2504 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2505 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2506 LL, LR, Result); 2507 } 2508 } 2509 2510 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2511 if (N0.getOpcode() == N1.getOpcode()) { 2512 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2513 if (Tmp.getNode()) return Tmp; 2514 } 2515 2516 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2517 if (N0.getOpcode() == ISD::AND && 2518 N1.getOpcode() == ISD::AND && 2519 N0.getOperand(1).getOpcode() == ISD::Constant && 2520 N1.getOperand(1).getOpcode() == ISD::Constant && 2521 // Don't increase # computations. 2522 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2523 // We can only do this xform if we know that bits from X that are set in C2 2524 // but not in C1 are already zero. Likewise for Y. 2525 const APInt &LHSMask = 2526 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2527 const APInt &RHSMask = 2528 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2529 2530 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2531 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2532 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2533 N0.getOperand(0), N1.getOperand(0)); 2534 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2535 DAG.getConstant(LHSMask | RHSMask, VT)); 2536 } 2537 } 2538 2539 // See if this is some rotate idiom. 2540 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2541 return SDValue(Rot, 0); 2542 2543 // Simplify the operands using demanded-bits information. 2544 if (!VT.isVector() && 2545 SimplifyDemandedBits(SDValue(N, 0))) 2546 return SDValue(N, 0); 2547 2548 return SDValue(); 2549} 2550 2551/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2552static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2553 if (Op.getOpcode() == ISD::AND) { 2554 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2555 Mask = Op.getOperand(1); 2556 Op = Op.getOperand(0); 2557 } else { 2558 return false; 2559 } 2560 } 2561 2562 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2563 Shift = Op; 2564 return true; 2565 } 2566 2567 return false; 2568} 2569 2570// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2571// idioms for rotate, and if the target supports rotation instructions, generate 2572// a rot[lr]. 2573SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2574 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2575 EVT VT = LHS.getValueType(); 2576 if (!TLI.isTypeLegal(VT)) return 0; 2577 2578 // The target must have at least one rotate flavor. 2579 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2580 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2581 if (!HasROTL && !HasROTR) return 0; 2582 2583 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2584 SDValue LHSShift; // The shift. 2585 SDValue LHSMask; // AND value if any. 2586 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2587 return 0; // Not part of a rotate. 2588 2589 SDValue RHSShift; // The shift. 2590 SDValue RHSMask; // AND value if any. 2591 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2592 return 0; // Not part of a rotate. 2593 2594 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2595 return 0; // Not shifting the same value. 2596 2597 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2598 return 0; // Shifts must disagree. 2599 2600 // Canonicalize shl to left side in a shl/srl pair. 2601 if (RHSShift.getOpcode() == ISD::SHL) { 2602 std::swap(LHS, RHS); 2603 std::swap(LHSShift, RHSShift); 2604 std::swap(LHSMask , RHSMask ); 2605 } 2606 2607 unsigned OpSizeInBits = VT.getSizeInBits(); 2608 SDValue LHSShiftArg = LHSShift.getOperand(0); 2609 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2610 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2611 2612 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2613 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2614 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2615 RHSShiftAmt.getOpcode() == ISD::Constant) { 2616 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2617 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2618 if ((LShVal + RShVal) != OpSizeInBits) 2619 return 0; 2620 2621 SDValue Rot; 2622 if (HasROTL) 2623 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2624 else 2625 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2626 2627 // If there is an AND of either shifted operand, apply it to the result. 2628 if (LHSMask.getNode() || RHSMask.getNode()) { 2629 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2630 2631 if (LHSMask.getNode()) { 2632 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2633 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2634 } 2635 if (RHSMask.getNode()) { 2636 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2637 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2638 } 2639 2640 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2641 } 2642 2643 return Rot.getNode(); 2644 } 2645 2646 // If there is a mask here, and we have a variable shift, we can't be sure 2647 // that we're masking out the right stuff. 2648 if (LHSMask.getNode() || RHSMask.getNode()) 2649 return 0; 2650 2651 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2652 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2653 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2654 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2655 if (ConstantSDNode *SUBC = 2656 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2657 if (SUBC->getAPIntValue() == OpSizeInBits) { 2658 if (HasROTL) 2659 return DAG.getNode(ISD::ROTL, DL, VT, 2660 LHSShiftArg, LHSShiftAmt).getNode(); 2661 else 2662 return DAG.getNode(ISD::ROTR, DL, VT, 2663 LHSShiftArg, RHSShiftAmt).getNode(); 2664 } 2665 } 2666 } 2667 2668 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2669 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2670 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2671 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2672 if (ConstantSDNode *SUBC = 2673 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2674 if (SUBC->getAPIntValue() == OpSizeInBits) { 2675 if (HasROTR) 2676 return DAG.getNode(ISD::ROTR, DL, VT, 2677 LHSShiftArg, RHSShiftAmt).getNode(); 2678 else 2679 return DAG.getNode(ISD::ROTL, DL, VT, 2680 LHSShiftArg, LHSShiftAmt).getNode(); 2681 } 2682 } 2683 } 2684 2685 // Look for sign/zext/any-extended or truncate cases: 2686 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2687 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2688 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2689 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2690 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2691 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2692 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2693 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2694 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2695 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2696 if (RExtOp0.getOpcode() == ISD::SUB && 2697 RExtOp0.getOperand(1) == LExtOp0) { 2698 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2699 // (rotl x, y) 2700 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2701 // (rotr x, (sub 32, y)) 2702 if (ConstantSDNode *SUBC = 2703 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2704 if (SUBC->getAPIntValue() == OpSizeInBits) { 2705 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2706 LHSShiftArg, 2707 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2708 } 2709 } 2710 } else if (LExtOp0.getOpcode() == ISD::SUB && 2711 RExtOp0 == LExtOp0.getOperand(1)) { 2712 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2713 // (rotr x, y) 2714 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2715 // (rotl x, (sub 32, y)) 2716 if (ConstantSDNode *SUBC = 2717 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2718 if (SUBC->getAPIntValue() == OpSizeInBits) { 2719 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2720 LHSShiftArg, 2721 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2722 } 2723 } 2724 } 2725 } 2726 2727 return 0; 2728} 2729 2730SDValue DAGCombiner::visitXOR(SDNode *N) { 2731 SDValue N0 = N->getOperand(0); 2732 SDValue N1 = N->getOperand(1); 2733 SDValue LHS, RHS, CC; 2734 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2735 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2736 EVT VT = N0.getValueType(); 2737 2738 // fold vector ops 2739 if (VT.isVector()) { 2740 SDValue FoldedVOp = SimplifyVBinOp(N); 2741 if (FoldedVOp.getNode()) return FoldedVOp; 2742 } 2743 2744 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2745 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2746 return DAG.getConstant(0, VT); 2747 // fold (xor x, undef) -> undef 2748 if (N0.getOpcode() == ISD::UNDEF) 2749 return N0; 2750 if (N1.getOpcode() == ISD::UNDEF) 2751 return N1; 2752 // fold (xor c1, c2) -> c1^c2 2753 if (N0C && N1C) 2754 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2755 // canonicalize constant to RHS 2756 if (N0C && !N1C) 2757 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2758 // fold (xor x, 0) -> x 2759 if (N1C && N1C->isNullValue()) 2760 return N0; 2761 // reassociate xor 2762 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2763 if (RXOR.getNode() != 0) 2764 return RXOR; 2765 2766 // fold !(x cc y) -> (x !cc y) 2767 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2768 bool isInt = LHS.getValueType().isInteger(); 2769 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2770 isInt); 2771 2772 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2773 switch (N0.getOpcode()) { 2774 default: 2775 llvm_unreachable("Unhandled SetCC Equivalent!"); 2776 case ISD::SETCC: 2777 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2778 case ISD::SELECT_CC: 2779 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2780 N0.getOperand(3), NotCC); 2781 } 2782 } 2783 } 2784 2785 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2786 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2787 N0.getNode()->hasOneUse() && 2788 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2789 SDValue V = N0.getOperand(0); 2790 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2791 DAG.getConstant(1, V.getValueType())); 2792 AddToWorkList(V.getNode()); 2793 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2794 } 2795 2796 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2797 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2798 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2799 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2800 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2801 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2802 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2803 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2804 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2805 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2806 } 2807 } 2808 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2809 if (N1C && N1C->isAllOnesValue() && 2810 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2811 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2812 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2813 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2814 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2815 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2816 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2817 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2818 } 2819 } 2820 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2821 if (N1C && N0.getOpcode() == ISD::XOR) { 2822 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2823 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2824 if (N00C) 2825 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2826 DAG.getConstant(N1C->getAPIntValue() ^ 2827 N00C->getAPIntValue(), VT)); 2828 if (N01C) 2829 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2830 DAG.getConstant(N1C->getAPIntValue() ^ 2831 N01C->getAPIntValue(), VT)); 2832 } 2833 // fold (xor x, x) -> 0 2834 if (N0 == N1) { 2835 if (!VT.isVector()) { 2836 return DAG.getConstant(0, VT); 2837 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2838 // Produce a vector of zeros. 2839 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2840 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2841 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2842 &Ops[0], Ops.size()); 2843 } 2844 } 2845 2846 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2847 if (N0.getOpcode() == N1.getOpcode()) { 2848 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2849 if (Tmp.getNode()) return Tmp; 2850 } 2851 2852 // Simplify the expression using non-local knowledge. 2853 if (!VT.isVector() && 2854 SimplifyDemandedBits(SDValue(N, 0))) 2855 return SDValue(N, 0); 2856 2857 return SDValue(); 2858} 2859 2860/// visitShiftByConstant - Handle transforms common to the three shifts, when 2861/// the shift amount is a constant. 2862SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2863 SDNode *LHS = N->getOperand(0).getNode(); 2864 if (!LHS->hasOneUse()) return SDValue(); 2865 2866 // We want to pull some binops through shifts, so that we have (and (shift)) 2867 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2868 // thing happens with address calculations, so it's important to canonicalize 2869 // it. 2870 bool HighBitSet = false; // Can we transform this if the high bit is set? 2871 2872 switch (LHS->getOpcode()) { 2873 default: return SDValue(); 2874 case ISD::OR: 2875 case ISD::XOR: 2876 HighBitSet = false; // We can only transform sra if the high bit is clear. 2877 break; 2878 case ISD::AND: 2879 HighBitSet = true; // We can only transform sra if the high bit is set. 2880 break; 2881 case ISD::ADD: 2882 if (N->getOpcode() != ISD::SHL) 2883 return SDValue(); // only shl(add) not sr[al](add). 2884 HighBitSet = false; // We can only transform sra if the high bit is clear. 2885 break; 2886 } 2887 2888 // We require the RHS of the binop to be a constant as well. 2889 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2890 if (!BinOpCst) return SDValue(); 2891 2892 // FIXME: disable this unless the input to the binop is a shift by a constant. 2893 // If it is not a shift, it pessimizes some common cases like: 2894 // 2895 // void foo(int *X, int i) { X[i & 1235] = 1; } 2896 // int bar(int *X, int i) { return X[i & 255]; } 2897 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2898 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2899 BinOpLHSVal->getOpcode() != ISD::SRA && 2900 BinOpLHSVal->getOpcode() != ISD::SRL) || 2901 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2902 return SDValue(); 2903 2904 EVT VT = N->getValueType(0); 2905 2906 // If this is a signed shift right, and the high bit is modified by the 2907 // logical operation, do not perform the transformation. The highBitSet 2908 // boolean indicates the value of the high bit of the constant which would 2909 // cause it to be modified for this operation. 2910 if (N->getOpcode() == ISD::SRA) { 2911 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2912 if (BinOpRHSSignSet != HighBitSet) 2913 return SDValue(); 2914 } 2915 2916 // Fold the constants, shifting the binop RHS by the shift amount. 2917 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2918 N->getValueType(0), 2919 LHS->getOperand(1), N->getOperand(1)); 2920 2921 // Create the new shift. 2922 SDValue NewShift = DAG.getNode(N->getOpcode(), 2923 LHS->getOperand(0).getDebugLoc(), 2924 VT, LHS->getOperand(0), N->getOperand(1)); 2925 2926 // Create the new binop. 2927 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2928} 2929 2930SDValue DAGCombiner::visitSHL(SDNode *N) { 2931 SDValue N0 = N->getOperand(0); 2932 SDValue N1 = N->getOperand(1); 2933 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2934 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2935 EVT VT = N0.getValueType(); 2936 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2937 2938 // fold (shl c1, c2) -> c1<<c2 2939 if (N0C && N1C) 2940 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2941 // fold (shl 0, x) -> 0 2942 if (N0C && N0C->isNullValue()) 2943 return N0; 2944 // fold (shl x, c >= size(x)) -> undef 2945 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2946 return DAG.getUNDEF(VT); 2947 // fold (shl x, 0) -> x 2948 if (N1C && N1C->isNullValue()) 2949 return N0; 2950 // if (shl x, c) is known to be zero, return 0 2951 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2952 APInt::getAllOnesValue(OpSizeInBits))) 2953 return DAG.getConstant(0, VT); 2954 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2955 if (N1.getOpcode() == ISD::TRUNCATE && 2956 N1.getOperand(0).getOpcode() == ISD::AND && 2957 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2958 SDValue N101 = N1.getOperand(0).getOperand(1); 2959 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2960 EVT TruncVT = N1.getValueType(); 2961 SDValue N100 = N1.getOperand(0).getOperand(0); 2962 APInt TruncC = N101C->getAPIntValue(); 2963 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 2964 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2965 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2966 DAG.getNode(ISD::TRUNCATE, 2967 N->getDebugLoc(), 2968 TruncVT, N100), 2969 DAG.getConstant(TruncC, TruncVT))); 2970 } 2971 } 2972 2973 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2974 return SDValue(N, 0); 2975 2976 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2977 if (N1C && N0.getOpcode() == ISD::SHL && 2978 N0.getOperand(1).getOpcode() == ISD::Constant) { 2979 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2980 uint64_t c2 = N1C->getZExtValue(); 2981 if (c1 + c2 >= OpSizeInBits) 2982 return DAG.getConstant(0, VT); 2983 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2984 DAG.getConstant(c1 + c2, N1.getValueType())); 2985 } 2986 2987 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 2988 // For this to be valid, the second form must not preserve any of the bits 2989 // that are shifted out by the inner shift in the first form. This means 2990 // the outer shift size must be >= the number of bits added by the ext. 2991 // As a corollary, we don't care what kind of ext it is. 2992 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 2993 N0.getOpcode() == ISD::ANY_EXTEND || 2994 N0.getOpcode() == ISD::SIGN_EXTEND) && 2995 N0.getOperand(0).getOpcode() == ISD::SHL && 2996 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 2997 uint64_t c1 = 2998 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 2999 uint64_t c2 = N1C->getZExtValue(); 3000 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3001 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3002 if (c2 >= OpSizeInBits - InnerShiftSize) { 3003 if (c1 + c2 >= OpSizeInBits) 3004 return DAG.getConstant(0, VT); 3005 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3006 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3007 N0.getOperand(0)->getOperand(0)), 3008 DAG.getConstant(c1 + c2, N1.getValueType())); 3009 } 3010 } 3011 3012 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 3013 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 3014 if (N1C && N0.getOpcode() == ISD::SRL && 3015 N0.getOperand(1).getOpcode() == ISD::Constant) { 3016 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3017 if (c1 < VT.getSizeInBits()) { 3018 uint64_t c2 = N1C->getZExtValue(); 3019 SDValue HiBitsMask = 3020 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3021 VT.getSizeInBits() - c1), 3022 VT); 3023 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 3024 N0.getOperand(0), 3025 HiBitsMask); 3026 if (c2 > c1) 3027 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 3028 DAG.getConstant(c2-c1, N1.getValueType())); 3029 else 3030 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 3031 DAG.getConstant(c1-c2, N1.getValueType())); 3032 } 3033 } 3034 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3035 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3036 SDValue HiBitsMask = 3037 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3038 VT.getSizeInBits() - 3039 N1C->getZExtValue()), 3040 VT); 3041 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3042 HiBitsMask); 3043 } 3044 3045 if (N1C) { 3046 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3047 if (NewSHL.getNode()) 3048 return NewSHL; 3049 } 3050 3051 return SDValue(); 3052} 3053 3054SDValue DAGCombiner::visitSRA(SDNode *N) { 3055 SDValue N0 = N->getOperand(0); 3056 SDValue N1 = N->getOperand(1); 3057 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3058 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3059 EVT VT = N0.getValueType(); 3060 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3061 3062 // fold (sra c1, c2) -> (sra c1, c2) 3063 if (N0C && N1C) 3064 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3065 // fold (sra 0, x) -> 0 3066 if (N0C && N0C->isNullValue()) 3067 return N0; 3068 // fold (sra -1, x) -> -1 3069 if (N0C && N0C->isAllOnesValue()) 3070 return N0; 3071 // fold (sra x, (setge c, size(x))) -> undef 3072 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3073 return DAG.getUNDEF(VT); 3074 // fold (sra x, 0) -> x 3075 if (N1C && N1C->isNullValue()) 3076 return N0; 3077 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3078 // sext_inreg. 3079 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3080 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3081 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3082 if (VT.isVector()) 3083 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3084 ExtVT, VT.getVectorNumElements()); 3085 if ((!LegalOperations || 3086 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3087 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3088 N0.getOperand(0), DAG.getValueType(ExtVT)); 3089 } 3090 3091 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3092 if (N1C && N0.getOpcode() == ISD::SRA) { 3093 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3094 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3095 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3096 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3097 DAG.getConstant(Sum, N1C->getValueType(0))); 3098 } 3099 } 3100 3101 // fold (sra (shl X, m), (sub result_size, n)) 3102 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3103 // result_size - n != m. 3104 // If truncate is free for the target sext(shl) is likely to result in better 3105 // code. 3106 if (N0.getOpcode() == ISD::SHL) { 3107 // Get the two constanst of the shifts, CN0 = m, CN = n. 3108 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3109 if (N01C && N1C) { 3110 // Determine what the truncate's result bitsize and type would be. 3111 EVT TruncVT = 3112 EVT::getIntegerVT(*DAG.getContext(), 3113 OpSizeInBits - N1C->getZExtValue()); 3114 // Determine the residual right-shift amount. 3115 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3116 3117 // If the shift is not a no-op (in which case this should be just a sign 3118 // extend already), the truncated to type is legal, sign_extend is legal 3119 // on that type, and the truncate to that type is both legal and free, 3120 // perform the transform. 3121 if ((ShiftAmt > 0) && 3122 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3123 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3124 TLI.isTruncateFree(VT, TruncVT)) { 3125 3126 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 3127 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3128 N0.getOperand(0), Amt); 3129 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3130 Shift); 3131 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3132 N->getValueType(0), Trunc); 3133 } 3134 } 3135 } 3136 3137 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3138 if (N1.getOpcode() == ISD::TRUNCATE && 3139 N1.getOperand(0).getOpcode() == ISD::AND && 3140 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3141 SDValue N101 = N1.getOperand(0).getOperand(1); 3142 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3143 EVT TruncVT = N1.getValueType(); 3144 SDValue N100 = N1.getOperand(0).getOperand(0); 3145 APInt TruncC = N101C->getAPIntValue(); 3146 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3147 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3148 DAG.getNode(ISD::AND, N->getDebugLoc(), 3149 TruncVT, 3150 DAG.getNode(ISD::TRUNCATE, 3151 N->getDebugLoc(), 3152 TruncVT, N100), 3153 DAG.getConstant(TruncC, TruncVT))); 3154 } 3155 } 3156 3157 // Simplify, based on bits shifted out of the LHS. 3158 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3159 return SDValue(N, 0); 3160 3161 3162 // If the sign bit is known to be zero, switch this to a SRL. 3163 if (DAG.SignBitIsZero(N0)) 3164 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3165 3166 if (N1C) { 3167 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3168 if (NewSRA.getNode()) 3169 return NewSRA; 3170 } 3171 3172 return SDValue(); 3173} 3174 3175SDValue DAGCombiner::visitSRL(SDNode *N) { 3176 SDValue N0 = N->getOperand(0); 3177 SDValue N1 = N->getOperand(1); 3178 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3179 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3180 EVT VT = N0.getValueType(); 3181 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3182 3183 // fold (srl c1, c2) -> c1 >>u c2 3184 if (N0C && N1C) 3185 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3186 // fold (srl 0, x) -> 0 3187 if (N0C && N0C->isNullValue()) 3188 return N0; 3189 // fold (srl x, c >= size(x)) -> undef 3190 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3191 return DAG.getUNDEF(VT); 3192 // fold (srl x, 0) -> x 3193 if (N1C && N1C->isNullValue()) 3194 return N0; 3195 // if (srl x, c) is known to be zero, return 0 3196 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3197 APInt::getAllOnesValue(OpSizeInBits))) 3198 return DAG.getConstant(0, VT); 3199 3200 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3201 if (N1C && N0.getOpcode() == ISD::SRL && 3202 N0.getOperand(1).getOpcode() == ISD::Constant) { 3203 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3204 uint64_t c2 = N1C->getZExtValue(); 3205 if (c1 + c2 >= OpSizeInBits) 3206 return DAG.getConstant(0, VT); 3207 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3208 DAG.getConstant(c1 + c2, N1.getValueType())); 3209 } 3210 3211 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3212 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3213 N0.getOperand(0).getOpcode() == ISD::SRL && 3214 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3215 uint64_t c1 = 3216 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3217 uint64_t c2 = N1C->getZExtValue(); 3218 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3219 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3220 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3221 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3222 if (c1 + OpSizeInBits == InnerShiftSize) { 3223 if (c1 + c2 >= InnerShiftSize) 3224 return DAG.getConstant(0, VT); 3225 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3226 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3227 N0.getOperand(0)->getOperand(0), 3228 DAG.getConstant(c1 + c2, ShiftCountVT))); 3229 } 3230 } 3231 3232 // fold (srl (shl x, c), c) -> (and x, cst2) 3233 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3234 N0.getValueSizeInBits() <= 64) { 3235 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3236 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3237 DAG.getConstant(~0ULL >> ShAmt, VT)); 3238 } 3239 3240 3241 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3242 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3243 // Shifting in all undef bits? 3244 EVT SmallVT = N0.getOperand(0).getValueType(); 3245 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3246 return DAG.getUNDEF(VT); 3247 3248 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3249 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3250 N0.getOperand(0), N1); 3251 AddToWorkList(SmallShift.getNode()); 3252 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3253 } 3254 } 3255 3256 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3257 // bit, which is unmodified by sra. 3258 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3259 if (N0.getOpcode() == ISD::SRA) 3260 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3261 } 3262 3263 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3264 if (N1C && N0.getOpcode() == ISD::CTLZ && 3265 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3266 APInt KnownZero, KnownOne; 3267 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3268 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3269 3270 // If any of the input bits are KnownOne, then the input couldn't be all 3271 // zeros, thus the result of the srl will always be zero. 3272 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3273 3274 // If all of the bits input the to ctlz node are known to be zero, then 3275 // the result of the ctlz is "32" and the result of the shift is one. 3276 APInt UnknownBits = ~KnownZero & Mask; 3277 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3278 3279 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3280 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3281 // Okay, we know that only that the single bit specified by UnknownBits 3282 // could be set on input to the CTLZ node. If this bit is set, the SRL 3283 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3284 // to an SRL/XOR pair, which is likely to simplify more. 3285 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3286 SDValue Op = N0.getOperand(0); 3287 3288 if (ShAmt) { 3289 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3290 DAG.getConstant(ShAmt, getShiftAmountTy())); 3291 AddToWorkList(Op.getNode()); 3292 } 3293 3294 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3295 Op, DAG.getConstant(1, VT)); 3296 } 3297 } 3298 3299 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3300 if (N1.getOpcode() == ISD::TRUNCATE && 3301 N1.getOperand(0).getOpcode() == ISD::AND && 3302 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3303 SDValue N101 = N1.getOperand(0).getOperand(1); 3304 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3305 EVT TruncVT = N1.getValueType(); 3306 SDValue N100 = N1.getOperand(0).getOperand(0); 3307 APInt TruncC = N101C->getAPIntValue(); 3308 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3309 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3310 DAG.getNode(ISD::AND, N->getDebugLoc(), 3311 TruncVT, 3312 DAG.getNode(ISD::TRUNCATE, 3313 N->getDebugLoc(), 3314 TruncVT, N100), 3315 DAG.getConstant(TruncC, TruncVT))); 3316 } 3317 } 3318 3319 // fold operands of srl based on knowledge that the low bits are not 3320 // demanded. 3321 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3322 return SDValue(N, 0); 3323 3324 if (N1C) { 3325 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3326 if (NewSRL.getNode()) 3327 return NewSRL; 3328 } 3329 3330 // Attempt to convert a srl of a load into a narrower zero-extending load. 3331 SDValue NarrowLoad = ReduceLoadWidth(N); 3332 if (NarrowLoad.getNode()) 3333 return NarrowLoad; 3334 3335 // Here is a common situation. We want to optimize: 3336 // 3337 // %a = ... 3338 // %b = and i32 %a, 2 3339 // %c = srl i32 %b, 1 3340 // brcond i32 %c ... 3341 // 3342 // into 3343 // 3344 // %a = ... 3345 // %b = and %a, 2 3346 // %c = setcc eq %b, 0 3347 // brcond %c ... 3348 // 3349 // However when after the source operand of SRL is optimized into AND, the SRL 3350 // itself may not be optimized further. Look for it and add the BRCOND into 3351 // the worklist. 3352 if (N->hasOneUse()) { 3353 SDNode *Use = *N->use_begin(); 3354 if (Use->getOpcode() == ISD::BRCOND) 3355 AddToWorkList(Use); 3356 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3357 // Also look pass the truncate. 3358 Use = *Use->use_begin(); 3359 if (Use->getOpcode() == ISD::BRCOND) 3360 AddToWorkList(Use); 3361 } 3362 } 3363 3364 return SDValue(); 3365} 3366 3367SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3368 SDValue N0 = N->getOperand(0); 3369 EVT VT = N->getValueType(0); 3370 3371 // fold (ctlz c1) -> c2 3372 if (isa<ConstantSDNode>(N0)) 3373 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3374 return SDValue(); 3375} 3376 3377SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3378 SDValue N0 = N->getOperand(0); 3379 EVT VT = N->getValueType(0); 3380 3381 // fold (cttz c1) -> c2 3382 if (isa<ConstantSDNode>(N0)) 3383 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3384 return SDValue(); 3385} 3386 3387SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3388 SDValue N0 = N->getOperand(0); 3389 EVT VT = N->getValueType(0); 3390 3391 // fold (ctpop c1) -> c2 3392 if (isa<ConstantSDNode>(N0)) 3393 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3394 return SDValue(); 3395} 3396 3397SDValue DAGCombiner::visitSELECT(SDNode *N) { 3398 SDValue N0 = N->getOperand(0); 3399 SDValue N1 = N->getOperand(1); 3400 SDValue N2 = N->getOperand(2); 3401 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3402 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3403 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3404 EVT VT = N->getValueType(0); 3405 EVT VT0 = N0.getValueType(); 3406 3407 // fold (select C, X, X) -> X 3408 if (N1 == N2) 3409 return N1; 3410 // fold (select true, X, Y) -> X 3411 if (N0C && !N0C->isNullValue()) 3412 return N1; 3413 // fold (select false, X, Y) -> Y 3414 if (N0C && N0C->isNullValue()) 3415 return N2; 3416 // fold (select C, 1, X) -> (or C, X) 3417 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3418 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3419 // fold (select C, 0, 1) -> (xor C, 1) 3420 if (VT.isInteger() && 3421 (VT0 == MVT::i1 || 3422 (VT0.isInteger() && 3423 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3424 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3425 SDValue XORNode; 3426 if (VT == VT0) 3427 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3428 N0, DAG.getConstant(1, VT0)); 3429 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3430 N0, DAG.getConstant(1, VT0)); 3431 AddToWorkList(XORNode.getNode()); 3432 if (VT.bitsGT(VT0)) 3433 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3434 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3435 } 3436 // fold (select C, 0, X) -> (and (not C), X) 3437 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3438 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3439 AddToWorkList(NOTNode.getNode()); 3440 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3441 } 3442 // fold (select C, X, 1) -> (or (not C), X) 3443 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3444 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3445 AddToWorkList(NOTNode.getNode()); 3446 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3447 } 3448 // fold (select C, X, 0) -> (and C, X) 3449 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3450 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3451 // fold (select X, X, Y) -> (or X, Y) 3452 // fold (select X, 1, Y) -> (or X, Y) 3453 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3454 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3455 // fold (select X, Y, X) -> (and X, Y) 3456 // fold (select X, Y, 0) -> (and X, Y) 3457 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3458 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3459 3460 // If we can fold this based on the true/false value, do so. 3461 if (SimplifySelectOps(N, N1, N2)) 3462 return SDValue(N, 0); // Don't revisit N. 3463 3464 // fold selects based on a setcc into other things, such as min/max/abs 3465 if (N0.getOpcode() == ISD::SETCC) { 3466 // FIXME: 3467 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3468 // having to say they don't support SELECT_CC on every type the DAG knows 3469 // about, since there is no way to mark an opcode illegal at all value types 3470 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3471 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3472 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3473 N0.getOperand(0), N0.getOperand(1), 3474 N1, N2, N0.getOperand(2)); 3475 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3476 } 3477 3478 return SDValue(); 3479} 3480 3481SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3482 SDValue N0 = N->getOperand(0); 3483 SDValue N1 = N->getOperand(1); 3484 SDValue N2 = N->getOperand(2); 3485 SDValue N3 = N->getOperand(3); 3486 SDValue N4 = N->getOperand(4); 3487 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3488 3489 // fold select_cc lhs, rhs, x, x, cc -> x 3490 if (N2 == N3) 3491 return N2; 3492 3493 // Determine if the condition we're dealing with is constant 3494 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3495 N0, N1, CC, N->getDebugLoc(), false); 3496 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3497 3498 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3499 if (!SCCC->isNullValue()) 3500 return N2; // cond always true -> true val 3501 else 3502 return N3; // cond always false -> false val 3503 } 3504 3505 // Fold to a simpler select_cc 3506 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3507 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3508 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3509 SCC.getOperand(2)); 3510 3511 // If we can fold this based on the true/false value, do so. 3512 if (SimplifySelectOps(N, N2, N3)) 3513 return SDValue(N, 0); // Don't revisit N. 3514 3515 // fold select_cc into other things, such as min/max/abs 3516 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3517} 3518 3519SDValue DAGCombiner::visitSETCC(SDNode *N) { 3520 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3521 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3522 N->getDebugLoc()); 3523} 3524 3525// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3526// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3527// transformation. Returns true if extension are possible and the above 3528// mentioned transformation is profitable. 3529static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3530 unsigned ExtOpc, 3531 SmallVector<SDNode*, 4> &ExtendNodes, 3532 const TargetLowering &TLI) { 3533 bool HasCopyToRegUses = false; 3534 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3535 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3536 UE = N0.getNode()->use_end(); 3537 UI != UE; ++UI) { 3538 SDNode *User = *UI; 3539 if (User == N) 3540 continue; 3541 if (UI.getUse().getResNo() != N0.getResNo()) 3542 continue; 3543 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3544 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3545 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3546 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3547 // Sign bits will be lost after a zext. 3548 return false; 3549 bool Add = false; 3550 for (unsigned i = 0; i != 2; ++i) { 3551 SDValue UseOp = User->getOperand(i); 3552 if (UseOp == N0) 3553 continue; 3554 if (!isa<ConstantSDNode>(UseOp)) 3555 return false; 3556 Add = true; 3557 } 3558 if (Add) 3559 ExtendNodes.push_back(User); 3560 continue; 3561 } 3562 // If truncates aren't free and there are users we can't 3563 // extend, it isn't worthwhile. 3564 if (!isTruncFree) 3565 return false; 3566 // Remember if this value is live-out. 3567 if (User->getOpcode() == ISD::CopyToReg) 3568 HasCopyToRegUses = true; 3569 } 3570 3571 if (HasCopyToRegUses) { 3572 bool BothLiveOut = false; 3573 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3574 UI != UE; ++UI) { 3575 SDUse &Use = UI.getUse(); 3576 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3577 BothLiveOut = true; 3578 break; 3579 } 3580 } 3581 if (BothLiveOut) 3582 // Both unextended and extended values are live out. There had better be 3583 // a good reason for the transformation. 3584 return ExtendNodes.size(); 3585 } 3586 return true; 3587} 3588 3589SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3590 SDValue N0 = N->getOperand(0); 3591 EVT VT = N->getValueType(0); 3592 3593 // fold (sext c1) -> c1 3594 if (isa<ConstantSDNode>(N0)) 3595 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3596 3597 // fold (sext (sext x)) -> (sext x) 3598 // fold (sext (aext x)) -> (sext x) 3599 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3600 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3601 N0.getOperand(0)); 3602 3603 if (N0.getOpcode() == ISD::TRUNCATE) { 3604 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3605 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3606 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3607 if (NarrowLoad.getNode()) { 3608 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3609 if (NarrowLoad.getNode() != N0.getNode()) { 3610 CombineTo(N0.getNode(), NarrowLoad); 3611 // CombineTo deleted the truncate, if needed, but not what's under it. 3612 AddToWorkList(oye); 3613 } 3614 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3615 } 3616 3617 // See if the value being truncated is already sign extended. If so, just 3618 // eliminate the trunc/sext pair. 3619 SDValue Op = N0.getOperand(0); 3620 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3621 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3622 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3623 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3624 3625 if (OpBits == DestBits) { 3626 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3627 // bits, it is already ready. 3628 if (NumSignBits > DestBits-MidBits) 3629 return Op; 3630 } else if (OpBits < DestBits) { 3631 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3632 // bits, just sext from i32. 3633 if (NumSignBits > OpBits-MidBits) 3634 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3635 } else { 3636 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3637 // bits, just truncate to i32. 3638 if (NumSignBits > OpBits-MidBits) 3639 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3640 } 3641 3642 // fold (sext (truncate x)) -> (sextinreg x). 3643 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3644 N0.getValueType())) { 3645 if (OpBits < DestBits) 3646 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3647 else if (OpBits > DestBits) 3648 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3649 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3650 DAG.getValueType(N0.getValueType())); 3651 } 3652 } 3653 3654 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3655 if (ISD::isNON_EXTLoad(N0.getNode()) && 3656 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3657 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3658 bool DoXform = true; 3659 SmallVector<SDNode*, 4> SetCCs; 3660 if (!N0.hasOneUse()) 3661 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3662 if (DoXform) { 3663 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3664 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 3665 LN0->getChain(), 3666 LN0->getBasePtr(), LN0->getPointerInfo(), 3667 N0.getValueType(), 3668 LN0->isVolatile(), LN0->isNonTemporal(), 3669 LN0->getAlignment()); 3670 CombineTo(N, ExtLoad); 3671 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3672 N0.getValueType(), ExtLoad); 3673 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3674 3675 // Extend SetCC uses if necessary. 3676 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3677 SDNode *SetCC = SetCCs[i]; 3678 SmallVector<SDValue, 4> Ops; 3679 3680 for (unsigned j = 0; j != 2; ++j) { 3681 SDValue SOp = SetCC->getOperand(j); 3682 if (SOp == Trunc) 3683 Ops.push_back(ExtLoad); 3684 else 3685 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3686 N->getDebugLoc(), VT, SOp)); 3687 } 3688 3689 Ops.push_back(SetCC->getOperand(2)); 3690 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3691 SetCC->getValueType(0), 3692 &Ops[0], Ops.size())); 3693 } 3694 3695 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3696 } 3697 } 3698 3699 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3700 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3701 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3702 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3703 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3704 EVT MemVT = LN0->getMemoryVT(); 3705 if ((!LegalOperations && !LN0->isVolatile()) || 3706 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3707 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 3708 LN0->getChain(), 3709 LN0->getBasePtr(), LN0->getPointerInfo(), 3710 MemVT, 3711 LN0->isVolatile(), LN0->isNonTemporal(), 3712 LN0->getAlignment()); 3713 CombineTo(N, ExtLoad); 3714 CombineTo(N0.getNode(), 3715 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3716 N0.getValueType(), ExtLoad), 3717 ExtLoad.getValue(1)); 3718 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3719 } 3720 } 3721 3722 if (N0.getOpcode() == ISD::SETCC) { 3723 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3724 // Only do this before legalize for now. 3725 if (VT.isVector() && !LegalOperations) { 3726 EVT N0VT = N0.getOperand(0).getValueType(); 3727 // We know that the # elements of the results is the same as the 3728 // # elements of the compare (and the # elements of the compare result 3729 // for that matter). Check to see that they are the same size. If so, 3730 // we know that the element size of the sext'd result matches the 3731 // element size of the compare operands. 3732 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3733 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3734 N0.getOperand(1), 3735 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3736 // If the desired elements are smaller or larger than the source 3737 // elements we can use a matching integer vector type and then 3738 // truncate/sign extend 3739 else { 3740 EVT MatchingElementType = 3741 EVT::getIntegerVT(*DAG.getContext(), 3742 N0VT.getScalarType().getSizeInBits()); 3743 EVT MatchingVectorType = 3744 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3745 N0VT.getVectorNumElements()); 3746 SDValue VsetCC = 3747 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3748 N0.getOperand(1), 3749 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3750 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3751 } 3752 } 3753 3754 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3755 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3756 SDValue NegOne = 3757 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3758 SDValue SCC = 3759 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3760 NegOne, DAG.getConstant(0, VT), 3761 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3762 if (SCC.getNode()) return SCC; 3763 if (!LegalOperations || 3764 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3765 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3766 DAG.getSetCC(N->getDebugLoc(), 3767 TLI.getSetCCResultType(VT), 3768 N0.getOperand(0), N0.getOperand(1), 3769 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3770 NegOne, DAG.getConstant(0, VT)); 3771 } 3772 3773 // fold (sext x) -> (zext x) if the sign bit is known zero. 3774 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3775 DAG.SignBitIsZero(N0)) 3776 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3777 3778 return SDValue(); 3779} 3780 3781SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3782 SDValue N0 = N->getOperand(0); 3783 EVT VT = N->getValueType(0); 3784 3785 // fold (zext c1) -> c1 3786 if (isa<ConstantSDNode>(N0)) 3787 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3788 // fold (zext (zext x)) -> (zext x) 3789 // fold (zext (aext x)) -> (zext x) 3790 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3791 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3792 N0.getOperand(0)); 3793 3794 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3795 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3796 if (N0.getOpcode() == ISD::TRUNCATE) { 3797 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3798 if (NarrowLoad.getNode()) { 3799 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3800 if (NarrowLoad.getNode() != N0.getNode()) { 3801 CombineTo(N0.getNode(), NarrowLoad); 3802 // CombineTo deleted the truncate, if needed, but not what's under it. 3803 AddToWorkList(oye); 3804 } 3805 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3806 } 3807 } 3808 3809 // fold (zext (truncate x)) -> (and x, mask) 3810 if (N0.getOpcode() == ISD::TRUNCATE && 3811 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3812 3813 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3814 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 3815 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3816 if (NarrowLoad.getNode()) { 3817 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3818 if (NarrowLoad.getNode() != N0.getNode()) { 3819 CombineTo(N0.getNode(), NarrowLoad); 3820 // CombineTo deleted the truncate, if needed, but not what's under it. 3821 AddToWorkList(oye); 3822 } 3823 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3824 } 3825 3826 SDValue Op = N0.getOperand(0); 3827 if (Op.getValueType().bitsLT(VT)) { 3828 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3829 } else if (Op.getValueType().bitsGT(VT)) { 3830 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3831 } 3832 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3833 N0.getValueType().getScalarType()); 3834 } 3835 3836 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3837 // if either of the casts is not free. 3838 if (N0.getOpcode() == ISD::AND && 3839 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3840 N0.getOperand(1).getOpcode() == ISD::Constant && 3841 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3842 N0.getValueType()) || 3843 !TLI.isZExtFree(N0.getValueType(), VT))) { 3844 SDValue X = N0.getOperand(0).getOperand(0); 3845 if (X.getValueType().bitsLT(VT)) { 3846 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3847 } else if (X.getValueType().bitsGT(VT)) { 3848 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3849 } 3850 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3851 Mask = Mask.zext(VT.getSizeInBits()); 3852 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3853 X, DAG.getConstant(Mask, VT)); 3854 } 3855 3856 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3857 if (ISD::isNON_EXTLoad(N0.getNode()) && 3858 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3859 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3860 bool DoXform = true; 3861 SmallVector<SDNode*, 4> SetCCs; 3862 if (!N0.hasOneUse()) 3863 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3864 if (DoXform) { 3865 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3866 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(), 3867 LN0->getChain(), 3868 LN0->getBasePtr(), LN0->getPointerInfo(), 3869 N0.getValueType(), 3870 LN0->isVolatile(), LN0->isNonTemporal(), 3871 LN0->getAlignment()); 3872 CombineTo(N, ExtLoad); 3873 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3874 N0.getValueType(), ExtLoad); 3875 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3876 3877 // Extend SetCC uses if necessary. 3878 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3879 SDNode *SetCC = SetCCs[i]; 3880 SmallVector<SDValue, 4> Ops; 3881 3882 for (unsigned j = 0; j != 2; ++j) { 3883 SDValue SOp = SetCC->getOperand(j); 3884 if (SOp == Trunc) 3885 Ops.push_back(ExtLoad); 3886 else 3887 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3888 N->getDebugLoc(), VT, SOp)); 3889 } 3890 3891 Ops.push_back(SetCC->getOperand(2)); 3892 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3893 SetCC->getValueType(0), 3894 &Ops[0], Ops.size())); 3895 } 3896 3897 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3898 } 3899 } 3900 3901 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3902 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3903 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3904 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3905 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3906 EVT MemVT = LN0->getMemoryVT(); 3907 if ((!LegalOperations && !LN0->isVolatile()) || 3908 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3909 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(), 3910 LN0->getChain(), 3911 LN0->getBasePtr(), LN0->getPointerInfo(), 3912 MemVT, 3913 LN0->isVolatile(), LN0->isNonTemporal(), 3914 LN0->getAlignment()); 3915 CombineTo(N, ExtLoad); 3916 CombineTo(N0.getNode(), 3917 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3918 ExtLoad), 3919 ExtLoad.getValue(1)); 3920 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3921 } 3922 } 3923 3924 if (N0.getOpcode() == ISD::SETCC) { 3925 if (!LegalOperations && VT.isVector()) { 3926 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 3927 // Only do this before legalize for now. 3928 EVT N0VT = N0.getOperand(0).getValueType(); 3929 EVT EltVT = VT.getVectorElementType(); 3930 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 3931 DAG.getConstant(1, EltVT)); 3932 if (VT.getSizeInBits() == N0VT.getSizeInBits()) { 3933 // We know that the # elements of the results is the same as the 3934 // # elements of the compare (and the # elements of the compare result 3935 // for that matter). Check to see that they are the same size. If so, 3936 // we know that the element size of the sext'd result matches the 3937 // element size of the compare operands. 3938 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3939 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3940 N0.getOperand(1), 3941 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3942 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3943 &OneOps[0], OneOps.size())); 3944 } else { 3945 // If the desired elements are smaller or larger than the source 3946 // elements we can use a matching integer vector type and then 3947 // truncate/sign extend 3948 EVT MatchingElementType = 3949 EVT::getIntegerVT(*DAG.getContext(), 3950 N0VT.getScalarType().getSizeInBits()); 3951 EVT MatchingVectorType = 3952 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3953 N0VT.getVectorNumElements()); 3954 SDValue VsetCC = 3955 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3956 N0.getOperand(1), 3957 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3958 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3959 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 3960 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3961 &OneOps[0], OneOps.size())); 3962 } 3963 } 3964 3965 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3966 SDValue SCC = 3967 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3968 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3969 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3970 if (SCC.getNode()) return SCC; 3971 } 3972 3973 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3974 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3975 isa<ConstantSDNode>(N0.getOperand(1)) && 3976 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3977 N0.hasOneUse()) { 3978 if (N0.getOpcode() == ISD::SHL) { 3979 // If the original shl may be shifting out bits, do not perform this 3980 // transformation. 3981 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3982 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3983 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3984 if (ShAmt > KnownZeroBits) 3985 return SDValue(); 3986 } 3987 DebugLoc dl = N->getDebugLoc(); 3988 return DAG.getNode(N0.getOpcode(), dl, VT, 3989 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3990 DAG.getNode(ISD::ZERO_EXTEND, dl, 3991 N0.getOperand(1).getValueType(), 3992 N0.getOperand(1))); 3993 } 3994 3995 return SDValue(); 3996} 3997 3998SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3999 SDValue N0 = N->getOperand(0); 4000 EVT VT = N->getValueType(0); 4001 4002 // fold (aext c1) -> c1 4003 if (isa<ConstantSDNode>(N0)) 4004 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4005 // fold (aext (aext x)) -> (aext x) 4006 // fold (aext (zext x)) -> (zext x) 4007 // fold (aext (sext x)) -> (sext x) 4008 if (N0.getOpcode() == ISD::ANY_EXTEND || 4009 N0.getOpcode() == ISD::ZERO_EXTEND || 4010 N0.getOpcode() == ISD::SIGN_EXTEND) 4011 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4012 4013 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4014 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4015 if (N0.getOpcode() == ISD::TRUNCATE) { 4016 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4017 if (NarrowLoad.getNode()) { 4018 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4019 if (NarrowLoad.getNode() != N0.getNode()) { 4020 CombineTo(N0.getNode(), NarrowLoad); 4021 // CombineTo deleted the truncate, if needed, but not what's under it. 4022 AddToWorkList(oye); 4023 } 4024 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 4025 } 4026 } 4027 4028 // fold (aext (truncate x)) 4029 if (N0.getOpcode() == ISD::TRUNCATE) { 4030 SDValue TruncOp = N0.getOperand(0); 4031 if (TruncOp.getValueType() == VT) 4032 return TruncOp; // x iff x size == zext size. 4033 if (TruncOp.getValueType().bitsGT(VT)) 4034 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4035 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4036 } 4037 4038 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4039 // if the trunc is not free. 4040 if (N0.getOpcode() == ISD::AND && 4041 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4042 N0.getOperand(1).getOpcode() == ISD::Constant && 4043 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4044 N0.getValueType())) { 4045 SDValue X = N0.getOperand(0).getOperand(0); 4046 if (X.getValueType().bitsLT(VT)) { 4047 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4048 } else if (X.getValueType().bitsGT(VT)) { 4049 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4050 } 4051 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4052 Mask = Mask.zext(VT.getSizeInBits()); 4053 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4054 X, DAG.getConstant(Mask, VT)); 4055 } 4056 4057 // fold (aext (load x)) -> (aext (truncate (extload x))) 4058 if (ISD::isNON_EXTLoad(N0.getNode()) && 4059 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4060 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4061 bool DoXform = true; 4062 SmallVector<SDNode*, 4> SetCCs; 4063 if (!N0.hasOneUse()) 4064 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4065 if (DoXform) { 4066 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4067 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(), 4068 LN0->getChain(), 4069 LN0->getBasePtr(), LN0->getPointerInfo(), 4070 N0.getValueType(), 4071 LN0->isVolatile(), LN0->isNonTemporal(), 4072 LN0->getAlignment()); 4073 CombineTo(N, ExtLoad); 4074 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4075 N0.getValueType(), ExtLoad); 4076 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4077 4078 // Extend SetCC uses if necessary. 4079 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4080 SDNode *SetCC = SetCCs[i]; 4081 SmallVector<SDValue, 4> Ops; 4082 4083 for (unsigned j = 0; j != 2; ++j) { 4084 SDValue SOp = SetCC->getOperand(j); 4085 if (SOp == Trunc) 4086 Ops.push_back(ExtLoad); 4087 else 4088 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 4089 N->getDebugLoc(), VT, SOp)); 4090 } 4091 4092 Ops.push_back(SetCC->getOperand(2)); 4093 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 4094 SetCC->getValueType(0), 4095 &Ops[0], Ops.size())); 4096 } 4097 4098 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4099 } 4100 } 4101 4102 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4103 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4104 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4105 if (N0.getOpcode() == ISD::LOAD && 4106 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4107 N0.hasOneUse()) { 4108 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4109 EVT MemVT = LN0->getMemoryVT(); 4110 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 4111 N->getDebugLoc(), 4112 LN0->getChain(), LN0->getBasePtr(), 4113 LN0->getPointerInfo(), MemVT, 4114 LN0->isVolatile(), LN0->isNonTemporal(), 4115 LN0->getAlignment()); 4116 CombineTo(N, ExtLoad); 4117 CombineTo(N0.getNode(), 4118 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4119 N0.getValueType(), ExtLoad), 4120 ExtLoad.getValue(1)); 4121 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4122 } 4123 4124 if (N0.getOpcode() == ISD::SETCC) { 4125 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4126 // Only do this before legalize for now. 4127 if (VT.isVector() && !LegalOperations) { 4128 EVT N0VT = N0.getOperand(0).getValueType(); 4129 // We know that the # elements of the results is the same as the 4130 // # elements of the compare (and the # elements of the compare result 4131 // for that matter). Check to see that they are the same size. If so, 4132 // we know that the element size of the sext'd result matches the 4133 // element size of the compare operands. 4134 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4135 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4136 N0.getOperand(1), 4137 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4138 // If the desired elements are smaller or larger than the source 4139 // elements we can use a matching integer vector type and then 4140 // truncate/sign extend 4141 else { 4142 EVT MatchingElementType = 4143 EVT::getIntegerVT(*DAG.getContext(), 4144 N0VT.getScalarType().getSizeInBits()); 4145 EVT MatchingVectorType = 4146 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4147 N0VT.getVectorNumElements()); 4148 SDValue VsetCC = 4149 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4150 N0.getOperand(1), 4151 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4152 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4153 } 4154 } 4155 4156 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4157 SDValue SCC = 4158 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4159 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4160 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4161 if (SCC.getNode()) 4162 return SCC; 4163 } 4164 4165 return SDValue(); 4166} 4167 4168/// GetDemandedBits - See if the specified operand can be simplified with the 4169/// knowledge that only the bits specified by Mask are used. If so, return the 4170/// simpler operand, otherwise return a null SDValue. 4171SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4172 switch (V.getOpcode()) { 4173 default: break; 4174 case ISD::OR: 4175 case ISD::XOR: 4176 // If the LHS or RHS don't contribute bits to the or, drop them. 4177 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4178 return V.getOperand(1); 4179 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4180 return V.getOperand(0); 4181 break; 4182 case ISD::SRL: 4183 // Only look at single-use SRLs. 4184 if (!V.getNode()->hasOneUse()) 4185 break; 4186 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4187 // See if we can recursively simplify the LHS. 4188 unsigned Amt = RHSC->getZExtValue(); 4189 4190 // Watch out for shift count overflow though. 4191 if (Amt >= Mask.getBitWidth()) break; 4192 APInt NewMask = Mask << Amt; 4193 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4194 if (SimplifyLHS.getNode()) 4195 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4196 SimplifyLHS, V.getOperand(1)); 4197 } 4198 } 4199 return SDValue(); 4200} 4201 4202/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4203/// bits and then truncated to a narrower type and where N is a multiple 4204/// of number of bits of the narrower type, transform it to a narrower load 4205/// from address + N / num of bits of new type. If the result is to be 4206/// extended, also fold the extension to form a extending load. 4207SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4208 unsigned Opc = N->getOpcode(); 4209 4210 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4211 SDValue N0 = N->getOperand(0); 4212 EVT VT = N->getValueType(0); 4213 EVT ExtVT = VT; 4214 4215 // This transformation isn't valid for vector loads. 4216 if (VT.isVector()) 4217 return SDValue(); 4218 4219 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4220 // extended to VT. 4221 if (Opc == ISD::SIGN_EXTEND_INREG) { 4222 ExtType = ISD::SEXTLOAD; 4223 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4224 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 4225 return SDValue(); 4226 } else if (Opc == ISD::SRL) { 4227 // Another special-case: SRL is basically zero-extending a narrower value. 4228 ExtType = ISD::ZEXTLOAD; 4229 N0 = SDValue(N, 0); 4230 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4231 if (!N01) return SDValue(); 4232 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4233 VT.getSizeInBits() - N01->getZExtValue()); 4234 } 4235 4236 unsigned EVTBits = ExtVT.getSizeInBits(); 4237 4238 // Do not generate loads of non-round integer types since these can 4239 // be expensive (and would be wrong if the type is not byte sized). 4240 if (!ExtVT.isRound()) 4241 return SDValue(); 4242 4243 unsigned ShAmt = 0; 4244 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4245 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4246 ShAmt = N01->getZExtValue(); 4247 // Is the shift amount a multiple of size of VT? 4248 if ((ShAmt & (EVTBits-1)) == 0) { 4249 N0 = N0.getOperand(0); 4250 // Is the load width a multiple of size of VT? 4251 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4252 return SDValue(); 4253 } 4254 4255 // At this point, we must have a load or else we can't do the transform. 4256 if (!isa<LoadSDNode>(N0)) return SDValue(); 4257 4258 // If the shift amount is larger than the input type then we're not 4259 // accessing any of the loaded bytes. If the load was a zextload/extload 4260 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4261 // If the load was a sextload then the result is a splat of the sign bit 4262 // of the extended byte. This is not worth optimizing for. 4263 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4264 return SDValue(); 4265 } 4266 } 4267 4268 // If the load is shifted left (and the result isn't shifted back right), 4269 // we can fold the truncate through the shift. 4270 unsigned ShLeftAmt = 0; 4271 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4272 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4273 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4274 ShLeftAmt = N01->getZExtValue(); 4275 N0 = N0.getOperand(0); 4276 } 4277 } 4278 4279 // If we haven't found a load, we can't narrow it. Don't transform one with 4280 // multiple uses, this would require adding a new load. 4281 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4282 // Don't change the width of a volatile load. 4283 cast<LoadSDNode>(N0)->isVolatile()) 4284 return SDValue(); 4285 4286 // Verify that we are actually reducing a load width here. 4287 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4288 return SDValue(); 4289 4290 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4291 EVT PtrType = N0.getOperand(1).getValueType(); 4292 4293 // For big endian targets, we need to adjust the offset to the pointer to 4294 // load the correct bytes. 4295 if (TLI.isBigEndian()) { 4296 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4297 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4298 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4299 } 4300 4301 uint64_t PtrOff = ShAmt / 8; 4302 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4303 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4304 PtrType, LN0->getBasePtr(), 4305 DAG.getConstant(PtrOff, PtrType)); 4306 AddToWorkList(NewPtr.getNode()); 4307 4308 SDValue Load; 4309 if (ExtType == ISD::NON_EXTLOAD) 4310 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4311 LN0->getPointerInfo().getWithOffset(PtrOff), 4312 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign); 4313 else 4314 Load = DAG.getExtLoad(ExtType, VT, N0.getDebugLoc(), LN0->getChain(),NewPtr, 4315 LN0->getPointerInfo().getWithOffset(PtrOff), 4316 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4317 NewAlign); 4318 4319 // Replace the old load's chain with the new load's chain. 4320 WorkListRemover DeadNodes(*this); 4321 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4322 &DeadNodes); 4323 4324 // Shift the result left, if we've swallowed a left shift. 4325 SDValue Result = Load; 4326 if (ShLeftAmt != 0) { 4327 EVT ShImmTy = getShiftAmountTy(); 4328 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4329 ShImmTy = VT; 4330 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4331 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4332 } 4333 4334 // Return the new loaded value. 4335 return Result; 4336} 4337 4338SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4339 SDValue N0 = N->getOperand(0); 4340 SDValue N1 = N->getOperand(1); 4341 EVT VT = N->getValueType(0); 4342 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4343 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4344 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4345 4346 // fold (sext_in_reg c1) -> c1 4347 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4348 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4349 4350 // If the input is already sign extended, just drop the extension. 4351 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4352 return N0; 4353 4354 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4355 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4356 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4357 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4358 N0.getOperand(0), N1); 4359 } 4360 4361 // fold (sext_in_reg (sext x)) -> (sext x) 4362 // fold (sext_in_reg (aext x)) -> (sext x) 4363 // if x is small enough. 4364 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4365 SDValue N00 = N0.getOperand(0); 4366 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4367 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4368 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4369 } 4370 4371 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4372 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4373 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4374 4375 // fold operands of sext_in_reg based on knowledge that the top bits are not 4376 // demanded. 4377 if (SimplifyDemandedBits(SDValue(N, 0))) 4378 return SDValue(N, 0); 4379 4380 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4381 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4382 SDValue NarrowLoad = ReduceLoadWidth(N); 4383 if (NarrowLoad.getNode()) 4384 return NarrowLoad; 4385 4386 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4387 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4388 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4389 if (N0.getOpcode() == ISD::SRL) { 4390 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4391 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4392 // We can turn this into an SRA iff the input to the SRL is already sign 4393 // extended enough. 4394 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4395 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4396 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4397 N0.getOperand(0), N0.getOperand(1)); 4398 } 4399 } 4400 4401 // fold (sext_inreg (extload x)) -> (sextload x) 4402 if (ISD::isEXTLoad(N0.getNode()) && 4403 ISD::isUNINDEXEDLoad(N0.getNode()) && 4404 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4405 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4406 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4407 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4408 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 4409 LN0->getChain(), 4410 LN0->getBasePtr(), LN0->getPointerInfo(), 4411 EVT, 4412 LN0->isVolatile(), LN0->isNonTemporal(), 4413 LN0->getAlignment()); 4414 CombineTo(N, ExtLoad); 4415 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4416 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4417 } 4418 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4419 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4420 N0.hasOneUse() && 4421 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4422 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4423 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4424 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4425 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 4426 LN0->getChain(), 4427 LN0->getBasePtr(), LN0->getPointerInfo(), 4428 EVT, 4429 LN0->isVolatile(), LN0->isNonTemporal(), 4430 LN0->getAlignment()); 4431 CombineTo(N, ExtLoad); 4432 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4433 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4434 } 4435 return SDValue(); 4436} 4437 4438SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4439 SDValue N0 = N->getOperand(0); 4440 EVT VT = N->getValueType(0); 4441 4442 // noop truncate 4443 if (N0.getValueType() == N->getValueType(0)) 4444 return N0; 4445 // fold (truncate c1) -> c1 4446 if (isa<ConstantSDNode>(N0)) 4447 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4448 // fold (truncate (truncate x)) -> (truncate x) 4449 if (N0.getOpcode() == ISD::TRUNCATE) 4450 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4451 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4452 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4453 N0.getOpcode() == ISD::SIGN_EXTEND || 4454 N0.getOpcode() == ISD::ANY_EXTEND) { 4455 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4456 // if the source is smaller than the dest, we still need an extend 4457 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4458 N0.getOperand(0)); 4459 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4460 // if the source is larger than the dest, than we just need the truncate 4461 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4462 else 4463 // if the source and dest are the same type, we can drop both the extend 4464 // and the truncate. 4465 return N0.getOperand(0); 4466 } 4467 4468 // See if we can simplify the input to this truncate through knowledge that 4469 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 4470 // -> trunc y 4471 SDValue Shorter = 4472 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4473 VT.getSizeInBits())); 4474 if (Shorter.getNode()) 4475 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4476 4477 // fold (truncate (load x)) -> (smaller load x) 4478 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4479 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4480 SDValue Reduced = ReduceLoadWidth(N); 4481 if (Reduced.getNode()) 4482 return Reduced; 4483 } 4484 4485 // Simplify the operands using demanded-bits information. 4486 if (!VT.isVector() && 4487 SimplifyDemandedBits(SDValue(N, 0))) 4488 return SDValue(N, 0); 4489 4490 return SDValue(); 4491} 4492 4493static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4494 SDValue Elt = N->getOperand(i); 4495 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4496 return Elt.getNode(); 4497 return Elt.getOperand(Elt.getResNo()).getNode(); 4498} 4499 4500/// CombineConsecutiveLoads - build_pair (load, load) -> load 4501/// if load locations are consecutive. 4502SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4503 assert(N->getOpcode() == ISD::BUILD_PAIR); 4504 4505 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4506 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4507 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4508 LD1->getPointerInfo().getAddrSpace() != 4509 LD2->getPointerInfo().getAddrSpace()) 4510 return SDValue(); 4511 EVT LD1VT = LD1->getValueType(0); 4512 4513 if (ISD::isNON_EXTLoad(LD2) && 4514 LD2->hasOneUse() && 4515 // If both are volatile this would reduce the number of volatile loads. 4516 // If one is volatile it might be ok, but play conservative and bail out. 4517 !LD1->isVolatile() && 4518 !LD2->isVolatile() && 4519 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4520 unsigned Align = LD1->getAlignment(); 4521 unsigned NewAlign = TLI.getTargetData()-> 4522 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4523 4524 if (NewAlign <= Align && 4525 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4526 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4527 LD1->getBasePtr(), LD1->getPointerInfo(), 4528 false, false, Align); 4529 } 4530 4531 return SDValue(); 4532} 4533 4534SDValue DAGCombiner::visitBITCAST(SDNode *N) { 4535 SDValue N0 = N->getOperand(0); 4536 EVT VT = N->getValueType(0); 4537 4538 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4539 // Only do this before legalize, since afterward the target may be depending 4540 // on the bitconvert. 4541 // First check to see if this is all constant. 4542 if (!LegalTypes && 4543 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4544 VT.isVector()) { 4545 bool isSimple = true; 4546 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4547 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4548 N0.getOperand(i).getOpcode() != ISD::Constant && 4549 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4550 isSimple = false; 4551 break; 4552 } 4553 4554 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4555 assert(!DestEltVT.isVector() && 4556 "Element type of vector ValueType must not be vector!"); 4557 if (isSimple) 4558 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4559 } 4560 4561 // If the input is a constant, let getNode fold it. 4562 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4563 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 4564 if (Res.getNode() != N) { 4565 if (!LegalOperations || 4566 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4567 return Res; 4568 4569 // Folding it resulted in an illegal node, and it's too late to 4570 // do that. Clean up the old node and forego the transformation. 4571 // Ideally this won't happen very often, because instcombine 4572 // and the earlier dagcombine runs (where illegal nodes are 4573 // permitted) should have folded most of them already. 4574 DAG.DeleteNode(Res.getNode()); 4575 } 4576 } 4577 4578 // (conv (conv x, t1), t2) -> (conv x, t2) 4579 if (N0.getOpcode() == ISD::BITCAST) 4580 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 4581 N0.getOperand(0)); 4582 4583 // fold (conv (load x)) -> (load (conv*)x) 4584 // If the resultant load doesn't need a higher alignment than the original! 4585 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4586 // Do not change the width of a volatile load. 4587 !cast<LoadSDNode>(N0)->isVolatile() && 4588 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4589 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4590 unsigned Align = TLI.getTargetData()-> 4591 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4592 unsigned OrigAlign = LN0->getAlignment(); 4593 4594 if (Align <= OrigAlign) { 4595 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4596 LN0->getBasePtr(), LN0->getPointerInfo(), 4597 LN0->isVolatile(), LN0->isNonTemporal(), 4598 OrigAlign); 4599 AddToWorkList(N); 4600 CombineTo(N0.getNode(), 4601 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4602 N0.getValueType(), Load), 4603 Load.getValue(1)); 4604 return Load; 4605 } 4606 } 4607 4608 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4609 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4610 // This often reduces constant pool loads. 4611 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4612 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4613 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 4614 N0.getOperand(0)); 4615 AddToWorkList(NewConv.getNode()); 4616 4617 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4618 if (N0.getOpcode() == ISD::FNEG) 4619 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4620 NewConv, DAG.getConstant(SignBit, VT)); 4621 assert(N0.getOpcode() == ISD::FABS); 4622 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4623 NewConv, DAG.getConstant(~SignBit, VT)); 4624 } 4625 4626 // fold (bitconvert (fcopysign cst, x)) -> 4627 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4628 // Note that we don't handle (copysign x, cst) because this can always be 4629 // folded to an fneg or fabs. 4630 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4631 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4632 VT.isInteger() && !VT.isVector()) { 4633 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4634 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4635 if (isTypeLegal(IntXVT)) { 4636 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4637 IntXVT, N0.getOperand(1)); 4638 AddToWorkList(X.getNode()); 4639 4640 // If X has a different width than the result/lhs, sext it or truncate it. 4641 unsigned VTWidth = VT.getSizeInBits(); 4642 if (OrigXWidth < VTWidth) { 4643 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4644 AddToWorkList(X.getNode()); 4645 } else if (OrigXWidth > VTWidth) { 4646 // To get the sign bit in the right place, we have to shift it right 4647 // before truncating. 4648 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4649 X.getValueType(), X, 4650 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4651 AddToWorkList(X.getNode()); 4652 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4653 AddToWorkList(X.getNode()); 4654 } 4655 4656 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4657 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4658 X, DAG.getConstant(SignBit, VT)); 4659 AddToWorkList(X.getNode()); 4660 4661 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4662 VT, N0.getOperand(0)); 4663 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4664 Cst, DAG.getConstant(~SignBit, VT)); 4665 AddToWorkList(Cst.getNode()); 4666 4667 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4668 } 4669 } 4670 4671 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4672 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4673 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4674 if (CombineLD.getNode()) 4675 return CombineLD; 4676 } 4677 4678 return SDValue(); 4679} 4680 4681SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4682 EVT VT = N->getValueType(0); 4683 return CombineConsecutiveLoads(N, VT); 4684} 4685 4686/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 4687/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4688/// destination element value type. 4689SDValue DAGCombiner:: 4690ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4691 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4692 4693 // If this is already the right type, we're done. 4694 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4695 4696 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4697 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4698 4699 // If this is a conversion of N elements of one type to N elements of another 4700 // type, convert each element. This handles FP<->INT cases. 4701 if (SrcBitSize == DstBitSize) { 4702 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4703 BV->getValueType(0).getVectorNumElements()); 4704 4705 // Due to the FP element handling below calling this routine recursively, 4706 // we can end up with a scalar-to-vector node here. 4707 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 4708 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4709 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4710 DstEltVT, BV->getOperand(0))); 4711 4712 SmallVector<SDValue, 8> Ops; 4713 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4714 SDValue Op = BV->getOperand(i); 4715 // If the vector element type is not legal, the BUILD_VECTOR operands 4716 // are promoted and implicitly truncated. Make that explicit here. 4717 if (Op.getValueType() != SrcEltVT) 4718 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4719 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4720 DstEltVT, Op)); 4721 AddToWorkList(Ops.back().getNode()); 4722 } 4723 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4724 &Ops[0], Ops.size()); 4725 } 4726 4727 // Otherwise, we're growing or shrinking the elements. To avoid having to 4728 // handle annoying details of growing/shrinking FP values, we convert them to 4729 // int first. 4730 if (SrcEltVT.isFloatingPoint()) { 4731 // Convert the input float vector to a int vector where the elements are the 4732 // same sizes. 4733 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4734 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4735 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 4736 SrcEltVT = IntVT; 4737 } 4738 4739 // Now we know the input is an integer vector. If the output is a FP type, 4740 // convert to integer first, then to FP of the right size. 4741 if (DstEltVT.isFloatingPoint()) { 4742 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4743 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4744 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 4745 4746 // Next, convert to FP elements of the same size. 4747 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 4748 } 4749 4750 // Okay, we know the src/dst types are both integers of differing types. 4751 // Handling growing first. 4752 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4753 if (SrcBitSize < DstBitSize) { 4754 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4755 4756 SmallVector<SDValue, 8> Ops; 4757 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4758 i += NumInputsPerOutput) { 4759 bool isLE = TLI.isLittleEndian(); 4760 APInt NewBits = APInt(DstBitSize, 0); 4761 bool EltIsUndef = true; 4762 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4763 // Shift the previously computed bits over. 4764 NewBits <<= SrcBitSize; 4765 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4766 if (Op.getOpcode() == ISD::UNDEF) continue; 4767 EltIsUndef = false; 4768 4769 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 4770 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4771 } 4772 4773 if (EltIsUndef) 4774 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4775 else 4776 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4777 } 4778 4779 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4780 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4781 &Ops[0], Ops.size()); 4782 } 4783 4784 // Finally, this must be the case where we are shrinking elements: each input 4785 // turns into multiple outputs. 4786 bool isS2V = ISD::isScalarToVector(BV); 4787 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4788 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4789 NumOutputsPerInput*BV->getNumOperands()); 4790 SmallVector<SDValue, 8> Ops; 4791 4792 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4793 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4794 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4795 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4796 continue; 4797 } 4798 4799 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 4800 getAPIntValue().zextOrTrunc(SrcBitSize); 4801 4802 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4803 APInt ThisVal = OpVal.trunc(DstBitSize); 4804 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4805 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 4806 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4807 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4808 Ops[0]); 4809 OpVal = OpVal.lshr(DstBitSize); 4810 } 4811 4812 // For big endian targets, swap the order of the pieces of each element. 4813 if (TLI.isBigEndian()) 4814 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4815 } 4816 4817 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4818 &Ops[0], Ops.size()); 4819} 4820 4821SDValue DAGCombiner::visitFADD(SDNode *N) { 4822 SDValue N0 = N->getOperand(0); 4823 SDValue N1 = N->getOperand(1); 4824 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4825 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4826 EVT VT = N->getValueType(0); 4827 4828 // fold vector ops 4829 if (VT.isVector()) { 4830 SDValue FoldedVOp = SimplifyVBinOp(N); 4831 if (FoldedVOp.getNode()) return FoldedVOp; 4832 } 4833 4834 // fold (fadd c1, c2) -> (fadd c1, c2) 4835 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4836 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4837 // canonicalize constant to RHS 4838 if (N0CFP && !N1CFP) 4839 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4840 // fold (fadd A, 0) -> A 4841 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4842 return N0; 4843 // fold (fadd A, (fneg B)) -> (fsub A, B) 4844 if (isNegatibleForFree(N1, LegalOperations) == 2) 4845 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4846 GetNegatedExpression(N1, DAG, LegalOperations)); 4847 // fold (fadd (fneg A), B) -> (fsub B, A) 4848 if (isNegatibleForFree(N0, LegalOperations) == 2) 4849 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4850 GetNegatedExpression(N0, DAG, LegalOperations)); 4851 4852 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4853 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4854 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4855 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4856 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4857 N0.getOperand(1), N1)); 4858 4859 return SDValue(); 4860} 4861 4862SDValue DAGCombiner::visitFSUB(SDNode *N) { 4863 SDValue N0 = N->getOperand(0); 4864 SDValue N1 = N->getOperand(1); 4865 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4866 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4867 EVT VT = N->getValueType(0); 4868 4869 // fold vector ops 4870 if (VT.isVector()) { 4871 SDValue FoldedVOp = SimplifyVBinOp(N); 4872 if (FoldedVOp.getNode()) return FoldedVOp; 4873 } 4874 4875 // fold (fsub c1, c2) -> c1-c2 4876 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4877 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4878 // fold (fsub A, 0) -> A 4879 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4880 return N0; 4881 // fold (fsub 0, B) -> -B 4882 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4883 if (isNegatibleForFree(N1, LegalOperations)) 4884 return GetNegatedExpression(N1, DAG, LegalOperations); 4885 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4886 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4887 } 4888 // fold (fsub A, (fneg B)) -> (fadd A, B) 4889 if (isNegatibleForFree(N1, LegalOperations)) 4890 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4891 GetNegatedExpression(N1, DAG, LegalOperations)); 4892 4893 return SDValue(); 4894} 4895 4896SDValue DAGCombiner::visitFMUL(SDNode *N) { 4897 SDValue N0 = N->getOperand(0); 4898 SDValue N1 = N->getOperand(1); 4899 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4900 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4901 EVT VT = N->getValueType(0); 4902 4903 // fold vector ops 4904 if (VT.isVector()) { 4905 SDValue FoldedVOp = SimplifyVBinOp(N); 4906 if (FoldedVOp.getNode()) return FoldedVOp; 4907 } 4908 4909 // fold (fmul c1, c2) -> c1*c2 4910 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4911 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4912 // canonicalize constant to RHS 4913 if (N0CFP && !N1CFP) 4914 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4915 // fold (fmul A, 0) -> 0 4916 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4917 return N1; 4918 // fold (fmul A, 0) -> 0, vector edition. 4919 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4920 return N1; 4921 // fold (fmul X, 2.0) -> (fadd X, X) 4922 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4923 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4924 // fold (fmul X, -1.0) -> (fneg X) 4925 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4926 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4927 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4928 4929 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4930 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4931 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4932 // Both can be negated for free, check to see if at least one is cheaper 4933 // negated. 4934 if (LHSNeg == 2 || RHSNeg == 2) 4935 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4936 GetNegatedExpression(N0, DAG, LegalOperations), 4937 GetNegatedExpression(N1, DAG, LegalOperations)); 4938 } 4939 } 4940 4941 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4942 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4943 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4944 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4945 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4946 N0.getOperand(1), N1)); 4947 4948 return SDValue(); 4949} 4950 4951SDValue DAGCombiner::visitFDIV(SDNode *N) { 4952 SDValue N0 = N->getOperand(0); 4953 SDValue N1 = N->getOperand(1); 4954 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4955 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4956 EVT VT = N->getValueType(0); 4957 4958 // fold vector ops 4959 if (VT.isVector()) { 4960 SDValue FoldedVOp = SimplifyVBinOp(N); 4961 if (FoldedVOp.getNode()) return FoldedVOp; 4962 } 4963 4964 // fold (fdiv c1, c2) -> c1/c2 4965 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4966 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4967 4968 4969 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4970 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4971 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4972 // Both can be negated for free, check to see if at least one is cheaper 4973 // negated. 4974 if (LHSNeg == 2 || RHSNeg == 2) 4975 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4976 GetNegatedExpression(N0, DAG, LegalOperations), 4977 GetNegatedExpression(N1, DAG, LegalOperations)); 4978 } 4979 } 4980 4981 return SDValue(); 4982} 4983 4984SDValue DAGCombiner::visitFREM(SDNode *N) { 4985 SDValue N0 = N->getOperand(0); 4986 SDValue N1 = N->getOperand(1); 4987 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4988 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4989 EVT VT = N->getValueType(0); 4990 4991 // fold (frem c1, c2) -> fmod(c1,c2) 4992 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4993 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4994 4995 return SDValue(); 4996} 4997 4998SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4999 SDValue N0 = N->getOperand(0); 5000 SDValue N1 = N->getOperand(1); 5001 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5002 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5003 EVT VT = N->getValueType(0); 5004 5005 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5006 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5007 5008 if (N1CFP) { 5009 const APFloat& V = N1CFP->getValueAPF(); 5010 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5011 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5012 if (!V.isNegative()) { 5013 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5014 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5015 } else { 5016 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5017 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5018 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5019 } 5020 } 5021 5022 // copysign(fabs(x), y) -> copysign(x, y) 5023 // copysign(fneg(x), y) -> copysign(x, y) 5024 // copysign(copysign(x,z), y) -> copysign(x, y) 5025 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5026 N0.getOpcode() == ISD::FCOPYSIGN) 5027 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5028 N0.getOperand(0), N1); 5029 5030 // copysign(x, abs(y)) -> abs(x) 5031 if (N1.getOpcode() == ISD::FABS) 5032 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5033 5034 // copysign(x, copysign(y,z)) -> copysign(x, z) 5035 if (N1.getOpcode() == ISD::FCOPYSIGN) 5036 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5037 N0, N1.getOperand(1)); 5038 5039 // copysign(x, fp_extend(y)) -> copysign(x, y) 5040 // copysign(x, fp_round(y)) -> copysign(x, y) 5041 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5042 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5043 N0, N1.getOperand(0)); 5044 5045 return SDValue(); 5046} 5047 5048SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5049 SDValue N0 = N->getOperand(0); 5050 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5051 EVT VT = N->getValueType(0); 5052 EVT OpVT = N0.getValueType(); 5053 5054 // fold (sint_to_fp c1) -> c1fp 5055 if (N0C && OpVT != MVT::ppcf128) 5056 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5057 5058 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5059 // but UINT_TO_FP is legal on this target, try to convert. 5060 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5061 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5062 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5063 if (DAG.SignBitIsZero(N0)) 5064 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5065 } 5066 5067 return SDValue(); 5068} 5069 5070SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5071 SDValue N0 = N->getOperand(0); 5072 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5073 EVT VT = N->getValueType(0); 5074 EVT OpVT = N0.getValueType(); 5075 5076 // fold (uint_to_fp c1) -> c1fp 5077 if (N0C && OpVT != MVT::ppcf128) 5078 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5079 5080 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5081 // but SINT_TO_FP is legal on this target, try to convert. 5082 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5083 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5084 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5085 if (DAG.SignBitIsZero(N0)) 5086 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5087 } 5088 5089 return SDValue(); 5090} 5091 5092SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5093 SDValue N0 = N->getOperand(0); 5094 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5095 EVT VT = N->getValueType(0); 5096 5097 // fold (fp_to_sint c1fp) -> c1 5098 if (N0CFP) 5099 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5100 5101 return SDValue(); 5102} 5103 5104SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5105 SDValue N0 = N->getOperand(0); 5106 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5107 EVT VT = N->getValueType(0); 5108 5109 // fold (fp_to_uint c1fp) -> c1 5110 if (N0CFP && VT != MVT::ppcf128) 5111 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5112 5113 return SDValue(); 5114} 5115 5116SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5117 SDValue N0 = N->getOperand(0); 5118 SDValue N1 = N->getOperand(1); 5119 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5120 EVT VT = N->getValueType(0); 5121 5122 // fold (fp_round c1fp) -> c1fp 5123 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5124 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5125 5126 // fold (fp_round (fp_extend x)) -> x 5127 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5128 return N0.getOperand(0); 5129 5130 // fold (fp_round (fp_round x)) -> (fp_round x) 5131 if (N0.getOpcode() == ISD::FP_ROUND) { 5132 // This is a value preserving truncation if both round's are. 5133 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5134 N0.getNode()->getConstantOperandVal(1) == 1; 5135 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5136 DAG.getIntPtrConstant(IsTrunc)); 5137 } 5138 5139 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5140 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5141 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5142 N0.getOperand(0), N1); 5143 AddToWorkList(Tmp.getNode()); 5144 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5145 Tmp, N0.getOperand(1)); 5146 } 5147 5148 return SDValue(); 5149} 5150 5151SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5152 SDValue N0 = N->getOperand(0); 5153 EVT VT = N->getValueType(0); 5154 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5155 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5156 5157 // fold (fp_round_inreg c1fp) -> c1fp 5158 if (N0CFP && isTypeLegal(EVT)) { 5159 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5160 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5161 } 5162 5163 return SDValue(); 5164} 5165 5166SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5167 SDValue N0 = N->getOperand(0); 5168 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5169 EVT VT = N->getValueType(0); 5170 5171 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5172 if (N->hasOneUse() && 5173 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5174 return SDValue(); 5175 5176 // fold (fp_extend c1fp) -> c1fp 5177 if (N0CFP && VT != MVT::ppcf128) 5178 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5179 5180 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5181 // value of X. 5182 if (N0.getOpcode() == ISD::FP_ROUND 5183 && N0.getNode()->getConstantOperandVal(1) == 1) { 5184 SDValue In = N0.getOperand(0); 5185 if (In.getValueType() == VT) return In; 5186 if (VT.bitsLT(In.getValueType())) 5187 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5188 In, N0.getOperand(1)); 5189 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5190 } 5191 5192 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5193 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5194 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5195 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5196 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5197 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(), 5198 LN0->getChain(), 5199 LN0->getBasePtr(), LN0->getPointerInfo(), 5200 N0.getValueType(), 5201 LN0->isVolatile(), LN0->isNonTemporal(), 5202 LN0->getAlignment()); 5203 CombineTo(N, ExtLoad); 5204 CombineTo(N0.getNode(), 5205 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5206 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5207 ExtLoad.getValue(1)); 5208 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5209 } 5210 5211 return SDValue(); 5212} 5213 5214SDValue DAGCombiner::visitFNEG(SDNode *N) { 5215 SDValue N0 = N->getOperand(0); 5216 EVT VT = N->getValueType(0); 5217 5218 if (isNegatibleForFree(N0, LegalOperations)) 5219 return GetNegatedExpression(N0, DAG, LegalOperations); 5220 5221 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5222 // constant pool values. 5223 if (N0.getOpcode() == ISD::BITCAST && 5224 !VT.isVector() && 5225 N0.getNode()->hasOneUse() && 5226 N0.getOperand(0).getValueType().isInteger()) { 5227 SDValue Int = N0.getOperand(0); 5228 EVT IntVT = Int.getValueType(); 5229 if (IntVT.isInteger() && !IntVT.isVector()) { 5230 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5231 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5232 AddToWorkList(Int.getNode()); 5233 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5234 VT, Int); 5235 } 5236 } 5237 5238 return SDValue(); 5239} 5240 5241SDValue DAGCombiner::visitFABS(SDNode *N) { 5242 SDValue N0 = N->getOperand(0); 5243 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5244 EVT VT = N->getValueType(0); 5245 5246 // fold (fabs c1) -> fabs(c1) 5247 if (N0CFP && VT != MVT::ppcf128) 5248 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5249 // fold (fabs (fabs x)) -> (fabs x) 5250 if (N0.getOpcode() == ISD::FABS) 5251 return N->getOperand(0); 5252 // fold (fabs (fneg x)) -> (fabs x) 5253 // fold (fabs (fcopysign x, y)) -> (fabs x) 5254 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5255 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5256 5257 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5258 // constant pool values. 5259 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5260 N0.getOperand(0).getValueType().isInteger() && 5261 !N0.getOperand(0).getValueType().isVector()) { 5262 SDValue Int = N0.getOperand(0); 5263 EVT IntVT = Int.getValueType(); 5264 if (IntVT.isInteger() && !IntVT.isVector()) { 5265 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5266 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5267 AddToWorkList(Int.getNode()); 5268 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5269 N->getValueType(0), Int); 5270 } 5271 } 5272 5273 return SDValue(); 5274} 5275 5276SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5277 SDValue Chain = N->getOperand(0); 5278 SDValue N1 = N->getOperand(1); 5279 SDValue N2 = N->getOperand(2); 5280 5281 // If N is a constant we could fold this into a fallthrough or unconditional 5282 // branch. However that doesn't happen very often in normal code, because 5283 // Instcombine/SimplifyCFG should have handled the available opportunities. 5284 // If we did this folding here, it would be necessary to update the 5285 // MachineBasicBlock CFG, which is awkward. 5286 5287 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5288 // on the target. 5289 if (N1.getOpcode() == ISD::SETCC && 5290 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5291 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5292 Chain, N1.getOperand(2), 5293 N1.getOperand(0), N1.getOperand(1), N2); 5294 } 5295 5296 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5297 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5298 (N1.getOperand(0).hasOneUse() && 5299 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5300 SDNode *Trunc = 0; 5301 if (N1.getOpcode() == ISD::TRUNCATE) { 5302 // Look pass the truncate. 5303 Trunc = N1.getNode(); 5304 N1 = N1.getOperand(0); 5305 } 5306 5307 // Match this pattern so that we can generate simpler code: 5308 // 5309 // %a = ... 5310 // %b = and i32 %a, 2 5311 // %c = srl i32 %b, 1 5312 // brcond i32 %c ... 5313 // 5314 // into 5315 // 5316 // %a = ... 5317 // %b = and i32 %a, 2 5318 // %c = setcc eq %b, 0 5319 // brcond %c ... 5320 // 5321 // This applies only when the AND constant value has one bit set and the 5322 // SRL constant is equal to the log2 of the AND constant. The back-end is 5323 // smart enough to convert the result into a TEST/JMP sequence. 5324 SDValue Op0 = N1.getOperand(0); 5325 SDValue Op1 = N1.getOperand(1); 5326 5327 if (Op0.getOpcode() == ISD::AND && 5328 Op1.getOpcode() == ISD::Constant) { 5329 SDValue AndOp1 = Op0.getOperand(1); 5330 5331 if (AndOp1.getOpcode() == ISD::Constant) { 5332 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5333 5334 if (AndConst.isPowerOf2() && 5335 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5336 SDValue SetCC = 5337 DAG.getSetCC(N->getDebugLoc(), 5338 TLI.getSetCCResultType(Op0.getValueType()), 5339 Op0, DAG.getConstant(0, Op0.getValueType()), 5340 ISD::SETNE); 5341 5342 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5343 MVT::Other, Chain, SetCC, N2); 5344 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5345 // will convert it back to (X & C1) >> C2. 5346 CombineTo(N, NewBRCond, false); 5347 // Truncate is dead. 5348 if (Trunc) { 5349 removeFromWorkList(Trunc); 5350 DAG.DeleteNode(Trunc); 5351 } 5352 // Replace the uses of SRL with SETCC 5353 WorkListRemover DeadNodes(*this); 5354 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5355 removeFromWorkList(N1.getNode()); 5356 DAG.DeleteNode(N1.getNode()); 5357 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5358 } 5359 } 5360 } 5361 5362 if (Trunc) 5363 // Restore N1 if the above transformation doesn't match. 5364 N1 = N->getOperand(1); 5365 } 5366 5367 // Transform br(xor(x, y)) -> br(x != y) 5368 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5369 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5370 SDNode *TheXor = N1.getNode(); 5371 SDValue Op0 = TheXor->getOperand(0); 5372 SDValue Op1 = TheXor->getOperand(1); 5373 if (Op0.getOpcode() == Op1.getOpcode()) { 5374 // Avoid missing important xor optimizations. 5375 SDValue Tmp = visitXOR(TheXor); 5376 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5377 DEBUG(dbgs() << "\nReplacing.8 "; 5378 TheXor->dump(&DAG); 5379 dbgs() << "\nWith: "; 5380 Tmp.getNode()->dump(&DAG); 5381 dbgs() << '\n'); 5382 WorkListRemover DeadNodes(*this); 5383 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5384 removeFromWorkList(TheXor); 5385 DAG.DeleteNode(TheXor); 5386 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5387 MVT::Other, Chain, Tmp, N2); 5388 } 5389 } 5390 5391 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5392 bool Equal = false; 5393 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5394 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5395 Op0.getOpcode() == ISD::XOR) { 5396 TheXor = Op0.getNode(); 5397 Equal = true; 5398 } 5399 5400 EVT SetCCVT = N1.getValueType(); 5401 if (LegalTypes) 5402 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5403 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5404 SetCCVT, 5405 Op0, Op1, 5406 Equal ? ISD::SETEQ : ISD::SETNE); 5407 // Replace the uses of XOR with SETCC 5408 WorkListRemover DeadNodes(*this); 5409 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5410 removeFromWorkList(N1.getNode()); 5411 DAG.DeleteNode(N1.getNode()); 5412 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5413 MVT::Other, Chain, SetCC, N2); 5414 } 5415 } 5416 5417 return SDValue(); 5418} 5419 5420// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5421// 5422SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5423 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5424 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5425 5426 // If N is a constant we could fold this into a fallthrough or unconditional 5427 // branch. However that doesn't happen very often in normal code, because 5428 // Instcombine/SimplifyCFG should have handled the available opportunities. 5429 // If we did this folding here, it would be necessary to update the 5430 // MachineBasicBlock CFG, which is awkward. 5431 5432 // Use SimplifySetCC to simplify SETCC's. 5433 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5434 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5435 false); 5436 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5437 5438 // fold to a simpler setcc 5439 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5440 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5441 N->getOperand(0), Simp.getOperand(2), 5442 Simp.getOperand(0), Simp.getOperand(1), 5443 N->getOperand(4)); 5444 5445 return SDValue(); 5446} 5447 5448/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5449/// pre-indexed load / store when the base pointer is an add or subtract 5450/// and it has other uses besides the load / store. After the 5451/// transformation, the new indexed load / store has effectively folded 5452/// the add / subtract in and all of its other uses are redirected to the 5453/// new load / store. 5454bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5455 if (!LegalOperations) 5456 return false; 5457 5458 bool isLoad = true; 5459 SDValue Ptr; 5460 EVT VT; 5461 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5462 if (LD->isIndexed()) 5463 return false; 5464 VT = LD->getMemoryVT(); 5465 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5466 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5467 return false; 5468 Ptr = LD->getBasePtr(); 5469 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5470 if (ST->isIndexed()) 5471 return false; 5472 VT = ST->getMemoryVT(); 5473 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5474 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5475 return false; 5476 Ptr = ST->getBasePtr(); 5477 isLoad = false; 5478 } else { 5479 return false; 5480 } 5481 5482 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5483 // out. There is no reason to make this a preinc/predec. 5484 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5485 Ptr.getNode()->hasOneUse()) 5486 return false; 5487 5488 // Ask the target to do addressing mode selection. 5489 SDValue BasePtr; 5490 SDValue Offset; 5491 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5492 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5493 return false; 5494 // Don't create a indexed load / store with zero offset. 5495 if (isa<ConstantSDNode>(Offset) && 5496 cast<ConstantSDNode>(Offset)->isNullValue()) 5497 return false; 5498 5499 // Try turning it into a pre-indexed load / store except when: 5500 // 1) The new base ptr is a frame index. 5501 // 2) If N is a store and the new base ptr is either the same as or is a 5502 // predecessor of the value being stored. 5503 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5504 // that would create a cycle. 5505 // 4) All uses are load / store ops that use it as old base ptr. 5506 5507 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5508 // (plus the implicit offset) to a register to preinc anyway. 5509 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5510 return false; 5511 5512 // Check #2. 5513 if (!isLoad) { 5514 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5515 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5516 return false; 5517 } 5518 5519 // Now check for #3 and #4. 5520 bool RealUse = false; 5521 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5522 E = Ptr.getNode()->use_end(); I != E; ++I) { 5523 SDNode *Use = *I; 5524 if (Use == N) 5525 continue; 5526 if (Use->isPredecessorOf(N)) 5527 return false; 5528 5529 if (!((Use->getOpcode() == ISD::LOAD && 5530 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5531 (Use->getOpcode() == ISD::STORE && 5532 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5533 RealUse = true; 5534 } 5535 5536 if (!RealUse) 5537 return false; 5538 5539 SDValue Result; 5540 if (isLoad) 5541 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5542 BasePtr, Offset, AM); 5543 else 5544 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5545 BasePtr, Offset, AM); 5546 ++PreIndexedNodes; 5547 ++NodesCombined; 5548 DEBUG(dbgs() << "\nReplacing.4 "; 5549 N->dump(&DAG); 5550 dbgs() << "\nWith: "; 5551 Result.getNode()->dump(&DAG); 5552 dbgs() << '\n'); 5553 WorkListRemover DeadNodes(*this); 5554 if (isLoad) { 5555 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5556 &DeadNodes); 5557 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5558 &DeadNodes); 5559 } else { 5560 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5561 &DeadNodes); 5562 } 5563 5564 // Finally, since the node is now dead, remove it from the graph. 5565 DAG.DeleteNode(N); 5566 5567 // Replace the uses of Ptr with uses of the updated base value. 5568 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5569 &DeadNodes); 5570 removeFromWorkList(Ptr.getNode()); 5571 DAG.DeleteNode(Ptr.getNode()); 5572 5573 return true; 5574} 5575 5576/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5577/// add / sub of the base pointer node into a post-indexed load / store. 5578/// The transformation folded the add / subtract into the new indexed 5579/// load / store effectively and all of its uses are redirected to the 5580/// new load / store. 5581bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5582 if (!LegalOperations) 5583 return false; 5584 5585 bool isLoad = true; 5586 SDValue Ptr; 5587 EVT VT; 5588 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5589 if (LD->isIndexed()) 5590 return false; 5591 VT = LD->getMemoryVT(); 5592 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5593 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5594 return false; 5595 Ptr = LD->getBasePtr(); 5596 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5597 if (ST->isIndexed()) 5598 return false; 5599 VT = ST->getMemoryVT(); 5600 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5601 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5602 return false; 5603 Ptr = ST->getBasePtr(); 5604 isLoad = false; 5605 } else { 5606 return false; 5607 } 5608 5609 if (Ptr.getNode()->hasOneUse()) 5610 return false; 5611 5612 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5613 E = Ptr.getNode()->use_end(); I != E; ++I) { 5614 SDNode *Op = *I; 5615 if (Op == N || 5616 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5617 continue; 5618 5619 SDValue BasePtr; 5620 SDValue Offset; 5621 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5622 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5623 // Don't create a indexed load / store with zero offset. 5624 if (isa<ConstantSDNode>(Offset) && 5625 cast<ConstantSDNode>(Offset)->isNullValue()) 5626 continue; 5627 5628 // Try turning it into a post-indexed load / store except when 5629 // 1) All uses are load / store ops that use it as base ptr. 5630 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5631 // nor a successor of N. Otherwise, if Op is folded that would 5632 // create a cycle. 5633 5634 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5635 continue; 5636 5637 // Check for #1. 5638 bool TryNext = false; 5639 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5640 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5641 SDNode *Use = *II; 5642 if (Use == Ptr.getNode()) 5643 continue; 5644 5645 // If all the uses are load / store addresses, then don't do the 5646 // transformation. 5647 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5648 bool RealUse = false; 5649 for (SDNode::use_iterator III = Use->use_begin(), 5650 EEE = Use->use_end(); III != EEE; ++III) { 5651 SDNode *UseUse = *III; 5652 if (!((UseUse->getOpcode() == ISD::LOAD && 5653 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5654 (UseUse->getOpcode() == ISD::STORE && 5655 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5656 RealUse = true; 5657 } 5658 5659 if (!RealUse) { 5660 TryNext = true; 5661 break; 5662 } 5663 } 5664 } 5665 5666 if (TryNext) 5667 continue; 5668 5669 // Check for #2 5670 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5671 SDValue Result = isLoad 5672 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5673 BasePtr, Offset, AM) 5674 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5675 BasePtr, Offset, AM); 5676 ++PostIndexedNodes; 5677 ++NodesCombined; 5678 DEBUG(dbgs() << "\nReplacing.5 "; 5679 N->dump(&DAG); 5680 dbgs() << "\nWith: "; 5681 Result.getNode()->dump(&DAG); 5682 dbgs() << '\n'); 5683 WorkListRemover DeadNodes(*this); 5684 if (isLoad) { 5685 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5686 &DeadNodes); 5687 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5688 &DeadNodes); 5689 } else { 5690 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5691 &DeadNodes); 5692 } 5693 5694 // Finally, since the node is now dead, remove it from the graph. 5695 DAG.DeleteNode(N); 5696 5697 // Replace the uses of Use with uses of the updated base value. 5698 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5699 Result.getValue(isLoad ? 1 : 0), 5700 &DeadNodes); 5701 removeFromWorkList(Op); 5702 DAG.DeleteNode(Op); 5703 return true; 5704 } 5705 } 5706 } 5707 5708 return false; 5709} 5710 5711SDValue DAGCombiner::visitLOAD(SDNode *N) { 5712 LoadSDNode *LD = cast<LoadSDNode>(N); 5713 SDValue Chain = LD->getChain(); 5714 SDValue Ptr = LD->getBasePtr(); 5715 5716 // If load is not volatile and there are no uses of the loaded value (and 5717 // the updated indexed value in case of indexed loads), change uses of the 5718 // chain value into uses of the chain input (i.e. delete the dead load). 5719 if (!LD->isVolatile()) { 5720 if (N->getValueType(1) == MVT::Other) { 5721 // Unindexed loads. 5722 if (N->hasNUsesOfValue(0, 0)) { 5723 // It's not safe to use the two value CombineTo variant here. e.g. 5724 // v1, chain2 = load chain1, loc 5725 // v2, chain3 = load chain2, loc 5726 // v3 = add v2, c 5727 // Now we replace use of chain2 with chain1. This makes the second load 5728 // isomorphic to the one we are deleting, and thus makes this load live. 5729 DEBUG(dbgs() << "\nReplacing.6 "; 5730 N->dump(&DAG); 5731 dbgs() << "\nWith chain: "; 5732 Chain.getNode()->dump(&DAG); 5733 dbgs() << "\n"); 5734 WorkListRemover DeadNodes(*this); 5735 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5736 5737 if (N->use_empty()) { 5738 removeFromWorkList(N); 5739 DAG.DeleteNode(N); 5740 } 5741 5742 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5743 } 5744 } else { 5745 // Indexed loads. 5746 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5747 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5748 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5749 DEBUG(dbgs() << "\nReplacing.7 "; 5750 N->dump(&DAG); 5751 dbgs() << "\nWith: "; 5752 Undef.getNode()->dump(&DAG); 5753 dbgs() << " and 2 other values\n"); 5754 WorkListRemover DeadNodes(*this); 5755 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5756 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5757 DAG.getUNDEF(N->getValueType(1)), 5758 &DeadNodes); 5759 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5760 removeFromWorkList(N); 5761 DAG.DeleteNode(N); 5762 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5763 } 5764 } 5765 } 5766 5767 // If this load is directly stored, replace the load value with the stored 5768 // value. 5769 // TODO: Handle store large -> read small portion. 5770 // TODO: Handle TRUNCSTORE/LOADEXT 5771 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5772 !LD->isVolatile()) { 5773 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5774 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5775 if (PrevST->getBasePtr() == Ptr && 5776 PrevST->getValue().getValueType() == N->getValueType(0)) 5777 return CombineTo(N, Chain.getOperand(1), Chain); 5778 } 5779 } 5780 5781 // Try to infer better alignment information than the load already has. 5782 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5783 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5784 if (Align > LD->getAlignment()) 5785 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 5786 N->getDebugLoc(), 5787 Chain, Ptr, LD->getPointerInfo(), 5788 LD->getMemoryVT(), 5789 LD->isVolatile(), LD->isNonTemporal(), Align); 5790 } 5791 } 5792 5793 if (CombinerAA) { 5794 // Walk up chain skipping non-aliasing memory nodes. 5795 SDValue BetterChain = FindBetterChain(N, Chain); 5796 5797 // If there is a better chain. 5798 if (Chain != BetterChain) { 5799 SDValue ReplLoad; 5800 5801 // Replace the chain to void dependency. 5802 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5803 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5804 BetterChain, Ptr, LD->getPointerInfo(), 5805 LD->isVolatile(), LD->isNonTemporal(), 5806 LD->getAlignment()); 5807 } else { 5808 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 5809 LD->getDebugLoc(), 5810 BetterChain, Ptr, LD->getPointerInfo(), 5811 LD->getMemoryVT(), 5812 LD->isVolatile(), 5813 LD->isNonTemporal(), 5814 LD->getAlignment()); 5815 } 5816 5817 // Create token factor to keep old chain connected. 5818 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5819 MVT::Other, Chain, ReplLoad.getValue(1)); 5820 5821 // Make sure the new and old chains are cleaned up. 5822 AddToWorkList(Token.getNode()); 5823 5824 // Replace uses with load result and token factor. Don't add users 5825 // to work list. 5826 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5827 } 5828 } 5829 5830 // Try transforming N to an indexed load. 5831 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5832 return SDValue(N, 0); 5833 5834 return SDValue(); 5835} 5836 5837/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5838/// load is having specific bytes cleared out. If so, return the byte size 5839/// being masked out and the shift amount. 5840static std::pair<unsigned, unsigned> 5841CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5842 std::pair<unsigned, unsigned> Result(0, 0); 5843 5844 // Check for the structure we're looking for. 5845 if (V->getOpcode() != ISD::AND || 5846 !isa<ConstantSDNode>(V->getOperand(1)) || 5847 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5848 return Result; 5849 5850 // Check the chain and pointer. 5851 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5852 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5853 5854 // The store should be chained directly to the load or be an operand of a 5855 // tokenfactor. 5856 if (LD == Chain.getNode()) 5857 ; // ok. 5858 else if (Chain->getOpcode() != ISD::TokenFactor) 5859 return Result; // Fail. 5860 else { 5861 bool isOk = false; 5862 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5863 if (Chain->getOperand(i).getNode() == LD) { 5864 isOk = true; 5865 break; 5866 } 5867 if (!isOk) return Result; 5868 } 5869 5870 // This only handles simple types. 5871 if (V.getValueType() != MVT::i16 && 5872 V.getValueType() != MVT::i32 && 5873 V.getValueType() != MVT::i64) 5874 return Result; 5875 5876 // Check the constant mask. Invert it so that the bits being masked out are 5877 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5878 // follow the sign bit for uniformity. 5879 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5880 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5881 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5882 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5883 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5884 if (NotMaskLZ == 64) return Result; // All zero mask. 5885 5886 // See if we have a continuous run of bits. If so, we have 0*1+0* 5887 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5888 return Result; 5889 5890 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5891 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5892 NotMaskLZ -= 64-V.getValueSizeInBits(); 5893 5894 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5895 switch (MaskedBytes) { 5896 case 1: 5897 case 2: 5898 case 4: break; 5899 default: return Result; // All one mask, or 5-byte mask. 5900 } 5901 5902 // Verify that the first bit starts at a multiple of mask so that the access 5903 // is aligned the same as the access width. 5904 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 5905 5906 Result.first = MaskedBytes; 5907 Result.second = NotMaskTZ/8; 5908 return Result; 5909} 5910 5911 5912/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 5913/// provides a value as specified by MaskInfo. If so, replace the specified 5914/// store with a narrower store of truncated IVal. 5915static SDNode * 5916ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 5917 SDValue IVal, StoreSDNode *St, 5918 DAGCombiner *DC) { 5919 unsigned NumBytes = MaskInfo.first; 5920 unsigned ByteShift = MaskInfo.second; 5921 SelectionDAG &DAG = DC->getDAG(); 5922 5923 // Check to see if IVal is all zeros in the part being masked in by the 'or' 5924 // that uses this. If not, this is not a replacement. 5925 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 5926 ByteShift*8, (ByteShift+NumBytes)*8); 5927 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 5928 5929 // Check that it is legal on the target to do this. It is legal if the new 5930 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 5931 // legalization. 5932 MVT VT = MVT::getIntegerVT(NumBytes*8); 5933 if (!DC->isTypeLegal(VT)) 5934 return 0; 5935 5936 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 5937 // shifted by ByteShift and truncated down to NumBytes. 5938 if (ByteShift) 5939 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 5940 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy())); 5941 5942 // Figure out the offset for the store and the alignment of the access. 5943 unsigned StOffset; 5944 unsigned NewAlign = St->getAlignment(); 5945 5946 if (DAG.getTargetLoweringInfo().isLittleEndian()) 5947 StOffset = ByteShift; 5948 else 5949 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 5950 5951 SDValue Ptr = St->getBasePtr(); 5952 if (StOffset) { 5953 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 5954 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 5955 NewAlign = MinAlign(NewAlign, StOffset); 5956 } 5957 5958 // Truncate down to the new size. 5959 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 5960 5961 ++OpsNarrowed; 5962 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 5963 St->getPointerInfo().getWithOffset(StOffset), 5964 false, false, NewAlign).getNode(); 5965} 5966 5967 5968/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5969/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5970/// of the loaded bits, try narrowing the load and store if it would end up 5971/// being a win for performance or code size. 5972SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5973 StoreSDNode *ST = cast<StoreSDNode>(N); 5974 if (ST->isVolatile()) 5975 return SDValue(); 5976 5977 SDValue Chain = ST->getChain(); 5978 SDValue Value = ST->getValue(); 5979 SDValue Ptr = ST->getBasePtr(); 5980 EVT VT = Value.getValueType(); 5981 5982 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5983 return SDValue(); 5984 5985 unsigned Opc = Value.getOpcode(); 5986 5987 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 5988 // is a byte mask indicating a consecutive number of bytes, check to see if 5989 // Y is known to provide just those bytes. If so, we try to replace the 5990 // load + replace + store sequence with a single (narrower) store, which makes 5991 // the load dead. 5992 if (Opc == ISD::OR) { 5993 std::pair<unsigned, unsigned> MaskedLoad; 5994 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 5995 if (MaskedLoad.first) 5996 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5997 Value.getOperand(1), ST,this)) 5998 return SDValue(NewST, 0); 5999 6000 // Or is commutative, so try swapping X and Y. 6001 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6002 if (MaskedLoad.first) 6003 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6004 Value.getOperand(0), ST,this)) 6005 return SDValue(NewST, 0); 6006 } 6007 6008 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6009 Value.getOperand(1).getOpcode() != ISD::Constant) 6010 return SDValue(); 6011 6012 SDValue N0 = Value.getOperand(0); 6013 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6014 Chain == SDValue(N0.getNode(), 1)) { 6015 LoadSDNode *LD = cast<LoadSDNode>(N0); 6016 if (LD->getBasePtr() != Ptr || 6017 LD->getPointerInfo().getAddrSpace() != 6018 ST->getPointerInfo().getAddrSpace()) 6019 return SDValue(); 6020 6021 // Find the type to narrow it the load / op / store to. 6022 SDValue N1 = Value.getOperand(1); 6023 unsigned BitWidth = N1.getValueSizeInBits(); 6024 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6025 if (Opc == ISD::AND) 6026 Imm ^= APInt::getAllOnesValue(BitWidth); 6027 if (Imm == 0 || Imm.isAllOnesValue()) 6028 return SDValue(); 6029 unsigned ShAmt = Imm.countTrailingZeros(); 6030 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6031 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6032 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6033 while (NewBW < BitWidth && 6034 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6035 TLI.isNarrowingProfitable(VT, NewVT))) { 6036 NewBW = NextPowerOf2(NewBW); 6037 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6038 } 6039 if (NewBW >= BitWidth) 6040 return SDValue(); 6041 6042 // If the lsb changed does not start at the type bitwidth boundary, 6043 // start at the previous one. 6044 if (ShAmt % NewBW) 6045 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6046 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6047 if ((Imm & Mask) == Imm) { 6048 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6049 if (Opc == ISD::AND) 6050 NewImm ^= APInt::getAllOnesValue(NewBW); 6051 uint64_t PtrOff = ShAmt / 8; 6052 // For big endian targets, we need to adjust the offset to the pointer to 6053 // load the correct bytes. 6054 if (TLI.isBigEndian()) 6055 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6056 6057 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6058 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6059 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6060 return SDValue(); 6061 6062 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6063 Ptr.getValueType(), Ptr, 6064 DAG.getConstant(PtrOff, Ptr.getValueType())); 6065 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6066 LD->getChain(), NewPtr, 6067 LD->getPointerInfo().getWithOffset(PtrOff), 6068 LD->isVolatile(), LD->isNonTemporal(), 6069 NewAlign); 6070 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6071 DAG.getConstant(NewImm, NewVT)); 6072 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6073 NewVal, NewPtr, 6074 ST->getPointerInfo().getWithOffset(PtrOff), 6075 false, false, NewAlign); 6076 6077 AddToWorkList(NewPtr.getNode()); 6078 AddToWorkList(NewLD.getNode()); 6079 AddToWorkList(NewVal.getNode()); 6080 WorkListRemover DeadNodes(*this); 6081 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6082 &DeadNodes); 6083 ++OpsNarrowed; 6084 return NewST; 6085 } 6086 } 6087 6088 return SDValue(); 6089} 6090 6091SDValue DAGCombiner::visitSTORE(SDNode *N) { 6092 StoreSDNode *ST = cast<StoreSDNode>(N); 6093 SDValue Chain = ST->getChain(); 6094 SDValue Value = ST->getValue(); 6095 SDValue Ptr = ST->getBasePtr(); 6096 6097 // If this is a store of a bit convert, store the input value if the 6098 // resultant store does not need a higher alignment than the original. 6099 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6100 ST->isUnindexed()) { 6101 unsigned OrigAlign = ST->getAlignment(); 6102 EVT SVT = Value.getOperand(0).getValueType(); 6103 unsigned Align = TLI.getTargetData()-> 6104 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6105 if (Align <= OrigAlign && 6106 ((!LegalOperations && !ST->isVolatile()) || 6107 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6108 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6109 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6110 ST->isNonTemporal(), OrigAlign); 6111 } 6112 6113 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6114 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6115 // NOTE: If the original store is volatile, this transform must not increase 6116 // the number of stores. For example, on x86-32 an f64 can be stored in one 6117 // processor operation but an i64 (which is not legal) requires two. So the 6118 // transform should not be done in this case. 6119 if (Value.getOpcode() != ISD::TargetConstantFP) { 6120 SDValue Tmp; 6121 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6122 default: llvm_unreachable("Unknown FP type"); 6123 case MVT::f80: // We don't do this for these yet. 6124 case MVT::f128: 6125 case MVT::ppcf128: 6126 break; 6127 case MVT::f32: 6128 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6129 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6130 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6131 bitcastToAPInt().getZExtValue(), MVT::i32); 6132 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6133 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6134 ST->isNonTemporal(), ST->getAlignment()); 6135 } 6136 break; 6137 case MVT::f64: 6138 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6139 !ST->isVolatile()) || 6140 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6141 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6142 getZExtValue(), MVT::i64); 6143 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6144 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6145 ST->isNonTemporal(), ST->getAlignment()); 6146 } else if (!ST->isVolatile() && 6147 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6148 // Many FP stores are not made apparent until after legalize, e.g. for 6149 // argument passing. Since this is so common, custom legalize the 6150 // 64-bit integer store into two 32-bit stores. 6151 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6152 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6153 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6154 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6155 6156 unsigned Alignment = ST->getAlignment(); 6157 bool isVolatile = ST->isVolatile(); 6158 bool isNonTemporal = ST->isNonTemporal(); 6159 6160 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6161 Ptr, ST->getPointerInfo(), 6162 isVolatile, isNonTemporal, 6163 ST->getAlignment()); 6164 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6165 DAG.getConstant(4, Ptr.getValueType())); 6166 Alignment = MinAlign(Alignment, 4U); 6167 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6168 Ptr, ST->getPointerInfo().getWithOffset(4), 6169 isVolatile, isNonTemporal, 6170 Alignment); 6171 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6172 St0, St1); 6173 } 6174 6175 break; 6176 } 6177 } 6178 } 6179 6180 // Try to infer better alignment information than the store already has. 6181 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6182 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6183 if (Align > ST->getAlignment()) 6184 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6185 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6186 ST->isVolatile(), ST->isNonTemporal(), Align); 6187 } 6188 } 6189 6190 if (CombinerAA) { 6191 // Walk up chain skipping non-aliasing memory nodes. 6192 SDValue BetterChain = FindBetterChain(N, Chain); 6193 6194 // If there is a better chain. 6195 if (Chain != BetterChain) { 6196 SDValue ReplStore; 6197 6198 // Replace the chain to avoid dependency. 6199 if (ST->isTruncatingStore()) { 6200 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6201 ST->getPointerInfo(), 6202 ST->getMemoryVT(), ST->isVolatile(), 6203 ST->isNonTemporal(), ST->getAlignment()); 6204 } else { 6205 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6206 ST->getPointerInfo(), 6207 ST->isVolatile(), ST->isNonTemporal(), 6208 ST->getAlignment()); 6209 } 6210 6211 // Create token to keep both nodes around. 6212 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6213 MVT::Other, Chain, ReplStore); 6214 6215 // Make sure the new and old chains are cleaned up. 6216 AddToWorkList(Token.getNode()); 6217 6218 // Don't add users to work list. 6219 return CombineTo(N, Token, false); 6220 } 6221 } 6222 6223 // Try transforming N to an indexed store. 6224 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6225 return SDValue(N, 0); 6226 6227 // FIXME: is there such a thing as a truncating indexed store? 6228 if (ST->isTruncatingStore() && ST->isUnindexed() && 6229 Value.getValueType().isInteger()) { 6230 // See if we can simplify the input to this truncstore with knowledge that 6231 // only the low bits are being used. For example: 6232 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6233 SDValue Shorter = 6234 GetDemandedBits(Value, 6235 APInt::getLowBitsSet(Value.getValueSizeInBits(), 6236 ST->getMemoryVT().getSizeInBits())); 6237 AddToWorkList(Value.getNode()); 6238 if (Shorter.getNode()) 6239 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6240 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6241 ST->isVolatile(), ST->isNonTemporal(), 6242 ST->getAlignment()); 6243 6244 // Otherwise, see if we can simplify the operation with 6245 // SimplifyDemandedBits, which only works if the value has a single use. 6246 if (SimplifyDemandedBits(Value, 6247 APInt::getLowBitsSet( 6248 Value.getValueType().getScalarType().getSizeInBits(), 6249 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6250 return SDValue(N, 0); 6251 } 6252 6253 // If this is a load followed by a store to the same location, then the store 6254 // is dead/noop. 6255 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6256 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6257 ST->isUnindexed() && !ST->isVolatile() && 6258 // There can't be any side effects between the load and store, such as 6259 // a call or store. 6260 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6261 // The store is dead, remove it. 6262 return Chain; 6263 } 6264 } 6265 6266 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6267 // truncating store. We can do this even if this is already a truncstore. 6268 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6269 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6270 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6271 ST->getMemoryVT())) { 6272 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6273 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6274 ST->isVolatile(), ST->isNonTemporal(), 6275 ST->getAlignment()); 6276 } 6277 6278 return ReduceLoadOpStoreWidth(N); 6279} 6280 6281SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6282 SDValue InVec = N->getOperand(0); 6283 SDValue InVal = N->getOperand(1); 6284 SDValue EltNo = N->getOperand(2); 6285 6286 // If the inserted element is an UNDEF, just use the input vector. 6287 if (InVal.getOpcode() == ISD::UNDEF) 6288 return InVec; 6289 6290 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6291 // vector with the inserted element. 6292 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6293 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6294 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6295 InVec.getNode()->op_end()); 6296 if (Elt < Ops.size()) 6297 Ops[Elt] = InVal; 6298 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6299 InVec.getValueType(), &Ops[0], Ops.size()); 6300 } 6301 // If the invec is an UNDEF and if EltNo is a constant, create a new 6302 // BUILD_VECTOR with undef elements and the inserted element. 6303 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 6304 isa<ConstantSDNode>(EltNo)) { 6305 EVT VT = InVec.getValueType(); 6306 EVT EltVT = VT.getVectorElementType(); 6307 unsigned NElts = VT.getVectorNumElements(); 6308 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6309 6310 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6311 if (Elt < Ops.size()) 6312 Ops[Elt] = InVal; 6313 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6314 InVec.getValueType(), &Ops[0], Ops.size()); 6315 } 6316 return SDValue(); 6317} 6318 6319SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6320 // (vextract (scalar_to_vector val, 0) -> val 6321 SDValue InVec = N->getOperand(0); 6322 6323 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6324 // Check if the result type doesn't match the inserted element type. A 6325 // SCALAR_TO_VECTOR may truncate the inserted element and the 6326 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6327 SDValue InOp = InVec.getOperand(0); 6328 EVT NVT = N->getValueType(0); 6329 if (InOp.getValueType() != NVT) { 6330 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6331 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6332 } 6333 return InOp; 6334 } 6335 6336 // Perform only after legalization to ensure build_vector / vector_shuffle 6337 // optimizations have already been done. 6338 if (!LegalOperations) return SDValue(); 6339 6340 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6341 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6342 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6343 SDValue EltNo = N->getOperand(1); 6344 6345 if (isa<ConstantSDNode>(EltNo)) { 6346 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6347 bool NewLoad = false; 6348 bool BCNumEltsChanged = false; 6349 EVT VT = InVec.getValueType(); 6350 EVT ExtVT = VT.getVectorElementType(); 6351 EVT LVT = ExtVT; 6352 6353 if (InVec.getOpcode() == ISD::BITCAST) { 6354 EVT BCVT = InVec.getOperand(0).getValueType(); 6355 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6356 return SDValue(); 6357 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6358 BCNumEltsChanged = true; 6359 InVec = InVec.getOperand(0); 6360 ExtVT = BCVT.getVectorElementType(); 6361 NewLoad = true; 6362 } 6363 6364 LoadSDNode *LN0 = NULL; 6365 const ShuffleVectorSDNode *SVN = NULL; 6366 if (ISD::isNormalLoad(InVec.getNode())) { 6367 LN0 = cast<LoadSDNode>(InVec); 6368 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6369 InVec.getOperand(0).getValueType() == ExtVT && 6370 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6371 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6372 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6373 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6374 // => 6375 // (load $addr+1*size) 6376 6377 // If the bit convert changed the number of elements, it is unsafe 6378 // to examine the mask. 6379 if (BCNumEltsChanged) 6380 return SDValue(); 6381 6382 // Select the input vector, guarding against out of range extract vector. 6383 unsigned NumElems = VT.getVectorNumElements(); 6384 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 6385 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6386 6387 if (InVec.getOpcode() == ISD::BITCAST) 6388 InVec = InVec.getOperand(0); 6389 if (ISD::isNormalLoad(InVec.getNode())) { 6390 LN0 = cast<LoadSDNode>(InVec); 6391 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6392 } 6393 } 6394 6395 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 6396 return SDValue(); 6397 6398 // If Idx was -1 above, Elt is going to be -1, so just return undef. 6399 if (Elt == -1) 6400 return DAG.getUNDEF(LN0->getBasePtr().getValueType()); 6401 6402 unsigned Align = LN0->getAlignment(); 6403 if (NewLoad) { 6404 // Check the resultant load doesn't need a higher alignment than the 6405 // original load. 6406 unsigned NewAlign = 6407 TLI.getTargetData() 6408 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6409 6410 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6411 return SDValue(); 6412 6413 Align = NewAlign; 6414 } 6415 6416 SDValue NewPtr = LN0->getBasePtr(); 6417 unsigned PtrOff = 0; 6418 6419 if (Elt) { 6420 PtrOff = LVT.getSizeInBits() * Elt / 8; 6421 EVT PtrType = NewPtr.getValueType(); 6422 if (TLI.isBigEndian()) 6423 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6424 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6425 DAG.getConstant(PtrOff, PtrType)); 6426 } 6427 6428 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6429 LN0->getPointerInfo().getWithOffset(PtrOff), 6430 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6431 } 6432 6433 return SDValue(); 6434} 6435 6436SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6437 unsigned NumInScalars = N->getNumOperands(); 6438 EVT VT = N->getValueType(0); 6439 6440 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6441 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6442 // at most two distinct vectors, turn this into a shuffle node. 6443 SDValue VecIn1, VecIn2; 6444 for (unsigned i = 0; i != NumInScalars; ++i) { 6445 // Ignore undef inputs. 6446 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6447 6448 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6449 // constant index, bail out. 6450 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6451 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6452 VecIn1 = VecIn2 = SDValue(0, 0); 6453 break; 6454 } 6455 6456 // If the input vector type disagrees with the result of the build_vector, 6457 // we can't make a shuffle. 6458 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6459 if (ExtractedFromVec.getValueType() != VT) { 6460 VecIn1 = VecIn2 = SDValue(0, 0); 6461 break; 6462 } 6463 6464 // Otherwise, remember this. We allow up to two distinct input vectors. 6465 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6466 continue; 6467 6468 if (VecIn1.getNode() == 0) { 6469 VecIn1 = ExtractedFromVec; 6470 } else if (VecIn2.getNode() == 0) { 6471 VecIn2 = ExtractedFromVec; 6472 } else { 6473 // Too many inputs. 6474 VecIn1 = VecIn2 = SDValue(0, 0); 6475 break; 6476 } 6477 } 6478 6479 // If everything is good, we can make a shuffle operation. 6480 if (VecIn1.getNode()) { 6481 SmallVector<int, 8> Mask; 6482 for (unsigned i = 0; i != NumInScalars; ++i) { 6483 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6484 Mask.push_back(-1); 6485 continue; 6486 } 6487 6488 // If extracting from the first vector, just use the index directly. 6489 SDValue Extract = N->getOperand(i); 6490 SDValue ExtVal = Extract.getOperand(1); 6491 if (Extract.getOperand(0) == VecIn1) { 6492 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6493 if (ExtIndex > VT.getVectorNumElements()) 6494 return SDValue(); 6495 6496 Mask.push_back(ExtIndex); 6497 continue; 6498 } 6499 6500 // Otherwise, use InIdx + VecSize 6501 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6502 Mask.push_back(Idx+NumInScalars); 6503 } 6504 6505 // Add count and size info. 6506 if (!isTypeLegal(VT)) 6507 return SDValue(); 6508 6509 // Return the new VECTOR_SHUFFLE node. 6510 SDValue Ops[2]; 6511 Ops[0] = VecIn1; 6512 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6513 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6514 } 6515 6516 return SDValue(); 6517} 6518 6519SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6520 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6521 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6522 // inputs come from at most two distinct vectors, turn this into a shuffle 6523 // node. 6524 6525 // If we only have one input vector, we don't need to do any concatenation. 6526 if (N->getNumOperands() == 1) 6527 return N->getOperand(0); 6528 6529 return SDValue(); 6530} 6531 6532SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6533 EVT VT = N->getValueType(0); 6534 unsigned NumElts = VT.getVectorNumElements(); 6535 6536 SDValue N0 = N->getOperand(0); 6537 6538 assert(N0.getValueType().getVectorNumElements() == NumElts && 6539 "Vector shuffle must be normalized in DAG"); 6540 6541 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6542 6543 // If it is a splat, check if the argument vector is another splat or a 6544 // build_vector with all scalar elements the same. 6545 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 6546 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 6547 SDNode *V = N0.getNode(); 6548 6549 // If this is a bit convert that changes the element type of the vector but 6550 // not the number of vector elements, look through it. Be careful not to 6551 // look though conversions that change things like v4f32 to v2f64. 6552 if (V->getOpcode() == ISD::BITCAST) { 6553 SDValue ConvInput = V->getOperand(0); 6554 if (ConvInput.getValueType().isVector() && 6555 ConvInput.getValueType().getVectorNumElements() == NumElts) 6556 V = ConvInput.getNode(); 6557 } 6558 6559 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6560 assert(V->getNumOperands() == NumElts && 6561 "BUILD_VECTOR has wrong number of operands"); 6562 SDValue Base; 6563 bool AllSame = true; 6564 for (unsigned i = 0; i != NumElts; ++i) { 6565 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6566 Base = V->getOperand(i); 6567 break; 6568 } 6569 } 6570 // Splat of <u, u, u, u>, return <u, u, u, u> 6571 if (!Base.getNode()) 6572 return N0; 6573 for (unsigned i = 0; i != NumElts; ++i) { 6574 if (V->getOperand(i) != Base) { 6575 AllSame = false; 6576 break; 6577 } 6578 } 6579 // Splat of <x, x, x, x>, return <x, x, x, x> 6580 if (AllSame) 6581 return N0; 6582 } 6583 } 6584 return SDValue(); 6585} 6586 6587SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 6588 if (!TLI.getShouldFoldAtomicFences()) 6589 return SDValue(); 6590 6591 SDValue atomic = N->getOperand(0); 6592 switch (atomic.getOpcode()) { 6593 case ISD::ATOMIC_CMP_SWAP: 6594 case ISD::ATOMIC_SWAP: 6595 case ISD::ATOMIC_LOAD_ADD: 6596 case ISD::ATOMIC_LOAD_SUB: 6597 case ISD::ATOMIC_LOAD_AND: 6598 case ISD::ATOMIC_LOAD_OR: 6599 case ISD::ATOMIC_LOAD_XOR: 6600 case ISD::ATOMIC_LOAD_NAND: 6601 case ISD::ATOMIC_LOAD_MIN: 6602 case ISD::ATOMIC_LOAD_MAX: 6603 case ISD::ATOMIC_LOAD_UMIN: 6604 case ISD::ATOMIC_LOAD_UMAX: 6605 break; 6606 default: 6607 return SDValue(); 6608 } 6609 6610 SDValue fence = atomic.getOperand(0); 6611 if (fence.getOpcode() != ISD::MEMBARRIER) 6612 return SDValue(); 6613 6614 switch (atomic.getOpcode()) { 6615 case ISD::ATOMIC_CMP_SWAP: 6616 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6617 fence.getOperand(0), 6618 atomic.getOperand(1), atomic.getOperand(2), 6619 atomic.getOperand(3)), atomic.getResNo()); 6620 case ISD::ATOMIC_SWAP: 6621 case ISD::ATOMIC_LOAD_ADD: 6622 case ISD::ATOMIC_LOAD_SUB: 6623 case ISD::ATOMIC_LOAD_AND: 6624 case ISD::ATOMIC_LOAD_OR: 6625 case ISD::ATOMIC_LOAD_XOR: 6626 case ISD::ATOMIC_LOAD_NAND: 6627 case ISD::ATOMIC_LOAD_MIN: 6628 case ISD::ATOMIC_LOAD_MAX: 6629 case ISD::ATOMIC_LOAD_UMIN: 6630 case ISD::ATOMIC_LOAD_UMAX: 6631 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6632 fence.getOperand(0), 6633 atomic.getOperand(1), atomic.getOperand(2)), 6634 atomic.getResNo()); 6635 default: 6636 return SDValue(); 6637 } 6638} 6639 6640/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6641/// an AND to a vector_shuffle with the destination vector and a zero vector. 6642/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6643/// vector_shuffle V, Zero, <0, 4, 2, 4> 6644SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6645 EVT VT = N->getValueType(0); 6646 DebugLoc dl = N->getDebugLoc(); 6647 SDValue LHS = N->getOperand(0); 6648 SDValue RHS = N->getOperand(1); 6649 if (N->getOpcode() == ISD::AND) { 6650 if (RHS.getOpcode() == ISD::BITCAST) 6651 RHS = RHS.getOperand(0); 6652 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6653 SmallVector<int, 8> Indices; 6654 unsigned NumElts = RHS.getNumOperands(); 6655 for (unsigned i = 0; i != NumElts; ++i) { 6656 SDValue Elt = RHS.getOperand(i); 6657 if (!isa<ConstantSDNode>(Elt)) 6658 return SDValue(); 6659 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6660 Indices.push_back(i); 6661 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6662 Indices.push_back(NumElts); 6663 else 6664 return SDValue(); 6665 } 6666 6667 // Let's see if the target supports this vector_shuffle. 6668 EVT RVT = RHS.getValueType(); 6669 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6670 return SDValue(); 6671 6672 // Return the new VECTOR_SHUFFLE node. 6673 EVT EltVT = RVT.getVectorElementType(); 6674 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6675 DAG.getConstant(0, EltVT)); 6676 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6677 RVT, &ZeroOps[0], ZeroOps.size()); 6678 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 6679 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6680 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 6681 } 6682 } 6683 6684 return SDValue(); 6685} 6686 6687/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6688SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6689 // After legalize, the target may be depending on adds and other 6690 // binary ops to provide legal ways to construct constants or other 6691 // things. Simplifying them may result in a loss of legality. 6692 if (LegalOperations) return SDValue(); 6693 6694 assert(N->getValueType(0).isVector() && 6695 "SimplifyVBinOp only works on vectors!"); 6696 6697 SDValue LHS = N->getOperand(0); 6698 SDValue RHS = N->getOperand(1); 6699 SDValue Shuffle = XformToShuffleWithZero(N); 6700 if (Shuffle.getNode()) return Shuffle; 6701 6702 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6703 // this operation. 6704 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6705 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6706 SmallVector<SDValue, 8> Ops; 6707 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6708 SDValue LHSOp = LHS.getOperand(i); 6709 SDValue RHSOp = RHS.getOperand(i); 6710 // If these two elements can't be folded, bail out. 6711 if ((LHSOp.getOpcode() != ISD::UNDEF && 6712 LHSOp.getOpcode() != ISD::Constant && 6713 LHSOp.getOpcode() != ISD::ConstantFP) || 6714 (RHSOp.getOpcode() != ISD::UNDEF && 6715 RHSOp.getOpcode() != ISD::Constant && 6716 RHSOp.getOpcode() != ISD::ConstantFP)) 6717 break; 6718 6719 // Can't fold divide by zero. 6720 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6721 N->getOpcode() == ISD::FDIV) { 6722 if ((RHSOp.getOpcode() == ISD::Constant && 6723 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6724 (RHSOp.getOpcode() == ISD::ConstantFP && 6725 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6726 break; 6727 } 6728 6729 EVT VT = LHSOp.getValueType(); 6730 assert(RHSOp.getValueType() == VT && 6731 "SimplifyVBinOp with different BUILD_VECTOR element types"); 6732 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 6733 LHSOp, RHSOp); 6734 if (FoldOp.getOpcode() != ISD::UNDEF && 6735 FoldOp.getOpcode() != ISD::Constant && 6736 FoldOp.getOpcode() != ISD::ConstantFP) 6737 break; 6738 Ops.push_back(FoldOp); 6739 AddToWorkList(FoldOp.getNode()); 6740 } 6741 6742 if (Ops.size() == LHS.getNumOperands()) 6743 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6744 LHS.getValueType(), &Ops[0], Ops.size()); 6745 } 6746 6747 return SDValue(); 6748} 6749 6750SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6751 SDValue N1, SDValue N2){ 6752 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6753 6754 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6755 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6756 6757 // If we got a simplified select_cc node back from SimplifySelectCC, then 6758 // break it down into a new SETCC node, and a new SELECT node, and then return 6759 // the SELECT node, since we were called with a SELECT node. 6760 if (SCC.getNode()) { 6761 // Check to see if we got a select_cc back (to turn into setcc/select). 6762 // Otherwise, just return whatever node we got back, like fabs. 6763 if (SCC.getOpcode() == ISD::SELECT_CC) { 6764 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6765 N0.getValueType(), 6766 SCC.getOperand(0), SCC.getOperand(1), 6767 SCC.getOperand(4)); 6768 AddToWorkList(SETCC.getNode()); 6769 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6770 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6771 } 6772 6773 return SCC; 6774 } 6775 return SDValue(); 6776} 6777 6778/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6779/// are the two values being selected between, see if we can simplify the 6780/// select. Callers of this should assume that TheSelect is deleted if this 6781/// returns true. As such, they should return the appropriate thing (e.g. the 6782/// node) back to the top-level of the DAG combiner loop to avoid it being 6783/// looked at. 6784bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6785 SDValue RHS) { 6786 6787 // If this is a select from two identical things, try to pull the operation 6788 // through the select. 6789 if (LHS.getOpcode() != RHS.getOpcode() || 6790 !LHS.hasOneUse() || !RHS.hasOneUse()) 6791 return false; 6792 6793 // If this is a load and the token chain is identical, replace the select 6794 // of two loads with a load through a select of the address to load from. 6795 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6796 // constants have been dropped into the constant pool. 6797 if (LHS.getOpcode() == ISD::LOAD) { 6798 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6799 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6800 6801 // Token chains must be identical. 6802 if (LHS.getOperand(0) != RHS.getOperand(0) || 6803 // Do not let this transformation reduce the number of volatile loads. 6804 LLD->isVolatile() || RLD->isVolatile() || 6805 // If this is an EXTLOAD, the VT's must match. 6806 LLD->getMemoryVT() != RLD->getMemoryVT() || 6807 // If this is an EXTLOAD, the kind of extension must match. 6808 (LLD->getExtensionType() != RLD->getExtensionType() && 6809 // The only exception is if one of the extensions is anyext. 6810 LLD->getExtensionType() != ISD::EXTLOAD && 6811 RLD->getExtensionType() != ISD::EXTLOAD) || 6812 // FIXME: this discards src value information. This is 6813 // over-conservative. It would be beneficial to be able to remember 6814 // both potential memory locations. Since we are discarding 6815 // src value info, don't do the transformation if the memory 6816 // locations are not in the default address space. 6817 LLD->getPointerInfo().getAddrSpace() != 0 || 6818 RLD->getPointerInfo().getAddrSpace() != 0) 6819 return false; 6820 6821 // Check that the select condition doesn't reach either load. If so, 6822 // folding this will induce a cycle into the DAG. If not, this is safe to 6823 // xform, so create a select of the addresses. 6824 SDValue Addr; 6825 if (TheSelect->getOpcode() == ISD::SELECT) { 6826 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 6827 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 6828 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 6829 return false; 6830 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 6831 LLD->getBasePtr().getValueType(), 6832 TheSelect->getOperand(0), LLD->getBasePtr(), 6833 RLD->getBasePtr()); 6834 } else { // Otherwise SELECT_CC 6835 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 6836 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 6837 6838 if ((LLD->hasAnyUseOfValue(1) && 6839 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 6840 (LLD->hasAnyUseOfValue(1) && 6841 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 6842 return false; 6843 6844 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 6845 LLD->getBasePtr().getValueType(), 6846 TheSelect->getOperand(0), 6847 TheSelect->getOperand(1), 6848 LLD->getBasePtr(), RLD->getBasePtr(), 6849 TheSelect->getOperand(4)); 6850 } 6851 6852 SDValue Load; 6853 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 6854 Load = DAG.getLoad(TheSelect->getValueType(0), 6855 TheSelect->getDebugLoc(), 6856 // FIXME: Discards pointer info. 6857 LLD->getChain(), Addr, MachinePointerInfo(), 6858 LLD->isVolatile(), LLD->isNonTemporal(), 6859 LLD->getAlignment()); 6860 } else { 6861 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 6862 RLD->getExtensionType() : LLD->getExtensionType(), 6863 TheSelect->getValueType(0), 6864 TheSelect->getDebugLoc(), 6865 // FIXME: Discards pointer info. 6866 LLD->getChain(), Addr, MachinePointerInfo(), 6867 LLD->getMemoryVT(), LLD->isVolatile(), 6868 LLD->isNonTemporal(), LLD->getAlignment()); 6869 } 6870 6871 // Users of the select now use the result of the load. 6872 CombineTo(TheSelect, Load); 6873 6874 // Users of the old loads now use the new load's chain. We know the 6875 // old-load value is dead now. 6876 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 6877 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 6878 return true; 6879 } 6880 6881 return false; 6882} 6883 6884/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 6885/// where 'cond' is the comparison specified by CC. 6886SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 6887 SDValue N2, SDValue N3, 6888 ISD::CondCode CC, bool NotExtCompare) { 6889 // (x ? y : y) -> y. 6890 if (N2 == N3) return N2; 6891 6892 EVT VT = N2.getValueType(); 6893 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 6894 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 6895 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 6896 6897 // Determine if the condition we're dealing with is constant 6898 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 6899 N0, N1, CC, DL, false); 6900 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 6901 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 6902 6903 // fold select_cc true, x, y -> x 6904 if (SCCC && !SCCC->isNullValue()) 6905 return N2; 6906 // fold select_cc false, x, y -> y 6907 if (SCCC && SCCC->isNullValue()) 6908 return N3; 6909 6910 // Check to see if we can simplify the select into an fabs node 6911 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 6912 // Allow either -0.0 or 0.0 6913 if (CFP->getValueAPF().isZero()) { 6914 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 6915 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 6916 N0 == N2 && N3.getOpcode() == ISD::FNEG && 6917 N2 == N3.getOperand(0)) 6918 return DAG.getNode(ISD::FABS, DL, VT, N0); 6919 6920 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 6921 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 6922 N0 == N3 && N2.getOpcode() == ISD::FNEG && 6923 N2.getOperand(0) == N3) 6924 return DAG.getNode(ISD::FABS, DL, VT, N3); 6925 } 6926 } 6927 6928 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 6929 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 6930 // in it. This is a win when the constant is not otherwise available because 6931 // it replaces two constant pool loads with one. We only do this if the FP 6932 // type is known to be legal, because if it isn't, then we are before legalize 6933 // types an we want the other legalization to happen first (e.g. to avoid 6934 // messing with soft float) and if the ConstantFP is not legal, because if 6935 // it is legal, we may not need to store the FP constant in a constant pool. 6936 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 6937 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 6938 if (TLI.isTypeLegal(N2.getValueType()) && 6939 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 6940 TargetLowering::Legal) && 6941 // If both constants have multiple uses, then we won't need to do an 6942 // extra load, they are likely around in registers for other users. 6943 (TV->hasOneUse() || FV->hasOneUse())) { 6944 Constant *Elts[] = { 6945 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6946 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6947 }; 6948 const Type *FPTy = Elts[0]->getType(); 6949 const TargetData &TD = *TLI.getTargetData(); 6950 6951 // Create a ConstantArray of the two constants. 6952 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6953 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6954 TD.getPrefTypeAlignment(FPTy)); 6955 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6956 6957 // Get the offsets to the 0 and 1 element of the array so that we can 6958 // select between them. 6959 SDValue Zero = DAG.getIntPtrConstant(0); 6960 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6961 SDValue One = DAG.getIntPtrConstant(EltSize); 6962 6963 SDValue Cond = DAG.getSetCC(DL, 6964 TLI.getSetCCResultType(N0.getValueType()), 6965 N0, N1, CC); 6966 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6967 Cond, One, Zero); 6968 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6969 CstOffset); 6970 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6971 MachinePointerInfo::getConstantPool(), false, 6972 false, Alignment); 6973 6974 } 6975 } 6976 6977 // Check to see if we can perform the "gzip trick", transforming 6978 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6979 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6980 N0.getValueType().isInteger() && 6981 N2.getValueType().isInteger() && 6982 (N1C->isNullValue() || // (a < 0) ? b : 0 6983 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6984 EVT XType = N0.getValueType(); 6985 EVT AType = N2.getValueType(); 6986 if (XType.bitsGE(AType)) { 6987 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6988 // single-bit constant. 6989 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6990 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6991 ShCtV = XType.getSizeInBits()-ShCtV-1; 6992 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6993 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6994 XType, N0, ShCt); 6995 AddToWorkList(Shift.getNode()); 6996 6997 if (XType.bitsGT(AType)) { 6998 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6999 AddToWorkList(Shift.getNode()); 7000 } 7001 7002 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7003 } 7004 7005 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 7006 XType, N0, 7007 DAG.getConstant(XType.getSizeInBits()-1, 7008 getShiftAmountTy())); 7009 AddToWorkList(Shift.getNode()); 7010 7011 if (XType.bitsGT(AType)) { 7012 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7013 AddToWorkList(Shift.getNode()); 7014 } 7015 7016 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7017 } 7018 } 7019 7020 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 7021 // where y is has a single bit set. 7022 // A plaintext description would be, we can turn the SELECT_CC into an AND 7023 // when the condition can be materialized as an all-ones register. Any 7024 // single bit-test can be materialized as an all-ones register with 7025 // shift-left and shift-right-arith. 7026 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 7027 N0->getValueType(0) == VT && 7028 N1C && N1C->isNullValue() && 7029 N2C && N2C->isNullValue()) { 7030 SDValue AndLHS = N0->getOperand(0); 7031 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 7032 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 7033 // Shift the tested bit over the sign bit. 7034 APInt AndMask = ConstAndRHS->getAPIntValue(); 7035 SDValue ShlAmt = 7036 DAG.getConstant(AndMask.countLeadingZeros(), getShiftAmountTy()); 7037 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 7038 7039 // Now arithmetic right shift it all the way over, so the result is either 7040 // all-ones, or zero. 7041 SDValue ShrAmt = 7042 DAG.getConstant(AndMask.getBitWidth()-1, getShiftAmountTy()); 7043 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 7044 7045 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 7046 } 7047 } 7048 7049 // fold select C, 16, 0 -> shl C, 4 7050 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 7051 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 7052 7053 // If the caller doesn't want us to simplify this into a zext of a compare, 7054 // don't do it. 7055 if (NotExtCompare && N2C->getAPIntValue() == 1) 7056 return SDValue(); 7057 7058 // Get a SetCC of the condition 7059 // FIXME: Should probably make sure that setcc is legal if we ever have a 7060 // target where it isn't. 7061 SDValue Temp, SCC; 7062 // cast from setcc result type to select result type 7063 if (LegalTypes) { 7064 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 7065 N0, N1, CC); 7066 if (N2.getValueType().bitsLT(SCC.getValueType())) 7067 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 7068 else 7069 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7070 N2.getValueType(), SCC); 7071 } else { 7072 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 7073 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7074 N2.getValueType(), SCC); 7075 } 7076 7077 AddToWorkList(SCC.getNode()); 7078 AddToWorkList(Temp.getNode()); 7079 7080 if (N2C->getAPIntValue() == 1) 7081 return Temp; 7082 7083 // shl setcc result by log2 n2c 7084 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 7085 DAG.getConstant(N2C->getAPIntValue().logBase2(), 7086 getShiftAmountTy())); 7087 } 7088 7089 // Check to see if this is the equivalent of setcc 7090 // FIXME: Turn all of these into setcc if setcc if setcc is legal 7091 // otherwise, go ahead with the folds. 7092 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 7093 EVT XType = N0.getValueType(); 7094 if (!LegalOperations || 7095 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 7096 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 7097 if (Res.getValueType() != VT) 7098 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 7099 return Res; 7100 } 7101 7102 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 7103 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 7104 (!LegalOperations || 7105 TLI.isOperationLegal(ISD::CTLZ, XType))) { 7106 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 7107 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 7108 DAG.getConstant(Log2_32(XType.getSizeInBits()), 7109 getShiftAmountTy())); 7110 } 7111 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 7112 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 7113 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 7114 XType, DAG.getConstant(0, XType), N0); 7115 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 7116 return DAG.getNode(ISD::SRL, DL, XType, 7117 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 7118 DAG.getConstant(XType.getSizeInBits()-1, 7119 getShiftAmountTy())); 7120 } 7121 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 7122 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 7123 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 7124 DAG.getConstant(XType.getSizeInBits()-1, 7125 getShiftAmountTy())); 7126 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 7127 } 7128 } 7129 7130 // Check to see if this is an integer abs. 7131 // select_cc setg[te] X, 0, X, -X -> 7132 // select_cc setgt X, -1, X, -X -> 7133 // select_cc setl[te] X, 0, -X, X -> 7134 // select_cc setlt X, 1, -X, X -> 7135 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 7136 if (N1C) { 7137 ConstantSDNode *SubC = NULL; 7138 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 7139 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 7140 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7141 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7142 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7143 (N1C->isOne() && CC == ISD::SETLT)) && 7144 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7145 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7146 7147 EVT XType = N0.getValueType(); 7148 if (SubC && SubC->isNullValue() && XType.isInteger()) { 7149 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7150 N0, 7151 DAG.getConstant(XType.getSizeInBits()-1, 7152 getShiftAmountTy())); 7153 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7154 XType, N0, Shift); 7155 AddToWorkList(Shift.getNode()); 7156 AddToWorkList(Add.getNode()); 7157 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7158 } 7159 } 7160 7161 return SDValue(); 7162} 7163 7164/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 7165SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 7166 SDValue N1, ISD::CondCode Cond, 7167 DebugLoc DL, bool foldBooleans) { 7168 TargetLowering::DAGCombinerInfo 7169 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 7170 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 7171} 7172 7173/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 7174/// return a DAG expression to select that will generate the same value by 7175/// multiplying by a magic number. See: 7176/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7177SDValue DAGCombiner::BuildSDIV(SDNode *N) { 7178 std::vector<SDNode*> Built; 7179 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 7180 7181 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7182 ii != ee; ++ii) 7183 AddToWorkList(*ii); 7184 return S; 7185} 7186 7187/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 7188/// return a DAG expression to select that will generate the same value by 7189/// multiplying by a magic number. See: 7190/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7191SDValue DAGCombiner::BuildUDIV(SDNode *N) { 7192 std::vector<SDNode*> Built; 7193 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 7194 7195 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7196 ii != ee; ++ii) 7197 AddToWorkList(*ii); 7198 return S; 7199} 7200 7201/// FindBaseOffset - Return true if base is a frame index, which is known not 7202// to alias with anything but itself. Provides base object and offset as 7203// results. 7204static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7205 const GlobalValue *&GV, void *&CV) { 7206 // Assume it is a primitive operation. 7207 Base = Ptr; Offset = 0; GV = 0; CV = 0; 7208 7209 // If it's an adding a simple constant then integrate the offset. 7210 if (Base.getOpcode() == ISD::ADD) { 7211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7212 Base = Base.getOperand(0); 7213 Offset += C->getZExtValue(); 7214 } 7215 } 7216 7217 // Return the underlying GlobalValue, and update the Offset. Return false 7218 // for GlobalAddressSDNode since the same GlobalAddress may be represented 7219 // by multiple nodes with different offsets. 7220 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7221 GV = G->getGlobal(); 7222 Offset += G->getOffset(); 7223 return false; 7224 } 7225 7226 // Return the underlying Constant value, and update the Offset. Return false 7227 // for ConstantSDNodes since the same constant pool entry may be represented 7228 // by multiple nodes with different offsets. 7229 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7230 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7231 : (void *)C->getConstVal(); 7232 Offset += C->getOffset(); 7233 return false; 7234 } 7235 // If it's any of the following then it can't alias with anything but itself. 7236 return isa<FrameIndexSDNode>(Base); 7237} 7238 7239/// isAlias - Return true if there is any possibility that the two addresses 7240/// overlap. 7241bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7242 const Value *SrcValue1, int SrcValueOffset1, 7243 unsigned SrcValueAlign1, 7244 const MDNode *TBAAInfo1, 7245 SDValue Ptr2, int64_t Size2, 7246 const Value *SrcValue2, int SrcValueOffset2, 7247 unsigned SrcValueAlign2, 7248 const MDNode *TBAAInfo2) const { 7249 // If they are the same then they must be aliases. 7250 if (Ptr1 == Ptr2) return true; 7251 7252 // Gather base node and offset information. 7253 SDValue Base1, Base2; 7254 int64_t Offset1, Offset2; 7255 const GlobalValue *GV1, *GV2; 7256 void *CV1, *CV2; 7257 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7258 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7259 7260 // If they have a same base address then check to see if they overlap. 7261 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7262 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7263 7264 // It is possible for different frame indices to alias each other, mostly 7265 // when tail call optimization reuses return address slots for arguments. 7266 // To catch this case, look up the actual index of frame indices to compute 7267 // the real alias relationship. 7268 if (isFrameIndex1 && isFrameIndex2) { 7269 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7270 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7271 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7272 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7273 } 7274 7275 // Otherwise, if we know what the bases are, and they aren't identical, then 7276 // we know they cannot alias. 7277 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7278 return false; 7279 7280 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7281 // compared to the size and offset of the access, we may be able to prove they 7282 // do not alias. This check is conservative for now to catch cases created by 7283 // splitting vector types. 7284 if ((SrcValueAlign1 == SrcValueAlign2) && 7285 (SrcValueOffset1 != SrcValueOffset2) && 7286 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7287 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7288 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7289 7290 // There is no overlap between these relatively aligned accesses of similar 7291 // size, return no alias. 7292 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7293 return false; 7294 } 7295 7296 if (CombinerGlobalAA) { 7297 // Use alias analysis information. 7298 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7299 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7300 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7301 AliasAnalysis::AliasResult AAResult = 7302 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 7303 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 7304 if (AAResult == AliasAnalysis::NoAlias) 7305 return false; 7306 } 7307 7308 // Otherwise we have to assume they alias. 7309 return true; 7310} 7311 7312/// FindAliasInfo - Extracts the relevant alias information from the memory 7313/// node. Returns true if the operand was a load. 7314bool DAGCombiner::FindAliasInfo(SDNode *N, 7315 SDValue &Ptr, int64_t &Size, 7316 const Value *&SrcValue, 7317 int &SrcValueOffset, 7318 unsigned &SrcValueAlign, 7319 const MDNode *&TBAAInfo) const { 7320 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7321 Ptr = LD->getBasePtr(); 7322 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7323 SrcValue = LD->getSrcValue(); 7324 SrcValueOffset = LD->getSrcValueOffset(); 7325 SrcValueAlign = LD->getOriginalAlignment(); 7326 TBAAInfo = LD->getTBAAInfo(); 7327 return true; 7328 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7329 Ptr = ST->getBasePtr(); 7330 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7331 SrcValue = ST->getSrcValue(); 7332 SrcValueOffset = ST->getSrcValueOffset(); 7333 SrcValueAlign = ST->getOriginalAlignment(); 7334 TBAAInfo = ST->getTBAAInfo(); 7335 } else { 7336 llvm_unreachable("FindAliasInfo expected a memory operand"); 7337 } 7338 7339 return false; 7340} 7341 7342/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7343/// looking for aliasing nodes and adding them to the Aliases vector. 7344void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7345 SmallVector<SDValue, 8> &Aliases) { 7346 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7347 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7348 7349 // Get alias information for node. 7350 SDValue Ptr; 7351 int64_t Size; 7352 const Value *SrcValue; 7353 int SrcValueOffset; 7354 unsigned SrcValueAlign; 7355 const MDNode *SrcTBAAInfo; 7356 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7357 SrcValueAlign, SrcTBAAInfo); 7358 7359 // Starting off. 7360 Chains.push_back(OriginalChain); 7361 unsigned Depth = 0; 7362 7363 // Look at each chain and determine if it is an alias. If so, add it to the 7364 // aliases list. If not, then continue up the chain looking for the next 7365 // candidate. 7366 while (!Chains.empty()) { 7367 SDValue Chain = Chains.back(); 7368 Chains.pop_back(); 7369 7370 // For TokenFactor nodes, look at each operand and only continue up the 7371 // chain until we find two aliases. If we've seen two aliases, assume we'll 7372 // find more and revert to original chain since the xform is unlikely to be 7373 // profitable. 7374 // 7375 // FIXME: The depth check could be made to return the last non-aliasing 7376 // chain we found before we hit a tokenfactor rather than the original 7377 // chain. 7378 if (Depth > 6 || Aliases.size() == 2) { 7379 Aliases.clear(); 7380 Aliases.push_back(OriginalChain); 7381 break; 7382 } 7383 7384 // Don't bother if we've been before. 7385 if (!Visited.insert(Chain.getNode())) 7386 continue; 7387 7388 switch (Chain.getOpcode()) { 7389 case ISD::EntryToken: 7390 // Entry token is ideal chain operand, but handled in FindBetterChain. 7391 break; 7392 7393 case ISD::LOAD: 7394 case ISD::STORE: { 7395 // Get alias information for Chain. 7396 SDValue OpPtr; 7397 int64_t OpSize; 7398 const Value *OpSrcValue; 7399 int OpSrcValueOffset; 7400 unsigned OpSrcValueAlign; 7401 const MDNode *OpSrcTBAAInfo; 7402 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7403 OpSrcValue, OpSrcValueOffset, 7404 OpSrcValueAlign, 7405 OpSrcTBAAInfo); 7406 7407 // If chain is alias then stop here. 7408 if (!(IsLoad && IsOpLoad) && 7409 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7410 SrcTBAAInfo, 7411 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7412 OpSrcValueAlign, OpSrcTBAAInfo)) { 7413 Aliases.push_back(Chain); 7414 } else { 7415 // Look further up the chain. 7416 Chains.push_back(Chain.getOperand(0)); 7417 ++Depth; 7418 } 7419 break; 7420 } 7421 7422 case ISD::TokenFactor: 7423 // We have to check each of the operands of the token factor for "small" 7424 // token factors, so we queue them up. Adding the operands to the queue 7425 // (stack) in reverse order maintains the original order and increases the 7426 // likelihood that getNode will find a matching token factor (CSE.) 7427 if (Chain.getNumOperands() > 16) { 7428 Aliases.push_back(Chain); 7429 break; 7430 } 7431 for (unsigned n = Chain.getNumOperands(); n;) 7432 Chains.push_back(Chain.getOperand(--n)); 7433 ++Depth; 7434 break; 7435 7436 default: 7437 // For all other instructions we will just have to take what we can get. 7438 Aliases.push_back(Chain); 7439 break; 7440 } 7441 } 7442} 7443 7444/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7445/// for a better chain (aliasing node.) 7446SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7447 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7448 7449 // Accumulate all the aliases to this node. 7450 GatherAllAliases(N, OldChain, Aliases); 7451 7452 if (Aliases.size() == 0) { 7453 // If no operands then chain to entry token. 7454 return DAG.getEntryNode(); 7455 } else if (Aliases.size() == 1) { 7456 // If a single operand then chain to it. We don't need to revisit it. 7457 return Aliases[0]; 7458 } 7459 7460 // Construct a custom tailored token factor. 7461 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7462 &Aliases[0], Aliases.size()); 7463} 7464 7465// SelectionDAG::Combine - This is the entry point for the file. 7466// 7467void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7468 CodeGenOpt::Level OptLevel) { 7469 /// run - This is the main entry point to this class. 7470 /// 7471 DAGCombiner(*this, AA, OptLevel).Run(Level); 7472} 7473