DAGCombiner.cpp revision 454627252b1cc43e81949d41eb20e9ea9560da58
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue SimplifyVUnaryOp(SDNode *N); 198 SDValue visitSHL(SDNode *N); 199 SDValue visitSRA(SDNode *N); 200 SDValue visitSRL(SDNode *N); 201 SDValue visitCTLZ(SDNode *N); 202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 203 SDValue visitCTTZ(SDNode *N); 204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 205 SDValue visitCTPOP(SDNode *N); 206 SDValue visitSELECT(SDNode *N); 207 SDValue visitSELECT_CC(SDNode *N); 208 SDValue visitSETCC(SDNode *N); 209 SDValue visitSIGN_EXTEND(SDNode *N); 210 SDValue visitZERO_EXTEND(SDNode *N); 211 SDValue visitANY_EXTEND(SDNode *N); 212 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 213 SDValue visitTRUNCATE(SDNode *N); 214 SDValue visitBITCAST(SDNode *N); 215 SDValue visitBUILD_PAIR(SDNode *N); 216 SDValue visitFADD(SDNode *N); 217 SDValue visitFSUB(SDNode *N); 218 SDValue visitFMUL(SDNode *N); 219 SDValue visitFMA(SDNode *N); 220 SDValue visitFDIV(SDNode *N); 221 SDValue visitFREM(SDNode *N); 222 SDValue visitFCOPYSIGN(SDNode *N); 223 SDValue visitSINT_TO_FP(SDNode *N); 224 SDValue visitUINT_TO_FP(SDNode *N); 225 SDValue visitFP_TO_SINT(SDNode *N); 226 SDValue visitFP_TO_UINT(SDNode *N); 227 SDValue visitFP_ROUND(SDNode *N); 228 SDValue visitFP_ROUND_INREG(SDNode *N); 229 SDValue visitFP_EXTEND(SDNode *N); 230 SDValue visitFNEG(SDNode *N); 231 SDValue visitFABS(SDNode *N); 232 SDValue visitFCEIL(SDNode *N); 233 SDValue visitFTRUNC(SDNode *N); 234 SDValue visitFFLOOR(SDNode *N); 235 SDValue visitBRCOND(SDNode *N); 236 SDValue visitBR_CC(SDNode *N); 237 SDValue visitLOAD(SDNode *N); 238 SDValue visitSTORE(SDNode *N); 239 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 241 SDValue visitBUILD_VECTOR(SDNode *N); 242 SDValue visitCONCAT_VECTORS(SDNode *N); 243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 244 SDValue visitVECTOR_SHUFFLE(SDNode *N); 245 SDValue visitMEMBARRIER(SDNode *N); 246 247 SDValue XformToShuffleWithZero(SDNode *N); 248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 249 250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 251 252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 256 SDValue N3, ISD::CondCode CC, 257 bool NotExtCompare = false); 258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 259 DebugLoc DL, bool foldBooleans = true); 260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 261 unsigned HiOp); 262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 264 SDValue BuildSDIV(SDNode *N); 265 SDValue BuildUDIV(SDNode *N); 266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 267 bool DemandHighBits = true); 268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 270 SDValue ReduceLoadWidth(SDNode *N); 271 SDValue ReduceLoadOpStoreWidth(SDNode *N); 272 SDValue TransformFPLoadStorePair(SDNode *N); 273 274 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 275 276 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 277 /// looking for aliasing nodes and adding them to the Aliases vector. 278 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 279 SmallVector<SDValue, 8> &Aliases); 280 281 /// isAlias - Return true if there is any possibility that the two addresses 282 /// overlap. 283 bool isAlias(SDValue Ptr1, int64_t Size1, 284 const Value *SrcValue1, int SrcValueOffset1, 285 unsigned SrcValueAlign1, 286 const MDNode *TBAAInfo1, 287 SDValue Ptr2, int64_t Size2, 288 const Value *SrcValue2, int SrcValueOffset2, 289 unsigned SrcValueAlign2, 290 const MDNode *TBAAInfo2) const; 291 292 /// FindAliasInfo - Extracts the relevant alias information from the memory 293 /// node. Returns true if the operand was a load. 294 bool FindAliasInfo(SDNode *N, 295 SDValue &Ptr, int64_t &Size, 296 const Value *&SrcValue, int &SrcValueOffset, 297 unsigned &SrcValueAlignment, 298 const MDNode *&TBAAInfo) const; 299 300 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 301 /// looking for a better chain (aliasing node.) 302 SDValue FindBetterChain(SDNode *N, SDValue Chain); 303 304 public: 305 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 306 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 307 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 308 309 /// Run - runs the dag combiner on all nodes in the work list 310 void Run(CombineLevel AtLevel); 311 312 SelectionDAG &getDAG() const { return DAG; } 313 314 /// getShiftAmountTy - Returns a type large enough to hold any valid 315 /// shift amount - before type legalization these can be huge. 316 EVT getShiftAmountTy(EVT LHSTy) { 317 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 318 } 319 320 /// isTypeLegal - This method returns true if we are running before type 321 /// legalization or if the specified VT is legal. 322 bool isTypeLegal(const EVT &VT) { 323 if (!LegalTypes) return true; 324 return TLI.isTypeLegal(VT); 325 } 326 }; 327} 328 329 330namespace { 331/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 332/// nodes from the worklist. 333class WorkListRemover : public SelectionDAG::DAGUpdateListener { 334 DAGCombiner &DC; 335public: 336 explicit WorkListRemover(DAGCombiner &dc) 337 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 338 339 virtual void NodeDeleted(SDNode *N, SDNode *E) { 340 DC.removeFromWorkList(N); 341 } 342}; 343} 344 345//===----------------------------------------------------------------------===// 346// TargetLowering::DAGCombinerInfo implementation 347//===----------------------------------------------------------------------===// 348 349void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 350 ((DAGCombiner*)DC)->AddToWorkList(N); 351} 352 353void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 354 ((DAGCombiner*)DC)->removeFromWorkList(N); 355} 356 357SDValue TargetLowering::DAGCombinerInfo:: 358CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 359 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 360} 361 362SDValue TargetLowering::DAGCombinerInfo:: 363CombineTo(SDNode *N, SDValue Res, bool AddTo) { 364 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 365} 366 367 368SDValue TargetLowering::DAGCombinerInfo:: 369CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 370 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 371} 372 373void TargetLowering::DAGCombinerInfo:: 374CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 375 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 376} 377 378//===----------------------------------------------------------------------===// 379// Helper Functions 380//===----------------------------------------------------------------------===// 381 382/// isNegatibleForFree - Return 1 if we can compute the negated form of the 383/// specified expression for the same cost as the expression itself, or 2 if we 384/// can compute the negated form more cheaply than the expression itself. 385static char isNegatibleForFree(SDValue Op, bool LegalOperations, 386 const TargetLowering &TLI, 387 const TargetOptions *Options, 388 unsigned Depth = 0) { 389 // No compile time optimizations on this type. 390 if (Op.getValueType() == MVT::ppcf128) 391 return 0; 392 393 // fneg is removable even if it has multiple uses. 394 if (Op.getOpcode() == ISD::FNEG) return 2; 395 396 // Don't allow anything with multiple uses. 397 if (!Op.hasOneUse()) return 0; 398 399 // Don't recurse exponentially. 400 if (Depth > 6) return 0; 401 402 switch (Op.getOpcode()) { 403 default: return false; 404 case ISD::ConstantFP: 405 // Don't invert constant FP values after legalize. The negated constant 406 // isn't necessarily legal. 407 return LegalOperations ? 0 : 1; 408 case ISD::FADD: 409 // FIXME: determine better conditions for this xform. 410 if (!Options->UnsafeFPMath) return 0; 411 412 // After operation legalization, it might not be legal to create new FSUBs. 413 if (LegalOperations && 414 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 415 return 0; 416 417 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 418 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 419 Options, Depth + 1)) 420 return V; 421 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 422 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 423 Depth + 1); 424 case ISD::FSUB: 425 // We can't turn -(A-B) into B-A when we honor signed zeros. 426 if (!Options->UnsafeFPMath) return 0; 427 428 // fold (fneg (fsub A, B)) -> (fsub B, A) 429 return 1; 430 431 case ISD::FMUL: 432 case ISD::FDIV: 433 if (Options->HonorSignDependentRoundingFPMath()) return 0; 434 435 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 436 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 437 Options, Depth + 1)) 438 return V; 439 440 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 441 Depth + 1); 442 443 case ISD::FP_EXTEND: 444 case ISD::FP_ROUND: 445 case ISD::FSIN: 446 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 447 Depth + 1); 448 } 449} 450 451/// GetNegatedExpression - If isNegatibleForFree returns true, this function 452/// returns the newly negated expression. 453static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 454 bool LegalOperations, unsigned Depth = 0) { 455 // fneg is removable even if it has multiple uses. 456 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 457 458 // Don't allow anything with multiple uses. 459 assert(Op.hasOneUse() && "Unknown reuse!"); 460 461 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 462 switch (Op.getOpcode()) { 463 default: llvm_unreachable("Unknown code"); 464 case ISD::ConstantFP: { 465 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 466 V.changeSign(); 467 return DAG.getConstantFP(V, Op.getValueType()); 468 } 469 case ISD::FADD: 470 // FIXME: determine better conditions for this xform. 471 assert(DAG.getTarget().Options.UnsafeFPMath); 472 473 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 474 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 475 DAG.getTargetLoweringInfo(), 476 &DAG.getTarget().Options, Depth+1)) 477 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 478 GetNegatedExpression(Op.getOperand(0), DAG, 479 LegalOperations, Depth+1), 480 Op.getOperand(1)); 481 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 482 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 483 GetNegatedExpression(Op.getOperand(1), DAG, 484 LegalOperations, Depth+1), 485 Op.getOperand(0)); 486 case ISD::FSUB: 487 // We can't turn -(A-B) into B-A when we honor signed zeros. 488 assert(DAG.getTarget().Options.UnsafeFPMath); 489 490 // fold (fneg (fsub 0, B)) -> B 491 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 492 if (N0CFP->getValueAPF().isZero()) 493 return Op.getOperand(1); 494 495 // fold (fneg (fsub A, B)) -> (fsub B, A) 496 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 497 Op.getOperand(1), Op.getOperand(0)); 498 499 case ISD::FMUL: 500 case ISD::FDIV: 501 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 502 503 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 504 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 505 DAG.getTargetLoweringInfo(), 506 &DAG.getTarget().Options, Depth+1)) 507 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 508 GetNegatedExpression(Op.getOperand(0), DAG, 509 LegalOperations, Depth+1), 510 Op.getOperand(1)); 511 512 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 513 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 514 Op.getOperand(0), 515 GetNegatedExpression(Op.getOperand(1), DAG, 516 LegalOperations, Depth+1)); 517 518 case ISD::FP_EXTEND: 519 case ISD::FSIN: 520 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 521 GetNegatedExpression(Op.getOperand(0), DAG, 522 LegalOperations, Depth+1)); 523 case ISD::FP_ROUND: 524 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 525 GetNegatedExpression(Op.getOperand(0), DAG, 526 LegalOperations, Depth+1), 527 Op.getOperand(1)); 528 } 529} 530 531 532// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 533// that selects between the values 1 and 0, making it equivalent to a setcc. 534// Also, set the incoming LHS, RHS, and CC references to the appropriate 535// nodes based on the type of node we are checking. This simplifies life a 536// bit for the callers. 537static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 538 SDValue &CC) { 539 if (N.getOpcode() == ISD::SETCC) { 540 LHS = N.getOperand(0); 541 RHS = N.getOperand(1); 542 CC = N.getOperand(2); 543 return true; 544 } 545 if (N.getOpcode() == ISD::SELECT_CC && 546 N.getOperand(2).getOpcode() == ISD::Constant && 547 N.getOperand(3).getOpcode() == ISD::Constant && 548 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 549 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 550 LHS = N.getOperand(0); 551 RHS = N.getOperand(1); 552 CC = N.getOperand(4); 553 return true; 554 } 555 return false; 556} 557 558// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 559// one use. If this is true, it allows the users to invert the operation for 560// free when it is profitable to do so. 561static bool isOneUseSetCC(SDValue N) { 562 SDValue N0, N1, N2; 563 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 564 return true; 565 return false; 566} 567 568SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 569 SDValue N0, SDValue N1) { 570 EVT VT = N0.getValueType(); 571 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 572 if (isa<ConstantSDNode>(N1)) { 573 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 574 SDValue OpNode = 575 DAG.FoldConstantArithmetic(Opc, VT, 576 cast<ConstantSDNode>(N0.getOperand(1)), 577 cast<ConstantSDNode>(N1)); 578 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 579 } 580 if (N0.hasOneUse()) { 581 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 582 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 583 N0.getOperand(0), N1); 584 AddToWorkList(OpNode.getNode()); 585 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 586 } 587 } 588 589 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 590 if (isa<ConstantSDNode>(N0)) { 591 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 592 SDValue OpNode = 593 DAG.FoldConstantArithmetic(Opc, VT, 594 cast<ConstantSDNode>(N1.getOperand(1)), 595 cast<ConstantSDNode>(N0)); 596 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 597 } 598 if (N1.hasOneUse()) { 599 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 600 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 601 N1.getOperand(0), N0); 602 AddToWorkList(OpNode.getNode()); 603 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 604 } 605 } 606 607 return SDValue(); 608} 609 610SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 611 bool AddTo) { 612 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 613 ++NodesCombined; 614 DEBUG(dbgs() << "\nReplacing.1 "; 615 N->dump(&DAG); 616 dbgs() << "\nWith: "; 617 To[0].getNode()->dump(&DAG); 618 dbgs() << " and " << NumTo-1 << " other values\n"; 619 for (unsigned i = 0, e = NumTo; i != e; ++i) 620 assert((!To[i].getNode() || 621 N->getValueType(i) == To[i].getValueType()) && 622 "Cannot combine value to value of different type!")); 623 WorkListRemover DeadNodes(*this); 624 DAG.ReplaceAllUsesWith(N, To); 625 if (AddTo) { 626 // Push the new nodes and any users onto the worklist 627 for (unsigned i = 0, e = NumTo; i != e; ++i) { 628 if (To[i].getNode()) { 629 AddToWorkList(To[i].getNode()); 630 AddUsersToWorkList(To[i].getNode()); 631 } 632 } 633 } 634 635 // Finally, if the node is now dead, remove it from the graph. The node 636 // may not be dead if the replacement process recursively simplified to 637 // something else needing this node. 638 if (N->use_empty()) { 639 // Nodes can be reintroduced into the worklist. Make sure we do not 640 // process a node that has been replaced. 641 removeFromWorkList(N); 642 643 // Finally, since the node is now dead, remove it from the graph. 644 DAG.DeleteNode(N); 645 } 646 return SDValue(N, 0); 647} 648 649void DAGCombiner:: 650CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 651 // Replace all uses. If any nodes become isomorphic to other nodes and 652 // are deleted, make sure to remove them from our worklist. 653 WorkListRemover DeadNodes(*this); 654 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 655 656 // Push the new node and any (possibly new) users onto the worklist. 657 AddToWorkList(TLO.New.getNode()); 658 AddUsersToWorkList(TLO.New.getNode()); 659 660 // Finally, if the node is now dead, remove it from the graph. The node 661 // may not be dead if the replacement process recursively simplified to 662 // something else needing this node. 663 if (TLO.Old.getNode()->use_empty()) { 664 removeFromWorkList(TLO.Old.getNode()); 665 666 // If the operands of this node are only used by the node, they will now 667 // be dead. Make sure to visit them first to delete dead nodes early. 668 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 669 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 670 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 671 672 DAG.DeleteNode(TLO.Old.getNode()); 673 } 674} 675 676/// SimplifyDemandedBits - Check the specified integer node value to see if 677/// it can be simplified or if things it uses can be simplified by bit 678/// propagation. If so, return true. 679bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 680 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 681 APInt KnownZero, KnownOne; 682 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 683 return false; 684 685 // Revisit the node. 686 AddToWorkList(Op.getNode()); 687 688 // Replace the old value with the new one. 689 ++NodesCombined; 690 DEBUG(dbgs() << "\nReplacing.2 "; 691 TLO.Old.getNode()->dump(&DAG); 692 dbgs() << "\nWith: "; 693 TLO.New.getNode()->dump(&DAG); 694 dbgs() << '\n'); 695 696 CommitTargetLoweringOpt(TLO); 697 return true; 698} 699 700void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 701 DebugLoc dl = Load->getDebugLoc(); 702 EVT VT = Load->getValueType(0); 703 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 704 705 DEBUG(dbgs() << "\nReplacing.9 "; 706 Load->dump(&DAG); 707 dbgs() << "\nWith: "; 708 Trunc.getNode()->dump(&DAG); 709 dbgs() << '\n'); 710 WorkListRemover DeadNodes(*this); 711 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 712 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 713 removeFromWorkList(Load); 714 DAG.DeleteNode(Load); 715 AddToWorkList(Trunc.getNode()); 716} 717 718SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 719 Replace = false; 720 DebugLoc dl = Op.getDebugLoc(); 721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 722 EVT MemVT = LD->getMemoryVT(); 723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 725 : ISD::EXTLOAD) 726 : LD->getExtensionType(); 727 Replace = true; 728 return DAG.getExtLoad(ExtType, dl, PVT, 729 LD->getChain(), LD->getBasePtr(), 730 LD->getPointerInfo(), 731 MemVT, LD->isVolatile(), 732 LD->isNonTemporal(), LD->getAlignment()); 733 } 734 735 unsigned Opc = Op.getOpcode(); 736 switch (Opc) { 737 default: break; 738 case ISD::AssertSext: 739 return DAG.getNode(ISD::AssertSext, dl, PVT, 740 SExtPromoteOperand(Op.getOperand(0), PVT), 741 Op.getOperand(1)); 742 case ISD::AssertZext: 743 return DAG.getNode(ISD::AssertZext, dl, PVT, 744 ZExtPromoteOperand(Op.getOperand(0), PVT), 745 Op.getOperand(1)); 746 case ISD::Constant: { 747 unsigned ExtOpc = 748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 749 return DAG.getNode(ExtOpc, dl, PVT, Op); 750 } 751 } 752 753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 754 return SDValue(); 755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 756} 757 758SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 760 return SDValue(); 761 EVT OldVT = Op.getValueType(); 762 DebugLoc dl = Op.getDebugLoc(); 763 bool Replace = false; 764 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 765 if (NewOp.getNode() == 0) 766 return SDValue(); 767 AddToWorkList(NewOp.getNode()); 768 769 if (Replace) 770 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 772 DAG.getValueType(OldVT)); 773} 774 775SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 776 EVT OldVT = Op.getValueType(); 777 DebugLoc dl = Op.getDebugLoc(); 778 bool Replace = false; 779 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 780 if (NewOp.getNode() == 0) 781 return SDValue(); 782 AddToWorkList(NewOp.getNode()); 783 784 if (Replace) 785 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 786 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 787} 788 789/// PromoteIntBinOp - Promote the specified integer binary operation if the 790/// target indicates it is beneficial. e.g. On x86, it's usually better to 791/// promote i16 operations to i32 since i16 instructions are longer. 792SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 793 if (!LegalOperations) 794 return SDValue(); 795 796 EVT VT = Op.getValueType(); 797 if (VT.isVector() || !VT.isInteger()) 798 return SDValue(); 799 800 // If operation type is 'undesirable', e.g. i16 on x86, consider 801 // promoting it. 802 unsigned Opc = Op.getOpcode(); 803 if (TLI.isTypeDesirableForOp(Opc, VT)) 804 return SDValue(); 805 806 EVT PVT = VT; 807 // Consult target whether it is a good idea to promote this operation and 808 // what's the right type to promote it to. 809 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 810 assert(PVT != VT && "Don't know what type to promote to!"); 811 812 bool Replace0 = false; 813 SDValue N0 = Op.getOperand(0); 814 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 815 if (NN0.getNode() == 0) 816 return SDValue(); 817 818 bool Replace1 = false; 819 SDValue N1 = Op.getOperand(1); 820 SDValue NN1; 821 if (N0 == N1) 822 NN1 = NN0; 823 else { 824 NN1 = PromoteOperand(N1, PVT, Replace1); 825 if (NN1.getNode() == 0) 826 return SDValue(); 827 } 828 829 AddToWorkList(NN0.getNode()); 830 if (NN1.getNode()) 831 AddToWorkList(NN1.getNode()); 832 833 if (Replace0) 834 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 835 if (Replace1) 836 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 837 838 DEBUG(dbgs() << "\nPromoting "; 839 Op.getNode()->dump(&DAG)); 840 DebugLoc dl = Op.getDebugLoc(); 841 return DAG.getNode(ISD::TRUNCATE, dl, VT, 842 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 843 } 844 return SDValue(); 845} 846 847/// PromoteIntShiftOp - Promote the specified integer shift operation if the 848/// target indicates it is beneficial. e.g. On x86, it's usually better to 849/// promote i16 operations to i32 since i16 instructions are longer. 850SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 851 if (!LegalOperations) 852 return SDValue(); 853 854 EVT VT = Op.getValueType(); 855 if (VT.isVector() || !VT.isInteger()) 856 return SDValue(); 857 858 // If operation type is 'undesirable', e.g. i16 on x86, consider 859 // promoting it. 860 unsigned Opc = Op.getOpcode(); 861 if (TLI.isTypeDesirableForOp(Opc, VT)) 862 return SDValue(); 863 864 EVT PVT = VT; 865 // Consult target whether it is a good idea to promote this operation and 866 // what's the right type to promote it to. 867 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 868 assert(PVT != VT && "Don't know what type to promote to!"); 869 870 bool Replace = false; 871 SDValue N0 = Op.getOperand(0); 872 if (Opc == ISD::SRA) 873 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 874 else if (Opc == ISD::SRL) 875 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 876 else 877 N0 = PromoteOperand(N0, PVT, Replace); 878 if (N0.getNode() == 0) 879 return SDValue(); 880 881 AddToWorkList(N0.getNode()); 882 if (Replace) 883 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 884 885 DEBUG(dbgs() << "\nPromoting "; 886 Op.getNode()->dump(&DAG)); 887 DebugLoc dl = Op.getDebugLoc(); 888 return DAG.getNode(ISD::TRUNCATE, dl, VT, 889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 890 } 891 return SDValue(); 892} 893 894SDValue DAGCombiner::PromoteExtend(SDValue Op) { 895 if (!LegalOperations) 896 return SDValue(); 897 898 EVT VT = Op.getValueType(); 899 if (VT.isVector() || !VT.isInteger()) 900 return SDValue(); 901 902 // If operation type is 'undesirable', e.g. i16 on x86, consider 903 // promoting it. 904 unsigned Opc = Op.getOpcode(); 905 if (TLI.isTypeDesirableForOp(Opc, VT)) 906 return SDValue(); 907 908 EVT PVT = VT; 909 // Consult target whether it is a good idea to promote this operation and 910 // what's the right type to promote it to. 911 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 912 assert(PVT != VT && "Don't know what type to promote to!"); 913 // fold (aext (aext x)) -> (aext x) 914 // fold (aext (zext x)) -> (zext x) 915 // fold (aext (sext x)) -> (sext x) 916 DEBUG(dbgs() << "\nPromoting "; 917 Op.getNode()->dump(&DAG)); 918 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 919 } 920 return SDValue(); 921} 922 923bool DAGCombiner::PromoteLoad(SDValue Op) { 924 if (!LegalOperations) 925 return false; 926 927 EVT VT = Op.getValueType(); 928 if (VT.isVector() || !VT.isInteger()) 929 return false; 930 931 // If operation type is 'undesirable', e.g. i16 on x86, consider 932 // promoting it. 933 unsigned Opc = Op.getOpcode(); 934 if (TLI.isTypeDesirableForOp(Opc, VT)) 935 return false; 936 937 EVT PVT = VT; 938 // Consult target whether it is a good idea to promote this operation and 939 // what's the right type to promote it to. 940 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 941 assert(PVT != VT && "Don't know what type to promote to!"); 942 943 DebugLoc dl = Op.getDebugLoc(); 944 SDNode *N = Op.getNode(); 945 LoadSDNode *LD = cast<LoadSDNode>(N); 946 EVT MemVT = LD->getMemoryVT(); 947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 949 : ISD::EXTLOAD) 950 : LD->getExtensionType(); 951 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 952 LD->getChain(), LD->getBasePtr(), 953 LD->getPointerInfo(), 954 MemVT, LD->isVolatile(), 955 LD->isNonTemporal(), LD->getAlignment()); 956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 957 958 DEBUG(dbgs() << "\nPromoting "; 959 N->dump(&DAG); 960 dbgs() << "\nTo: "; 961 Result.getNode()->dump(&DAG); 962 dbgs() << '\n'); 963 WorkListRemover DeadNodes(*this); 964 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 965 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 966 removeFromWorkList(N); 967 DAG.DeleteNode(N); 968 AddToWorkList(Result.getNode()); 969 return true; 970 } 971 return false; 972} 973 974 975//===----------------------------------------------------------------------===// 976// Main DAG Combiner implementation 977//===----------------------------------------------------------------------===// 978 979void DAGCombiner::Run(CombineLevel AtLevel) { 980 // set the instance variables, so that the various visit routines may use it. 981 Level = AtLevel; 982 LegalOperations = Level >= AfterLegalizeVectorOps; 983 LegalTypes = Level >= AfterLegalizeTypes; 984 985 // Add all the dag nodes to the worklist. 986 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 987 E = DAG.allnodes_end(); I != E; ++I) 988 AddToWorkList(I); 989 990 // Create a dummy node (which is not added to allnodes), that adds a reference 991 // to the root node, preventing it from being deleted, and tracking any 992 // changes of the root. 993 HandleSDNode Dummy(DAG.getRoot()); 994 995 // The root of the dag may dangle to deleted nodes until the dag combiner is 996 // done. Set it to null to avoid confusion. 997 DAG.setRoot(SDValue()); 998 999 // while the worklist isn't empty, find a node and 1000 // try and combine it. 1001 while (!WorkListContents.empty()) { 1002 SDNode *N; 1003 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1004 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1005 // worklist *should* contain, and check the node we want to visit is should 1006 // actually be visited. 1007 do { 1008 N = WorkListOrder.pop_back_val(); 1009 } while (!WorkListContents.erase(N)); 1010 1011 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1012 // N is deleted from the DAG, since they too may now be dead or may have a 1013 // reduced number of uses, allowing other xforms. 1014 if (N->use_empty() && N != &Dummy) { 1015 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1016 AddToWorkList(N->getOperand(i).getNode()); 1017 1018 DAG.DeleteNode(N); 1019 continue; 1020 } 1021 1022 SDValue RV = combine(N); 1023 1024 if (RV.getNode() == 0) 1025 continue; 1026 1027 ++NodesCombined; 1028 1029 // If we get back the same node we passed in, rather than a new node or 1030 // zero, we know that the node must have defined multiple values and 1031 // CombineTo was used. Since CombineTo takes care of the worklist 1032 // mechanics for us, we have no work to do in this case. 1033 if (RV.getNode() == N) 1034 continue; 1035 1036 assert(N->getOpcode() != ISD::DELETED_NODE && 1037 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1038 "Node was deleted but visit returned new node!"); 1039 1040 DEBUG(dbgs() << "\nReplacing.3 "; 1041 N->dump(&DAG); 1042 dbgs() << "\nWith: "; 1043 RV.getNode()->dump(&DAG); 1044 dbgs() << '\n'); 1045 1046 // Transfer debug value. 1047 DAG.TransferDbgValues(SDValue(N, 0), RV); 1048 WorkListRemover DeadNodes(*this); 1049 if (N->getNumValues() == RV.getNode()->getNumValues()) 1050 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1051 else { 1052 assert(N->getValueType(0) == RV.getValueType() && 1053 N->getNumValues() == 1 && "Type mismatch"); 1054 SDValue OpV = RV; 1055 DAG.ReplaceAllUsesWith(N, &OpV); 1056 } 1057 1058 // Push the new node and any users onto the worklist 1059 AddToWorkList(RV.getNode()); 1060 AddUsersToWorkList(RV.getNode()); 1061 1062 // Add any uses of the old node to the worklist in case this node is the 1063 // last one that uses them. They may become dead after this node is 1064 // deleted. 1065 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1066 AddToWorkList(N->getOperand(i).getNode()); 1067 1068 // Finally, if the node is now dead, remove it from the graph. The node 1069 // may not be dead if the replacement process recursively simplified to 1070 // something else needing this node. 1071 if (N->use_empty()) { 1072 // Nodes can be reintroduced into the worklist. Make sure we do not 1073 // process a node that has been replaced. 1074 removeFromWorkList(N); 1075 1076 // Finally, since the node is now dead, remove it from the graph. 1077 DAG.DeleteNode(N); 1078 } 1079 } 1080 1081 // If the root changed (e.g. it was a dead load, update the root). 1082 DAG.setRoot(Dummy.getValue()); 1083 DAG.RemoveDeadNodes(); 1084} 1085 1086SDValue DAGCombiner::visit(SDNode *N) { 1087 switch (N->getOpcode()) { 1088 default: break; 1089 case ISD::TokenFactor: return visitTokenFactor(N); 1090 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1091 case ISD::ADD: return visitADD(N); 1092 case ISD::SUB: return visitSUB(N); 1093 case ISD::ADDC: return visitADDC(N); 1094 case ISD::SUBC: return visitSUBC(N); 1095 case ISD::ADDE: return visitADDE(N); 1096 case ISD::SUBE: return visitSUBE(N); 1097 case ISD::MUL: return visitMUL(N); 1098 case ISD::SDIV: return visitSDIV(N); 1099 case ISD::UDIV: return visitUDIV(N); 1100 case ISD::SREM: return visitSREM(N); 1101 case ISD::UREM: return visitUREM(N); 1102 case ISD::MULHU: return visitMULHU(N); 1103 case ISD::MULHS: return visitMULHS(N); 1104 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1105 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1106 case ISD::SMULO: return visitSMULO(N); 1107 case ISD::UMULO: return visitUMULO(N); 1108 case ISD::SDIVREM: return visitSDIVREM(N); 1109 case ISD::UDIVREM: return visitUDIVREM(N); 1110 case ISD::AND: return visitAND(N); 1111 case ISD::OR: return visitOR(N); 1112 case ISD::XOR: return visitXOR(N); 1113 case ISD::SHL: return visitSHL(N); 1114 case ISD::SRA: return visitSRA(N); 1115 case ISD::SRL: return visitSRL(N); 1116 case ISD::CTLZ: return visitCTLZ(N); 1117 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1118 case ISD::CTTZ: return visitCTTZ(N); 1119 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1120 case ISD::CTPOP: return visitCTPOP(N); 1121 case ISD::SELECT: return visitSELECT(N); 1122 case ISD::SELECT_CC: return visitSELECT_CC(N); 1123 case ISD::SETCC: return visitSETCC(N); 1124 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1125 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1126 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1127 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1128 case ISD::TRUNCATE: return visitTRUNCATE(N); 1129 case ISD::BITCAST: return visitBITCAST(N); 1130 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1131 case ISD::FADD: return visitFADD(N); 1132 case ISD::FSUB: return visitFSUB(N); 1133 case ISD::FMUL: return visitFMUL(N); 1134 case ISD::FMA: return visitFMA(N); 1135 case ISD::FDIV: return visitFDIV(N); 1136 case ISD::FREM: return visitFREM(N); 1137 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1138 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1139 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1140 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1141 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1142 case ISD::FP_ROUND: return visitFP_ROUND(N); 1143 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1144 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1145 case ISD::FNEG: return visitFNEG(N); 1146 case ISD::FABS: return visitFABS(N); 1147 case ISD::FFLOOR: return visitFFLOOR(N); 1148 case ISD::FCEIL: return visitFCEIL(N); 1149 case ISD::FTRUNC: return visitFTRUNC(N); 1150 case ISD::BRCOND: return visitBRCOND(N); 1151 case ISD::BR_CC: return visitBR_CC(N); 1152 case ISD::LOAD: return visitLOAD(N); 1153 case ISD::STORE: return visitSTORE(N); 1154 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1155 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1156 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1157 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1158 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1159 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1160 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1161 } 1162 return SDValue(); 1163} 1164 1165SDValue DAGCombiner::combine(SDNode *N) { 1166 SDValue RV = visit(N); 1167 1168 // If nothing happened, try a target-specific DAG combine. 1169 if (RV.getNode() == 0) { 1170 assert(N->getOpcode() != ISD::DELETED_NODE && 1171 "Node was deleted but visit returned NULL!"); 1172 1173 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1174 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1175 1176 // Expose the DAG combiner to the target combiner impls. 1177 TargetLowering::DAGCombinerInfo 1178 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1179 1180 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1181 } 1182 } 1183 1184 // If nothing happened still, try promoting the operation. 1185 if (RV.getNode() == 0) { 1186 switch (N->getOpcode()) { 1187 default: break; 1188 case ISD::ADD: 1189 case ISD::SUB: 1190 case ISD::MUL: 1191 case ISD::AND: 1192 case ISD::OR: 1193 case ISD::XOR: 1194 RV = PromoteIntBinOp(SDValue(N, 0)); 1195 break; 1196 case ISD::SHL: 1197 case ISD::SRA: 1198 case ISD::SRL: 1199 RV = PromoteIntShiftOp(SDValue(N, 0)); 1200 break; 1201 case ISD::SIGN_EXTEND: 1202 case ISD::ZERO_EXTEND: 1203 case ISD::ANY_EXTEND: 1204 RV = PromoteExtend(SDValue(N, 0)); 1205 break; 1206 case ISD::LOAD: 1207 if (PromoteLoad(SDValue(N, 0))) 1208 RV = SDValue(N, 0); 1209 break; 1210 } 1211 } 1212 1213 // If N is a commutative binary node, try commuting it to enable more 1214 // sdisel CSE. 1215 if (RV.getNode() == 0 && 1216 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1217 N->getNumValues() == 1) { 1218 SDValue N0 = N->getOperand(0); 1219 SDValue N1 = N->getOperand(1); 1220 1221 // Constant operands are canonicalized to RHS. 1222 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1223 SDValue Ops[] = { N1, N0 }; 1224 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1225 Ops, 2); 1226 if (CSENode) 1227 return SDValue(CSENode, 0); 1228 } 1229 } 1230 1231 return RV; 1232} 1233 1234/// getInputChainForNode - Given a node, return its input chain if it has one, 1235/// otherwise return a null sd operand. 1236static SDValue getInputChainForNode(SDNode *N) { 1237 if (unsigned NumOps = N->getNumOperands()) { 1238 if (N->getOperand(0).getValueType() == MVT::Other) 1239 return N->getOperand(0); 1240 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1241 return N->getOperand(NumOps-1); 1242 for (unsigned i = 1; i < NumOps-1; ++i) 1243 if (N->getOperand(i).getValueType() == MVT::Other) 1244 return N->getOperand(i); 1245 } 1246 return SDValue(); 1247} 1248 1249SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1250 // If N has two operands, where one has an input chain equal to the other, 1251 // the 'other' chain is redundant. 1252 if (N->getNumOperands() == 2) { 1253 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1254 return N->getOperand(0); 1255 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1256 return N->getOperand(1); 1257 } 1258 1259 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1260 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1261 SmallPtrSet<SDNode*, 16> SeenOps; 1262 bool Changed = false; // If we should replace this token factor. 1263 1264 // Start out with this token factor. 1265 TFs.push_back(N); 1266 1267 // Iterate through token factors. The TFs grows when new token factors are 1268 // encountered. 1269 for (unsigned i = 0; i < TFs.size(); ++i) { 1270 SDNode *TF = TFs[i]; 1271 1272 // Check each of the operands. 1273 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1274 SDValue Op = TF->getOperand(i); 1275 1276 switch (Op.getOpcode()) { 1277 case ISD::EntryToken: 1278 // Entry tokens don't need to be added to the list. They are 1279 // rededundant. 1280 Changed = true; 1281 break; 1282 1283 case ISD::TokenFactor: 1284 if (Op.hasOneUse() && 1285 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1286 // Queue up for processing. 1287 TFs.push_back(Op.getNode()); 1288 // Clean up in case the token factor is removed. 1289 AddToWorkList(Op.getNode()); 1290 Changed = true; 1291 break; 1292 } 1293 // Fall thru 1294 1295 default: 1296 // Only add if it isn't already in the list. 1297 if (SeenOps.insert(Op.getNode())) 1298 Ops.push_back(Op); 1299 else 1300 Changed = true; 1301 break; 1302 } 1303 } 1304 } 1305 1306 SDValue Result; 1307 1308 // If we've change things around then replace token factor. 1309 if (Changed) { 1310 if (Ops.empty()) { 1311 // The entry token is the only possible outcome. 1312 Result = DAG.getEntryNode(); 1313 } else { 1314 // New and improved token factor. 1315 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1316 MVT::Other, &Ops[0], Ops.size()); 1317 } 1318 1319 // Don't add users to work list. 1320 return CombineTo(N, Result, false); 1321 } 1322 1323 return Result; 1324} 1325 1326/// MERGE_VALUES can always be eliminated. 1327SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1328 WorkListRemover DeadNodes(*this); 1329 // Replacing results may cause a different MERGE_VALUES to suddenly 1330 // be CSE'd with N, and carry its uses with it. Iterate until no 1331 // uses remain, to ensure that the node can be safely deleted. 1332 // First add the users of this node to the work list so that they 1333 // can be tried again once they have new operands. 1334 AddUsersToWorkList(N); 1335 do { 1336 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1337 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1338 } while (!N->use_empty()); 1339 removeFromWorkList(N); 1340 DAG.DeleteNode(N); 1341 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1342} 1343 1344static 1345SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1346 SelectionDAG &DAG) { 1347 EVT VT = N0.getValueType(); 1348 SDValue N00 = N0.getOperand(0); 1349 SDValue N01 = N0.getOperand(1); 1350 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1351 1352 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1353 isa<ConstantSDNode>(N00.getOperand(1))) { 1354 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1355 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1356 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1357 N00.getOperand(0), N01), 1358 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1359 N00.getOperand(1), N01)); 1360 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1361 } 1362 1363 return SDValue(); 1364} 1365 1366SDValue DAGCombiner::visitADD(SDNode *N) { 1367 SDValue N0 = N->getOperand(0); 1368 SDValue N1 = N->getOperand(1); 1369 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1370 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1371 EVT VT = N0.getValueType(); 1372 1373 // fold vector ops 1374 if (VT.isVector()) { 1375 SDValue FoldedVOp = SimplifyVBinOp(N); 1376 if (FoldedVOp.getNode()) return FoldedVOp; 1377 } 1378 1379 // fold (add x, undef) -> undef 1380 if (N0.getOpcode() == ISD::UNDEF) 1381 return N0; 1382 if (N1.getOpcode() == ISD::UNDEF) 1383 return N1; 1384 // fold (add c1, c2) -> c1+c2 1385 if (N0C && N1C) 1386 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1387 // canonicalize constant to RHS 1388 if (N0C && !N1C) 1389 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1390 // fold (add x, 0) -> x 1391 if (N1C && N1C->isNullValue()) 1392 return N0; 1393 // fold (add Sym, c) -> Sym+c 1394 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1395 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1396 GA->getOpcode() == ISD::GlobalAddress) 1397 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1398 GA->getOffset() + 1399 (uint64_t)N1C->getSExtValue()); 1400 // fold ((c1-A)+c2) -> (c1+c2)-A 1401 if (N1C && N0.getOpcode() == ISD::SUB) 1402 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1403 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1404 DAG.getConstant(N1C->getAPIntValue()+ 1405 N0C->getAPIntValue(), VT), 1406 N0.getOperand(1)); 1407 // reassociate add 1408 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1409 if (RADD.getNode() != 0) 1410 return RADD; 1411 // fold ((0-A) + B) -> B-A 1412 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1413 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1414 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1415 // fold (A + (0-B)) -> A-B 1416 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1417 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1418 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1419 // fold (A+(B-A)) -> B 1420 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1421 return N1.getOperand(0); 1422 // fold ((B-A)+A) -> B 1423 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1424 return N0.getOperand(0); 1425 // fold (A+(B-(A+C))) to (B-C) 1426 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1427 N0 == N1.getOperand(1).getOperand(0)) 1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1429 N1.getOperand(1).getOperand(1)); 1430 // fold (A+(B-(C+A))) to (B-C) 1431 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1432 N0 == N1.getOperand(1).getOperand(1)) 1433 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1434 N1.getOperand(1).getOperand(0)); 1435 // fold (A+((B-A)+or-C)) to (B+or-C) 1436 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1437 N1.getOperand(0).getOpcode() == ISD::SUB && 1438 N0 == N1.getOperand(0).getOperand(1)) 1439 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1440 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1441 1442 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1443 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1444 SDValue N00 = N0.getOperand(0); 1445 SDValue N01 = N0.getOperand(1); 1446 SDValue N10 = N1.getOperand(0); 1447 SDValue N11 = N1.getOperand(1); 1448 1449 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1450 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1451 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1452 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1453 } 1454 1455 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1456 return SDValue(N, 0); 1457 1458 // fold (a+b) -> (a|b) iff a and b share no bits. 1459 if (VT.isInteger() && !VT.isVector()) { 1460 APInt LHSZero, LHSOne; 1461 APInt RHSZero, RHSOne; 1462 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1463 1464 if (LHSZero.getBoolValue()) { 1465 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1466 1467 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1468 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1469 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1470 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1471 } 1472 } 1473 1474 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1475 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1476 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1477 if (Result.getNode()) return Result; 1478 } 1479 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1480 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1481 if (Result.getNode()) return Result; 1482 } 1483 1484 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1485 if (N1.getOpcode() == ISD::SHL && 1486 N1.getOperand(0).getOpcode() == ISD::SUB) 1487 if (ConstantSDNode *C = 1488 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1489 if (C->getAPIntValue() == 0) 1490 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1491 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1492 N1.getOperand(0).getOperand(1), 1493 N1.getOperand(1))); 1494 if (N0.getOpcode() == ISD::SHL && 1495 N0.getOperand(0).getOpcode() == ISD::SUB) 1496 if (ConstantSDNode *C = 1497 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1498 if (C->getAPIntValue() == 0) 1499 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1500 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1501 N0.getOperand(0).getOperand(1), 1502 N0.getOperand(1))); 1503 1504 if (N1.getOpcode() == ISD::AND) { 1505 SDValue AndOp0 = N1.getOperand(0); 1506 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1507 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1508 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1509 1510 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1511 // and similar xforms where the inner op is either ~0 or 0. 1512 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1513 DebugLoc DL = N->getDebugLoc(); 1514 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1515 } 1516 } 1517 1518 // add (sext i1), X -> sub X, (zext i1) 1519 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1520 N0.getOperand(0).getValueType() == MVT::i1 && 1521 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1522 DebugLoc DL = N->getDebugLoc(); 1523 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1524 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1525 } 1526 1527 return SDValue(); 1528} 1529 1530SDValue DAGCombiner::visitADDC(SDNode *N) { 1531 SDValue N0 = N->getOperand(0); 1532 SDValue N1 = N->getOperand(1); 1533 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1534 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1535 EVT VT = N0.getValueType(); 1536 1537 // If the flag result is dead, turn this into an ADD. 1538 if (!N->hasAnyUseOfValue(1)) 1539 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1540 DAG.getNode(ISD::CARRY_FALSE, 1541 N->getDebugLoc(), MVT::Glue)); 1542 1543 // canonicalize constant to RHS. 1544 if (N0C && !N1C) 1545 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1546 1547 // fold (addc x, 0) -> x + no carry out 1548 if (N1C && N1C->isNullValue()) 1549 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1550 N->getDebugLoc(), MVT::Glue)); 1551 1552 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1553 APInt LHSZero, LHSOne; 1554 APInt RHSZero, RHSOne; 1555 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1556 1557 if (LHSZero.getBoolValue()) { 1558 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1559 1560 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1561 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1562 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1563 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1564 DAG.getNode(ISD::CARRY_FALSE, 1565 N->getDebugLoc(), MVT::Glue)); 1566 } 1567 1568 return SDValue(); 1569} 1570 1571SDValue DAGCombiner::visitADDE(SDNode *N) { 1572 SDValue N0 = N->getOperand(0); 1573 SDValue N1 = N->getOperand(1); 1574 SDValue CarryIn = N->getOperand(2); 1575 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1576 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1577 1578 // canonicalize constant to RHS 1579 if (N0C && !N1C) 1580 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1581 N1, N0, CarryIn); 1582 1583 // fold (adde x, y, false) -> (addc x, y) 1584 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1585 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1586 1587 return SDValue(); 1588} 1589 1590// Since it may not be valid to emit a fold to zero for vector initializers 1591// check if we can before folding. 1592static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1593 SelectionDAG &DAG, bool LegalOperations) { 1594 if (!VT.isVector()) { 1595 return DAG.getConstant(0, VT); 1596 } 1597 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1598 // Produce a vector of zeros. 1599 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1600 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1601 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1602 &Ops[0], Ops.size()); 1603 } 1604 return SDValue(); 1605} 1606 1607SDValue DAGCombiner::visitSUB(SDNode *N) { 1608 SDValue N0 = N->getOperand(0); 1609 SDValue N1 = N->getOperand(1); 1610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1612 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1613 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1614 EVT VT = N0.getValueType(); 1615 1616 // fold vector ops 1617 if (VT.isVector()) { 1618 SDValue FoldedVOp = SimplifyVBinOp(N); 1619 if (FoldedVOp.getNode()) return FoldedVOp; 1620 } 1621 1622 // fold (sub x, x) -> 0 1623 // FIXME: Refactor this and xor and other similar operations together. 1624 if (N0 == N1) 1625 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1626 // fold (sub c1, c2) -> c1-c2 1627 if (N0C && N1C) 1628 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1629 // fold (sub x, c) -> (add x, -c) 1630 if (N1C) 1631 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1632 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1633 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1634 if (N0C && N0C->isAllOnesValue()) 1635 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1636 // fold A-(A-B) -> B 1637 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1638 return N1.getOperand(1); 1639 // fold (A+B)-A -> B 1640 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1641 return N0.getOperand(1); 1642 // fold (A+B)-B -> A 1643 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1644 return N0.getOperand(0); 1645 // fold C2-(A+C1) -> (C2-C1)-A 1646 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1647 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), 1648 VT); 1649 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1650 N1.getOperand(0)); 1651 } 1652 // fold ((A+(B+or-C))-B) -> A+or-C 1653 if (N0.getOpcode() == ISD::ADD && 1654 (N0.getOperand(1).getOpcode() == ISD::SUB || 1655 N0.getOperand(1).getOpcode() == ISD::ADD) && 1656 N0.getOperand(1).getOperand(0) == N1) 1657 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1658 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1659 // fold ((A+(C+B))-B) -> A+C 1660 if (N0.getOpcode() == ISD::ADD && 1661 N0.getOperand(1).getOpcode() == ISD::ADD && 1662 N0.getOperand(1).getOperand(1) == N1) 1663 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1664 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1665 // fold ((A-(B-C))-C) -> A-B 1666 if (N0.getOpcode() == ISD::SUB && 1667 N0.getOperand(1).getOpcode() == ISD::SUB && 1668 N0.getOperand(1).getOperand(1) == N1) 1669 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1670 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1671 1672 // If either operand of a sub is undef, the result is undef 1673 if (N0.getOpcode() == ISD::UNDEF) 1674 return N0; 1675 if (N1.getOpcode() == ISD::UNDEF) 1676 return N1; 1677 1678 // If the relocation model supports it, consider symbol offsets. 1679 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1680 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1681 // fold (sub Sym, c) -> Sym-c 1682 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1683 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1684 GA->getOffset() - 1685 (uint64_t)N1C->getSExtValue()); 1686 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1687 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1688 if (GA->getGlobal() == GB->getGlobal()) 1689 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1690 VT); 1691 } 1692 1693 return SDValue(); 1694} 1695 1696SDValue DAGCombiner::visitSUBC(SDNode *N) { 1697 SDValue N0 = N->getOperand(0); 1698 SDValue N1 = N->getOperand(1); 1699 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1700 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1701 EVT VT = N0.getValueType(); 1702 1703 // If the flag result is dead, turn this into an SUB. 1704 if (!N->hasAnyUseOfValue(1)) 1705 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1706 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1707 MVT::Glue)); 1708 1709 // fold (subc x, x) -> 0 + no borrow 1710 if (N0 == N1) 1711 return CombineTo(N, DAG.getConstant(0, VT), 1712 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1713 MVT::Glue)); 1714 1715 // fold (subc x, 0) -> x + no borrow 1716 if (N1C && N1C->isNullValue()) 1717 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1718 MVT::Glue)); 1719 1720 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1721 if (N0C && N0C->isAllOnesValue()) 1722 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1723 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1724 MVT::Glue)); 1725 1726 return SDValue(); 1727} 1728 1729SDValue DAGCombiner::visitSUBE(SDNode *N) { 1730 SDValue N0 = N->getOperand(0); 1731 SDValue N1 = N->getOperand(1); 1732 SDValue CarryIn = N->getOperand(2); 1733 1734 // fold (sube x, y, false) -> (subc x, y) 1735 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1736 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1737 1738 return SDValue(); 1739} 1740 1741SDValue DAGCombiner::visitMUL(SDNode *N) { 1742 SDValue N0 = N->getOperand(0); 1743 SDValue N1 = N->getOperand(1); 1744 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1745 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1746 EVT VT = N0.getValueType(); 1747 1748 // fold vector ops 1749 if (VT.isVector()) { 1750 SDValue FoldedVOp = SimplifyVBinOp(N); 1751 if (FoldedVOp.getNode()) return FoldedVOp; 1752 } 1753 1754 // fold (mul x, undef) -> 0 1755 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1756 return DAG.getConstant(0, VT); 1757 // fold (mul c1, c2) -> c1*c2 1758 if (N0C && N1C) 1759 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1760 // canonicalize constant to RHS 1761 if (N0C && !N1C) 1762 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1763 // fold (mul x, 0) -> 0 1764 if (N1C && N1C->isNullValue()) 1765 return N1; 1766 // fold (mul x, -1) -> 0-x 1767 if (N1C && N1C->isAllOnesValue()) 1768 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1769 DAG.getConstant(0, VT), N0); 1770 // fold (mul x, (1 << c)) -> x << c 1771 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1772 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1773 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1774 getShiftAmountTy(N0.getValueType()))); 1775 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1776 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1777 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1778 // FIXME: If the input is something that is easily negated (e.g. a 1779 // single-use add), we should put the negate there. 1780 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1781 DAG.getConstant(0, VT), 1782 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1783 DAG.getConstant(Log2Val, 1784 getShiftAmountTy(N0.getValueType())))); 1785 } 1786 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1787 if (N1C && N0.getOpcode() == ISD::SHL && 1788 isa<ConstantSDNode>(N0.getOperand(1))) { 1789 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1790 N1, N0.getOperand(1)); 1791 AddToWorkList(C3.getNode()); 1792 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1793 N0.getOperand(0), C3); 1794 } 1795 1796 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1797 // use. 1798 { 1799 SDValue Sh(0,0), Y(0,0); 1800 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1801 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1802 N0.getNode()->hasOneUse()) { 1803 Sh = N0; Y = N1; 1804 } else if (N1.getOpcode() == ISD::SHL && 1805 isa<ConstantSDNode>(N1.getOperand(1)) && 1806 N1.getNode()->hasOneUse()) { 1807 Sh = N1; Y = N0; 1808 } 1809 1810 if (Sh.getNode()) { 1811 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1812 Sh.getOperand(0), Y); 1813 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1814 Mul, Sh.getOperand(1)); 1815 } 1816 } 1817 1818 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1819 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1820 isa<ConstantSDNode>(N0.getOperand(1))) 1821 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1822 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1823 N0.getOperand(0), N1), 1824 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1825 N0.getOperand(1), N1)); 1826 1827 // reassociate mul 1828 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1829 if (RMUL.getNode() != 0) 1830 return RMUL; 1831 1832 return SDValue(); 1833} 1834 1835SDValue DAGCombiner::visitSDIV(SDNode *N) { 1836 SDValue N0 = N->getOperand(0); 1837 SDValue N1 = N->getOperand(1); 1838 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1839 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1840 EVT VT = N->getValueType(0); 1841 1842 // fold vector ops 1843 if (VT.isVector()) { 1844 SDValue FoldedVOp = SimplifyVBinOp(N); 1845 if (FoldedVOp.getNode()) return FoldedVOp; 1846 } 1847 1848 // fold (sdiv c1, c2) -> c1/c2 1849 if (N0C && N1C && !N1C->isNullValue()) 1850 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1851 // fold (sdiv X, 1) -> X 1852 if (N1C && N1C->getAPIntValue() == 1LL) 1853 return N0; 1854 // fold (sdiv X, -1) -> 0-X 1855 if (N1C && N1C->isAllOnesValue()) 1856 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1857 DAG.getConstant(0, VT), N0); 1858 // If we know the sign bits of both operands are zero, strength reduce to a 1859 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1860 if (!VT.isVector()) { 1861 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1862 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1863 N0, N1); 1864 } 1865 // fold (sdiv X, pow2) -> simple ops after legalize 1866 if (N1C && !N1C->isNullValue() && 1867 (N1C->getAPIntValue().isPowerOf2() || 1868 (-N1C->getAPIntValue()).isPowerOf2())) { 1869 // If dividing by powers of two is cheap, then don't perform the following 1870 // fold. 1871 if (TLI.isPow2DivCheap()) 1872 return SDValue(); 1873 1874 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1875 1876 // Splat the sign bit into the register 1877 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1878 DAG.getConstant(VT.getSizeInBits()-1, 1879 getShiftAmountTy(N0.getValueType()))); 1880 AddToWorkList(SGN.getNode()); 1881 1882 // Add (N0 < 0) ? abs2 - 1 : 0; 1883 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1884 DAG.getConstant(VT.getSizeInBits() - lg2, 1885 getShiftAmountTy(SGN.getValueType()))); 1886 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1887 AddToWorkList(SRL.getNode()); 1888 AddToWorkList(ADD.getNode()); // Divide by pow2 1889 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1890 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1891 1892 // If we're dividing by a positive value, we're done. Otherwise, we must 1893 // negate the result. 1894 if (N1C->getAPIntValue().isNonNegative()) 1895 return SRA; 1896 1897 AddToWorkList(SRA.getNode()); 1898 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1899 DAG.getConstant(0, VT), SRA); 1900 } 1901 1902 // if integer divide is expensive and we satisfy the requirements, emit an 1903 // alternate sequence. 1904 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1905 SDValue Op = BuildSDIV(N); 1906 if (Op.getNode()) return Op; 1907 } 1908 1909 // undef / X -> 0 1910 if (N0.getOpcode() == ISD::UNDEF) 1911 return DAG.getConstant(0, VT); 1912 // X / undef -> undef 1913 if (N1.getOpcode() == ISD::UNDEF) 1914 return N1; 1915 1916 return SDValue(); 1917} 1918 1919SDValue DAGCombiner::visitUDIV(SDNode *N) { 1920 SDValue N0 = N->getOperand(0); 1921 SDValue N1 = N->getOperand(1); 1922 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1923 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1924 EVT VT = N->getValueType(0); 1925 1926 // fold vector ops 1927 if (VT.isVector()) { 1928 SDValue FoldedVOp = SimplifyVBinOp(N); 1929 if (FoldedVOp.getNode()) return FoldedVOp; 1930 } 1931 1932 // fold (udiv c1, c2) -> c1/c2 1933 if (N0C && N1C && !N1C->isNullValue()) 1934 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1935 // fold (udiv x, (1 << c)) -> x >>u c 1936 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1937 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1938 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1939 getShiftAmountTy(N0.getValueType()))); 1940 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1941 if (N1.getOpcode() == ISD::SHL) { 1942 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1943 if (SHC->getAPIntValue().isPowerOf2()) { 1944 EVT ADDVT = N1.getOperand(1).getValueType(); 1945 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1946 N1.getOperand(1), 1947 DAG.getConstant(SHC->getAPIntValue() 1948 .logBase2(), 1949 ADDVT)); 1950 AddToWorkList(Add.getNode()); 1951 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1952 } 1953 } 1954 } 1955 // fold (udiv x, c) -> alternate 1956 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1957 SDValue Op = BuildUDIV(N); 1958 if (Op.getNode()) return Op; 1959 } 1960 1961 // undef / X -> 0 1962 if (N0.getOpcode() == ISD::UNDEF) 1963 return DAG.getConstant(0, VT); 1964 // X / undef -> undef 1965 if (N1.getOpcode() == ISD::UNDEF) 1966 return N1; 1967 1968 return SDValue(); 1969} 1970 1971SDValue DAGCombiner::visitSREM(SDNode *N) { 1972 SDValue N0 = N->getOperand(0); 1973 SDValue N1 = N->getOperand(1); 1974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1976 EVT VT = N->getValueType(0); 1977 1978 // fold (srem c1, c2) -> c1%c2 1979 if (N0C && N1C && !N1C->isNullValue()) 1980 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1981 // If we know the sign bits of both operands are zero, strength reduce to a 1982 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1983 if (!VT.isVector()) { 1984 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1985 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1986 } 1987 1988 // If X/C can be simplified by the division-by-constant logic, lower 1989 // X%C to the equivalent of X-X/C*C. 1990 if (N1C && !N1C->isNullValue()) { 1991 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1992 AddToWorkList(Div.getNode()); 1993 SDValue OptimizedDiv = combine(Div.getNode()); 1994 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1995 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1996 OptimizedDiv, N1); 1997 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1998 AddToWorkList(Mul.getNode()); 1999 return Sub; 2000 } 2001 } 2002 2003 // undef % X -> 0 2004 if (N0.getOpcode() == ISD::UNDEF) 2005 return DAG.getConstant(0, VT); 2006 // X % undef -> undef 2007 if (N1.getOpcode() == ISD::UNDEF) 2008 return N1; 2009 2010 return SDValue(); 2011} 2012 2013SDValue DAGCombiner::visitUREM(SDNode *N) { 2014 SDValue N0 = N->getOperand(0); 2015 SDValue N1 = N->getOperand(1); 2016 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2017 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2018 EVT VT = N->getValueType(0); 2019 2020 // fold (urem c1, c2) -> c1%c2 2021 if (N0C && N1C && !N1C->isNullValue()) 2022 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2023 // fold (urem x, pow2) -> (and x, pow2-1) 2024 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2025 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2026 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2027 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2028 if (N1.getOpcode() == ISD::SHL) { 2029 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2030 if (SHC->getAPIntValue().isPowerOf2()) { 2031 SDValue Add = 2032 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2033 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2034 VT)); 2035 AddToWorkList(Add.getNode()); 2036 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2037 } 2038 } 2039 } 2040 2041 // If X/C can be simplified by the division-by-constant logic, lower 2042 // X%C to the equivalent of X-X/C*C. 2043 if (N1C && !N1C->isNullValue()) { 2044 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2045 AddToWorkList(Div.getNode()); 2046 SDValue OptimizedDiv = combine(Div.getNode()); 2047 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2048 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2049 OptimizedDiv, N1); 2050 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2051 AddToWorkList(Mul.getNode()); 2052 return Sub; 2053 } 2054 } 2055 2056 // undef % X -> 0 2057 if (N0.getOpcode() == ISD::UNDEF) 2058 return DAG.getConstant(0, VT); 2059 // X % undef -> undef 2060 if (N1.getOpcode() == ISD::UNDEF) 2061 return N1; 2062 2063 return SDValue(); 2064} 2065 2066SDValue DAGCombiner::visitMULHS(SDNode *N) { 2067 SDValue N0 = N->getOperand(0); 2068 SDValue N1 = N->getOperand(1); 2069 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2070 EVT VT = N->getValueType(0); 2071 DebugLoc DL = N->getDebugLoc(); 2072 2073 // fold (mulhs x, 0) -> 0 2074 if (N1C && N1C->isNullValue()) 2075 return N1; 2076 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2077 if (N1C && N1C->getAPIntValue() == 1) 2078 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2079 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2080 getShiftAmountTy(N0.getValueType()))); 2081 // fold (mulhs x, undef) -> 0 2082 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2083 return DAG.getConstant(0, VT); 2084 2085 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2086 // plus a shift. 2087 if (VT.isSimple() && !VT.isVector()) { 2088 MVT Simple = VT.getSimpleVT(); 2089 unsigned SimpleSize = Simple.getSizeInBits(); 2090 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2091 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2092 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2093 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2094 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2095 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2096 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2097 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2098 } 2099 } 2100 2101 return SDValue(); 2102} 2103 2104SDValue DAGCombiner::visitMULHU(SDNode *N) { 2105 SDValue N0 = N->getOperand(0); 2106 SDValue N1 = N->getOperand(1); 2107 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2108 EVT VT = N->getValueType(0); 2109 DebugLoc DL = N->getDebugLoc(); 2110 2111 // fold (mulhu x, 0) -> 0 2112 if (N1C && N1C->isNullValue()) 2113 return N1; 2114 // fold (mulhu x, 1) -> 0 2115 if (N1C && N1C->getAPIntValue() == 1) 2116 return DAG.getConstant(0, N0.getValueType()); 2117 // fold (mulhu x, undef) -> 0 2118 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2119 return DAG.getConstant(0, VT); 2120 2121 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2122 // plus a shift. 2123 if (VT.isSimple() && !VT.isVector()) { 2124 MVT Simple = VT.getSimpleVT(); 2125 unsigned SimpleSize = Simple.getSizeInBits(); 2126 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2127 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2128 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2129 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2130 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2131 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2132 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2133 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2134 } 2135 } 2136 2137 return SDValue(); 2138} 2139 2140/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2141/// compute two values. LoOp and HiOp give the opcodes for the two computations 2142/// that are being performed. Return true if a simplification was made. 2143/// 2144SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2145 unsigned HiOp) { 2146 // If the high half is not needed, just compute the low half. 2147 bool HiExists = N->hasAnyUseOfValue(1); 2148 if (!HiExists && 2149 (!LegalOperations || 2150 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2151 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2152 N->op_begin(), N->getNumOperands()); 2153 return CombineTo(N, Res, Res); 2154 } 2155 2156 // If the low half is not needed, just compute the high half. 2157 bool LoExists = N->hasAnyUseOfValue(0); 2158 if (!LoExists && 2159 (!LegalOperations || 2160 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2161 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2162 N->op_begin(), N->getNumOperands()); 2163 return CombineTo(N, Res, Res); 2164 } 2165 2166 // If both halves are used, return as it is. 2167 if (LoExists && HiExists) 2168 return SDValue(); 2169 2170 // If the two computed results can be simplified separately, separate them. 2171 if (LoExists) { 2172 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2173 N->op_begin(), N->getNumOperands()); 2174 AddToWorkList(Lo.getNode()); 2175 SDValue LoOpt = combine(Lo.getNode()); 2176 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2177 (!LegalOperations || 2178 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2179 return CombineTo(N, LoOpt, LoOpt); 2180 } 2181 2182 if (HiExists) { 2183 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2184 N->op_begin(), N->getNumOperands()); 2185 AddToWorkList(Hi.getNode()); 2186 SDValue HiOpt = combine(Hi.getNode()); 2187 if (HiOpt.getNode() && HiOpt != Hi && 2188 (!LegalOperations || 2189 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2190 return CombineTo(N, HiOpt, HiOpt); 2191 } 2192 2193 return SDValue(); 2194} 2195 2196SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2197 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2198 if (Res.getNode()) return Res; 2199 2200 EVT VT = N->getValueType(0); 2201 DebugLoc DL = N->getDebugLoc(); 2202 2203 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2204 // plus a shift. 2205 if (VT.isSimple() && !VT.isVector()) { 2206 MVT Simple = VT.getSimpleVT(); 2207 unsigned SimpleSize = Simple.getSizeInBits(); 2208 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2209 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2210 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2211 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2212 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2213 // Compute the high part as N1. 2214 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2215 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2216 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2217 // Compute the low part as N0. 2218 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2219 return CombineTo(N, Lo, Hi); 2220 } 2221 } 2222 2223 return SDValue(); 2224} 2225 2226SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2227 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2228 if (Res.getNode()) return Res; 2229 2230 EVT VT = N->getValueType(0); 2231 DebugLoc DL = N->getDebugLoc(); 2232 2233 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2234 // plus a shift. 2235 if (VT.isSimple() && !VT.isVector()) { 2236 MVT Simple = VT.getSimpleVT(); 2237 unsigned SimpleSize = Simple.getSizeInBits(); 2238 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2239 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2240 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2241 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2242 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2243 // Compute the high part as N1. 2244 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2245 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2246 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2247 // Compute the low part as N0. 2248 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2249 return CombineTo(N, Lo, Hi); 2250 } 2251 } 2252 2253 return SDValue(); 2254} 2255 2256SDValue DAGCombiner::visitSMULO(SDNode *N) { 2257 // (smulo x, 2) -> (saddo x, x) 2258 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2259 if (C2->getAPIntValue() == 2) 2260 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2261 N->getOperand(0), N->getOperand(0)); 2262 2263 return SDValue(); 2264} 2265 2266SDValue DAGCombiner::visitUMULO(SDNode *N) { 2267 // (umulo x, 2) -> (uaddo x, x) 2268 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2269 if (C2->getAPIntValue() == 2) 2270 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2271 N->getOperand(0), N->getOperand(0)); 2272 2273 return SDValue(); 2274} 2275 2276SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2277 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2278 if (Res.getNode()) return Res; 2279 2280 return SDValue(); 2281} 2282 2283SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2284 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2285 if (Res.getNode()) return Res; 2286 2287 return SDValue(); 2288} 2289 2290/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2291/// two operands of the same opcode, try to simplify it. 2292SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2293 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2294 EVT VT = N0.getValueType(); 2295 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2296 2297 // Bail early if none of these transforms apply. 2298 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2299 2300 // For each of OP in AND/OR/XOR: 2301 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2302 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2303 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2304 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2305 // 2306 // do not sink logical op inside of a vector extend, since it may combine 2307 // into a vsetcc. 2308 EVT Op0VT = N0.getOperand(0).getValueType(); 2309 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2310 N0.getOpcode() == ISD::SIGN_EXTEND || 2311 // Avoid infinite looping with PromoteIntBinOp. 2312 (N0.getOpcode() == ISD::ANY_EXTEND && 2313 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2314 (N0.getOpcode() == ISD::TRUNCATE && 2315 (!TLI.isZExtFree(VT, Op0VT) || 2316 !TLI.isTruncateFree(Op0VT, VT)) && 2317 TLI.isTypeLegal(Op0VT))) && 2318 !VT.isVector() && 2319 Op0VT == N1.getOperand(0).getValueType() && 2320 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2321 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2322 N0.getOperand(0).getValueType(), 2323 N0.getOperand(0), N1.getOperand(0)); 2324 AddToWorkList(ORNode.getNode()); 2325 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2326 } 2327 2328 // For each of OP in SHL/SRL/SRA/AND... 2329 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2330 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2331 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2332 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2333 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2334 N0.getOperand(1) == N1.getOperand(1)) { 2335 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2336 N0.getOperand(0).getValueType(), 2337 N0.getOperand(0), N1.getOperand(0)); 2338 AddToWorkList(ORNode.getNode()); 2339 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2340 ORNode, N0.getOperand(1)); 2341 } 2342 2343 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2344 // Only perform this optimization after type legalization and before 2345 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2346 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2347 // we don't want to undo this promotion. 2348 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2349 // on scalars. 2350 if ((N0.getOpcode() == ISD::BITCAST || 2351 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && 2352 Level == AfterLegalizeTypes) { 2353 SDValue In0 = N0.getOperand(0); 2354 SDValue In1 = N1.getOperand(0); 2355 EVT In0Ty = In0.getValueType(); 2356 EVT In1Ty = In1.getValueType(); 2357 DebugLoc DL = N->getDebugLoc(); 2358 // If both incoming values are integers, and the original types are the 2359 // same. 2360 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2361 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1); 2362 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op); 2363 AddToWorkList(Op.getNode()); 2364 return BC; 2365 } 2366 } 2367 2368 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2369 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2370 // If both shuffles use the same mask, and both shuffle within a single 2371 // vector, then it is worthwhile to move the swizzle after the operation. 2372 // The type-legalizer generates this pattern when loading illegal 2373 // vector types from memory. In many cases this allows additional shuffle 2374 // optimizations. 2375 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2376 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2377 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2378 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2379 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2380 2381 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2382 "Inputs to shuffles are not the same type"); 2383 2384 unsigned NumElts = VT.getVectorNumElements(); 2385 2386 // Check that both shuffles use the same mask. The masks are known to be of 2387 // the same length because the result vector type is the same. 2388 bool SameMask = true; 2389 for (unsigned i = 0; i != NumElts; ++i) { 2390 int Idx0 = SVN0->getMaskElt(i); 2391 int Idx1 = SVN1->getMaskElt(i); 2392 if (Idx0 != Idx1) { 2393 SameMask = false; 2394 break; 2395 } 2396 } 2397 2398 if (SameMask) { 2399 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2400 N0.getOperand(0), N1.getOperand(0)); 2401 AddToWorkList(Op.getNode()); 2402 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2403 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2404 } 2405 } 2406 2407 return SDValue(); 2408} 2409 2410SDValue DAGCombiner::visitAND(SDNode *N) { 2411 SDValue N0 = N->getOperand(0); 2412 SDValue N1 = N->getOperand(1); 2413 SDValue LL, LR, RL, RR, CC0, CC1; 2414 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2415 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2416 EVT VT = N1.getValueType(); 2417 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2418 2419 // fold vector ops 2420 if (VT.isVector()) { 2421 SDValue FoldedVOp = SimplifyVBinOp(N); 2422 if (FoldedVOp.getNode()) return FoldedVOp; 2423 } 2424 2425 // fold (and x, undef) -> 0 2426 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2427 return DAG.getConstant(0, VT); 2428 // fold (and c1, c2) -> c1&c2 2429 if (N0C && N1C) 2430 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2431 // canonicalize constant to RHS 2432 if (N0C && !N1C) 2433 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2434 // fold (and x, -1) -> x 2435 if (N1C && N1C->isAllOnesValue()) 2436 return N0; 2437 // if (and x, c) is known to be zero, return 0 2438 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2439 APInt::getAllOnesValue(BitWidth))) 2440 return DAG.getConstant(0, VT); 2441 // reassociate and 2442 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2443 if (RAND.getNode() != 0) 2444 return RAND; 2445 // fold (and (or x, C), D) -> D if (C & D) == D 2446 if (N1C && N0.getOpcode() == ISD::OR) 2447 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2448 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2449 return N1; 2450 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2451 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2452 SDValue N0Op0 = N0.getOperand(0); 2453 APInt Mask = ~N1C->getAPIntValue(); 2454 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2455 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2456 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2457 N0.getValueType(), N0Op0); 2458 2459 // Replace uses of the AND with uses of the Zero extend node. 2460 CombineTo(N, Zext); 2461 2462 // We actually want to replace all uses of the any_extend with the 2463 // zero_extend, to avoid duplicating things. This will later cause this 2464 // AND to be folded. 2465 CombineTo(N0.getNode(), Zext); 2466 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2467 } 2468 } 2469 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2470 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2471 // already be zero by virtue of the width of the base type of the load. 2472 // 2473 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2474 // more cases. 2475 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2476 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2477 N0.getOpcode() == ISD::LOAD) { 2478 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2479 N0 : N0.getOperand(0) ); 2480 2481 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2482 // This can be a pure constant or a vector splat, in which case we treat the 2483 // vector as a scalar and use the splat value. 2484 APInt Constant = APInt::getNullValue(1); 2485 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2486 Constant = C->getAPIntValue(); 2487 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2488 APInt SplatValue, SplatUndef; 2489 unsigned SplatBitSize; 2490 bool HasAnyUndefs; 2491 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2492 SplatBitSize, HasAnyUndefs); 2493 if (IsSplat) { 2494 // Undef bits can contribute to a possible optimisation if set, so 2495 // set them. 2496 SplatValue |= SplatUndef; 2497 2498 // The splat value may be something like "0x00FFFFFF", which means 0 for 2499 // the first vector value and FF for the rest, repeating. We need a mask 2500 // that will apply equally to all members of the vector, so AND all the 2501 // lanes of the constant together. 2502 EVT VT = Vector->getValueType(0); 2503 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2504 2505 // If the splat value has been compressed to a bitlength lower 2506 // than the size of the vector lane, we need to re-expand it to 2507 // the lane size. 2508 if (BitWidth > SplatBitSize) 2509 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2510 SplatBitSize < BitWidth; 2511 SplatBitSize = SplatBitSize * 2) 2512 SplatValue |= SplatValue.shl(SplatBitSize); 2513 2514 Constant = APInt::getAllOnesValue(BitWidth); 2515 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2516 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2517 } 2518 } 2519 2520 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2521 // actually legal and isn't going to get expanded, else this is a false 2522 // optimisation. 2523 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2524 Load->getMemoryVT()); 2525 2526 // Resize the constant to the same size as the original memory access before 2527 // extension. If it is still the AllOnesValue then this AND is completely 2528 // unneeded. 2529 Constant = 2530 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2531 2532 bool B; 2533 switch (Load->getExtensionType()) { 2534 default: B = false; break; 2535 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2536 case ISD::ZEXTLOAD: 2537 case ISD::NON_EXTLOAD: B = true; break; 2538 } 2539 2540 if (B && Constant.isAllOnesValue()) { 2541 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2542 // preserve semantics once we get rid of the AND. 2543 SDValue NewLoad(Load, 0); 2544 if (Load->getExtensionType() == ISD::EXTLOAD) { 2545 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2546 Load->getValueType(0), Load->getDebugLoc(), 2547 Load->getChain(), Load->getBasePtr(), 2548 Load->getOffset(), Load->getMemoryVT(), 2549 Load->getMemOperand()); 2550 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2551 if (Load->getNumValues() == 3) { 2552 // PRE/POST_INC loads have 3 values. 2553 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2554 NewLoad.getValue(2) }; 2555 CombineTo(Load, To, 3, true); 2556 } else { 2557 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2558 } 2559 } 2560 2561 // Fold the AND away, taking care not to fold to the old load node if we 2562 // replaced it. 2563 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2564 2565 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2566 } 2567 } 2568 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2569 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2570 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2571 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2572 2573 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2574 LL.getValueType().isInteger()) { 2575 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2576 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2577 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2578 LR.getValueType(), LL, RL); 2579 AddToWorkList(ORNode.getNode()); 2580 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2581 } 2582 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2583 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2584 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2585 LR.getValueType(), LL, RL); 2586 AddToWorkList(ANDNode.getNode()); 2587 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2588 } 2589 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2590 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2591 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2592 LR.getValueType(), LL, RL); 2593 AddToWorkList(ORNode.getNode()); 2594 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2595 } 2596 } 2597 // canonicalize equivalent to ll == rl 2598 if (LL == RR && LR == RL) { 2599 Op1 = ISD::getSetCCSwappedOperands(Op1); 2600 std::swap(RL, RR); 2601 } 2602 if (LL == RL && LR == RR) { 2603 bool isInteger = LL.getValueType().isInteger(); 2604 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2605 if (Result != ISD::SETCC_INVALID && 2606 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2607 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2608 LL, LR, Result); 2609 } 2610 } 2611 2612 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2613 if (N0.getOpcode() == N1.getOpcode()) { 2614 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2615 if (Tmp.getNode()) return Tmp; 2616 } 2617 2618 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2619 // fold (and (sra)) -> (and (srl)) when possible. 2620 if (!VT.isVector() && 2621 SimplifyDemandedBits(SDValue(N, 0))) 2622 return SDValue(N, 0); 2623 2624 // fold (zext_inreg (extload x)) -> (zextload x) 2625 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2626 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2627 EVT MemVT = LN0->getMemoryVT(); 2628 // If we zero all the possible extended bits, then we can turn this into 2629 // a zextload if we are running before legalize or the operation is legal. 2630 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2631 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2632 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2633 ((!LegalOperations && !LN0->isVolatile()) || 2634 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2635 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2636 LN0->getChain(), LN0->getBasePtr(), 2637 LN0->getPointerInfo(), MemVT, 2638 LN0->isVolatile(), LN0->isNonTemporal(), 2639 LN0->getAlignment()); 2640 AddToWorkList(N); 2641 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2642 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2643 } 2644 } 2645 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2646 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2647 N0.hasOneUse()) { 2648 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2649 EVT MemVT = LN0->getMemoryVT(); 2650 // If we zero all the possible extended bits, then we can turn this into 2651 // a zextload if we are running before legalize or the operation is legal. 2652 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2653 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2654 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2655 ((!LegalOperations && !LN0->isVolatile()) || 2656 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2657 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2658 LN0->getChain(), 2659 LN0->getBasePtr(), LN0->getPointerInfo(), 2660 MemVT, 2661 LN0->isVolatile(), LN0->isNonTemporal(), 2662 LN0->getAlignment()); 2663 AddToWorkList(N); 2664 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2665 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2666 } 2667 } 2668 2669 // fold (and (load x), 255) -> (zextload x, i8) 2670 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2671 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2672 if (N1C && (N0.getOpcode() == ISD::LOAD || 2673 (N0.getOpcode() == ISD::ANY_EXTEND && 2674 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2675 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2676 LoadSDNode *LN0 = HasAnyExt 2677 ? cast<LoadSDNode>(N0.getOperand(0)) 2678 : cast<LoadSDNode>(N0); 2679 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2680 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2681 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2682 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2683 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2684 EVT LoadedVT = LN0->getMemoryVT(); 2685 2686 if (ExtVT == LoadedVT && 2687 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2688 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2689 2690 SDValue NewLoad = 2691 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2692 LN0->getChain(), LN0->getBasePtr(), 2693 LN0->getPointerInfo(), 2694 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2695 LN0->getAlignment()); 2696 AddToWorkList(N); 2697 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2698 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2699 } 2700 2701 // Do not change the width of a volatile load. 2702 // Do not generate loads of non-round integer types since these can 2703 // be expensive (and would be wrong if the type is not byte sized). 2704 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2705 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2706 EVT PtrType = LN0->getOperand(1).getValueType(); 2707 2708 unsigned Alignment = LN0->getAlignment(); 2709 SDValue NewPtr = LN0->getBasePtr(); 2710 2711 // For big endian targets, we need to add an offset to the pointer 2712 // to load the correct bytes. For little endian systems, we merely 2713 // need to read fewer bytes from the same pointer. 2714 if (TLI.isBigEndian()) { 2715 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2716 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2717 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2718 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2719 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2720 Alignment = MinAlign(Alignment, PtrOff); 2721 } 2722 2723 AddToWorkList(NewPtr.getNode()); 2724 2725 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2726 SDValue Load = 2727 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2728 LN0->getChain(), NewPtr, 2729 LN0->getPointerInfo(), 2730 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2731 Alignment); 2732 AddToWorkList(N); 2733 CombineTo(LN0, Load, Load.getValue(1)); 2734 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2735 } 2736 } 2737 } 2738 } 2739 2740 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2741 VT.getSizeInBits() <= 64) { 2742 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2743 APInt ADDC = ADDI->getAPIntValue(); 2744 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2745 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2746 // immediate for an add, but it is legal if its top c2 bits are set, 2747 // transform the ADD so the immediate doesn't need to be materialized 2748 // in a register. 2749 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2750 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2751 SRLI->getZExtValue()); 2752 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2753 ADDC |= Mask; 2754 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2755 SDValue NewAdd = 2756 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 2757 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2758 CombineTo(N0.getNode(), NewAdd); 2759 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2760 } 2761 } 2762 } 2763 } 2764 } 2765 } 2766 2767 2768 return SDValue(); 2769} 2770 2771/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2772/// 2773SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2774 bool DemandHighBits) { 2775 if (!LegalOperations) 2776 return SDValue(); 2777 2778 EVT VT = N->getValueType(0); 2779 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2780 return SDValue(); 2781 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2782 return SDValue(); 2783 2784 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2785 bool LookPassAnd0 = false; 2786 bool LookPassAnd1 = false; 2787 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2788 std::swap(N0, N1); 2789 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2790 std::swap(N0, N1); 2791 if (N0.getOpcode() == ISD::AND) { 2792 if (!N0.getNode()->hasOneUse()) 2793 return SDValue(); 2794 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2795 if (!N01C || N01C->getZExtValue() != 0xFF00) 2796 return SDValue(); 2797 N0 = N0.getOperand(0); 2798 LookPassAnd0 = true; 2799 } 2800 2801 if (N1.getOpcode() == ISD::AND) { 2802 if (!N1.getNode()->hasOneUse()) 2803 return SDValue(); 2804 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2805 if (!N11C || N11C->getZExtValue() != 0xFF) 2806 return SDValue(); 2807 N1 = N1.getOperand(0); 2808 LookPassAnd1 = true; 2809 } 2810 2811 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2812 std::swap(N0, N1); 2813 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2814 return SDValue(); 2815 if (!N0.getNode()->hasOneUse() || 2816 !N1.getNode()->hasOneUse()) 2817 return SDValue(); 2818 2819 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2820 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2821 if (!N01C || !N11C) 2822 return SDValue(); 2823 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2824 return SDValue(); 2825 2826 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2827 SDValue N00 = N0->getOperand(0); 2828 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2829 if (!N00.getNode()->hasOneUse()) 2830 return SDValue(); 2831 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2832 if (!N001C || N001C->getZExtValue() != 0xFF) 2833 return SDValue(); 2834 N00 = N00.getOperand(0); 2835 LookPassAnd0 = true; 2836 } 2837 2838 SDValue N10 = N1->getOperand(0); 2839 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2840 if (!N10.getNode()->hasOneUse()) 2841 return SDValue(); 2842 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2843 if (!N101C || N101C->getZExtValue() != 0xFF00) 2844 return SDValue(); 2845 N10 = N10.getOperand(0); 2846 LookPassAnd1 = true; 2847 } 2848 2849 if (N00 != N10) 2850 return SDValue(); 2851 2852 // Make sure everything beyond the low halfword is zero since the SRL 16 2853 // will clear the top bits. 2854 unsigned OpSizeInBits = VT.getSizeInBits(); 2855 if (DemandHighBits && OpSizeInBits > 16 && 2856 (!LookPassAnd0 || !LookPassAnd1) && 2857 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2858 return SDValue(); 2859 2860 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2861 if (OpSizeInBits > 16) 2862 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2863 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2864 return Res; 2865} 2866 2867/// isBSwapHWordElement - Return true if the specified node is an element 2868/// that makes up a 32-bit packed halfword byteswap. i.e. 2869/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2870static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2871 if (!N.getNode()->hasOneUse()) 2872 return false; 2873 2874 unsigned Opc = N.getOpcode(); 2875 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2876 return false; 2877 2878 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2879 if (!N1C) 2880 return false; 2881 2882 unsigned Num; 2883 switch (N1C->getZExtValue()) { 2884 default: 2885 return false; 2886 case 0xFF: Num = 0; break; 2887 case 0xFF00: Num = 1; break; 2888 case 0xFF0000: Num = 2; break; 2889 case 0xFF000000: Num = 3; break; 2890 } 2891 2892 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2893 SDValue N0 = N.getOperand(0); 2894 if (Opc == ISD::AND) { 2895 if (Num == 0 || Num == 2) { 2896 // (x >> 8) & 0xff 2897 // (x >> 8) & 0xff0000 2898 if (N0.getOpcode() != ISD::SRL) 2899 return false; 2900 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2901 if (!C || C->getZExtValue() != 8) 2902 return false; 2903 } else { 2904 // (x << 8) & 0xff00 2905 // (x << 8) & 0xff000000 2906 if (N0.getOpcode() != ISD::SHL) 2907 return false; 2908 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2909 if (!C || C->getZExtValue() != 8) 2910 return false; 2911 } 2912 } else if (Opc == ISD::SHL) { 2913 // (x & 0xff) << 8 2914 // (x & 0xff0000) << 8 2915 if (Num != 0 && Num != 2) 2916 return false; 2917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2918 if (!C || C->getZExtValue() != 8) 2919 return false; 2920 } else { // Opc == ISD::SRL 2921 // (x & 0xff00) >> 8 2922 // (x & 0xff000000) >> 8 2923 if (Num != 1 && Num != 3) 2924 return false; 2925 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2926 if (!C || C->getZExtValue() != 8) 2927 return false; 2928 } 2929 2930 if (Parts[Num]) 2931 return false; 2932 2933 Parts[Num] = N0.getOperand(0).getNode(); 2934 return true; 2935} 2936 2937/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2938/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2939/// => (rotl (bswap x), 16) 2940SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2941 if (!LegalOperations) 2942 return SDValue(); 2943 2944 EVT VT = N->getValueType(0); 2945 if (VT != MVT::i32) 2946 return SDValue(); 2947 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2948 return SDValue(); 2949 2950 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2951 // Look for either 2952 // (or (or (and), (and)), (or (and), (and))) 2953 // (or (or (or (and), (and)), (and)), (and)) 2954 if (N0.getOpcode() != ISD::OR) 2955 return SDValue(); 2956 SDValue N00 = N0.getOperand(0); 2957 SDValue N01 = N0.getOperand(1); 2958 2959 if (N1.getOpcode() == ISD::OR) { 2960 // (or (or (and), (and)), (or (and), (and))) 2961 SDValue N000 = N00.getOperand(0); 2962 if (!isBSwapHWordElement(N000, Parts)) 2963 return SDValue(); 2964 2965 SDValue N001 = N00.getOperand(1); 2966 if (!isBSwapHWordElement(N001, Parts)) 2967 return SDValue(); 2968 SDValue N010 = N01.getOperand(0); 2969 if (!isBSwapHWordElement(N010, Parts)) 2970 return SDValue(); 2971 SDValue N011 = N01.getOperand(1); 2972 if (!isBSwapHWordElement(N011, Parts)) 2973 return SDValue(); 2974 } else { 2975 // (or (or (or (and), (and)), (and)), (and)) 2976 if (!isBSwapHWordElement(N1, Parts)) 2977 return SDValue(); 2978 if (!isBSwapHWordElement(N01, Parts)) 2979 return SDValue(); 2980 if (N00.getOpcode() != ISD::OR) 2981 return SDValue(); 2982 SDValue N000 = N00.getOperand(0); 2983 if (!isBSwapHWordElement(N000, Parts)) 2984 return SDValue(); 2985 SDValue N001 = N00.getOperand(1); 2986 if (!isBSwapHWordElement(N001, Parts)) 2987 return SDValue(); 2988 } 2989 2990 // Make sure the parts are all coming from the same node. 2991 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2992 return SDValue(); 2993 2994 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2995 SDValue(Parts[0],0)); 2996 2997 // Result of the bswap should be rotated by 16. If it's not legal, than 2998 // do (x << 16) | (x >> 16). 2999 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 3000 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3001 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 3002 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3003 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 3004 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 3005 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 3006 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 3007} 3008 3009SDValue DAGCombiner::visitOR(SDNode *N) { 3010 SDValue N0 = N->getOperand(0); 3011 SDValue N1 = N->getOperand(1); 3012 SDValue LL, LR, RL, RR, CC0, CC1; 3013 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3015 EVT VT = N1.getValueType(); 3016 3017 // fold vector ops 3018 if (VT.isVector()) { 3019 SDValue FoldedVOp = SimplifyVBinOp(N); 3020 if (FoldedVOp.getNode()) return FoldedVOp; 3021 } 3022 3023 // fold (or x, undef) -> -1 3024 if (!LegalOperations && 3025 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3026 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3027 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3028 } 3029 // fold (or c1, c2) -> c1|c2 3030 if (N0C && N1C) 3031 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3032 // canonicalize constant to RHS 3033 if (N0C && !N1C) 3034 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 3035 // fold (or x, 0) -> x 3036 if (N1C && N1C->isNullValue()) 3037 return N0; 3038 // fold (or x, -1) -> -1 3039 if (N1C && N1C->isAllOnesValue()) 3040 return N1; 3041 // fold (or x, c) -> c iff (x & ~c) == 0 3042 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3043 return N1; 3044 3045 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3046 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3047 if (BSwap.getNode() != 0) 3048 return BSwap; 3049 BSwap = MatchBSwapHWordLow(N, N0, N1); 3050 if (BSwap.getNode() != 0) 3051 return BSwap; 3052 3053 // reassociate or 3054 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3055 if (ROR.getNode() != 0) 3056 return ROR; 3057 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3058 // iff (c1 & c2) == 0. 3059 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3060 isa<ConstantSDNode>(N0.getOperand(1))) { 3061 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3062 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3063 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3064 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3065 N0.getOperand(0), N1), 3066 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3067 } 3068 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3069 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3070 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3071 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3072 3073 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3074 LL.getValueType().isInteger()) { 3075 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3076 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3077 if (cast<ConstantSDNode>(LR)->isNullValue() && 3078 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3079 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3080 LR.getValueType(), LL, RL); 3081 AddToWorkList(ORNode.getNode()); 3082 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3083 } 3084 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3085 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3086 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3087 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3088 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3089 LR.getValueType(), LL, RL); 3090 AddToWorkList(ANDNode.getNode()); 3091 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3092 } 3093 } 3094 // canonicalize equivalent to ll == rl 3095 if (LL == RR && LR == RL) { 3096 Op1 = ISD::getSetCCSwappedOperands(Op1); 3097 std::swap(RL, RR); 3098 } 3099 if (LL == RL && LR == RR) { 3100 bool isInteger = LL.getValueType().isInteger(); 3101 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3102 if (Result != ISD::SETCC_INVALID && 3103 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3104 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3105 LL, LR, Result); 3106 } 3107 } 3108 3109 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3110 if (N0.getOpcode() == N1.getOpcode()) { 3111 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3112 if (Tmp.getNode()) return Tmp; 3113 } 3114 3115 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3116 if (N0.getOpcode() == ISD::AND && 3117 N1.getOpcode() == ISD::AND && 3118 N0.getOperand(1).getOpcode() == ISD::Constant && 3119 N1.getOperand(1).getOpcode() == ISD::Constant && 3120 // Don't increase # computations. 3121 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3122 // We can only do this xform if we know that bits from X that are set in C2 3123 // but not in C1 are already zero. Likewise for Y. 3124 const APInt &LHSMask = 3125 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3126 const APInt &RHSMask = 3127 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3128 3129 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3130 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3131 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3132 N0.getOperand(0), N1.getOperand(0)); 3133 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3134 DAG.getConstant(LHSMask | RHSMask, VT)); 3135 } 3136 } 3137 3138 // See if this is some rotate idiom. 3139 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3140 return SDValue(Rot, 0); 3141 3142 // Simplify the operands using demanded-bits information. 3143 if (!VT.isVector() && 3144 SimplifyDemandedBits(SDValue(N, 0))) 3145 return SDValue(N, 0); 3146 3147 return SDValue(); 3148} 3149 3150/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3151static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3152 if (Op.getOpcode() == ISD::AND) { 3153 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3154 Mask = Op.getOperand(1); 3155 Op = Op.getOperand(0); 3156 } else { 3157 return false; 3158 } 3159 } 3160 3161 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3162 Shift = Op; 3163 return true; 3164 } 3165 3166 return false; 3167} 3168 3169// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3170// idioms for rotate, and if the target supports rotation instructions, generate 3171// a rot[lr]. 3172SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3173 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3174 EVT VT = LHS.getValueType(); 3175 if (!TLI.isTypeLegal(VT)) return 0; 3176 3177 // The target must have at least one rotate flavor. 3178 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3179 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3180 if (!HasROTL && !HasROTR) return 0; 3181 3182 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3183 SDValue LHSShift; // The shift. 3184 SDValue LHSMask; // AND value if any. 3185 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3186 return 0; // Not part of a rotate. 3187 3188 SDValue RHSShift; // The shift. 3189 SDValue RHSMask; // AND value if any. 3190 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3191 return 0; // Not part of a rotate. 3192 3193 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3194 return 0; // Not shifting the same value. 3195 3196 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3197 return 0; // Shifts must disagree. 3198 3199 // Canonicalize shl to left side in a shl/srl pair. 3200 if (RHSShift.getOpcode() == ISD::SHL) { 3201 std::swap(LHS, RHS); 3202 std::swap(LHSShift, RHSShift); 3203 std::swap(LHSMask , RHSMask ); 3204 } 3205 3206 unsigned OpSizeInBits = VT.getSizeInBits(); 3207 SDValue LHSShiftArg = LHSShift.getOperand(0); 3208 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3209 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3210 3211 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3212 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3213 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3214 RHSShiftAmt.getOpcode() == ISD::Constant) { 3215 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3216 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3217 if ((LShVal + RShVal) != OpSizeInBits) 3218 return 0; 3219 3220 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3221 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt); 3222 3223 // If there is an AND of either shifted operand, apply it to the result. 3224 if (LHSMask.getNode() || RHSMask.getNode()) { 3225 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3226 3227 if (LHSMask.getNode()) { 3228 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3229 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3230 } 3231 if (RHSMask.getNode()) { 3232 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3233 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3234 } 3235 3236 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3237 } 3238 3239 return Rot.getNode(); 3240 } 3241 3242 // If there is a mask here, and we have a variable shift, we can't be sure 3243 // that we're masking out the right stuff. 3244 if (LHSMask.getNode() || RHSMask.getNode()) 3245 return 0; 3246 3247 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3248 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3249 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3250 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3251 if (ConstantSDNode *SUBC = 3252 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3253 if (SUBC->getAPIntValue() == OpSizeInBits) { 3254 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, 3255 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3256 } 3257 } 3258 } 3259 3260 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3261 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3262 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3263 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3264 if (ConstantSDNode *SUBC = 3265 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3266 if (SUBC->getAPIntValue() == OpSizeInBits) { 3267 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, 3268 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3269 } 3270 } 3271 } 3272 3273 // Look for sign/zext/any-extended or truncate cases: 3274 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3275 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3276 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3277 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3278 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3279 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3280 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3281 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3282 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3283 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3284 if (RExtOp0.getOpcode() == ISD::SUB && 3285 RExtOp0.getOperand(1) == LExtOp0) { 3286 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3287 // (rotl x, y) 3288 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3289 // (rotr x, (sub 32, y)) 3290 if (ConstantSDNode *SUBC = 3291 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3292 if (SUBC->getAPIntValue() == OpSizeInBits) { 3293 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3294 LHSShiftArg, 3295 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3296 } 3297 } 3298 } else if (LExtOp0.getOpcode() == ISD::SUB && 3299 RExtOp0 == LExtOp0.getOperand(1)) { 3300 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3301 // (rotr x, y) 3302 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3303 // (rotl x, (sub 32, y)) 3304 if (ConstantSDNode *SUBC = 3305 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3306 if (SUBC->getAPIntValue() == OpSizeInBits) { 3307 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3308 LHSShiftArg, 3309 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3310 } 3311 } 3312 } 3313 } 3314 3315 return 0; 3316} 3317 3318SDValue DAGCombiner::visitXOR(SDNode *N) { 3319 SDValue N0 = N->getOperand(0); 3320 SDValue N1 = N->getOperand(1); 3321 SDValue LHS, RHS, CC; 3322 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3323 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3324 EVT VT = N0.getValueType(); 3325 3326 // fold vector ops 3327 if (VT.isVector()) { 3328 SDValue FoldedVOp = SimplifyVBinOp(N); 3329 if (FoldedVOp.getNode()) return FoldedVOp; 3330 } 3331 3332 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3333 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3334 return DAG.getConstant(0, VT); 3335 // fold (xor x, undef) -> undef 3336 if (N0.getOpcode() == ISD::UNDEF) 3337 return N0; 3338 if (N1.getOpcode() == ISD::UNDEF) 3339 return N1; 3340 // fold (xor c1, c2) -> c1^c2 3341 if (N0C && N1C) 3342 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3343 // canonicalize constant to RHS 3344 if (N0C && !N1C) 3345 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3346 // fold (xor x, 0) -> x 3347 if (N1C && N1C->isNullValue()) 3348 return N0; 3349 // reassociate xor 3350 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3351 if (RXOR.getNode() != 0) 3352 return RXOR; 3353 3354 // fold !(x cc y) -> (x !cc y) 3355 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3356 bool isInt = LHS.getValueType().isInteger(); 3357 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3358 isInt); 3359 3360 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3361 switch (N0.getOpcode()) { 3362 default: 3363 llvm_unreachable("Unhandled SetCC Equivalent!"); 3364 case ISD::SETCC: 3365 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3366 case ISD::SELECT_CC: 3367 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3368 N0.getOperand(3), NotCC); 3369 } 3370 } 3371 } 3372 3373 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3374 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3375 N0.getNode()->hasOneUse() && 3376 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3377 SDValue V = N0.getOperand(0); 3378 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3379 DAG.getConstant(1, V.getValueType())); 3380 AddToWorkList(V.getNode()); 3381 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3382 } 3383 3384 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3385 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3386 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3387 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3388 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3389 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3390 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3391 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3392 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3393 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3394 } 3395 } 3396 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3397 if (N1C && N1C->isAllOnesValue() && 3398 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3399 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3400 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3401 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3402 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3403 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3404 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3405 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3406 } 3407 } 3408 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3409 if (N1C && N0.getOpcode() == ISD::XOR) { 3410 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3411 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3412 if (N00C) 3413 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3414 DAG.getConstant(N1C->getAPIntValue() ^ 3415 N00C->getAPIntValue(), VT)); 3416 if (N01C) 3417 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3418 DAG.getConstant(N1C->getAPIntValue() ^ 3419 N01C->getAPIntValue(), VT)); 3420 } 3421 // fold (xor x, x) -> 0 3422 if (N0 == N1) 3423 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3424 3425 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3426 if (N0.getOpcode() == N1.getOpcode()) { 3427 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3428 if (Tmp.getNode()) return Tmp; 3429 } 3430 3431 // Simplify the expression using non-local knowledge. 3432 if (!VT.isVector() && 3433 SimplifyDemandedBits(SDValue(N, 0))) 3434 return SDValue(N, 0); 3435 3436 return SDValue(); 3437} 3438 3439/// visitShiftByConstant - Handle transforms common to the three shifts, when 3440/// the shift amount is a constant. 3441SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3442 SDNode *LHS = N->getOperand(0).getNode(); 3443 if (!LHS->hasOneUse()) return SDValue(); 3444 3445 // We want to pull some binops through shifts, so that we have (and (shift)) 3446 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3447 // thing happens with address calculations, so it's important to canonicalize 3448 // it. 3449 bool HighBitSet = false; // Can we transform this if the high bit is set? 3450 3451 switch (LHS->getOpcode()) { 3452 default: return SDValue(); 3453 case ISD::OR: 3454 case ISD::XOR: 3455 HighBitSet = false; // We can only transform sra if the high bit is clear. 3456 break; 3457 case ISD::AND: 3458 HighBitSet = true; // We can only transform sra if the high bit is set. 3459 break; 3460 case ISD::ADD: 3461 if (N->getOpcode() != ISD::SHL) 3462 return SDValue(); // only shl(add) not sr[al](add). 3463 HighBitSet = false; // We can only transform sra if the high bit is clear. 3464 break; 3465 } 3466 3467 // We require the RHS of the binop to be a constant as well. 3468 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3469 if (!BinOpCst) return SDValue(); 3470 3471 // FIXME: disable this unless the input to the binop is a shift by a constant. 3472 // If it is not a shift, it pessimizes some common cases like: 3473 // 3474 // void foo(int *X, int i) { X[i & 1235] = 1; } 3475 // int bar(int *X, int i) { return X[i & 255]; } 3476 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3477 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3478 BinOpLHSVal->getOpcode() != ISD::SRA && 3479 BinOpLHSVal->getOpcode() != ISD::SRL) || 3480 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3481 return SDValue(); 3482 3483 EVT VT = N->getValueType(0); 3484 3485 // If this is a signed shift right, and the high bit is modified by the 3486 // logical operation, do not perform the transformation. The highBitSet 3487 // boolean indicates the value of the high bit of the constant which would 3488 // cause it to be modified for this operation. 3489 if (N->getOpcode() == ISD::SRA) { 3490 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3491 if (BinOpRHSSignSet != HighBitSet) 3492 return SDValue(); 3493 } 3494 3495 // Fold the constants, shifting the binop RHS by the shift amount. 3496 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3497 N->getValueType(0), 3498 LHS->getOperand(1), N->getOperand(1)); 3499 3500 // Create the new shift. 3501 SDValue NewShift = DAG.getNode(N->getOpcode(), 3502 LHS->getOperand(0).getDebugLoc(), 3503 VT, LHS->getOperand(0), N->getOperand(1)); 3504 3505 // Create the new binop. 3506 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3507} 3508 3509SDValue DAGCombiner::visitSHL(SDNode *N) { 3510 SDValue N0 = N->getOperand(0); 3511 SDValue N1 = N->getOperand(1); 3512 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3513 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3514 EVT VT = N0.getValueType(); 3515 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3516 3517 // fold (shl c1, c2) -> c1<<c2 3518 if (N0C && N1C) 3519 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3520 // fold (shl 0, x) -> 0 3521 if (N0C && N0C->isNullValue()) 3522 return N0; 3523 // fold (shl x, c >= size(x)) -> undef 3524 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3525 return DAG.getUNDEF(VT); 3526 // fold (shl x, 0) -> x 3527 if (N1C && N1C->isNullValue()) 3528 return N0; 3529 // fold (shl undef, x) -> 0 3530 if (N0.getOpcode() == ISD::UNDEF) 3531 return DAG.getConstant(0, VT); 3532 // if (shl x, c) is known to be zero, return 0 3533 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3534 APInt::getAllOnesValue(OpSizeInBits))) 3535 return DAG.getConstant(0, VT); 3536 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3537 if (N1.getOpcode() == ISD::TRUNCATE && 3538 N1.getOperand(0).getOpcode() == ISD::AND && 3539 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3540 SDValue N101 = N1.getOperand(0).getOperand(1); 3541 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3542 EVT TruncVT = N1.getValueType(); 3543 SDValue N100 = N1.getOperand(0).getOperand(0); 3544 APInt TruncC = N101C->getAPIntValue(); 3545 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3546 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3547 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3548 DAG.getNode(ISD::TRUNCATE, 3549 N->getDebugLoc(), 3550 TruncVT, N100), 3551 DAG.getConstant(TruncC, TruncVT))); 3552 } 3553 } 3554 3555 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3556 return SDValue(N, 0); 3557 3558 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3559 if (N1C && N0.getOpcode() == ISD::SHL && 3560 N0.getOperand(1).getOpcode() == ISD::Constant) { 3561 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3562 uint64_t c2 = N1C->getZExtValue(); 3563 if (c1 + c2 >= OpSizeInBits) 3564 return DAG.getConstant(0, VT); 3565 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3566 DAG.getConstant(c1 + c2, N1.getValueType())); 3567 } 3568 3569 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3570 // For this to be valid, the second form must not preserve any of the bits 3571 // that are shifted out by the inner shift in the first form. This means 3572 // the outer shift size must be >= the number of bits added by the ext. 3573 // As a corollary, we don't care what kind of ext it is. 3574 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3575 N0.getOpcode() == ISD::ANY_EXTEND || 3576 N0.getOpcode() == ISD::SIGN_EXTEND) && 3577 N0.getOperand(0).getOpcode() == ISD::SHL && 3578 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3579 uint64_t c1 = 3580 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3581 uint64_t c2 = N1C->getZExtValue(); 3582 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3583 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3584 if (c2 >= OpSizeInBits - InnerShiftSize) { 3585 if (c1 + c2 >= OpSizeInBits) 3586 return DAG.getConstant(0, VT); 3587 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3588 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3589 N0.getOperand(0)->getOperand(0)), 3590 DAG.getConstant(c1 + c2, N1.getValueType())); 3591 } 3592 } 3593 3594 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3595 // (and (srl x, (sub c1, c2), MASK) 3596 // Only fold this if the inner shift has no other uses -- if it does, folding 3597 // this will increase the total number of instructions. 3598 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3599 N0.getOperand(1).getOpcode() == ISD::Constant) { 3600 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3601 if (c1 < VT.getSizeInBits()) { 3602 uint64_t c2 = N1C->getZExtValue(); 3603 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3604 VT.getSizeInBits() - c1); 3605 SDValue Shift; 3606 if (c2 > c1) { 3607 Mask = Mask.shl(c2-c1); 3608 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3609 DAG.getConstant(c2-c1, N1.getValueType())); 3610 } else { 3611 Mask = Mask.lshr(c1-c2); 3612 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3613 DAG.getConstant(c1-c2, N1.getValueType())); 3614 } 3615 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3616 DAG.getConstant(Mask, VT)); 3617 } 3618 } 3619 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3620 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3621 SDValue HiBitsMask = 3622 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3623 VT.getSizeInBits() - 3624 N1C->getZExtValue()), 3625 VT); 3626 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3627 HiBitsMask); 3628 } 3629 3630 if (N1C) { 3631 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3632 if (NewSHL.getNode()) 3633 return NewSHL; 3634 } 3635 3636 return SDValue(); 3637} 3638 3639SDValue DAGCombiner::visitSRA(SDNode *N) { 3640 SDValue N0 = N->getOperand(0); 3641 SDValue N1 = N->getOperand(1); 3642 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3643 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3644 EVT VT = N0.getValueType(); 3645 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3646 3647 // fold (sra c1, c2) -> (sra c1, c2) 3648 if (N0C && N1C) 3649 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3650 // fold (sra 0, x) -> 0 3651 if (N0C && N0C->isNullValue()) 3652 return N0; 3653 // fold (sra -1, x) -> -1 3654 if (N0C && N0C->isAllOnesValue()) 3655 return N0; 3656 // fold (sra x, (setge c, size(x))) -> undef 3657 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3658 return DAG.getUNDEF(VT); 3659 // fold (sra x, 0) -> x 3660 if (N1C && N1C->isNullValue()) 3661 return N0; 3662 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3663 // sext_inreg. 3664 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3665 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3666 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3667 if (VT.isVector()) 3668 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3669 ExtVT, VT.getVectorNumElements()); 3670 if ((!LegalOperations || 3671 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3672 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3673 N0.getOperand(0), DAG.getValueType(ExtVT)); 3674 } 3675 3676 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3677 if (N1C && N0.getOpcode() == ISD::SRA) { 3678 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3679 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3680 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3681 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3682 DAG.getConstant(Sum, N1C->getValueType(0))); 3683 } 3684 } 3685 3686 // fold (sra (shl X, m), (sub result_size, n)) 3687 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3688 // result_size - n != m. 3689 // If truncate is free for the target sext(shl) is likely to result in better 3690 // code. 3691 if (N0.getOpcode() == ISD::SHL) { 3692 // Get the two constanst of the shifts, CN0 = m, CN = n. 3693 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3694 if (N01C && N1C) { 3695 // Determine what the truncate's result bitsize and type would be. 3696 EVT TruncVT = 3697 EVT::getIntegerVT(*DAG.getContext(), 3698 OpSizeInBits - N1C->getZExtValue()); 3699 // Determine the residual right-shift amount. 3700 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3701 3702 // If the shift is not a no-op (in which case this should be just a sign 3703 // extend already), the truncated to type is legal, sign_extend is legal 3704 // on that type, and the truncate to that type is both legal and free, 3705 // perform the transform. 3706 if ((ShiftAmt > 0) && 3707 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3708 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3709 TLI.isTruncateFree(VT, TruncVT)) { 3710 3711 SDValue Amt = DAG.getConstant(ShiftAmt, 3712 getShiftAmountTy(N0.getOperand(0).getValueType())); 3713 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3714 N0.getOperand(0), Amt); 3715 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3716 Shift); 3717 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3718 N->getValueType(0), Trunc); 3719 } 3720 } 3721 } 3722 3723 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3724 if (N1.getOpcode() == ISD::TRUNCATE && 3725 N1.getOperand(0).getOpcode() == ISD::AND && 3726 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3727 SDValue N101 = N1.getOperand(0).getOperand(1); 3728 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3729 EVT TruncVT = N1.getValueType(); 3730 SDValue N100 = N1.getOperand(0).getOperand(0); 3731 APInt TruncC = N101C->getAPIntValue(); 3732 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3733 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3734 DAG.getNode(ISD::AND, N->getDebugLoc(), 3735 TruncVT, 3736 DAG.getNode(ISD::TRUNCATE, 3737 N->getDebugLoc(), 3738 TruncVT, N100), 3739 DAG.getConstant(TruncC, TruncVT))); 3740 } 3741 } 3742 3743 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3744 // if c1 is equal to the number of bits the trunc removes 3745 if (N0.getOpcode() == ISD::TRUNCATE && 3746 (N0.getOperand(0).getOpcode() == ISD::SRL || 3747 N0.getOperand(0).getOpcode() == ISD::SRA) && 3748 N0.getOperand(0).hasOneUse() && 3749 N0.getOperand(0).getOperand(1).hasOneUse() && 3750 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3751 EVT LargeVT = N0.getOperand(0).getValueType(); 3752 ConstantSDNode *LargeShiftAmt = 3753 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3754 3755 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3756 LargeShiftAmt->getZExtValue()) { 3757 SDValue Amt = 3758 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3759 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3760 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3761 N0.getOperand(0).getOperand(0), Amt); 3762 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3763 } 3764 } 3765 3766 // Simplify, based on bits shifted out of the LHS. 3767 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3768 return SDValue(N, 0); 3769 3770 3771 // If the sign bit is known to be zero, switch this to a SRL. 3772 if (DAG.SignBitIsZero(N0)) 3773 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3774 3775 if (N1C) { 3776 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3777 if (NewSRA.getNode()) 3778 return NewSRA; 3779 } 3780 3781 return SDValue(); 3782} 3783 3784SDValue DAGCombiner::visitSRL(SDNode *N) { 3785 SDValue N0 = N->getOperand(0); 3786 SDValue N1 = N->getOperand(1); 3787 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3788 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3789 EVT VT = N0.getValueType(); 3790 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3791 3792 // fold (srl c1, c2) -> c1 >>u c2 3793 if (N0C && N1C) 3794 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3795 // fold (srl 0, x) -> 0 3796 if (N0C && N0C->isNullValue()) 3797 return N0; 3798 // fold (srl x, c >= size(x)) -> undef 3799 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3800 return DAG.getUNDEF(VT); 3801 // fold (srl x, 0) -> x 3802 if (N1C && N1C->isNullValue()) 3803 return N0; 3804 // if (srl x, c) is known to be zero, return 0 3805 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3806 APInt::getAllOnesValue(OpSizeInBits))) 3807 return DAG.getConstant(0, VT); 3808 3809 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3810 if (N1C && N0.getOpcode() == ISD::SRL && 3811 N0.getOperand(1).getOpcode() == ISD::Constant) { 3812 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3813 uint64_t c2 = N1C->getZExtValue(); 3814 if (c1 + c2 >= OpSizeInBits) 3815 return DAG.getConstant(0, VT); 3816 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3817 DAG.getConstant(c1 + c2, N1.getValueType())); 3818 } 3819 3820 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3821 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3822 N0.getOperand(0).getOpcode() == ISD::SRL && 3823 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3824 uint64_t c1 = 3825 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3826 uint64_t c2 = N1C->getZExtValue(); 3827 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3828 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3829 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3830 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3831 if (c1 + OpSizeInBits == InnerShiftSize) { 3832 if (c1 + c2 >= InnerShiftSize) 3833 return DAG.getConstant(0, VT); 3834 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3835 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3836 N0.getOperand(0)->getOperand(0), 3837 DAG.getConstant(c1 + c2, ShiftCountVT))); 3838 } 3839 } 3840 3841 // fold (srl (shl x, c), c) -> (and x, cst2) 3842 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3843 N0.getValueSizeInBits() <= 64) { 3844 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3845 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3846 DAG.getConstant(~0ULL >> ShAmt, VT)); 3847 } 3848 3849 3850 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3851 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3852 // Shifting in all undef bits? 3853 EVT SmallVT = N0.getOperand(0).getValueType(); 3854 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3855 return DAG.getUNDEF(VT); 3856 3857 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3858 uint64_t ShiftAmt = N1C->getZExtValue(); 3859 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3860 N0.getOperand(0), 3861 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3862 AddToWorkList(SmallShift.getNode()); 3863 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3864 } 3865 } 3866 3867 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3868 // bit, which is unmodified by sra. 3869 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3870 if (N0.getOpcode() == ISD::SRA) 3871 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3872 } 3873 3874 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3875 if (N1C && N0.getOpcode() == ISD::CTLZ && 3876 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3877 APInt KnownZero, KnownOne; 3878 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3879 3880 // If any of the input bits are KnownOne, then the input couldn't be all 3881 // zeros, thus the result of the srl will always be zero. 3882 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3883 3884 // If all of the bits input the to ctlz node are known to be zero, then 3885 // the result of the ctlz is "32" and the result of the shift is one. 3886 APInt UnknownBits = ~KnownZero; 3887 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3888 3889 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3890 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3891 // Okay, we know that only that the single bit specified by UnknownBits 3892 // could be set on input to the CTLZ node. If this bit is set, the SRL 3893 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3894 // to an SRL/XOR pair, which is likely to simplify more. 3895 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3896 SDValue Op = N0.getOperand(0); 3897 3898 if (ShAmt) { 3899 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3900 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3901 AddToWorkList(Op.getNode()); 3902 } 3903 3904 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3905 Op, DAG.getConstant(1, VT)); 3906 } 3907 } 3908 3909 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3910 if (N1.getOpcode() == ISD::TRUNCATE && 3911 N1.getOperand(0).getOpcode() == ISD::AND && 3912 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3913 SDValue N101 = N1.getOperand(0).getOperand(1); 3914 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3915 EVT TruncVT = N1.getValueType(); 3916 SDValue N100 = N1.getOperand(0).getOperand(0); 3917 APInt TruncC = N101C->getAPIntValue(); 3918 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3919 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3920 DAG.getNode(ISD::AND, N->getDebugLoc(), 3921 TruncVT, 3922 DAG.getNode(ISD::TRUNCATE, 3923 N->getDebugLoc(), 3924 TruncVT, N100), 3925 DAG.getConstant(TruncC, TruncVT))); 3926 } 3927 } 3928 3929 // fold operands of srl based on knowledge that the low bits are not 3930 // demanded. 3931 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3932 return SDValue(N, 0); 3933 3934 if (N1C) { 3935 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3936 if (NewSRL.getNode()) 3937 return NewSRL; 3938 } 3939 3940 // Attempt to convert a srl of a load into a narrower zero-extending load. 3941 SDValue NarrowLoad = ReduceLoadWidth(N); 3942 if (NarrowLoad.getNode()) 3943 return NarrowLoad; 3944 3945 // Here is a common situation. We want to optimize: 3946 // 3947 // %a = ... 3948 // %b = and i32 %a, 2 3949 // %c = srl i32 %b, 1 3950 // brcond i32 %c ... 3951 // 3952 // into 3953 // 3954 // %a = ... 3955 // %b = and %a, 2 3956 // %c = setcc eq %b, 0 3957 // brcond %c ... 3958 // 3959 // However when after the source operand of SRL is optimized into AND, the SRL 3960 // itself may not be optimized further. Look for it and add the BRCOND into 3961 // the worklist. 3962 if (N->hasOneUse()) { 3963 SDNode *Use = *N->use_begin(); 3964 if (Use->getOpcode() == ISD::BRCOND) 3965 AddToWorkList(Use); 3966 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3967 // Also look pass the truncate. 3968 Use = *Use->use_begin(); 3969 if (Use->getOpcode() == ISD::BRCOND) 3970 AddToWorkList(Use); 3971 } 3972 } 3973 3974 return SDValue(); 3975} 3976 3977SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3978 SDValue N0 = N->getOperand(0); 3979 EVT VT = N->getValueType(0); 3980 3981 // fold (ctlz c1) -> c2 3982 if (isa<ConstantSDNode>(N0)) 3983 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3984 return SDValue(); 3985} 3986 3987SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3988 SDValue N0 = N->getOperand(0); 3989 EVT VT = N->getValueType(0); 3990 3991 // fold (ctlz_zero_undef c1) -> c2 3992 if (isa<ConstantSDNode>(N0)) 3993 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3994 return SDValue(); 3995} 3996 3997SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3998 SDValue N0 = N->getOperand(0); 3999 EVT VT = N->getValueType(0); 4000 4001 // fold (cttz c1) -> c2 4002 if (isa<ConstantSDNode>(N0)) 4003 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 4004 return SDValue(); 4005} 4006 4007SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4008 SDValue N0 = N->getOperand(0); 4009 EVT VT = N->getValueType(0); 4010 4011 // fold (cttz_zero_undef c1) -> c2 4012 if (isa<ConstantSDNode>(N0)) 4013 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4014 return SDValue(); 4015} 4016 4017SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4018 SDValue N0 = N->getOperand(0); 4019 EVT VT = N->getValueType(0); 4020 4021 // fold (ctpop c1) -> c2 4022 if (isa<ConstantSDNode>(N0)) 4023 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 4024 return SDValue(); 4025} 4026 4027SDValue DAGCombiner::visitSELECT(SDNode *N) { 4028 SDValue N0 = N->getOperand(0); 4029 SDValue N1 = N->getOperand(1); 4030 SDValue N2 = N->getOperand(2); 4031 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4032 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4033 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4034 EVT VT = N->getValueType(0); 4035 EVT VT0 = N0.getValueType(); 4036 4037 // fold (select C, X, X) -> X 4038 if (N1 == N2) 4039 return N1; 4040 // fold (select true, X, Y) -> X 4041 if (N0C && !N0C->isNullValue()) 4042 return N1; 4043 // fold (select false, X, Y) -> Y 4044 if (N0C && N0C->isNullValue()) 4045 return N2; 4046 // fold (select C, 1, X) -> (or C, X) 4047 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4048 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4049 // fold (select C, 0, 1) -> (xor C, 1) 4050 if (VT.isInteger() && 4051 (VT0 == MVT::i1 || 4052 (VT0.isInteger() && 4053 TLI.getBooleanContents(false) == 4054 TargetLowering::ZeroOrOneBooleanContent)) && 4055 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4056 SDValue XORNode; 4057 if (VT == VT0) 4058 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4059 N0, DAG.getConstant(1, VT0)); 4060 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4061 N0, DAG.getConstant(1, VT0)); 4062 AddToWorkList(XORNode.getNode()); 4063 if (VT.bitsGT(VT0)) 4064 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4065 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4066 } 4067 // fold (select C, 0, X) -> (and (not C), X) 4068 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4069 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4070 AddToWorkList(NOTNode.getNode()); 4071 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4072 } 4073 // fold (select C, X, 1) -> (or (not C), X) 4074 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4075 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4076 AddToWorkList(NOTNode.getNode()); 4077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4078 } 4079 // fold (select C, X, 0) -> (and C, X) 4080 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4081 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4082 // fold (select X, X, Y) -> (or X, Y) 4083 // fold (select X, 1, Y) -> (or X, Y) 4084 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4085 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4086 // fold (select X, Y, X) -> (and X, Y) 4087 // fold (select X, Y, 0) -> (and X, Y) 4088 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4089 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4090 4091 // If we can fold this based on the true/false value, do so. 4092 if (SimplifySelectOps(N, N1, N2)) 4093 return SDValue(N, 0); // Don't revisit N. 4094 4095 // fold selects based on a setcc into other things, such as min/max/abs 4096 if (N0.getOpcode() == ISD::SETCC) { 4097 // FIXME: 4098 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4099 // having to say they don't support SELECT_CC on every type the DAG knows 4100 // about, since there is no way to mark an opcode illegal at all value types 4101 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4102 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4103 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4104 N0.getOperand(0), N0.getOperand(1), 4105 N1, N2, N0.getOperand(2)); 4106 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4107 } 4108 4109 return SDValue(); 4110} 4111 4112SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4113 SDValue N0 = N->getOperand(0); 4114 SDValue N1 = N->getOperand(1); 4115 SDValue N2 = N->getOperand(2); 4116 SDValue N3 = N->getOperand(3); 4117 SDValue N4 = N->getOperand(4); 4118 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4119 4120 // fold select_cc lhs, rhs, x, x, cc -> x 4121 if (N2 == N3) 4122 return N2; 4123 4124 // Determine if the condition we're dealing with is constant 4125 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4126 N0, N1, CC, N->getDebugLoc(), false); 4127 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4128 4129 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4130 if (!SCCC->isNullValue()) 4131 return N2; // cond always true -> true val 4132 else 4133 return N3; // cond always false -> false val 4134 } 4135 4136 // Fold to a simpler select_cc 4137 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4138 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4139 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4140 SCC.getOperand(2)); 4141 4142 // If we can fold this based on the true/false value, do so. 4143 if (SimplifySelectOps(N, N2, N3)) 4144 return SDValue(N, 0); // Don't revisit N. 4145 4146 // fold select_cc into other things, such as min/max/abs 4147 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4148} 4149 4150SDValue DAGCombiner::visitSETCC(SDNode *N) { 4151 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4152 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4153 N->getDebugLoc()); 4154} 4155 4156// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4157// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4158// transformation. Returns true if extension are possible and the above 4159// mentioned transformation is profitable. 4160static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4161 unsigned ExtOpc, 4162 SmallVector<SDNode*, 4> &ExtendNodes, 4163 const TargetLowering &TLI) { 4164 bool HasCopyToRegUses = false; 4165 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4166 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4167 UE = N0.getNode()->use_end(); 4168 UI != UE; ++UI) { 4169 SDNode *User = *UI; 4170 if (User == N) 4171 continue; 4172 if (UI.getUse().getResNo() != N0.getResNo()) 4173 continue; 4174 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4175 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4176 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4177 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4178 // Sign bits will be lost after a zext. 4179 return false; 4180 bool Add = false; 4181 for (unsigned i = 0; i != 2; ++i) { 4182 SDValue UseOp = User->getOperand(i); 4183 if (UseOp == N0) 4184 continue; 4185 if (!isa<ConstantSDNode>(UseOp)) 4186 return false; 4187 Add = true; 4188 } 4189 if (Add) 4190 ExtendNodes.push_back(User); 4191 continue; 4192 } 4193 // If truncates aren't free and there are users we can't 4194 // extend, it isn't worthwhile. 4195 if (!isTruncFree) 4196 return false; 4197 // Remember if this value is live-out. 4198 if (User->getOpcode() == ISD::CopyToReg) 4199 HasCopyToRegUses = true; 4200 } 4201 4202 if (HasCopyToRegUses) { 4203 bool BothLiveOut = false; 4204 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4205 UI != UE; ++UI) { 4206 SDUse &Use = UI.getUse(); 4207 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4208 BothLiveOut = true; 4209 break; 4210 } 4211 } 4212 if (BothLiveOut) 4213 // Both unextended and extended values are live out. There had better be 4214 // a good reason for the transformation. 4215 return ExtendNodes.size(); 4216 } 4217 return true; 4218} 4219 4220void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4221 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4222 ISD::NodeType ExtType) { 4223 // Extend SetCC uses if necessary. 4224 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4225 SDNode *SetCC = SetCCs[i]; 4226 SmallVector<SDValue, 4> Ops; 4227 4228 for (unsigned j = 0; j != 2; ++j) { 4229 SDValue SOp = SetCC->getOperand(j); 4230 if (SOp == Trunc) 4231 Ops.push_back(ExtLoad); 4232 else 4233 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4234 } 4235 4236 Ops.push_back(SetCC->getOperand(2)); 4237 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4238 &Ops[0], Ops.size())); 4239 } 4240} 4241 4242SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4243 SDValue N0 = N->getOperand(0); 4244 EVT VT = N->getValueType(0); 4245 4246 // fold (sext c1) -> c1 4247 if (isa<ConstantSDNode>(N0)) 4248 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4249 4250 // fold (sext (sext x)) -> (sext x) 4251 // fold (sext (aext x)) -> (sext x) 4252 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4253 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4254 N0.getOperand(0)); 4255 4256 if (N0.getOpcode() == ISD::TRUNCATE) { 4257 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4258 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4259 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4260 if (NarrowLoad.getNode()) { 4261 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4262 if (NarrowLoad.getNode() != N0.getNode()) { 4263 CombineTo(N0.getNode(), NarrowLoad); 4264 // CombineTo deleted the truncate, if needed, but not what's under it. 4265 AddToWorkList(oye); 4266 } 4267 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4268 } 4269 4270 // See if the value being truncated is already sign extended. If so, just 4271 // eliminate the trunc/sext pair. 4272 SDValue Op = N0.getOperand(0); 4273 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4274 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4275 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4276 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4277 4278 if (OpBits == DestBits) { 4279 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4280 // bits, it is already ready. 4281 if (NumSignBits > DestBits-MidBits) 4282 return Op; 4283 } else if (OpBits < DestBits) { 4284 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4285 // bits, just sext from i32. 4286 if (NumSignBits > OpBits-MidBits) 4287 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4288 } else { 4289 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4290 // bits, just truncate to i32. 4291 if (NumSignBits > OpBits-MidBits) 4292 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4293 } 4294 4295 // fold (sext (truncate x)) -> (sextinreg x). 4296 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4297 N0.getValueType())) { 4298 if (OpBits < DestBits) 4299 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4300 else if (OpBits > DestBits) 4301 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4302 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4303 DAG.getValueType(N0.getValueType())); 4304 } 4305 } 4306 4307 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4308 // None of the supported targets knows how to perform load and sign extend 4309 // on vectors in one instruction. We only perform this transformation on 4310 // scalars. 4311 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4312 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4313 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4314 bool DoXform = true; 4315 SmallVector<SDNode*, 4> SetCCs; 4316 if (!N0.hasOneUse()) 4317 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4318 if (DoXform) { 4319 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4320 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4321 LN0->getChain(), 4322 LN0->getBasePtr(), LN0->getPointerInfo(), 4323 N0.getValueType(), 4324 LN0->isVolatile(), LN0->isNonTemporal(), 4325 LN0->getAlignment()); 4326 CombineTo(N, ExtLoad); 4327 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4328 N0.getValueType(), ExtLoad); 4329 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4330 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4331 ISD::SIGN_EXTEND); 4332 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4333 } 4334 } 4335 4336 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4337 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4338 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4339 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4340 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4341 EVT MemVT = LN0->getMemoryVT(); 4342 if ((!LegalOperations && !LN0->isVolatile()) || 4343 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4344 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4345 LN0->getChain(), 4346 LN0->getBasePtr(), LN0->getPointerInfo(), 4347 MemVT, 4348 LN0->isVolatile(), LN0->isNonTemporal(), 4349 LN0->getAlignment()); 4350 CombineTo(N, ExtLoad); 4351 CombineTo(N0.getNode(), 4352 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4353 N0.getValueType(), ExtLoad), 4354 ExtLoad.getValue(1)); 4355 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4356 } 4357 } 4358 4359 // fold (sext (and/or/xor (load x), cst)) -> 4360 // (and/or/xor (sextload x), (sext cst)) 4361 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4362 N0.getOpcode() == ISD::XOR) && 4363 isa<LoadSDNode>(N0.getOperand(0)) && 4364 N0.getOperand(1).getOpcode() == ISD::Constant && 4365 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4366 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4367 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4368 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4369 bool DoXform = true; 4370 SmallVector<SDNode*, 4> SetCCs; 4371 if (!N0.hasOneUse()) 4372 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4373 SetCCs, TLI); 4374 if (DoXform) { 4375 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4376 LN0->getChain(), LN0->getBasePtr(), 4377 LN0->getPointerInfo(), 4378 LN0->getMemoryVT(), 4379 LN0->isVolatile(), 4380 LN0->isNonTemporal(), 4381 LN0->getAlignment()); 4382 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4383 Mask = Mask.sext(VT.getSizeInBits()); 4384 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4385 ExtLoad, DAG.getConstant(Mask, VT)); 4386 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4387 N0.getOperand(0).getDebugLoc(), 4388 N0.getOperand(0).getValueType(), ExtLoad); 4389 CombineTo(N, And); 4390 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4391 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4392 ISD::SIGN_EXTEND); 4393 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4394 } 4395 } 4396 } 4397 4398 if (N0.getOpcode() == ISD::SETCC) { 4399 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4400 // Only do this before legalize for now. 4401 if (VT.isVector() && !LegalOperations) { 4402 EVT N0VT = N0.getOperand(0).getValueType(); 4403 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4404 // of the same size as the compared operands. Only optimize sext(setcc()) 4405 // if this is the case. 4406 EVT SVT = TLI.getSetCCResultType(N0VT); 4407 4408 // We know that the # elements of the results is the same as the 4409 // # elements of the compare (and the # elements of the compare result 4410 // for that matter). Check to see that they are the same size. If so, 4411 // we know that the element size of the sext'd result matches the 4412 // element size of the compare operands. 4413 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4414 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4415 N0.getOperand(1), 4416 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4417 // If the desired elements are smaller or larger than the source 4418 // elements we can use a matching integer vector type and then 4419 // truncate/sign extend 4420 EVT MatchingElementType = 4421 EVT::getIntegerVT(*DAG.getContext(), 4422 N0VT.getScalarType().getSizeInBits()); 4423 EVT MatchingVectorType = 4424 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4425 N0VT.getVectorNumElements()); 4426 4427 if (SVT == MatchingVectorType) { 4428 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4429 N0.getOperand(0), N0.getOperand(1), 4430 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4431 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4432 } 4433 } 4434 4435 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4436 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4437 SDValue NegOne = 4438 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4439 SDValue SCC = 4440 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4441 NegOne, DAG.getConstant(0, VT), 4442 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4443 if (SCC.getNode()) return SCC; 4444 if (!LegalOperations || 4445 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4446 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4447 DAG.getSetCC(N->getDebugLoc(), 4448 TLI.getSetCCResultType(VT), 4449 N0.getOperand(0), N0.getOperand(1), 4450 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4451 NegOne, DAG.getConstant(0, VT)); 4452 } 4453 4454 // fold (sext x) -> (zext x) if the sign bit is known zero. 4455 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4456 DAG.SignBitIsZero(N0)) 4457 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4458 4459 return SDValue(); 4460} 4461 4462// isTruncateOf - If N is a truncate of some other value, return true, record 4463// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4464// This function computes KnownZero to avoid a duplicated call to 4465// ComputeMaskedBits in the caller. 4466static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4467 APInt &KnownZero) { 4468 APInt KnownOne; 4469 if (N->getOpcode() == ISD::TRUNCATE) { 4470 Op = N->getOperand(0); 4471 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4472 return true; 4473 } 4474 4475 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4476 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4477 return false; 4478 4479 SDValue Op0 = N->getOperand(0); 4480 SDValue Op1 = N->getOperand(1); 4481 assert(Op0.getValueType() == Op1.getValueType()); 4482 4483 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4484 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4485 if (COp0 && COp0->isNullValue()) 4486 Op = Op1; 4487 else if (COp1 && COp1->isNullValue()) 4488 Op = Op0; 4489 else 4490 return false; 4491 4492 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4493 4494 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4495 return false; 4496 4497 return true; 4498} 4499 4500SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4501 SDValue N0 = N->getOperand(0); 4502 EVT VT = N->getValueType(0); 4503 4504 // fold (zext c1) -> c1 4505 if (isa<ConstantSDNode>(N0)) 4506 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4507 // fold (zext (zext x)) -> (zext x) 4508 // fold (zext (aext x)) -> (zext x) 4509 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4510 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4511 N0.getOperand(0)); 4512 4513 // fold (zext (truncate x)) -> (zext x) or 4514 // (zext (truncate x)) -> (truncate x) 4515 // This is valid when the truncated bits of x are already zero. 4516 // FIXME: We should extend this to work for vectors too. 4517 SDValue Op; 4518 APInt KnownZero; 4519 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4520 APInt TruncatedBits = 4521 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4522 APInt(Op.getValueSizeInBits(), 0) : 4523 APInt::getBitsSet(Op.getValueSizeInBits(), 4524 N0.getValueSizeInBits(), 4525 std::min(Op.getValueSizeInBits(), 4526 VT.getSizeInBits())); 4527 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4528 if (VT.bitsGT(Op.getValueType())) 4529 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4530 if (VT.bitsLT(Op.getValueType())) 4531 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4532 4533 return Op; 4534 } 4535 } 4536 4537 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4538 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4539 if (N0.getOpcode() == ISD::TRUNCATE) { 4540 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4541 if (NarrowLoad.getNode()) { 4542 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4543 if (NarrowLoad.getNode() != N0.getNode()) { 4544 CombineTo(N0.getNode(), NarrowLoad); 4545 // CombineTo deleted the truncate, if needed, but not what's under it. 4546 AddToWorkList(oye); 4547 } 4548 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4549 } 4550 } 4551 4552 // fold (zext (truncate x)) -> (and x, mask) 4553 if (N0.getOpcode() == ISD::TRUNCATE && 4554 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4555 4556 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4557 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4558 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4559 if (NarrowLoad.getNode()) { 4560 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4561 if (NarrowLoad.getNode() != N0.getNode()) { 4562 CombineTo(N0.getNode(), NarrowLoad); 4563 // CombineTo deleted the truncate, if needed, but not what's under it. 4564 AddToWorkList(oye); 4565 } 4566 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4567 } 4568 4569 SDValue Op = N0.getOperand(0); 4570 if (Op.getValueType().bitsLT(VT)) { 4571 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4572 AddToWorkList(Op.getNode()); 4573 } else if (Op.getValueType().bitsGT(VT)) { 4574 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4575 AddToWorkList(Op.getNode()); 4576 } 4577 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4578 N0.getValueType().getScalarType()); 4579 } 4580 4581 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4582 // if either of the casts is not free. 4583 if (N0.getOpcode() == ISD::AND && 4584 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4585 N0.getOperand(1).getOpcode() == ISD::Constant && 4586 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4587 N0.getValueType()) || 4588 !TLI.isZExtFree(N0.getValueType(), VT))) { 4589 SDValue X = N0.getOperand(0).getOperand(0); 4590 if (X.getValueType().bitsLT(VT)) { 4591 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4592 } else if (X.getValueType().bitsGT(VT)) { 4593 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4594 } 4595 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4596 Mask = Mask.zext(VT.getSizeInBits()); 4597 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4598 X, DAG.getConstant(Mask, VT)); 4599 } 4600 4601 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4602 // None of the supported targets knows how to perform load and vector_zext 4603 // on vectors in one instruction. We only perform this transformation on 4604 // scalars. 4605 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4606 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4607 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4608 bool DoXform = true; 4609 SmallVector<SDNode*, 4> SetCCs; 4610 if (!N0.hasOneUse()) 4611 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4612 if (DoXform) { 4613 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4614 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4615 LN0->getChain(), 4616 LN0->getBasePtr(), LN0->getPointerInfo(), 4617 N0.getValueType(), 4618 LN0->isVolatile(), LN0->isNonTemporal(), 4619 LN0->getAlignment()); 4620 CombineTo(N, ExtLoad); 4621 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4622 N0.getValueType(), ExtLoad); 4623 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4624 4625 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4626 ISD::ZERO_EXTEND); 4627 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4628 } 4629 } 4630 4631 // fold (zext (and/or/xor (load x), cst)) -> 4632 // (and/or/xor (zextload x), (zext cst)) 4633 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4634 N0.getOpcode() == ISD::XOR) && 4635 isa<LoadSDNode>(N0.getOperand(0)) && 4636 N0.getOperand(1).getOpcode() == ISD::Constant && 4637 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4638 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4639 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4640 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4641 bool DoXform = true; 4642 SmallVector<SDNode*, 4> SetCCs; 4643 if (!N0.hasOneUse()) 4644 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4645 SetCCs, TLI); 4646 if (DoXform) { 4647 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4648 LN0->getChain(), LN0->getBasePtr(), 4649 LN0->getPointerInfo(), 4650 LN0->getMemoryVT(), 4651 LN0->isVolatile(), 4652 LN0->isNonTemporal(), 4653 LN0->getAlignment()); 4654 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4655 Mask = Mask.zext(VT.getSizeInBits()); 4656 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4657 ExtLoad, DAG.getConstant(Mask, VT)); 4658 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4659 N0.getOperand(0).getDebugLoc(), 4660 N0.getOperand(0).getValueType(), ExtLoad); 4661 CombineTo(N, And); 4662 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4663 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4664 ISD::ZERO_EXTEND); 4665 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4666 } 4667 } 4668 } 4669 4670 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4671 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4672 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4673 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4674 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4675 EVT MemVT = LN0->getMemoryVT(); 4676 if ((!LegalOperations && !LN0->isVolatile()) || 4677 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4678 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4679 LN0->getChain(), 4680 LN0->getBasePtr(), LN0->getPointerInfo(), 4681 MemVT, 4682 LN0->isVolatile(), LN0->isNonTemporal(), 4683 LN0->getAlignment()); 4684 CombineTo(N, ExtLoad); 4685 CombineTo(N0.getNode(), 4686 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4687 ExtLoad), 4688 ExtLoad.getValue(1)); 4689 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4690 } 4691 } 4692 4693 if (N0.getOpcode() == ISD::SETCC) { 4694 if (!LegalOperations && VT.isVector()) { 4695 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4696 // Only do this before legalize for now. 4697 EVT N0VT = N0.getOperand(0).getValueType(); 4698 EVT EltVT = VT.getVectorElementType(); 4699 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4700 DAG.getConstant(1, EltVT)); 4701 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4702 // We know that the # elements of the results is the same as the 4703 // # elements of the compare (and the # elements of the compare result 4704 // for that matter). Check to see that they are the same size. If so, 4705 // we know that the element size of the sext'd result matches the 4706 // element size of the compare operands. 4707 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4708 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4709 N0.getOperand(1), 4710 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4711 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4712 &OneOps[0], OneOps.size())); 4713 4714 // If the desired elements are smaller or larger than the source 4715 // elements we can use a matching integer vector type and then 4716 // truncate/sign extend 4717 EVT MatchingElementType = 4718 EVT::getIntegerVT(*DAG.getContext(), 4719 N0VT.getScalarType().getSizeInBits()); 4720 EVT MatchingVectorType = 4721 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4722 N0VT.getVectorNumElements()); 4723 SDValue VsetCC = 4724 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4725 N0.getOperand(1), 4726 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4727 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4728 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4729 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4730 &OneOps[0], OneOps.size())); 4731 } 4732 4733 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4734 SDValue SCC = 4735 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4736 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4737 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4738 if (SCC.getNode()) return SCC; 4739 } 4740 4741 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4742 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4743 isa<ConstantSDNode>(N0.getOperand(1)) && 4744 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4745 N0.hasOneUse()) { 4746 SDValue ShAmt = N0.getOperand(1); 4747 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4748 if (N0.getOpcode() == ISD::SHL) { 4749 SDValue InnerZExt = N0.getOperand(0); 4750 // If the original shl may be shifting out bits, do not perform this 4751 // transformation. 4752 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4753 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4754 if (ShAmtVal > KnownZeroBits) 4755 return SDValue(); 4756 } 4757 4758 DebugLoc DL = N->getDebugLoc(); 4759 4760 // Ensure that the shift amount is wide enough for the shifted value. 4761 if (VT.getSizeInBits() >= 256) 4762 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4763 4764 return DAG.getNode(N0.getOpcode(), DL, VT, 4765 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4766 ShAmt); 4767 } 4768 4769 return SDValue(); 4770} 4771 4772SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4773 SDValue N0 = N->getOperand(0); 4774 EVT VT = N->getValueType(0); 4775 4776 // fold (aext c1) -> c1 4777 if (isa<ConstantSDNode>(N0)) 4778 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4779 // fold (aext (aext x)) -> (aext x) 4780 // fold (aext (zext x)) -> (zext x) 4781 // fold (aext (sext x)) -> (sext x) 4782 if (N0.getOpcode() == ISD::ANY_EXTEND || 4783 N0.getOpcode() == ISD::ZERO_EXTEND || 4784 N0.getOpcode() == ISD::SIGN_EXTEND) 4785 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4786 4787 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4788 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4789 if (N0.getOpcode() == ISD::TRUNCATE) { 4790 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4791 if (NarrowLoad.getNode()) { 4792 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4793 if (NarrowLoad.getNode() != N0.getNode()) { 4794 CombineTo(N0.getNode(), NarrowLoad); 4795 // CombineTo deleted the truncate, if needed, but not what's under it. 4796 AddToWorkList(oye); 4797 } 4798 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4799 } 4800 } 4801 4802 // fold (aext (truncate x)) 4803 if (N0.getOpcode() == ISD::TRUNCATE) { 4804 SDValue TruncOp = N0.getOperand(0); 4805 if (TruncOp.getValueType() == VT) 4806 return TruncOp; // x iff x size == zext size. 4807 if (TruncOp.getValueType().bitsGT(VT)) 4808 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4809 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4810 } 4811 4812 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4813 // if the trunc is not free. 4814 if (N0.getOpcode() == ISD::AND && 4815 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4816 N0.getOperand(1).getOpcode() == ISD::Constant && 4817 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4818 N0.getValueType())) { 4819 SDValue X = N0.getOperand(0).getOperand(0); 4820 if (X.getValueType().bitsLT(VT)) { 4821 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4822 } else if (X.getValueType().bitsGT(VT)) { 4823 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4824 } 4825 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4826 Mask = Mask.zext(VT.getSizeInBits()); 4827 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4828 X, DAG.getConstant(Mask, VT)); 4829 } 4830 4831 // fold (aext (load x)) -> (aext (truncate (extload x))) 4832 // None of the supported targets knows how to perform load and any_ext 4833 // on vectors in one instruction. We only perform this transformation on 4834 // scalars. 4835 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4836 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4837 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4838 bool DoXform = true; 4839 SmallVector<SDNode*, 4> SetCCs; 4840 if (!N0.hasOneUse()) 4841 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4842 if (DoXform) { 4843 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4844 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4845 LN0->getChain(), 4846 LN0->getBasePtr(), LN0->getPointerInfo(), 4847 N0.getValueType(), 4848 LN0->isVolatile(), LN0->isNonTemporal(), 4849 LN0->getAlignment()); 4850 CombineTo(N, ExtLoad); 4851 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4852 N0.getValueType(), ExtLoad); 4853 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4854 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4855 ISD::ANY_EXTEND); 4856 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4857 } 4858 } 4859 4860 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4861 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4862 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4863 if (N0.getOpcode() == ISD::LOAD && 4864 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4865 N0.hasOneUse()) { 4866 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4867 EVT MemVT = LN0->getMemoryVT(); 4868 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4869 VT, LN0->getChain(), LN0->getBasePtr(), 4870 LN0->getPointerInfo(), MemVT, 4871 LN0->isVolatile(), LN0->isNonTemporal(), 4872 LN0->getAlignment()); 4873 CombineTo(N, ExtLoad); 4874 CombineTo(N0.getNode(), 4875 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4876 N0.getValueType(), ExtLoad), 4877 ExtLoad.getValue(1)); 4878 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4879 } 4880 4881 if (N0.getOpcode() == ISD::SETCC) { 4882 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4883 // Only do this before legalize for now. 4884 if (VT.isVector() && !LegalOperations) { 4885 EVT N0VT = N0.getOperand(0).getValueType(); 4886 // We know that the # elements of the results is the same as the 4887 // # elements of the compare (and the # elements of the compare result 4888 // for that matter). Check to see that they are the same size. If so, 4889 // we know that the element size of the sext'd result matches the 4890 // element size of the compare operands. 4891 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4892 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4893 N0.getOperand(1), 4894 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4895 // If the desired elements are smaller or larger than the source 4896 // elements we can use a matching integer vector type and then 4897 // truncate/sign extend 4898 else { 4899 EVT MatchingElementType = 4900 EVT::getIntegerVT(*DAG.getContext(), 4901 N0VT.getScalarType().getSizeInBits()); 4902 EVT MatchingVectorType = 4903 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4904 N0VT.getVectorNumElements()); 4905 SDValue VsetCC = 4906 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4907 N0.getOperand(1), 4908 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4909 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4910 } 4911 } 4912 4913 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4914 SDValue SCC = 4915 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4916 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4917 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4918 if (SCC.getNode()) 4919 return SCC; 4920 } 4921 4922 return SDValue(); 4923} 4924 4925/// GetDemandedBits - See if the specified operand can be simplified with the 4926/// knowledge that only the bits specified by Mask are used. If so, return the 4927/// simpler operand, otherwise return a null SDValue. 4928SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4929 switch (V.getOpcode()) { 4930 default: break; 4931 case ISD::Constant: { 4932 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4933 assert(CV != 0 && "Const value should be ConstSDNode."); 4934 const APInt &CVal = CV->getAPIntValue(); 4935 APInt NewVal = CVal & Mask; 4936 if (NewVal != CVal) { 4937 return DAG.getConstant(NewVal, V.getValueType()); 4938 } 4939 break; 4940 } 4941 case ISD::OR: 4942 case ISD::XOR: 4943 // If the LHS or RHS don't contribute bits to the or, drop them. 4944 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4945 return V.getOperand(1); 4946 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4947 return V.getOperand(0); 4948 break; 4949 case ISD::SRL: 4950 // Only look at single-use SRLs. 4951 if (!V.getNode()->hasOneUse()) 4952 break; 4953 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4954 // See if we can recursively simplify the LHS. 4955 unsigned Amt = RHSC->getZExtValue(); 4956 4957 // Watch out for shift count overflow though. 4958 if (Amt >= Mask.getBitWidth()) break; 4959 APInt NewMask = Mask << Amt; 4960 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4961 if (SimplifyLHS.getNode()) 4962 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4963 SimplifyLHS, V.getOperand(1)); 4964 } 4965 } 4966 return SDValue(); 4967} 4968 4969/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4970/// bits and then truncated to a narrower type and where N is a multiple 4971/// of number of bits of the narrower type, transform it to a narrower load 4972/// from address + N / num of bits of new type. If the result is to be 4973/// extended, also fold the extension to form a extending load. 4974SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4975 unsigned Opc = N->getOpcode(); 4976 4977 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4978 SDValue N0 = N->getOperand(0); 4979 EVT VT = N->getValueType(0); 4980 EVT ExtVT = VT; 4981 4982 // This transformation isn't valid for vector loads. 4983 if (VT.isVector()) 4984 return SDValue(); 4985 4986 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4987 // extended to VT. 4988 if (Opc == ISD::SIGN_EXTEND_INREG) { 4989 ExtType = ISD::SEXTLOAD; 4990 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4991 } else if (Opc == ISD::SRL) { 4992 // Another special-case: SRL is basically zero-extending a narrower value. 4993 ExtType = ISD::ZEXTLOAD; 4994 N0 = SDValue(N, 0); 4995 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4996 if (!N01) return SDValue(); 4997 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4998 VT.getSizeInBits() - N01->getZExtValue()); 4999 } 5000 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5001 return SDValue(); 5002 5003 unsigned EVTBits = ExtVT.getSizeInBits(); 5004 5005 // Do not generate loads of non-round integer types since these can 5006 // be expensive (and would be wrong if the type is not byte sized). 5007 if (!ExtVT.isRound()) 5008 return SDValue(); 5009 5010 unsigned ShAmt = 0; 5011 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5012 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5013 ShAmt = N01->getZExtValue(); 5014 // Is the shift amount a multiple of size of VT? 5015 if ((ShAmt & (EVTBits-1)) == 0) { 5016 N0 = N0.getOperand(0); 5017 // Is the load width a multiple of size of VT? 5018 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5019 return SDValue(); 5020 } 5021 5022 // At this point, we must have a load or else we can't do the transform. 5023 if (!isa<LoadSDNode>(N0)) return SDValue(); 5024 5025 // If the shift amount is larger than the input type then we're not 5026 // accessing any of the loaded bytes. If the load was a zextload/extload 5027 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5028 // If the load was a sextload then the result is a splat of the sign bit 5029 // of the extended byte. This is not worth optimizing for. 5030 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5031 return SDValue(); 5032 } 5033 } 5034 5035 // If the load is shifted left (and the result isn't shifted back right), 5036 // we can fold the truncate through the shift. 5037 unsigned ShLeftAmt = 0; 5038 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5039 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5040 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5041 ShLeftAmt = N01->getZExtValue(); 5042 N0 = N0.getOperand(0); 5043 } 5044 } 5045 5046 // If we haven't found a load, we can't narrow it. Don't transform one with 5047 // multiple uses, this would require adding a new load. 5048 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 5049 // Don't change the width of a volatile load. 5050 cast<LoadSDNode>(N0)->isVolatile()) 5051 return SDValue(); 5052 5053 // Verify that we are actually reducing a load width here. 5054 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 5055 return SDValue(); 5056 5057 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5058 EVT PtrType = N0.getOperand(1).getValueType(); 5059 5060 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5061 // It's not possible to generate a constant of extended or untyped type. 5062 return SDValue(); 5063 5064 // For big endian targets, we need to adjust the offset to the pointer to 5065 // load the correct bytes. 5066 if (TLI.isBigEndian()) { 5067 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5068 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5069 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5070 } 5071 5072 uint64_t PtrOff = ShAmt / 8; 5073 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5074 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5075 PtrType, LN0->getBasePtr(), 5076 DAG.getConstant(PtrOff, PtrType)); 5077 AddToWorkList(NewPtr.getNode()); 5078 5079 SDValue Load; 5080 if (ExtType == ISD::NON_EXTLOAD) 5081 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5082 LN0->getPointerInfo().getWithOffset(PtrOff), 5083 LN0->isVolatile(), LN0->isNonTemporal(), 5084 LN0->isInvariant(), NewAlign); 5085 else 5086 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5087 LN0->getPointerInfo().getWithOffset(PtrOff), 5088 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5089 NewAlign); 5090 5091 // Replace the old load's chain with the new load's chain. 5092 WorkListRemover DeadNodes(*this); 5093 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5094 5095 // Shift the result left, if we've swallowed a left shift. 5096 SDValue Result = Load; 5097 if (ShLeftAmt != 0) { 5098 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5099 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5100 ShImmTy = VT; 5101 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5102 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5103 } 5104 5105 // Return the new loaded value. 5106 return Result; 5107} 5108 5109SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5110 SDValue N0 = N->getOperand(0); 5111 SDValue N1 = N->getOperand(1); 5112 EVT VT = N->getValueType(0); 5113 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5114 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5115 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5116 5117 // fold (sext_in_reg c1) -> c1 5118 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5119 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5120 5121 // If the input is already sign extended, just drop the extension. 5122 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5123 return N0; 5124 5125 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5126 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5127 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5128 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5129 N0.getOperand(0), N1); 5130 } 5131 5132 // fold (sext_in_reg (sext x)) -> (sext x) 5133 // fold (sext_in_reg (aext x)) -> (sext x) 5134 // if x is small enough. 5135 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5136 SDValue N00 = N0.getOperand(0); 5137 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5138 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5139 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5140 } 5141 5142 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5143 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5144 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5145 5146 // fold operands of sext_in_reg based on knowledge that the top bits are not 5147 // demanded. 5148 if (SimplifyDemandedBits(SDValue(N, 0))) 5149 return SDValue(N, 0); 5150 5151 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5152 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5153 SDValue NarrowLoad = ReduceLoadWidth(N); 5154 if (NarrowLoad.getNode()) 5155 return NarrowLoad; 5156 5157 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5158 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5159 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5160 if (N0.getOpcode() == ISD::SRL) { 5161 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5162 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5163 // We can turn this into an SRA iff the input to the SRL is already sign 5164 // extended enough. 5165 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5166 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5167 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5168 N0.getOperand(0), N0.getOperand(1)); 5169 } 5170 } 5171 5172 // fold (sext_inreg (extload x)) -> (sextload x) 5173 if (ISD::isEXTLoad(N0.getNode()) && 5174 ISD::isUNINDEXEDLoad(N0.getNode()) && 5175 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5176 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5177 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5178 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5179 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5180 LN0->getChain(), 5181 LN0->getBasePtr(), LN0->getPointerInfo(), 5182 EVT, 5183 LN0->isVolatile(), LN0->isNonTemporal(), 5184 LN0->getAlignment()); 5185 CombineTo(N, ExtLoad); 5186 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5187 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5188 } 5189 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5190 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5191 N0.hasOneUse() && 5192 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5193 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5194 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5195 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5196 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5197 LN0->getChain(), 5198 LN0->getBasePtr(), LN0->getPointerInfo(), 5199 EVT, 5200 LN0->isVolatile(), LN0->isNonTemporal(), 5201 LN0->getAlignment()); 5202 CombineTo(N, ExtLoad); 5203 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5204 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5205 } 5206 5207 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5208 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5209 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5210 N0.getOperand(1), false); 5211 if (BSwap.getNode() != 0) 5212 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5213 BSwap, N1); 5214 } 5215 5216 return SDValue(); 5217} 5218 5219SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5220 SDValue N0 = N->getOperand(0); 5221 EVT VT = N->getValueType(0); 5222 bool isLE = TLI.isLittleEndian(); 5223 5224 // noop truncate 5225 if (N0.getValueType() == N->getValueType(0)) 5226 return N0; 5227 // fold (truncate c1) -> c1 5228 if (isa<ConstantSDNode>(N0)) 5229 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5230 // fold (truncate (truncate x)) -> (truncate x) 5231 if (N0.getOpcode() == ISD::TRUNCATE) 5232 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5233 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5234 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5235 N0.getOpcode() == ISD::SIGN_EXTEND || 5236 N0.getOpcode() == ISD::ANY_EXTEND) { 5237 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5238 // if the source is smaller than the dest, we still need an extend 5239 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5240 N0.getOperand(0)); 5241 if (N0.getOperand(0).getValueType().bitsGT(VT)) 5242 // if the source is larger than the dest, than we just need the truncate 5243 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5244 // if the source and dest are the same type, we can drop both the extend 5245 // and the truncate. 5246 return N0.getOperand(0); 5247 } 5248 5249 // Fold extract-and-trunc into a narrow extract. For example: 5250 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5251 // i32 y = TRUNCATE(i64 x) 5252 // -- becomes -- 5253 // v16i8 b = BITCAST (v2i64 val) 5254 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5255 // 5256 // Note: We only run this optimization after type legalization (which often 5257 // creates this pattern) and before operation legalization after which 5258 // we need to be more careful about the vector instructions that we generate. 5259 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5260 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5261 5262 EVT VecTy = N0.getOperand(0).getValueType(); 5263 EVT ExTy = N0.getValueType(); 5264 EVT TrTy = N->getValueType(0); 5265 5266 unsigned NumElem = VecTy.getVectorNumElements(); 5267 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5268 5269 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5270 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5271 5272 SDValue EltNo = N0->getOperand(1); 5273 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5274 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5275 EVT IndexTy = N0->getOperand(1).getValueType(); 5276 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5277 5278 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5279 NVT, N0.getOperand(0)); 5280 5281 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5282 N->getDebugLoc(), TrTy, V, 5283 DAG.getConstant(Index, IndexTy)); 5284 } 5285 } 5286 5287 // See if we can simplify the input to this truncate through knowledge that 5288 // only the low bits are being used. 5289 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5290 // Currently we only perform this optimization on scalars because vectors 5291 // may have different active low bits. 5292 if (!VT.isVector()) { 5293 SDValue Shorter = 5294 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5295 VT.getSizeInBits())); 5296 if (Shorter.getNode()) 5297 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5298 } 5299 // fold (truncate (load x)) -> (smaller load x) 5300 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5301 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5302 SDValue Reduced = ReduceLoadWidth(N); 5303 if (Reduced.getNode()) 5304 return Reduced; 5305 } 5306 5307 // Simplify the operands using demanded-bits information. 5308 if (!VT.isVector() && 5309 SimplifyDemandedBits(SDValue(N, 0))) 5310 return SDValue(N, 0); 5311 5312 return SDValue(); 5313} 5314 5315static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5316 SDValue Elt = N->getOperand(i); 5317 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5318 return Elt.getNode(); 5319 return Elt.getOperand(Elt.getResNo()).getNode(); 5320} 5321 5322/// CombineConsecutiveLoads - build_pair (load, load) -> load 5323/// if load locations are consecutive. 5324SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5325 assert(N->getOpcode() == ISD::BUILD_PAIR); 5326 5327 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5328 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5329 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5330 LD1->getPointerInfo().getAddrSpace() != 5331 LD2->getPointerInfo().getAddrSpace()) 5332 return SDValue(); 5333 EVT LD1VT = LD1->getValueType(0); 5334 5335 if (ISD::isNON_EXTLoad(LD2) && 5336 LD2->hasOneUse() && 5337 // If both are volatile this would reduce the number of volatile loads. 5338 // If one is volatile it might be ok, but play conservative and bail out. 5339 !LD1->isVolatile() && 5340 !LD2->isVolatile() && 5341 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5342 unsigned Align = LD1->getAlignment(); 5343 unsigned NewAlign = TLI.getTargetData()-> 5344 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5345 5346 if (NewAlign <= Align && 5347 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5348 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5349 LD1->getBasePtr(), LD1->getPointerInfo(), 5350 false, false, false, Align); 5351 } 5352 5353 return SDValue(); 5354} 5355 5356SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5357 SDValue N0 = N->getOperand(0); 5358 EVT VT = N->getValueType(0); 5359 5360 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5361 // Only do this before legalize, since afterward the target may be depending 5362 // on the bitconvert. 5363 // First check to see if this is all constant. 5364 if (!LegalTypes && 5365 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5366 VT.isVector()) { 5367 bool isSimple = true; 5368 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5369 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5370 N0.getOperand(i).getOpcode() != ISD::Constant && 5371 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5372 isSimple = false; 5373 break; 5374 } 5375 5376 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5377 assert(!DestEltVT.isVector() && 5378 "Element type of vector ValueType must not be vector!"); 5379 if (isSimple) 5380 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5381 } 5382 5383 // If the input is a constant, let getNode fold it. 5384 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5385 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5386 if (Res.getNode() != N) { 5387 if (!LegalOperations || 5388 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5389 return Res; 5390 5391 // Folding it resulted in an illegal node, and it's too late to 5392 // do that. Clean up the old node and forego the transformation. 5393 // Ideally this won't happen very often, because instcombine 5394 // and the earlier dagcombine runs (where illegal nodes are 5395 // permitted) should have folded most of them already. 5396 DAG.DeleteNode(Res.getNode()); 5397 } 5398 } 5399 5400 // (conv (conv x, t1), t2) -> (conv x, t2) 5401 if (N0.getOpcode() == ISD::BITCAST) 5402 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5403 N0.getOperand(0)); 5404 5405 // fold (conv (load x)) -> (load (conv*)x) 5406 // If the resultant load doesn't need a higher alignment than the original! 5407 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5408 // Do not change the width of a volatile load. 5409 !cast<LoadSDNode>(N0)->isVolatile() && 5410 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5411 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5412 unsigned Align = TLI.getTargetData()-> 5413 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5414 unsigned OrigAlign = LN0->getAlignment(); 5415 5416 if (Align <= OrigAlign) { 5417 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5418 LN0->getBasePtr(), LN0->getPointerInfo(), 5419 LN0->isVolatile(), LN0->isNonTemporal(), 5420 LN0->isInvariant(), OrigAlign); 5421 AddToWorkList(N); 5422 CombineTo(N0.getNode(), 5423 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5424 N0.getValueType(), Load), 5425 Load.getValue(1)); 5426 return Load; 5427 } 5428 } 5429 5430 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5431 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5432 // This often reduces constant pool loads. 5433 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5434 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5435 N0.getNode()->hasOneUse() && VT.isInteger() && 5436 !VT.isVector() && !N0.getValueType().isVector()) { 5437 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5438 N0.getOperand(0)); 5439 AddToWorkList(NewConv.getNode()); 5440 5441 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5442 if (N0.getOpcode() == ISD::FNEG) 5443 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5444 NewConv, DAG.getConstant(SignBit, VT)); 5445 assert(N0.getOpcode() == ISD::FABS); 5446 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5447 NewConv, DAG.getConstant(~SignBit, VT)); 5448 } 5449 5450 // fold (bitconvert (fcopysign cst, x)) -> 5451 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5452 // Note that we don't handle (copysign x, cst) because this can always be 5453 // folded to an fneg or fabs. 5454 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5455 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5456 VT.isInteger() && !VT.isVector()) { 5457 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5458 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5459 if (isTypeLegal(IntXVT)) { 5460 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5461 IntXVT, N0.getOperand(1)); 5462 AddToWorkList(X.getNode()); 5463 5464 // If X has a different width than the result/lhs, sext it or truncate it. 5465 unsigned VTWidth = VT.getSizeInBits(); 5466 if (OrigXWidth < VTWidth) { 5467 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5468 AddToWorkList(X.getNode()); 5469 } else if (OrigXWidth > VTWidth) { 5470 // To get the sign bit in the right place, we have to shift it right 5471 // before truncating. 5472 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5473 X.getValueType(), X, 5474 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5475 AddToWorkList(X.getNode()); 5476 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5477 AddToWorkList(X.getNode()); 5478 } 5479 5480 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5481 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5482 X, DAG.getConstant(SignBit, VT)); 5483 AddToWorkList(X.getNode()); 5484 5485 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5486 VT, N0.getOperand(0)); 5487 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5488 Cst, DAG.getConstant(~SignBit, VT)); 5489 AddToWorkList(Cst.getNode()); 5490 5491 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5492 } 5493 } 5494 5495 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5496 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5497 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5498 if (CombineLD.getNode()) 5499 return CombineLD; 5500 } 5501 5502 return SDValue(); 5503} 5504 5505SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5506 EVT VT = N->getValueType(0); 5507 return CombineConsecutiveLoads(N, VT); 5508} 5509 5510/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5511/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5512/// destination element value type. 5513SDValue DAGCombiner:: 5514ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5515 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5516 5517 // If this is already the right type, we're done. 5518 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5519 5520 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5521 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5522 5523 // If this is a conversion of N elements of one type to N elements of another 5524 // type, convert each element. This handles FP<->INT cases. 5525 if (SrcBitSize == DstBitSize) { 5526 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5527 BV->getValueType(0).getVectorNumElements()); 5528 5529 // Due to the FP element handling below calling this routine recursively, 5530 // we can end up with a scalar-to-vector node here. 5531 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5532 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5533 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5534 DstEltVT, BV->getOperand(0))); 5535 5536 SmallVector<SDValue, 8> Ops; 5537 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5538 SDValue Op = BV->getOperand(i); 5539 // If the vector element type is not legal, the BUILD_VECTOR operands 5540 // are promoted and implicitly truncated. Make that explicit here. 5541 if (Op.getValueType() != SrcEltVT) 5542 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5543 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5544 DstEltVT, Op)); 5545 AddToWorkList(Ops.back().getNode()); 5546 } 5547 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5548 &Ops[0], Ops.size()); 5549 } 5550 5551 // Otherwise, we're growing or shrinking the elements. To avoid having to 5552 // handle annoying details of growing/shrinking FP values, we convert them to 5553 // int first. 5554 if (SrcEltVT.isFloatingPoint()) { 5555 // Convert the input float vector to a int vector where the elements are the 5556 // same sizes. 5557 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5558 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5559 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5560 SrcEltVT = IntVT; 5561 } 5562 5563 // Now we know the input is an integer vector. If the output is a FP type, 5564 // convert to integer first, then to FP of the right size. 5565 if (DstEltVT.isFloatingPoint()) { 5566 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5567 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5568 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5569 5570 // Next, convert to FP elements of the same size. 5571 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5572 } 5573 5574 // Okay, we know the src/dst types are both integers of differing types. 5575 // Handling growing first. 5576 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5577 if (SrcBitSize < DstBitSize) { 5578 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5579 5580 SmallVector<SDValue, 8> Ops; 5581 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5582 i += NumInputsPerOutput) { 5583 bool isLE = TLI.isLittleEndian(); 5584 APInt NewBits = APInt(DstBitSize, 0); 5585 bool EltIsUndef = true; 5586 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5587 // Shift the previously computed bits over. 5588 NewBits <<= SrcBitSize; 5589 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5590 if (Op.getOpcode() == ISD::UNDEF) continue; 5591 EltIsUndef = false; 5592 5593 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5594 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5595 } 5596 5597 if (EltIsUndef) 5598 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5599 else 5600 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5601 } 5602 5603 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5604 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5605 &Ops[0], Ops.size()); 5606 } 5607 5608 // Finally, this must be the case where we are shrinking elements: each input 5609 // turns into multiple outputs. 5610 bool isS2V = ISD::isScalarToVector(BV); 5611 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5612 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5613 NumOutputsPerInput*BV->getNumOperands()); 5614 SmallVector<SDValue, 8> Ops; 5615 5616 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5617 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5618 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5619 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5620 continue; 5621 } 5622 5623 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5624 getAPIntValue().zextOrTrunc(SrcBitSize); 5625 5626 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5627 APInt ThisVal = OpVal.trunc(DstBitSize); 5628 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5629 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5630 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5631 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5632 Ops[0]); 5633 OpVal = OpVal.lshr(DstBitSize); 5634 } 5635 5636 // For big endian targets, swap the order of the pieces of each element. 5637 if (TLI.isBigEndian()) 5638 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5639 } 5640 5641 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5642 &Ops[0], Ops.size()); 5643} 5644 5645SDValue DAGCombiner::visitFADD(SDNode *N) { 5646 SDValue N0 = N->getOperand(0); 5647 SDValue N1 = N->getOperand(1); 5648 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5649 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5650 EVT VT = N->getValueType(0); 5651 5652 // fold vector ops 5653 if (VT.isVector()) { 5654 SDValue FoldedVOp = SimplifyVBinOp(N); 5655 if (FoldedVOp.getNode()) return FoldedVOp; 5656 } 5657 5658 // fold (fadd c1, c2) -> c1 + c2 5659 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5660 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5661 // canonicalize constant to RHS 5662 if (N0CFP && !N1CFP) 5663 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5664 // fold (fadd A, 0) -> A 5665 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5666 N1CFP->getValueAPF().isZero()) 5667 return N0; 5668 // fold (fadd A, (fneg B)) -> (fsub A, B) 5669 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5670 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5671 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5672 GetNegatedExpression(N1, DAG, LegalOperations)); 5673 // fold (fadd (fneg A), B) -> (fsub B, A) 5674 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5675 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5676 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5677 GetNegatedExpression(N0, DAG, LegalOperations)); 5678 5679 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5680 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5681 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5682 isa<ConstantFPSDNode>(N0.getOperand(1))) 5683 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5684 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5685 N0.getOperand(1), N1)); 5686 5687 // In unsafe math mode, we can fold chains of FADD's of the same value 5688 // into multiplications. This transform is not safe in general because 5689 // we are reducing the number of rounding steps. 5690 if (DAG.getTarget().Options.UnsafeFPMath && 5691 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5692 !N0CFP && !N1CFP) { 5693 if (N0.getOpcode() == ISD::FMUL) { 5694 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5695 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 5696 5697 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5698 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 5699 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5700 SDValue(CFP00, 0), 5701 DAG.getConstantFP(1.0, VT)); 5702 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5703 N1, NewCFP); 5704 } 5705 5706 // (fadd (fmul x, c), x) -> (fmul c+1, x) 5707 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 5708 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5709 SDValue(CFP01, 0), 5710 DAG.getConstantFP(1.0, VT)); 5711 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5712 N1, NewCFP); 5713 } 5714 5715 // (fadd (fadd x, x), x) -> (fmul 3.0, x) 5716 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) && 5717 N0.getOperand(0) == N1) { 5718 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5719 N1, DAG.getConstantFP(3.0, VT)); 5720 } 5721 5722 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x) 5723 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 5724 N1.getOperand(0) == N1.getOperand(1) && 5725 N0.getOperand(1) == N1.getOperand(0)) { 5726 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5727 SDValue(CFP00, 0), 5728 DAG.getConstantFP(2.0, VT)); 5729 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5730 N0.getOperand(1), NewCFP); 5731 } 5732 5733 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x) 5734 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 5735 N1.getOperand(0) == N1.getOperand(1) && 5736 N0.getOperand(0) == N1.getOperand(0)) { 5737 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5738 SDValue(CFP01, 0), 5739 DAG.getConstantFP(2.0, VT)); 5740 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5741 N0.getOperand(0), NewCFP); 5742 } 5743 } 5744 5745 if (N1.getOpcode() == ISD::FMUL) { 5746 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5747 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 5748 5749 // (fadd x, (fmul c, x)) -> (fmul c+1, x) 5750 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 5751 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5752 SDValue(CFP10, 0), 5753 DAG.getConstantFP(1.0, VT)); 5754 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5755 N0, NewCFP); 5756 } 5757 5758 // (fadd x, (fmul x, c)) -> (fmul c+1, x) 5759 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 5760 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5761 SDValue(CFP11, 0), 5762 DAG.getConstantFP(1.0, VT)); 5763 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5764 N0, NewCFP); 5765 } 5766 5767 // (fadd x, (fadd x, x)) -> (fmul 3.0, x) 5768 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) && 5769 N1.getOperand(0) == N0) { 5770 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5771 N0, DAG.getConstantFP(3.0, VT)); 5772 } 5773 5774 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x) 5775 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD && 5776 N1.getOperand(0) == N1.getOperand(1) && 5777 N0.getOperand(1) == N1.getOperand(0)) { 5778 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5779 SDValue(CFP10, 0), 5780 DAG.getConstantFP(2.0, VT)); 5781 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5782 N0.getOperand(1), NewCFP); 5783 } 5784 5785 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x) 5786 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD && 5787 N1.getOperand(0) == N1.getOperand(1) && 5788 N0.getOperand(0) == N1.getOperand(0)) { 5789 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5790 SDValue(CFP11, 0), 5791 DAG.getConstantFP(2.0, VT)); 5792 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5793 N0.getOperand(0), NewCFP); 5794 } 5795 } 5796 5797 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x) 5798 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 5799 N0.getOperand(0) == N0.getOperand(1) && 5800 N1.getOperand(0) == N1.getOperand(1) && 5801 N0.getOperand(0) == N1.getOperand(0)) { 5802 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5803 N0.getOperand(0), 5804 DAG.getConstantFP(4.0, VT)); 5805 } 5806 } 5807 5808 // FADD -> FMA combines: 5809 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5810 DAG.getTarget().Options.UnsafeFPMath) && 5811 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5812 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5813 5814 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 5815 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5816 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5817 N0.getOperand(0), N0.getOperand(1), N1); 5818 } 5819 5820 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 5821 // Note: Commutes FADD operands. 5822 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5823 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5824 N1.getOperand(0), N1.getOperand(1), N0); 5825 } 5826 } 5827 5828 return SDValue(); 5829} 5830 5831SDValue DAGCombiner::visitFSUB(SDNode *N) { 5832 SDValue N0 = N->getOperand(0); 5833 SDValue N1 = N->getOperand(1); 5834 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5835 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5836 EVT VT = N->getValueType(0); 5837 DebugLoc dl = N->getDebugLoc(); 5838 5839 // fold vector ops 5840 if (VT.isVector()) { 5841 SDValue FoldedVOp = SimplifyVBinOp(N); 5842 if (FoldedVOp.getNode()) return FoldedVOp; 5843 } 5844 5845 // fold (fsub c1, c2) -> c1-c2 5846 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5847 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5848 // fold (fsub A, 0) -> A 5849 if (DAG.getTarget().Options.UnsafeFPMath && 5850 N1CFP && N1CFP->getValueAPF().isZero()) 5851 return N0; 5852 // fold (fsub 0, B) -> -B 5853 if (DAG.getTarget().Options.UnsafeFPMath && 5854 N0CFP && N0CFP->getValueAPF().isZero()) { 5855 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5856 return GetNegatedExpression(N1, DAG, LegalOperations); 5857 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5858 return DAG.getNode(ISD::FNEG, dl, VT, N1); 5859 } 5860 // fold (fsub A, (fneg B)) -> (fadd A, B) 5861 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5862 return DAG.getNode(ISD::FADD, dl, VT, N0, 5863 GetNegatedExpression(N1, DAG, LegalOperations)); 5864 5865 // If 'unsafe math' is enabled, fold 5866 // (fsub x, x) -> 0.0 & 5867 // (fsub x, (fadd x, y)) -> (fneg y) & 5868 // (fsub x, (fadd y, x)) -> (fneg y) 5869 if (DAG.getTarget().Options.UnsafeFPMath) { 5870 if (N0 == N1) 5871 return DAG.getConstantFP(0.0f, VT); 5872 5873 if (N1.getOpcode() == ISD::FADD) { 5874 SDValue N10 = N1->getOperand(0); 5875 SDValue N11 = N1->getOperand(1); 5876 5877 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5878 &DAG.getTarget().Options)) 5879 return GetNegatedExpression(N11, DAG, LegalOperations); 5880 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5881 &DAG.getTarget().Options)) 5882 return GetNegatedExpression(N10, DAG, LegalOperations); 5883 } 5884 } 5885 5886 // FSUB -> FMA combines: 5887 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5888 DAG.getTarget().Options.UnsafeFPMath) && 5889 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5890 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5891 5892 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 5893 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5894 return DAG.getNode(ISD::FMA, dl, VT, 5895 N0.getOperand(0), N0.getOperand(1), 5896 DAG.getNode(ISD::FNEG, dl, VT, N1)); 5897 } 5898 5899 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 5900 // Note: Commutes FSUB operands. 5901 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5902 return DAG.getNode(ISD::FMA, dl, VT, 5903 DAG.getNode(ISD::FNEG, dl, VT, 5904 N1.getOperand(0)), 5905 N1.getOperand(1), N0); 5906 } 5907 5908 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 5909 if (N0.getOpcode() == ISD::FNEG && 5910 N0.getOperand(0).getOpcode() == ISD::FMUL && 5911 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 5912 SDValue N00 = N0.getOperand(0).getOperand(0); 5913 SDValue N01 = N0.getOperand(0).getOperand(1); 5914 return DAG.getNode(ISD::FMA, dl, VT, 5915 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 5916 DAG.getNode(ISD::FNEG, dl, VT, N1)); 5917 } 5918 } 5919 5920 return SDValue(); 5921} 5922 5923SDValue DAGCombiner::visitFMUL(SDNode *N) { 5924 SDValue N0 = N->getOperand(0); 5925 SDValue N1 = N->getOperand(1); 5926 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5927 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5928 EVT VT = N->getValueType(0); 5929 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5930 5931 // fold vector ops 5932 if (VT.isVector()) { 5933 SDValue FoldedVOp = SimplifyVBinOp(N); 5934 if (FoldedVOp.getNode()) return FoldedVOp; 5935 } 5936 5937 // fold (fmul c1, c2) -> c1*c2 5938 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5939 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5940 // canonicalize constant to RHS 5941 if (N0CFP && !N1CFP) 5942 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5943 // fold (fmul A, 0) -> 0 5944 if (DAG.getTarget().Options.UnsafeFPMath && 5945 N1CFP && N1CFP->getValueAPF().isZero()) 5946 return N1; 5947 // fold (fmul A, 0) -> 0, vector edition. 5948 if (DAG.getTarget().Options.UnsafeFPMath && 5949 ISD::isBuildVectorAllZeros(N1.getNode())) 5950 return N1; 5951 // fold (fmul A, 1.0) -> A 5952 if (N1CFP && N1CFP->isExactlyValue(1.0)) 5953 return N0; 5954 // fold (fmul X, 2.0) -> (fadd X, X) 5955 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5956 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5957 // fold (fmul X, -1.0) -> (fneg X) 5958 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5959 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5960 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5961 5962 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5963 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5964 &DAG.getTarget().Options)) { 5965 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5966 &DAG.getTarget().Options)) { 5967 // Both can be negated for free, check to see if at least one is cheaper 5968 // negated. 5969 if (LHSNeg == 2 || RHSNeg == 2) 5970 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5971 GetNegatedExpression(N0, DAG, LegalOperations), 5972 GetNegatedExpression(N1, DAG, LegalOperations)); 5973 } 5974 } 5975 5976 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5977 if (DAG.getTarget().Options.UnsafeFPMath && 5978 N1CFP && N0.getOpcode() == ISD::FMUL && 5979 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5980 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5981 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5982 N0.getOperand(1), N1)); 5983 5984 return SDValue(); 5985} 5986 5987SDValue DAGCombiner::visitFMA(SDNode *N) { 5988 SDValue N0 = N->getOperand(0); 5989 SDValue N1 = N->getOperand(1); 5990 SDValue N2 = N->getOperand(2); 5991 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5992 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5993 EVT VT = N->getValueType(0); 5994 DebugLoc dl = N->getDebugLoc(); 5995 5996 if (N0CFP && N0CFP->isExactlyValue(1.0)) 5997 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); 5998 if (N1CFP && N1CFP->isExactlyValue(1.0)) 5999 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); 6000 6001 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6002 if (N0CFP && !N1CFP) 6003 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); 6004 6005 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6006 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6007 N2.getOpcode() == ISD::FMUL && 6008 N0 == N2.getOperand(0) && 6009 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6010 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6011 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6012 } 6013 6014 6015 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6016 if (DAG.getTarget().Options.UnsafeFPMath && 6017 N0.getOpcode() == ISD::FMUL && N1CFP && 6018 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6019 return DAG.getNode(ISD::FMA, dl, VT, 6020 N0.getOperand(0), 6021 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6022 N2); 6023 } 6024 6025 // (fma x, 1, y) -> (fadd x, y) 6026 // (fma x, -1, y) -> (fadd (fneg x), y) 6027 if (N1CFP) { 6028 if (N1CFP->isExactlyValue(1.0)) 6029 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6030 6031 if (N1CFP->isExactlyValue(-1.0) && 6032 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6033 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6034 AddToWorkList(RHSNeg.getNode()); 6035 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6036 } 6037 } 6038 6039 // (fma x, c, x) -> (fmul x, (c+1)) 6040 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) { 6041 return DAG.getNode(ISD::FMUL, dl, VT, 6042 N0, 6043 DAG.getNode(ISD::FADD, dl, VT, 6044 N1, DAG.getConstantFP(1.0, VT))); 6045 } 6046 6047 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6048 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6049 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { 6050 return DAG.getNode(ISD::FMUL, dl, VT, 6051 N0, 6052 DAG.getNode(ISD::FADD, dl, VT, 6053 N1, DAG.getConstantFP(-1.0, VT))); 6054 } 6055 6056 6057 return SDValue(); 6058} 6059 6060SDValue DAGCombiner::visitFDIV(SDNode *N) { 6061 SDValue N0 = N->getOperand(0); 6062 SDValue N1 = N->getOperand(1); 6063 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6064 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6065 EVT VT = N->getValueType(0); 6066 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6067 6068 // fold vector ops 6069 if (VT.isVector()) { 6070 SDValue FoldedVOp = SimplifyVBinOp(N); 6071 if (FoldedVOp.getNode()) return FoldedVOp; 6072 } 6073 6074 // fold (fdiv c1, c2) -> c1/c2 6075 if (N0CFP && N1CFP && VT != MVT::ppcf128) 6076 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 6077 6078 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6079 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) { 6080 // Compute the reciprocal 1.0 / c2. 6081 APFloat N1APF = N1CFP->getValueAPF(); 6082 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6083 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6084 // Only do the transform if the reciprocal is a legal fp immediate that 6085 // isn't too nasty (eg NaN, denormal, ...). 6086 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6087 (!LegalOperations || 6088 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6089 // backend)... we should handle this gracefully after Legalize. 6090 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6091 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6092 TLI.isFPImmLegal(Recip, VT))) 6093 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 6094 DAG.getConstantFP(Recip, VT)); 6095 } 6096 6097 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6098 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6099 &DAG.getTarget().Options)) { 6100 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6101 &DAG.getTarget().Options)) { 6102 // Both can be negated for free, check to see if at least one is cheaper 6103 // negated. 6104 if (LHSNeg == 2 || RHSNeg == 2) 6105 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 6106 GetNegatedExpression(N0, DAG, LegalOperations), 6107 GetNegatedExpression(N1, DAG, LegalOperations)); 6108 } 6109 } 6110 6111 return SDValue(); 6112} 6113 6114SDValue DAGCombiner::visitFREM(SDNode *N) { 6115 SDValue N0 = N->getOperand(0); 6116 SDValue N1 = N->getOperand(1); 6117 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6118 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6119 EVT VT = N->getValueType(0); 6120 6121 // fold (frem c1, c2) -> fmod(c1,c2) 6122 if (N0CFP && N1CFP && VT != MVT::ppcf128) 6123 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 6124 6125 return SDValue(); 6126} 6127 6128SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6129 SDValue N0 = N->getOperand(0); 6130 SDValue N1 = N->getOperand(1); 6131 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6132 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6133 EVT VT = N->getValueType(0); 6134 6135 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 6136 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 6137 6138 if (N1CFP) { 6139 const APFloat& V = N1CFP->getValueAPF(); 6140 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6141 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6142 if (!V.isNegative()) { 6143 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6144 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6145 } else { 6146 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6147 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6148 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 6149 } 6150 } 6151 6152 // copysign(fabs(x), y) -> copysign(x, y) 6153 // copysign(fneg(x), y) -> copysign(x, y) 6154 // copysign(copysign(x,z), y) -> copysign(x, y) 6155 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6156 N0.getOpcode() == ISD::FCOPYSIGN) 6157 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6158 N0.getOperand(0), N1); 6159 6160 // copysign(x, abs(y)) -> abs(x) 6161 if (N1.getOpcode() == ISD::FABS) 6162 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6163 6164 // copysign(x, copysign(y,z)) -> copysign(x, z) 6165 if (N1.getOpcode() == ISD::FCOPYSIGN) 6166 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6167 N0, N1.getOperand(1)); 6168 6169 // copysign(x, fp_extend(y)) -> copysign(x, y) 6170 // copysign(x, fp_round(y)) -> copysign(x, y) 6171 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6172 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6173 N0, N1.getOperand(0)); 6174 6175 return SDValue(); 6176} 6177 6178SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6179 SDValue N0 = N->getOperand(0); 6180 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6181 EVT VT = N->getValueType(0); 6182 EVT OpVT = N0.getValueType(); 6183 6184 // fold (sint_to_fp c1) -> c1fp 6185 if (N0C && OpVT != MVT::ppcf128 && 6186 // ...but only if the target supports immediate floating-point values 6187 (!LegalOperations || 6188 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6189 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6190 6191 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6192 // but UINT_TO_FP is legal on this target, try to convert. 6193 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6194 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6195 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6196 if (DAG.SignBitIsZero(N0)) 6197 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6198 } 6199 6200 // The next optimizations are desireable only if SELECT_CC can be lowered. 6201 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6202 // having to say they don't support SELECT_CC on every type the DAG knows 6203 // about, since there is no way to mark an opcode illegal at all value types 6204 // (See also visitSELECT) 6205 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6206 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6207 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6208 !VT.isVector() && 6209 (!LegalOperations || 6210 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6211 SDValue Ops[] = 6212 { N0.getOperand(0), N0.getOperand(1), 6213 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6214 N0.getOperand(2) }; 6215 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6216 } 6217 6218 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6219 // (select_cc x, y, 1.0, 0.0,, cc) 6220 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6221 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6222 (!LegalOperations || 6223 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6224 SDValue Ops[] = 6225 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6226 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6227 N0.getOperand(0).getOperand(2) }; 6228 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6229 } 6230 } 6231 6232 return SDValue(); 6233} 6234 6235SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6236 SDValue N0 = N->getOperand(0); 6237 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6238 EVT VT = N->getValueType(0); 6239 EVT OpVT = N0.getValueType(); 6240 6241 // fold (uint_to_fp c1) -> c1fp 6242 if (N0C && OpVT != MVT::ppcf128 && 6243 // ...but only if the target supports immediate floating-point values 6244 (!LegalOperations || 6245 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6246 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6247 6248 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6249 // but SINT_TO_FP is legal on this target, try to convert. 6250 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6251 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6252 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6253 if (DAG.SignBitIsZero(N0)) 6254 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6255 } 6256 6257 // The next optimizations are desireable only if SELECT_CC can be lowered. 6258 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6259 // having to say they don't support SELECT_CC on every type the DAG knows 6260 // about, since there is no way to mark an opcode illegal at all value types 6261 // (See also visitSELECT) 6262 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6263 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6264 6265 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6266 (!LegalOperations || 6267 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6268 SDValue Ops[] = 6269 { N0.getOperand(0), N0.getOperand(1), 6270 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6271 N0.getOperand(2) }; 6272 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6273 } 6274 } 6275 6276 return SDValue(); 6277} 6278 6279SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6280 SDValue N0 = N->getOperand(0); 6281 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6282 EVT VT = N->getValueType(0); 6283 6284 // fold (fp_to_sint c1fp) -> c1 6285 if (N0CFP) 6286 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 6287 6288 return SDValue(); 6289} 6290 6291SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6292 SDValue N0 = N->getOperand(0); 6293 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6294 EVT VT = N->getValueType(0); 6295 6296 // fold (fp_to_uint c1fp) -> c1 6297 if (N0CFP && VT != MVT::ppcf128) 6298 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 6299 6300 return SDValue(); 6301} 6302 6303SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6304 SDValue N0 = N->getOperand(0); 6305 SDValue N1 = N->getOperand(1); 6306 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6307 EVT VT = N->getValueType(0); 6308 6309 // fold (fp_round c1fp) -> c1fp 6310 if (N0CFP && N0.getValueType() != MVT::ppcf128) 6311 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 6312 6313 // fold (fp_round (fp_extend x)) -> x 6314 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6315 return N0.getOperand(0); 6316 6317 // fold (fp_round (fp_round x)) -> (fp_round x) 6318 if (N0.getOpcode() == ISD::FP_ROUND) { 6319 // This is a value preserving truncation if both round's are. 6320 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6321 N0.getNode()->getConstantOperandVal(1) == 1; 6322 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 6323 DAG.getIntPtrConstant(IsTrunc)); 6324 } 6325 6326 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6327 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6328 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 6329 N0.getOperand(0), N1); 6330 AddToWorkList(Tmp.getNode()); 6331 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6332 Tmp, N0.getOperand(1)); 6333 } 6334 6335 return SDValue(); 6336} 6337 6338SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6339 SDValue N0 = N->getOperand(0); 6340 EVT VT = N->getValueType(0); 6341 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6342 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6343 6344 // fold (fp_round_inreg c1fp) -> c1fp 6345 if (N0CFP && isTypeLegal(EVT)) { 6346 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6347 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 6348 } 6349 6350 return SDValue(); 6351} 6352 6353SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6354 SDValue N0 = N->getOperand(0); 6355 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6356 EVT VT = N->getValueType(0); 6357 6358 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6359 if (N->hasOneUse() && 6360 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6361 return SDValue(); 6362 6363 // fold (fp_extend c1fp) -> c1fp 6364 if (N0CFP && VT != MVT::ppcf128) 6365 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6366 6367 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6368 // value of X. 6369 if (N0.getOpcode() == ISD::FP_ROUND 6370 && N0.getNode()->getConstantOperandVal(1) == 1) { 6371 SDValue In = N0.getOperand(0); 6372 if (In.getValueType() == VT) return In; 6373 if (VT.bitsLT(In.getValueType())) 6374 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6375 In, N0.getOperand(1)); 6376 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6377 } 6378 6379 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6380 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6381 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6382 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6383 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6384 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6385 LN0->getChain(), 6386 LN0->getBasePtr(), LN0->getPointerInfo(), 6387 N0.getValueType(), 6388 LN0->isVolatile(), LN0->isNonTemporal(), 6389 LN0->getAlignment()); 6390 CombineTo(N, ExtLoad); 6391 CombineTo(N0.getNode(), 6392 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6393 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6394 ExtLoad.getValue(1)); 6395 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6396 } 6397 6398 return SDValue(); 6399} 6400 6401SDValue DAGCombiner::visitFNEG(SDNode *N) { 6402 SDValue N0 = N->getOperand(0); 6403 EVT VT = N->getValueType(0); 6404 6405 if (VT.isVector()) { 6406 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6407 if (FoldedVOp.getNode()) return FoldedVOp; 6408 } 6409 6410 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6411 &DAG.getTarget().Options)) 6412 return GetNegatedExpression(N0, DAG, LegalOperations); 6413 6414 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6415 // constant pool values. 6416 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6417 !VT.isVector() && 6418 N0.getNode()->hasOneUse() && 6419 N0.getOperand(0).getValueType().isInteger()) { 6420 SDValue Int = N0.getOperand(0); 6421 EVT IntVT = Int.getValueType(); 6422 if (IntVT.isInteger() && !IntVT.isVector()) { 6423 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6424 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6425 AddToWorkList(Int.getNode()); 6426 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6427 VT, Int); 6428 } 6429 } 6430 6431 // (fneg (fmul c, x)) -> (fmul -c, x) 6432 if (N0.getOpcode() == ISD::FMUL) { 6433 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6434 if (CFP1) { 6435 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6436 N0.getOperand(0), 6437 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6438 N0.getOperand(1))); 6439 } 6440 } 6441 6442 return SDValue(); 6443} 6444 6445SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6446 SDValue N0 = N->getOperand(0); 6447 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6448 EVT VT = N->getValueType(0); 6449 6450 // fold (fceil c1) -> fceil(c1) 6451 if (N0CFP && VT != MVT::ppcf128) 6452 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0); 6453 6454 return SDValue(); 6455} 6456 6457SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6458 SDValue N0 = N->getOperand(0); 6459 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6460 EVT VT = N->getValueType(0); 6461 6462 // fold (ftrunc c1) -> ftrunc(c1) 6463 if (N0CFP && VT != MVT::ppcf128) 6464 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0); 6465 6466 return SDValue(); 6467} 6468 6469SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6470 SDValue N0 = N->getOperand(0); 6471 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6472 EVT VT = N->getValueType(0); 6473 6474 // fold (ffloor c1) -> ffloor(c1) 6475 if (N0CFP && VT != MVT::ppcf128) 6476 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0); 6477 6478 return SDValue(); 6479} 6480 6481SDValue DAGCombiner::visitFABS(SDNode *N) { 6482 SDValue N0 = N->getOperand(0); 6483 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6484 EVT VT = N->getValueType(0); 6485 6486 if (VT.isVector()) { 6487 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6488 if (FoldedVOp.getNode()) return FoldedVOp; 6489 } 6490 6491 // fold (fabs c1) -> fabs(c1) 6492 if (N0CFP && VT != MVT::ppcf128) 6493 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6494 // fold (fabs (fabs x)) -> (fabs x) 6495 if (N0.getOpcode() == ISD::FABS) 6496 return N->getOperand(0); 6497 // fold (fabs (fneg x)) -> (fabs x) 6498 // fold (fabs (fcopysign x, y)) -> (fabs x) 6499 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6500 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6501 6502 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6503 // constant pool values. 6504 if (!TLI.isFAbsFree(VT) && 6505 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6506 N0.getOperand(0).getValueType().isInteger() && 6507 !N0.getOperand(0).getValueType().isVector()) { 6508 SDValue Int = N0.getOperand(0); 6509 EVT IntVT = Int.getValueType(); 6510 if (IntVT.isInteger() && !IntVT.isVector()) { 6511 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6512 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6513 AddToWorkList(Int.getNode()); 6514 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6515 N->getValueType(0), Int); 6516 } 6517 } 6518 6519 return SDValue(); 6520} 6521 6522SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6523 SDValue Chain = N->getOperand(0); 6524 SDValue N1 = N->getOperand(1); 6525 SDValue N2 = N->getOperand(2); 6526 6527 // If N is a constant we could fold this into a fallthrough or unconditional 6528 // branch. However that doesn't happen very often in normal code, because 6529 // Instcombine/SimplifyCFG should have handled the available opportunities. 6530 // If we did this folding here, it would be necessary to update the 6531 // MachineBasicBlock CFG, which is awkward. 6532 6533 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6534 // on the target. 6535 if (N1.getOpcode() == ISD::SETCC && 6536 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6537 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6538 Chain, N1.getOperand(2), 6539 N1.getOperand(0), N1.getOperand(1), N2); 6540 } 6541 6542 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6543 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6544 (N1.getOperand(0).hasOneUse() && 6545 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6546 SDNode *Trunc = 0; 6547 if (N1.getOpcode() == ISD::TRUNCATE) { 6548 // Look pass the truncate. 6549 Trunc = N1.getNode(); 6550 N1 = N1.getOperand(0); 6551 } 6552 6553 // Match this pattern so that we can generate simpler code: 6554 // 6555 // %a = ... 6556 // %b = and i32 %a, 2 6557 // %c = srl i32 %b, 1 6558 // brcond i32 %c ... 6559 // 6560 // into 6561 // 6562 // %a = ... 6563 // %b = and i32 %a, 2 6564 // %c = setcc eq %b, 0 6565 // brcond %c ... 6566 // 6567 // This applies only when the AND constant value has one bit set and the 6568 // SRL constant is equal to the log2 of the AND constant. The back-end is 6569 // smart enough to convert the result into a TEST/JMP sequence. 6570 SDValue Op0 = N1.getOperand(0); 6571 SDValue Op1 = N1.getOperand(1); 6572 6573 if (Op0.getOpcode() == ISD::AND && 6574 Op1.getOpcode() == ISD::Constant) { 6575 SDValue AndOp1 = Op0.getOperand(1); 6576 6577 if (AndOp1.getOpcode() == ISD::Constant) { 6578 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6579 6580 if (AndConst.isPowerOf2() && 6581 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6582 SDValue SetCC = 6583 DAG.getSetCC(N->getDebugLoc(), 6584 TLI.getSetCCResultType(Op0.getValueType()), 6585 Op0, DAG.getConstant(0, Op0.getValueType()), 6586 ISD::SETNE); 6587 6588 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6589 MVT::Other, Chain, SetCC, N2); 6590 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6591 // will convert it back to (X & C1) >> C2. 6592 CombineTo(N, NewBRCond, false); 6593 // Truncate is dead. 6594 if (Trunc) { 6595 removeFromWorkList(Trunc); 6596 DAG.DeleteNode(Trunc); 6597 } 6598 // Replace the uses of SRL with SETCC 6599 WorkListRemover DeadNodes(*this); 6600 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6601 removeFromWorkList(N1.getNode()); 6602 DAG.DeleteNode(N1.getNode()); 6603 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6604 } 6605 } 6606 } 6607 6608 if (Trunc) 6609 // Restore N1 if the above transformation doesn't match. 6610 N1 = N->getOperand(1); 6611 } 6612 6613 // Transform br(xor(x, y)) -> br(x != y) 6614 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6615 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6616 SDNode *TheXor = N1.getNode(); 6617 SDValue Op0 = TheXor->getOperand(0); 6618 SDValue Op1 = TheXor->getOperand(1); 6619 if (Op0.getOpcode() == Op1.getOpcode()) { 6620 // Avoid missing important xor optimizations. 6621 SDValue Tmp = visitXOR(TheXor); 6622 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6623 DEBUG(dbgs() << "\nReplacing.8 "; 6624 TheXor->dump(&DAG); 6625 dbgs() << "\nWith: "; 6626 Tmp.getNode()->dump(&DAG); 6627 dbgs() << '\n'); 6628 WorkListRemover DeadNodes(*this); 6629 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6630 removeFromWorkList(TheXor); 6631 DAG.DeleteNode(TheXor); 6632 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6633 MVT::Other, Chain, Tmp, N2); 6634 } 6635 } 6636 6637 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6638 bool Equal = false; 6639 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6640 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6641 Op0.getOpcode() == ISD::XOR) { 6642 TheXor = Op0.getNode(); 6643 Equal = true; 6644 } 6645 6646 EVT SetCCVT = N1.getValueType(); 6647 if (LegalTypes) 6648 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6649 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6650 SetCCVT, 6651 Op0, Op1, 6652 Equal ? ISD::SETEQ : ISD::SETNE); 6653 // Replace the uses of XOR with SETCC 6654 WorkListRemover DeadNodes(*this); 6655 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6656 removeFromWorkList(N1.getNode()); 6657 DAG.DeleteNode(N1.getNode()); 6658 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6659 MVT::Other, Chain, SetCC, N2); 6660 } 6661 } 6662 6663 return SDValue(); 6664} 6665 6666// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6667// 6668SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6669 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6670 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6671 6672 // If N is a constant we could fold this into a fallthrough or unconditional 6673 // branch. However that doesn't happen very often in normal code, because 6674 // Instcombine/SimplifyCFG should have handled the available opportunities. 6675 // If we did this folding here, it would be necessary to update the 6676 // MachineBasicBlock CFG, which is awkward. 6677 6678 // Use SimplifySetCC to simplify SETCC's. 6679 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6680 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6681 false); 6682 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6683 6684 // fold to a simpler setcc 6685 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6686 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6687 N->getOperand(0), Simp.getOperand(2), 6688 Simp.getOperand(0), Simp.getOperand(1), 6689 N->getOperand(4)); 6690 6691 return SDValue(); 6692} 6693 6694/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6695/// uses N as its base pointer and that N may be folded in the load / store 6696/// addressing mode. 6697static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6698 SelectionDAG &DAG, 6699 const TargetLowering &TLI) { 6700 EVT VT; 6701 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6702 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6703 return false; 6704 VT = Use->getValueType(0); 6705 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6706 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6707 return false; 6708 VT = ST->getValue().getValueType(); 6709 } else 6710 return false; 6711 6712 TargetLowering::AddrMode AM; 6713 if (N->getOpcode() == ISD::ADD) { 6714 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6715 if (Offset) 6716 // [reg +/- imm] 6717 AM.BaseOffs = Offset->getSExtValue(); 6718 else 6719 // [reg +/- reg] 6720 AM.Scale = 1; 6721 } else if (N->getOpcode() == ISD::SUB) { 6722 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6723 if (Offset) 6724 // [reg +/- imm] 6725 AM.BaseOffs = -Offset->getSExtValue(); 6726 else 6727 // [reg +/- reg] 6728 AM.Scale = 1; 6729 } else 6730 return false; 6731 6732 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6733} 6734 6735/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6736/// pre-indexed load / store when the base pointer is an add or subtract 6737/// and it has other uses besides the load / store. After the 6738/// transformation, the new indexed load / store has effectively folded 6739/// the add / subtract in and all of its other uses are redirected to the 6740/// new load / store. 6741bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6742 if (Level < AfterLegalizeDAG) 6743 return false; 6744 6745 bool isLoad = true; 6746 SDValue Ptr; 6747 EVT VT; 6748 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6749 if (LD->isIndexed()) 6750 return false; 6751 VT = LD->getMemoryVT(); 6752 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6753 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6754 return false; 6755 Ptr = LD->getBasePtr(); 6756 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6757 if (ST->isIndexed()) 6758 return false; 6759 VT = ST->getMemoryVT(); 6760 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6761 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6762 return false; 6763 Ptr = ST->getBasePtr(); 6764 isLoad = false; 6765 } else { 6766 return false; 6767 } 6768 6769 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6770 // out. There is no reason to make this a preinc/predec. 6771 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6772 Ptr.getNode()->hasOneUse()) 6773 return false; 6774 6775 // Ask the target to do addressing mode selection. 6776 SDValue BasePtr; 6777 SDValue Offset; 6778 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6779 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6780 return false; 6781 // Don't create a indexed load / store with zero offset. 6782 if (isa<ConstantSDNode>(Offset) && 6783 cast<ConstantSDNode>(Offset)->isNullValue()) 6784 return false; 6785 6786 // Try turning it into a pre-indexed load / store except when: 6787 // 1) The new base ptr is a frame index. 6788 // 2) If N is a store and the new base ptr is either the same as or is a 6789 // predecessor of the value being stored. 6790 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6791 // that would create a cycle. 6792 // 4) All uses are load / store ops that use it as old base ptr. 6793 6794 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6795 // (plus the implicit offset) to a register to preinc anyway. 6796 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6797 return false; 6798 6799 // Check #2. 6800 if (!isLoad) { 6801 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6802 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6803 return false; 6804 } 6805 6806 // Now check for #3 and #4. 6807 bool RealUse = false; 6808 6809 // Caches for hasPredecessorHelper 6810 SmallPtrSet<const SDNode *, 32> Visited; 6811 SmallVector<const SDNode *, 16> Worklist; 6812 6813 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6814 E = Ptr.getNode()->use_end(); I != E; ++I) { 6815 SDNode *Use = *I; 6816 if (Use == N) 6817 continue; 6818 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6819 return false; 6820 6821 // If Ptr may be folded in addressing mode of other use, then it's 6822 // not profitable to do this transformation. 6823 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6824 RealUse = true; 6825 } 6826 6827 if (!RealUse) 6828 return false; 6829 6830 SDValue Result; 6831 if (isLoad) 6832 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6833 BasePtr, Offset, AM); 6834 else 6835 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6836 BasePtr, Offset, AM); 6837 ++PreIndexedNodes; 6838 ++NodesCombined; 6839 DEBUG(dbgs() << "\nReplacing.4 "; 6840 N->dump(&DAG); 6841 dbgs() << "\nWith: "; 6842 Result.getNode()->dump(&DAG); 6843 dbgs() << '\n'); 6844 WorkListRemover DeadNodes(*this); 6845 if (isLoad) { 6846 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6847 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6848 } else { 6849 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6850 } 6851 6852 // Finally, since the node is now dead, remove it from the graph. 6853 DAG.DeleteNode(N); 6854 6855 // Replace the uses of Ptr with uses of the updated base value. 6856 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 6857 removeFromWorkList(Ptr.getNode()); 6858 DAG.DeleteNode(Ptr.getNode()); 6859 6860 return true; 6861} 6862 6863/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6864/// add / sub of the base pointer node into a post-indexed load / store. 6865/// The transformation folded the add / subtract into the new indexed 6866/// load / store effectively and all of its uses are redirected to the 6867/// new load / store. 6868bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6869 if (Level < AfterLegalizeDAG) 6870 return false; 6871 6872 bool isLoad = true; 6873 SDValue Ptr; 6874 EVT VT; 6875 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6876 if (LD->isIndexed()) 6877 return false; 6878 VT = LD->getMemoryVT(); 6879 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6880 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6881 return false; 6882 Ptr = LD->getBasePtr(); 6883 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6884 if (ST->isIndexed()) 6885 return false; 6886 VT = ST->getMemoryVT(); 6887 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6888 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6889 return false; 6890 Ptr = ST->getBasePtr(); 6891 isLoad = false; 6892 } else { 6893 return false; 6894 } 6895 6896 if (Ptr.getNode()->hasOneUse()) 6897 return false; 6898 6899 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6900 E = Ptr.getNode()->use_end(); I != E; ++I) { 6901 SDNode *Op = *I; 6902 if (Op == N || 6903 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6904 continue; 6905 6906 SDValue BasePtr; 6907 SDValue Offset; 6908 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6909 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6910 // Don't create a indexed load / store with zero offset. 6911 if (isa<ConstantSDNode>(Offset) && 6912 cast<ConstantSDNode>(Offset)->isNullValue()) 6913 continue; 6914 6915 // Try turning it into a post-indexed load / store except when 6916 // 1) All uses are load / store ops that use it as base ptr (and 6917 // it may be folded as addressing mmode). 6918 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6919 // nor a successor of N. Otherwise, if Op is folded that would 6920 // create a cycle. 6921 6922 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6923 continue; 6924 6925 // Check for #1. 6926 bool TryNext = false; 6927 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6928 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6929 SDNode *Use = *II; 6930 if (Use == Ptr.getNode()) 6931 continue; 6932 6933 // If all the uses are load / store addresses, then don't do the 6934 // transformation. 6935 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6936 bool RealUse = false; 6937 for (SDNode::use_iterator III = Use->use_begin(), 6938 EEE = Use->use_end(); III != EEE; ++III) { 6939 SDNode *UseUse = *III; 6940 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6941 RealUse = true; 6942 } 6943 6944 if (!RealUse) { 6945 TryNext = true; 6946 break; 6947 } 6948 } 6949 } 6950 6951 if (TryNext) 6952 continue; 6953 6954 // Check for #2 6955 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6956 SDValue Result = isLoad 6957 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6958 BasePtr, Offset, AM) 6959 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6960 BasePtr, Offset, AM); 6961 ++PostIndexedNodes; 6962 ++NodesCombined; 6963 DEBUG(dbgs() << "\nReplacing.5 "; 6964 N->dump(&DAG); 6965 dbgs() << "\nWith: "; 6966 Result.getNode()->dump(&DAG); 6967 dbgs() << '\n'); 6968 WorkListRemover DeadNodes(*this); 6969 if (isLoad) { 6970 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6971 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6972 } else { 6973 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6974 } 6975 6976 // Finally, since the node is now dead, remove it from the graph. 6977 DAG.DeleteNode(N); 6978 6979 // Replace the uses of Use with uses of the updated base value. 6980 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6981 Result.getValue(isLoad ? 1 : 0)); 6982 removeFromWorkList(Op); 6983 DAG.DeleteNode(Op); 6984 return true; 6985 } 6986 } 6987 } 6988 6989 return false; 6990} 6991 6992SDValue DAGCombiner::visitLOAD(SDNode *N) { 6993 LoadSDNode *LD = cast<LoadSDNode>(N); 6994 SDValue Chain = LD->getChain(); 6995 SDValue Ptr = LD->getBasePtr(); 6996 6997 // If load is not volatile and there are no uses of the loaded value (and 6998 // the updated indexed value in case of indexed loads), change uses of the 6999 // chain value into uses of the chain input (i.e. delete the dead load). 7000 if (!LD->isVolatile()) { 7001 if (N->getValueType(1) == MVT::Other) { 7002 // Unindexed loads. 7003 if (!N->hasAnyUseOfValue(0)) { 7004 // It's not safe to use the two value CombineTo variant here. e.g. 7005 // v1, chain2 = load chain1, loc 7006 // v2, chain3 = load chain2, loc 7007 // v3 = add v2, c 7008 // Now we replace use of chain2 with chain1. This makes the second load 7009 // isomorphic to the one we are deleting, and thus makes this load live. 7010 DEBUG(dbgs() << "\nReplacing.6 "; 7011 N->dump(&DAG); 7012 dbgs() << "\nWith chain: "; 7013 Chain.getNode()->dump(&DAG); 7014 dbgs() << "\n"); 7015 WorkListRemover DeadNodes(*this); 7016 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7017 7018 if (N->use_empty()) { 7019 removeFromWorkList(N); 7020 DAG.DeleteNode(N); 7021 } 7022 7023 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7024 } 7025 } else { 7026 // Indexed loads. 7027 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7028 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7029 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7030 DEBUG(dbgs() << "\nReplacing.7 "; 7031 N->dump(&DAG); 7032 dbgs() << "\nWith: "; 7033 Undef.getNode()->dump(&DAG); 7034 dbgs() << " and 2 other values\n"); 7035 WorkListRemover DeadNodes(*this); 7036 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7037 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7038 DAG.getUNDEF(N->getValueType(1))); 7039 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7040 removeFromWorkList(N); 7041 DAG.DeleteNode(N); 7042 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7043 } 7044 } 7045 } 7046 7047 // If this load is directly stored, replace the load value with the stored 7048 // value. 7049 // TODO: Handle store large -> read small portion. 7050 // TODO: Handle TRUNCSTORE/LOADEXT 7051 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7052 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7053 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7054 if (PrevST->getBasePtr() == Ptr && 7055 PrevST->getValue().getValueType() == N->getValueType(0)) 7056 return CombineTo(N, Chain.getOperand(1), Chain); 7057 } 7058 } 7059 7060 // Try to infer better alignment information than the load already has. 7061 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7062 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7063 if (Align > LD->getAlignment()) 7064 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 7065 LD->getValueType(0), 7066 Chain, Ptr, LD->getPointerInfo(), 7067 LD->getMemoryVT(), 7068 LD->isVolatile(), LD->isNonTemporal(), Align); 7069 } 7070 } 7071 7072 if (CombinerAA) { 7073 // Walk up chain skipping non-aliasing memory nodes. 7074 SDValue BetterChain = FindBetterChain(N, Chain); 7075 7076 // If there is a better chain. 7077 if (Chain != BetterChain) { 7078 SDValue ReplLoad; 7079 7080 // Replace the chain to void dependency. 7081 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7082 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 7083 BetterChain, Ptr, LD->getPointerInfo(), 7084 LD->isVolatile(), LD->isNonTemporal(), 7085 LD->isInvariant(), LD->getAlignment()); 7086 } else { 7087 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 7088 LD->getValueType(0), 7089 BetterChain, Ptr, LD->getPointerInfo(), 7090 LD->getMemoryVT(), 7091 LD->isVolatile(), 7092 LD->isNonTemporal(), 7093 LD->getAlignment()); 7094 } 7095 7096 // Create token factor to keep old chain connected. 7097 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7098 MVT::Other, Chain, ReplLoad.getValue(1)); 7099 7100 // Make sure the new and old chains are cleaned up. 7101 AddToWorkList(Token.getNode()); 7102 7103 // Replace uses with load result and token factor. Don't add users 7104 // to work list. 7105 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7106 } 7107 } 7108 7109 // Try transforming N to an indexed load. 7110 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7111 return SDValue(N, 0); 7112 7113 return SDValue(); 7114} 7115 7116/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 7117/// load is having specific bytes cleared out. If so, return the byte size 7118/// being masked out and the shift amount. 7119static std::pair<unsigned, unsigned> 7120CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 7121 std::pair<unsigned, unsigned> Result(0, 0); 7122 7123 // Check for the structure we're looking for. 7124 if (V->getOpcode() != ISD::AND || 7125 !isa<ConstantSDNode>(V->getOperand(1)) || 7126 !ISD::isNormalLoad(V->getOperand(0).getNode())) 7127 return Result; 7128 7129 // Check the chain and pointer. 7130 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 7131 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 7132 7133 // The store should be chained directly to the load or be an operand of a 7134 // tokenfactor. 7135 if (LD == Chain.getNode()) 7136 ; // ok. 7137 else if (Chain->getOpcode() != ISD::TokenFactor) 7138 return Result; // Fail. 7139 else { 7140 bool isOk = false; 7141 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 7142 if (Chain->getOperand(i).getNode() == LD) { 7143 isOk = true; 7144 break; 7145 } 7146 if (!isOk) return Result; 7147 } 7148 7149 // This only handles simple types. 7150 if (V.getValueType() != MVT::i16 && 7151 V.getValueType() != MVT::i32 && 7152 V.getValueType() != MVT::i64) 7153 return Result; 7154 7155 // Check the constant mask. Invert it so that the bits being masked out are 7156 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 7157 // follow the sign bit for uniformity. 7158 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 7159 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 7160 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 7161 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 7162 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 7163 if (NotMaskLZ == 64) return Result; // All zero mask. 7164 7165 // See if we have a continuous run of bits. If so, we have 0*1+0* 7166 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 7167 return Result; 7168 7169 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 7170 if (V.getValueType() != MVT::i64 && NotMaskLZ) 7171 NotMaskLZ -= 64-V.getValueSizeInBits(); 7172 7173 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 7174 switch (MaskedBytes) { 7175 case 1: 7176 case 2: 7177 case 4: break; 7178 default: return Result; // All one mask, or 5-byte mask. 7179 } 7180 7181 // Verify that the first bit starts at a multiple of mask so that the access 7182 // is aligned the same as the access width. 7183 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 7184 7185 Result.first = MaskedBytes; 7186 Result.second = NotMaskTZ/8; 7187 return Result; 7188} 7189 7190 7191/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 7192/// provides a value as specified by MaskInfo. If so, replace the specified 7193/// store with a narrower store of truncated IVal. 7194static SDNode * 7195ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 7196 SDValue IVal, StoreSDNode *St, 7197 DAGCombiner *DC) { 7198 unsigned NumBytes = MaskInfo.first; 7199 unsigned ByteShift = MaskInfo.second; 7200 SelectionDAG &DAG = DC->getDAG(); 7201 7202 // Check to see if IVal is all zeros in the part being masked in by the 'or' 7203 // that uses this. If not, this is not a replacement. 7204 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 7205 ByteShift*8, (ByteShift+NumBytes)*8); 7206 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 7207 7208 // Check that it is legal on the target to do this. It is legal if the new 7209 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 7210 // legalization. 7211 MVT VT = MVT::getIntegerVT(NumBytes*8); 7212 if (!DC->isTypeLegal(VT)) 7213 return 0; 7214 7215 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 7216 // shifted by ByteShift and truncated down to NumBytes. 7217 if (ByteShift) 7218 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 7219 DAG.getConstant(ByteShift*8, 7220 DC->getShiftAmountTy(IVal.getValueType()))); 7221 7222 // Figure out the offset for the store and the alignment of the access. 7223 unsigned StOffset; 7224 unsigned NewAlign = St->getAlignment(); 7225 7226 if (DAG.getTargetLoweringInfo().isLittleEndian()) 7227 StOffset = ByteShift; 7228 else 7229 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 7230 7231 SDValue Ptr = St->getBasePtr(); 7232 if (StOffset) { 7233 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 7234 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 7235 NewAlign = MinAlign(NewAlign, StOffset); 7236 } 7237 7238 // Truncate down to the new size. 7239 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 7240 7241 ++OpsNarrowed; 7242 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 7243 St->getPointerInfo().getWithOffset(StOffset), 7244 false, false, NewAlign).getNode(); 7245} 7246 7247 7248/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 7249/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 7250/// of the loaded bits, try narrowing the load and store if it would end up 7251/// being a win for performance or code size. 7252SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 7253 StoreSDNode *ST = cast<StoreSDNode>(N); 7254 if (ST->isVolatile()) 7255 return SDValue(); 7256 7257 SDValue Chain = ST->getChain(); 7258 SDValue Value = ST->getValue(); 7259 SDValue Ptr = ST->getBasePtr(); 7260 EVT VT = Value.getValueType(); 7261 7262 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 7263 return SDValue(); 7264 7265 unsigned Opc = Value.getOpcode(); 7266 7267 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 7268 // is a byte mask indicating a consecutive number of bytes, check to see if 7269 // Y is known to provide just those bytes. If so, we try to replace the 7270 // load + replace + store sequence with a single (narrower) store, which makes 7271 // the load dead. 7272 if (Opc == ISD::OR) { 7273 std::pair<unsigned, unsigned> MaskedLoad; 7274 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 7275 if (MaskedLoad.first) 7276 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7277 Value.getOperand(1), ST,this)) 7278 return SDValue(NewST, 0); 7279 7280 // Or is commutative, so try swapping X and Y. 7281 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 7282 if (MaskedLoad.first) 7283 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7284 Value.getOperand(0), ST,this)) 7285 return SDValue(NewST, 0); 7286 } 7287 7288 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 7289 Value.getOperand(1).getOpcode() != ISD::Constant) 7290 return SDValue(); 7291 7292 SDValue N0 = Value.getOperand(0); 7293 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 7294 Chain == SDValue(N0.getNode(), 1)) { 7295 LoadSDNode *LD = cast<LoadSDNode>(N0); 7296 if (LD->getBasePtr() != Ptr || 7297 LD->getPointerInfo().getAddrSpace() != 7298 ST->getPointerInfo().getAddrSpace()) 7299 return SDValue(); 7300 7301 // Find the type to narrow it the load / op / store to. 7302 SDValue N1 = Value.getOperand(1); 7303 unsigned BitWidth = N1.getValueSizeInBits(); 7304 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 7305 if (Opc == ISD::AND) 7306 Imm ^= APInt::getAllOnesValue(BitWidth); 7307 if (Imm == 0 || Imm.isAllOnesValue()) 7308 return SDValue(); 7309 unsigned ShAmt = Imm.countTrailingZeros(); 7310 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 7311 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 7312 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7313 while (NewBW < BitWidth && 7314 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 7315 TLI.isNarrowingProfitable(VT, NewVT))) { 7316 NewBW = NextPowerOf2(NewBW); 7317 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7318 } 7319 if (NewBW >= BitWidth) 7320 return SDValue(); 7321 7322 // If the lsb changed does not start at the type bitwidth boundary, 7323 // start at the previous one. 7324 if (ShAmt % NewBW) 7325 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 7326 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 7327 if ((Imm & Mask) == Imm) { 7328 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 7329 if (Opc == ISD::AND) 7330 NewImm ^= APInt::getAllOnesValue(NewBW); 7331 uint64_t PtrOff = ShAmt / 8; 7332 // For big endian targets, we need to adjust the offset to the pointer to 7333 // load the correct bytes. 7334 if (TLI.isBigEndian()) 7335 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 7336 7337 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 7338 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 7339 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 7340 return SDValue(); 7341 7342 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 7343 Ptr.getValueType(), Ptr, 7344 DAG.getConstant(PtrOff, Ptr.getValueType())); 7345 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 7346 LD->getChain(), NewPtr, 7347 LD->getPointerInfo().getWithOffset(PtrOff), 7348 LD->isVolatile(), LD->isNonTemporal(), 7349 LD->isInvariant(), NewAlign); 7350 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 7351 DAG.getConstant(NewImm, NewVT)); 7352 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 7353 NewVal, NewPtr, 7354 ST->getPointerInfo().getWithOffset(PtrOff), 7355 false, false, NewAlign); 7356 7357 AddToWorkList(NewPtr.getNode()); 7358 AddToWorkList(NewLD.getNode()); 7359 AddToWorkList(NewVal.getNode()); 7360 WorkListRemover DeadNodes(*this); 7361 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7362 ++OpsNarrowed; 7363 return NewST; 7364 } 7365 } 7366 7367 return SDValue(); 7368} 7369 7370/// TransformFPLoadStorePair - For a given floating point load / store pair, 7371/// if the load value isn't used by any other operations, then consider 7372/// transforming the pair to integer load / store operations if the target 7373/// deems the transformation profitable. 7374SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7375 StoreSDNode *ST = cast<StoreSDNode>(N); 7376 SDValue Chain = ST->getChain(); 7377 SDValue Value = ST->getValue(); 7378 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7379 Value.hasOneUse() && 7380 Chain == SDValue(Value.getNode(), 1)) { 7381 LoadSDNode *LD = cast<LoadSDNode>(Value); 7382 EVT VT = LD->getMemoryVT(); 7383 if (!VT.isFloatingPoint() || 7384 VT != ST->getMemoryVT() || 7385 LD->isNonTemporal() || 7386 ST->isNonTemporal() || 7387 LD->getPointerInfo().getAddrSpace() != 0 || 7388 ST->getPointerInfo().getAddrSpace() != 0) 7389 return SDValue(); 7390 7391 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7392 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7393 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7394 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7395 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7396 return SDValue(); 7397 7398 unsigned LDAlign = LD->getAlignment(); 7399 unsigned STAlign = ST->getAlignment(); 7400 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7401 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 7402 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7403 return SDValue(); 7404 7405 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 7406 LD->getChain(), LD->getBasePtr(), 7407 LD->getPointerInfo(), 7408 false, false, false, LDAlign); 7409 7410 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 7411 NewLD, ST->getBasePtr(), 7412 ST->getPointerInfo(), 7413 false, false, STAlign); 7414 7415 AddToWorkList(NewLD.getNode()); 7416 AddToWorkList(NewST.getNode()); 7417 WorkListRemover DeadNodes(*this); 7418 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7419 ++LdStFP2Int; 7420 return NewST; 7421 } 7422 7423 return SDValue(); 7424} 7425 7426SDValue DAGCombiner::visitSTORE(SDNode *N) { 7427 StoreSDNode *ST = cast<StoreSDNode>(N); 7428 SDValue Chain = ST->getChain(); 7429 SDValue Value = ST->getValue(); 7430 SDValue Ptr = ST->getBasePtr(); 7431 7432 // If this is a store of a bit convert, store the input value if the 7433 // resultant store does not need a higher alignment than the original. 7434 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 7435 ST->isUnindexed()) { 7436 unsigned OrigAlign = ST->getAlignment(); 7437 EVT SVT = Value.getOperand(0).getValueType(); 7438 unsigned Align = TLI.getTargetData()-> 7439 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 7440 if (Align <= OrigAlign && 7441 ((!LegalOperations && !ST->isVolatile()) || 7442 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 7443 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7444 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7445 ST->isNonTemporal(), OrigAlign); 7446 } 7447 7448 // Turn 'store undef, Ptr' -> nothing. 7449 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 7450 return Chain; 7451 7452 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 7453 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 7454 // NOTE: If the original store is volatile, this transform must not increase 7455 // the number of stores. For example, on x86-32 an f64 can be stored in one 7456 // processor operation but an i64 (which is not legal) requires two. So the 7457 // transform should not be done in this case. 7458 if (Value.getOpcode() != ISD::TargetConstantFP) { 7459 SDValue Tmp; 7460 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 7461 default: llvm_unreachable("Unknown FP type"); 7462 case MVT::f16: // We don't do this for these yet. 7463 case MVT::f80: 7464 case MVT::f128: 7465 case MVT::ppcf128: 7466 break; 7467 case MVT::f32: 7468 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 7469 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7470 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 7471 bitcastToAPInt().getZExtValue(), MVT::i32); 7472 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7473 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7474 ST->isNonTemporal(), ST->getAlignment()); 7475 } 7476 break; 7477 case MVT::f64: 7478 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 7479 !ST->isVolatile()) || 7480 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 7481 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 7482 getZExtValue(), MVT::i64); 7483 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7484 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7485 ST->isNonTemporal(), ST->getAlignment()); 7486 } 7487 7488 if (!ST->isVolatile() && 7489 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7490 // Many FP stores are not made apparent until after legalize, e.g. for 7491 // argument passing. Since this is so common, custom legalize the 7492 // 64-bit integer store into two 32-bit stores. 7493 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 7494 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 7495 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 7496 if (TLI.isBigEndian()) std::swap(Lo, Hi); 7497 7498 unsigned Alignment = ST->getAlignment(); 7499 bool isVolatile = ST->isVolatile(); 7500 bool isNonTemporal = ST->isNonTemporal(); 7501 7502 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 7503 Ptr, ST->getPointerInfo(), 7504 isVolatile, isNonTemporal, 7505 ST->getAlignment()); 7506 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 7507 DAG.getConstant(4, Ptr.getValueType())); 7508 Alignment = MinAlign(Alignment, 4U); 7509 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 7510 Ptr, ST->getPointerInfo().getWithOffset(4), 7511 isVolatile, isNonTemporal, 7512 Alignment); 7513 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7514 St0, St1); 7515 } 7516 7517 break; 7518 } 7519 } 7520 } 7521 7522 // Try to infer better alignment information than the store already has. 7523 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 7524 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7525 if (Align > ST->getAlignment()) 7526 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 7527 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7528 ST->isVolatile(), ST->isNonTemporal(), Align); 7529 } 7530 } 7531 7532 // Try transforming a pair floating point load / store ops to integer 7533 // load / store ops. 7534 SDValue NewST = TransformFPLoadStorePair(N); 7535 if (NewST.getNode()) 7536 return NewST; 7537 7538 if (CombinerAA) { 7539 // Walk up chain skipping non-aliasing memory nodes. 7540 SDValue BetterChain = FindBetterChain(N, Chain); 7541 7542 // If there is a better chain. 7543 if (Chain != BetterChain) { 7544 SDValue ReplStore; 7545 7546 // Replace the chain to avoid dependency. 7547 if (ST->isTruncatingStore()) { 7548 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7549 ST->getPointerInfo(), 7550 ST->getMemoryVT(), ST->isVolatile(), 7551 ST->isNonTemporal(), ST->getAlignment()); 7552 } else { 7553 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7554 ST->getPointerInfo(), 7555 ST->isVolatile(), ST->isNonTemporal(), 7556 ST->getAlignment()); 7557 } 7558 7559 // Create token to keep both nodes around. 7560 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7561 MVT::Other, Chain, ReplStore); 7562 7563 // Make sure the new and old chains are cleaned up. 7564 AddToWorkList(Token.getNode()); 7565 7566 // Don't add users to work list. 7567 return CombineTo(N, Token, false); 7568 } 7569 } 7570 7571 // Try transforming N to an indexed store. 7572 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7573 return SDValue(N, 0); 7574 7575 // FIXME: is there such a thing as a truncating indexed store? 7576 if (ST->isTruncatingStore() && ST->isUnindexed() && 7577 Value.getValueType().isInteger()) { 7578 // See if we can simplify the input to this truncstore with knowledge that 7579 // only the low bits are being used. For example: 7580 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 7581 SDValue Shorter = 7582 GetDemandedBits(Value, 7583 APInt::getLowBitsSet( 7584 Value.getValueType().getScalarType().getSizeInBits(), 7585 ST->getMemoryVT().getScalarType().getSizeInBits())); 7586 AddToWorkList(Value.getNode()); 7587 if (Shorter.getNode()) 7588 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 7589 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7590 ST->isVolatile(), ST->isNonTemporal(), 7591 ST->getAlignment()); 7592 7593 // Otherwise, see if we can simplify the operation with 7594 // SimplifyDemandedBits, which only works if the value has a single use. 7595 if (SimplifyDemandedBits(Value, 7596 APInt::getLowBitsSet( 7597 Value.getValueType().getScalarType().getSizeInBits(), 7598 ST->getMemoryVT().getScalarType().getSizeInBits()))) 7599 return SDValue(N, 0); 7600 } 7601 7602 // If this is a load followed by a store to the same location, then the store 7603 // is dead/noop. 7604 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 7605 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 7606 ST->isUnindexed() && !ST->isVolatile() && 7607 // There can't be any side effects between the load and store, such as 7608 // a call or store. 7609 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 7610 // The store is dead, remove it. 7611 return Chain; 7612 } 7613 } 7614 7615 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 7616 // truncating store. We can do this even if this is already a truncstore. 7617 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 7618 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 7619 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 7620 ST->getMemoryVT())) { 7621 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7622 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7623 ST->isVolatile(), ST->isNonTemporal(), 7624 ST->getAlignment()); 7625 } 7626 7627 return ReduceLoadOpStoreWidth(N); 7628} 7629 7630SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 7631 SDValue InVec = N->getOperand(0); 7632 SDValue InVal = N->getOperand(1); 7633 SDValue EltNo = N->getOperand(2); 7634 DebugLoc dl = N->getDebugLoc(); 7635 7636 // If the inserted element is an UNDEF, just use the input vector. 7637 if (InVal.getOpcode() == ISD::UNDEF) 7638 return InVec; 7639 7640 EVT VT = InVec.getValueType(); 7641 7642 // If we can't generate a legal BUILD_VECTOR, exit 7643 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 7644 return SDValue(); 7645 7646 // Check that we know which element is being inserted 7647 if (!isa<ConstantSDNode>(EltNo)) 7648 return SDValue(); 7649 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7650 7651 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 7652 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 7653 // vector elements. 7654 SmallVector<SDValue, 8> Ops; 7655 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 7656 Ops.append(InVec.getNode()->op_begin(), 7657 InVec.getNode()->op_end()); 7658 } else if (InVec.getOpcode() == ISD::UNDEF) { 7659 unsigned NElts = VT.getVectorNumElements(); 7660 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 7661 } else { 7662 return SDValue(); 7663 } 7664 7665 // Insert the element 7666 if (Elt < Ops.size()) { 7667 // All the operands of BUILD_VECTOR must have the same type; 7668 // we enforce that here. 7669 EVT OpVT = Ops[0].getValueType(); 7670 if (InVal.getValueType() != OpVT) 7671 InVal = OpVT.bitsGT(InVal.getValueType()) ? 7672 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 7673 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 7674 Ops[Elt] = InVal; 7675 } 7676 7677 // Return the new vector 7678 return DAG.getNode(ISD::BUILD_VECTOR, dl, 7679 VT, &Ops[0], Ops.size()); 7680} 7681 7682SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 7683 // (vextract (scalar_to_vector val, 0) -> val 7684 SDValue InVec = N->getOperand(0); 7685 EVT VT = InVec.getValueType(); 7686 EVT NVT = N->getValueType(0); 7687 7688 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 7689 // Check if the result type doesn't match the inserted element type. A 7690 // SCALAR_TO_VECTOR may truncate the inserted element and the 7691 // EXTRACT_VECTOR_ELT may widen the extracted vector. 7692 SDValue InOp = InVec.getOperand(0); 7693 if (InOp.getValueType() != NVT) { 7694 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 7695 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 7696 } 7697 return InOp; 7698 } 7699 7700 SDValue EltNo = N->getOperand(1); 7701 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 7702 7703 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 7704 // We only perform this optimization before the op legalization phase because 7705 // we may introduce new vector instructions which are not backed by TD 7706 // patterns. For example on AVX, extracting elements from a wide vector 7707 // without using extract_subvector. 7708 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 7709 && ConstEltNo && !LegalOperations) { 7710 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7711 int NumElem = VT.getVectorNumElements(); 7712 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 7713 // Find the new index to extract from. 7714 int OrigElt = SVOp->getMaskElt(Elt); 7715 7716 // Extracting an undef index is undef. 7717 if (OrigElt == -1) 7718 return DAG.getUNDEF(NVT); 7719 7720 // Select the right vector half to extract from. 7721 if (OrigElt < NumElem) { 7722 InVec = InVec->getOperand(0); 7723 } else { 7724 InVec = InVec->getOperand(1); 7725 OrigElt -= NumElem; 7726 } 7727 7728 EVT IndexTy = N->getOperand(1).getValueType(); 7729 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 7730 InVec, DAG.getConstant(OrigElt, IndexTy)); 7731 } 7732 7733 // Perform only after legalization to ensure build_vector / vector_shuffle 7734 // optimizations have already been done. 7735 if (!LegalOperations) return SDValue(); 7736 7737 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 7738 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 7739 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 7740 7741 if (ConstEltNo) { 7742 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7743 bool NewLoad = false; 7744 bool BCNumEltsChanged = false; 7745 EVT ExtVT = VT.getVectorElementType(); 7746 EVT LVT = ExtVT; 7747 7748 // If the result of load has to be truncated, then it's not necessarily 7749 // profitable. 7750 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 7751 return SDValue(); 7752 7753 if (InVec.getOpcode() == ISD::BITCAST) { 7754 // Don't duplicate a load with other uses. 7755 if (!InVec.hasOneUse()) 7756 return SDValue(); 7757 7758 EVT BCVT = InVec.getOperand(0).getValueType(); 7759 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 7760 return SDValue(); 7761 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 7762 BCNumEltsChanged = true; 7763 InVec = InVec.getOperand(0); 7764 ExtVT = BCVT.getVectorElementType(); 7765 NewLoad = true; 7766 } 7767 7768 LoadSDNode *LN0 = NULL; 7769 const ShuffleVectorSDNode *SVN = NULL; 7770 if (ISD::isNormalLoad(InVec.getNode())) { 7771 LN0 = cast<LoadSDNode>(InVec); 7772 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 7773 InVec.getOperand(0).getValueType() == ExtVT && 7774 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 7775 // Don't duplicate a load with other uses. 7776 if (!InVec.hasOneUse()) 7777 return SDValue(); 7778 7779 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 7780 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 7781 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 7782 // => 7783 // (load $addr+1*size) 7784 7785 // Don't duplicate a load with other uses. 7786 if (!InVec.hasOneUse()) 7787 return SDValue(); 7788 7789 // If the bit convert changed the number of elements, it is unsafe 7790 // to examine the mask. 7791 if (BCNumEltsChanged) 7792 return SDValue(); 7793 7794 // Select the input vector, guarding against out of range extract vector. 7795 unsigned NumElems = VT.getVectorNumElements(); 7796 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7797 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7798 7799 if (InVec.getOpcode() == ISD::BITCAST) { 7800 // Don't duplicate a load with other uses. 7801 if (!InVec.hasOneUse()) 7802 return SDValue(); 7803 7804 InVec = InVec.getOperand(0); 7805 } 7806 if (ISD::isNormalLoad(InVec.getNode())) { 7807 LN0 = cast<LoadSDNode>(InVec); 7808 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7809 } 7810 } 7811 7812 // Make sure we found a non-volatile load and the extractelement is 7813 // the only use. 7814 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7815 return SDValue(); 7816 7817 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7818 if (Elt == -1) 7819 return DAG.getUNDEF(LVT); 7820 7821 unsigned Align = LN0->getAlignment(); 7822 if (NewLoad) { 7823 // Check the resultant load doesn't need a higher alignment than the 7824 // original load. 7825 unsigned NewAlign = 7826 TLI.getTargetData() 7827 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7828 7829 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7830 return SDValue(); 7831 7832 Align = NewAlign; 7833 } 7834 7835 SDValue NewPtr = LN0->getBasePtr(); 7836 unsigned PtrOff = 0; 7837 7838 if (Elt) { 7839 PtrOff = LVT.getSizeInBits() * Elt / 8; 7840 EVT PtrType = NewPtr.getValueType(); 7841 if (TLI.isBigEndian()) 7842 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7843 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7844 DAG.getConstant(PtrOff, PtrType)); 7845 } 7846 7847 // The replacement we need to do here is a little tricky: we need to 7848 // replace an extractelement of a load with a load. 7849 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7850 // Note that this replacement assumes that the extractvalue is the only 7851 // use of the load; that's okay because we don't want to perform this 7852 // transformation in other cases anyway. 7853 SDValue Load; 7854 SDValue Chain; 7855 if (NVT.bitsGT(LVT)) { 7856 // If the result type of vextract is wider than the load, then issue an 7857 // extending load instead. 7858 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 7859 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 7860 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 7861 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 7862 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 7863 Chain = Load.getValue(1); 7864 } else { 7865 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7866 LN0->getPointerInfo().getWithOffset(PtrOff), 7867 LN0->isVolatile(), LN0->isNonTemporal(), 7868 LN0->isInvariant(), Align); 7869 Chain = Load.getValue(1); 7870 if (NVT.bitsLT(LVT)) 7871 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 7872 else 7873 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 7874 } 7875 WorkListRemover DeadNodes(*this); 7876 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7877 SDValue To[] = { Load, Chain }; 7878 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 7879 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7880 // worklist explicitly as well. 7881 AddToWorkList(Load.getNode()); 7882 AddUsersToWorkList(Load.getNode()); // Add users too 7883 // Make sure to revisit this node to clean it up; it will usually be dead. 7884 AddToWorkList(N); 7885 return SDValue(N, 0); 7886 } 7887 7888 return SDValue(); 7889} 7890 7891SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7892 unsigned NumInScalars = N->getNumOperands(); 7893 DebugLoc dl = N->getDebugLoc(); 7894 EVT VT = N->getValueType(0); 7895 7896 // A vector built entirely of undefs is undef. 7897 if (ISD::allOperandsUndef(N)) 7898 return DAG.getUNDEF(VT); 7899 7900 // Check to see if this is a BUILD_VECTOR of a bunch of values 7901 // which come from any_extend or zero_extend nodes. If so, we can create 7902 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7903 // optimizations. We do not handle sign-extend because we can't fill the sign 7904 // using shuffles. 7905 EVT SourceType = MVT::Other; 7906 bool AllAnyExt = true; 7907 7908 for (unsigned i = 0; i != NumInScalars; ++i) { 7909 SDValue In = N->getOperand(i); 7910 // Ignore undef inputs. 7911 if (In.getOpcode() == ISD::UNDEF) continue; 7912 7913 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7914 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7915 7916 // Abort if the element is not an extension. 7917 if (!ZeroExt && !AnyExt) { 7918 SourceType = MVT::Other; 7919 break; 7920 } 7921 7922 // The input is a ZeroExt or AnyExt. Check the original type. 7923 EVT InTy = In.getOperand(0).getValueType(); 7924 7925 // Check that all of the widened source types are the same. 7926 if (SourceType == MVT::Other) 7927 // First time. 7928 SourceType = InTy; 7929 else if (InTy != SourceType) { 7930 // Multiple income types. Abort. 7931 SourceType = MVT::Other; 7932 break; 7933 } 7934 7935 // Check if all of the extends are ANY_EXTENDs. 7936 AllAnyExt &= AnyExt; 7937 } 7938 7939 // In order to have valid types, all of the inputs must be extended from the 7940 // same source type and all of the inputs must be any or zero extend. 7941 // Scalar sizes must be a power of two. 7942 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7943 bool ValidTypes = SourceType != MVT::Other && 7944 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7945 isPowerOf2_32(SourceType.getSizeInBits()); 7946 7947 // We perform this optimization post type-legalization because 7948 // the type-legalizer often scalarizes integer-promoted vectors. 7949 // Performing this optimization before may create bit-casts which 7950 // will be type-legalized to complex code sequences. 7951 // We perform this optimization only before the operation legalizer because we 7952 // may introduce illegal operations. 7953 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 7954 // turn into a single shuffle instruction. 7955 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 7956 ValidTypes) { 7957 bool isLE = TLI.isLittleEndian(); 7958 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7959 assert(ElemRatio > 1 && "Invalid element size ratio"); 7960 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 7961 DAG.getConstant(0, SourceType); 7962 7963 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7964 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7965 7966 // Populate the new build_vector 7967 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7968 SDValue Cast = N->getOperand(i); 7969 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7970 Cast.getOpcode() == ISD::ZERO_EXTEND || 7971 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7972 SDValue In; 7973 if (Cast.getOpcode() == ISD::UNDEF) 7974 In = DAG.getUNDEF(SourceType); 7975 else 7976 In = Cast->getOperand(0); 7977 unsigned Index = isLE ? (i * ElemRatio) : 7978 (i * ElemRatio + (ElemRatio - 1)); 7979 7980 assert(Index < Ops.size() && "Invalid index"); 7981 Ops[Index] = In; 7982 } 7983 7984 // The type of the new BUILD_VECTOR node. 7985 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 7986 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 7987 "Invalid vector size"); 7988 // Check if the new vector type is legal. 7989 if (!isTypeLegal(VecVT)) return SDValue(); 7990 7991 // Make the new BUILD_VECTOR. 7992 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7993 VecVT, &Ops[0], Ops.size()); 7994 7995 // The new BUILD_VECTOR node has the potential to be further optimized. 7996 AddToWorkList(BV.getNode()); 7997 // Bitcast to the desired type. 7998 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 7999 } 8000 8001 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 8002 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 8003 // at most two distinct vectors, turn this into a shuffle node. 8004 8005 // May only combine to shuffle after legalize if shuffle is legal. 8006 if (LegalOperations && 8007 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 8008 return SDValue(); 8009 8010 SDValue VecIn1, VecIn2; 8011 for (unsigned i = 0; i != NumInScalars; ++i) { 8012 // Ignore undef inputs. 8013 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 8014 8015 // If this input is something other than a EXTRACT_VECTOR_ELT with a 8016 // constant index, bail out. 8017 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 8018 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 8019 VecIn1 = VecIn2 = SDValue(0, 0); 8020 break; 8021 } 8022 8023 // We allow up to two distinct input vectors. 8024 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 8025 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 8026 continue; 8027 8028 if (VecIn1.getNode() == 0) { 8029 VecIn1 = ExtractedFromVec; 8030 } else if (VecIn2.getNode() == 0) { 8031 VecIn2 = ExtractedFromVec; 8032 } else { 8033 // Too many inputs. 8034 VecIn1 = VecIn2 = SDValue(0, 0); 8035 break; 8036 } 8037 } 8038 8039 // If everything is good, we can make a shuffle operation. 8040 if (VecIn1.getNode()) { 8041 SmallVector<int, 8> Mask; 8042 for (unsigned i = 0; i != NumInScalars; ++i) { 8043 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 8044 Mask.push_back(-1); 8045 continue; 8046 } 8047 8048 // If extracting from the first vector, just use the index directly. 8049 SDValue Extract = N->getOperand(i); 8050 SDValue ExtVal = Extract.getOperand(1); 8051 if (Extract.getOperand(0) == VecIn1) { 8052 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8053 if (ExtIndex > VT.getVectorNumElements()) 8054 return SDValue(); 8055 8056 Mask.push_back(ExtIndex); 8057 continue; 8058 } 8059 8060 // Otherwise, use InIdx + VecSize 8061 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8062 Mask.push_back(Idx+NumInScalars); 8063 } 8064 8065 // We can't generate a shuffle node with mismatched input and output types. 8066 // Attempt to transform a single input vector to the correct type. 8067 if ((VT != VecIn1.getValueType())) { 8068 // We don't support shuffeling between TWO values of different types. 8069 if (VecIn2.getNode() != 0) 8070 return SDValue(); 8071 8072 // We only support widening of vectors which are half the size of the 8073 // output registers. For example XMM->YMM widening on X86 with AVX. 8074 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 8075 return SDValue(); 8076 8077 // If the input vector type has a different base type to the output 8078 // vector type, bail out. 8079 if (VecIn1.getValueType().getVectorElementType() != 8080 VT.getVectorElementType()) 8081 return SDValue(); 8082 8083 // Widen the input vector by adding undef values. 8084 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 8085 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 8086 } 8087 8088 // If VecIn2 is unused then change it to undef. 8089 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 8090 8091 // Check that we were able to transform all incoming values to the same 8092 // type. 8093 if (VecIn2.getValueType() != VecIn1.getValueType() || 8094 VecIn1.getValueType() != VT) 8095 return SDValue(); 8096 8097 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 8098 if (!isTypeLegal(VT)) 8099 return SDValue(); 8100 8101 // Return the new VECTOR_SHUFFLE node. 8102 SDValue Ops[2]; 8103 Ops[0] = VecIn1; 8104 Ops[1] = VecIn2; 8105 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 8106 } 8107 8108 return SDValue(); 8109} 8110 8111SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 8112 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 8113 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 8114 // inputs come from at most two distinct vectors, turn this into a shuffle 8115 // node. 8116 8117 // If we only have one input vector, we don't need to do any concatenation. 8118 if (N->getNumOperands() == 1) 8119 return N->getOperand(0); 8120 8121 // Check if all of the operands are undefs. 8122 if (ISD::allOperandsUndef(N)) 8123 return DAG.getUNDEF(N->getValueType(0)); 8124 8125 return SDValue(); 8126} 8127 8128SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 8129 EVT NVT = N->getValueType(0); 8130 SDValue V = N->getOperand(0); 8131 8132 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 8133 // Handle only simple case where vector being inserted and vector 8134 // being extracted are of same type, and are half size of larger vectors. 8135 EVT BigVT = V->getOperand(0).getValueType(); 8136 EVT SmallVT = V->getOperand(1).getValueType(); 8137 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 8138 return SDValue(); 8139 8140 // Only handle cases where both indexes are constants with the same type. 8141 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8142 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 8143 8144 if (InsIdx && ExtIdx && 8145 InsIdx->getValueType(0).getSizeInBits() <= 64 && 8146 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 8147 // Combine: 8148 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 8149 // Into: 8150 // indices are equal => V1 8151 // otherwise => (extract_subvec V1, ExtIdx) 8152 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 8153 return V->getOperand(1); 8154 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 8155 V->getOperand(0), N->getOperand(1)); 8156 } 8157 } 8158 8159 return SDValue(); 8160} 8161 8162SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 8163 EVT VT = N->getValueType(0); 8164 unsigned NumElts = VT.getVectorNumElements(); 8165 8166 SDValue N0 = N->getOperand(0); 8167 SDValue N1 = N->getOperand(1); 8168 8169 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 8170 8171 // Canonicalize shuffle undef, undef -> undef 8172 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 8173 return DAG.getUNDEF(VT); 8174 8175 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8176 8177 // Canonicalize shuffle v, v -> v, undef 8178 if (N0 == N1) { 8179 SmallVector<int, 8> NewMask; 8180 for (unsigned i = 0; i != NumElts; ++i) { 8181 int Idx = SVN->getMaskElt(i); 8182 if (Idx >= (int)NumElts) Idx -= NumElts; 8183 NewMask.push_back(Idx); 8184 } 8185 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 8186 &NewMask[0]); 8187 } 8188 8189 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 8190 if (N0.getOpcode() == ISD::UNDEF) { 8191 SmallVector<int, 8> NewMask; 8192 for (unsigned i = 0; i != NumElts; ++i) { 8193 int Idx = SVN->getMaskElt(i); 8194 if (Idx >= 0) { 8195 if (Idx < (int)NumElts) 8196 Idx += NumElts; 8197 else 8198 Idx -= NumElts; 8199 } 8200 NewMask.push_back(Idx); 8201 } 8202 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 8203 &NewMask[0]); 8204 } 8205 8206 // Remove references to rhs if it is undef 8207 if (N1.getOpcode() == ISD::UNDEF) { 8208 bool Changed = false; 8209 SmallVector<int, 8> NewMask; 8210 for (unsigned i = 0; i != NumElts; ++i) { 8211 int Idx = SVN->getMaskElt(i); 8212 if (Idx >= (int)NumElts) { 8213 Idx = -1; 8214 Changed = true; 8215 } 8216 NewMask.push_back(Idx); 8217 } 8218 if (Changed) 8219 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 8220 } 8221 8222 // If it is a splat, check if the argument vector is another splat or a 8223 // build_vector with all scalar elements the same. 8224 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 8225 SDNode *V = N0.getNode(); 8226 8227 // If this is a bit convert that changes the element type of the vector but 8228 // not the number of vector elements, look through it. Be careful not to 8229 // look though conversions that change things like v4f32 to v2f64. 8230 if (V->getOpcode() == ISD::BITCAST) { 8231 SDValue ConvInput = V->getOperand(0); 8232 if (ConvInput.getValueType().isVector() && 8233 ConvInput.getValueType().getVectorNumElements() == NumElts) 8234 V = ConvInput.getNode(); 8235 } 8236 8237 if (V->getOpcode() == ISD::BUILD_VECTOR) { 8238 assert(V->getNumOperands() == NumElts && 8239 "BUILD_VECTOR has wrong number of operands"); 8240 SDValue Base; 8241 bool AllSame = true; 8242 for (unsigned i = 0; i != NumElts; ++i) { 8243 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 8244 Base = V->getOperand(i); 8245 break; 8246 } 8247 } 8248 // Splat of <u, u, u, u>, return <u, u, u, u> 8249 if (!Base.getNode()) 8250 return N0; 8251 for (unsigned i = 0; i != NumElts; ++i) { 8252 if (V->getOperand(i) != Base) { 8253 AllSame = false; 8254 break; 8255 } 8256 } 8257 // Splat of <x, x, x, x>, return <x, x, x, x> 8258 if (AllSame) 8259 return N0; 8260 } 8261 } 8262 8263 // If this shuffle node is simply a swizzle of another shuffle node, 8264 // and it reverses the swizzle of the previous shuffle then we can 8265 // optimize shuffle(shuffle(x, undef), undef) -> x. 8266 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 8267 N1.getOpcode() == ISD::UNDEF) { 8268 8269 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 8270 8271 // Shuffle nodes can only reverse shuffles with a single non-undef value. 8272 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 8273 return SDValue(); 8274 8275 // The incoming shuffle must be of the same type as the result of the 8276 // current shuffle. 8277 assert(OtherSV->getOperand(0).getValueType() == VT && 8278 "Shuffle types don't match"); 8279 8280 for (unsigned i = 0; i != NumElts; ++i) { 8281 int Idx = SVN->getMaskElt(i); 8282 assert(Idx < (int)NumElts && "Index references undef operand"); 8283 // Next, this index comes from the first value, which is the incoming 8284 // shuffle. Adopt the incoming index. 8285 if (Idx >= 0) 8286 Idx = OtherSV->getMaskElt(Idx); 8287 8288 // The combined shuffle must map each index to itself. 8289 if (Idx >= 0 && (unsigned)Idx != i) 8290 return SDValue(); 8291 } 8292 8293 return OtherSV->getOperand(0); 8294 } 8295 8296 return SDValue(); 8297} 8298 8299SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 8300 if (!TLI.getShouldFoldAtomicFences()) 8301 return SDValue(); 8302 8303 SDValue atomic = N->getOperand(0); 8304 switch (atomic.getOpcode()) { 8305 case ISD::ATOMIC_CMP_SWAP: 8306 case ISD::ATOMIC_SWAP: 8307 case ISD::ATOMIC_LOAD_ADD: 8308 case ISD::ATOMIC_LOAD_SUB: 8309 case ISD::ATOMIC_LOAD_AND: 8310 case ISD::ATOMIC_LOAD_OR: 8311 case ISD::ATOMIC_LOAD_XOR: 8312 case ISD::ATOMIC_LOAD_NAND: 8313 case ISD::ATOMIC_LOAD_MIN: 8314 case ISD::ATOMIC_LOAD_MAX: 8315 case ISD::ATOMIC_LOAD_UMIN: 8316 case ISD::ATOMIC_LOAD_UMAX: 8317 break; 8318 default: 8319 return SDValue(); 8320 } 8321 8322 SDValue fence = atomic.getOperand(0); 8323 if (fence.getOpcode() != ISD::MEMBARRIER) 8324 return SDValue(); 8325 8326 switch (atomic.getOpcode()) { 8327 case ISD::ATOMIC_CMP_SWAP: 8328 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 8329 fence.getOperand(0), 8330 atomic.getOperand(1), atomic.getOperand(2), 8331 atomic.getOperand(3)), atomic.getResNo()); 8332 case ISD::ATOMIC_SWAP: 8333 case ISD::ATOMIC_LOAD_ADD: 8334 case ISD::ATOMIC_LOAD_SUB: 8335 case ISD::ATOMIC_LOAD_AND: 8336 case ISD::ATOMIC_LOAD_OR: 8337 case ISD::ATOMIC_LOAD_XOR: 8338 case ISD::ATOMIC_LOAD_NAND: 8339 case ISD::ATOMIC_LOAD_MIN: 8340 case ISD::ATOMIC_LOAD_MAX: 8341 case ISD::ATOMIC_LOAD_UMIN: 8342 case ISD::ATOMIC_LOAD_UMAX: 8343 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 8344 fence.getOperand(0), 8345 atomic.getOperand(1), atomic.getOperand(2)), 8346 atomic.getResNo()); 8347 default: 8348 return SDValue(); 8349 } 8350} 8351 8352/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 8353/// an AND to a vector_shuffle with the destination vector and a zero vector. 8354/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 8355/// vector_shuffle V, Zero, <0, 4, 2, 4> 8356SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 8357 EVT VT = N->getValueType(0); 8358 DebugLoc dl = N->getDebugLoc(); 8359 SDValue LHS = N->getOperand(0); 8360 SDValue RHS = N->getOperand(1); 8361 if (N->getOpcode() == ISD::AND) { 8362 if (RHS.getOpcode() == ISD::BITCAST) 8363 RHS = RHS.getOperand(0); 8364 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 8365 SmallVector<int, 8> Indices; 8366 unsigned NumElts = RHS.getNumOperands(); 8367 for (unsigned i = 0; i != NumElts; ++i) { 8368 SDValue Elt = RHS.getOperand(i); 8369 if (!isa<ConstantSDNode>(Elt)) 8370 return SDValue(); 8371 8372 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 8373 Indices.push_back(i); 8374 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 8375 Indices.push_back(NumElts); 8376 else 8377 return SDValue(); 8378 } 8379 8380 // Let's see if the target supports this vector_shuffle. 8381 EVT RVT = RHS.getValueType(); 8382 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 8383 return SDValue(); 8384 8385 // Return the new VECTOR_SHUFFLE node. 8386 EVT EltVT = RVT.getVectorElementType(); 8387 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 8388 DAG.getConstant(0, EltVT)); 8389 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8390 RVT, &ZeroOps[0], ZeroOps.size()); 8391 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 8392 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 8393 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 8394 } 8395 } 8396 8397 return SDValue(); 8398} 8399 8400/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 8401SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 8402 // After legalize, the target may be depending on adds and other 8403 // binary ops to provide legal ways to construct constants or other 8404 // things. Simplifying them may result in a loss of legality. 8405 if (LegalOperations) return SDValue(); 8406 8407 assert(N->getValueType(0).isVector() && 8408 "SimplifyVBinOp only works on vectors!"); 8409 8410 SDValue LHS = N->getOperand(0); 8411 SDValue RHS = N->getOperand(1); 8412 SDValue Shuffle = XformToShuffleWithZero(N); 8413 if (Shuffle.getNode()) return Shuffle; 8414 8415 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 8416 // this operation. 8417 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 8418 RHS.getOpcode() == ISD::BUILD_VECTOR) { 8419 SmallVector<SDValue, 8> Ops; 8420 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 8421 SDValue LHSOp = LHS.getOperand(i); 8422 SDValue RHSOp = RHS.getOperand(i); 8423 // If these two elements can't be folded, bail out. 8424 if ((LHSOp.getOpcode() != ISD::UNDEF && 8425 LHSOp.getOpcode() != ISD::Constant && 8426 LHSOp.getOpcode() != ISD::ConstantFP) || 8427 (RHSOp.getOpcode() != ISD::UNDEF && 8428 RHSOp.getOpcode() != ISD::Constant && 8429 RHSOp.getOpcode() != ISD::ConstantFP)) 8430 break; 8431 8432 // Can't fold divide by zero. 8433 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 8434 N->getOpcode() == ISD::FDIV) { 8435 if ((RHSOp.getOpcode() == ISD::Constant && 8436 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 8437 (RHSOp.getOpcode() == ISD::ConstantFP && 8438 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 8439 break; 8440 } 8441 8442 EVT VT = LHSOp.getValueType(); 8443 EVT RVT = RHSOp.getValueType(); 8444 if (RVT != VT) { 8445 // Integer BUILD_VECTOR operands may have types larger than the element 8446 // size (e.g., when the element type is not legal). Prior to type 8447 // legalization, the types may not match between the two BUILD_VECTORS. 8448 // Truncate one of the operands to make them match. 8449 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 8450 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 8451 } else { 8452 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 8453 VT = RVT; 8454 } 8455 } 8456 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 8457 LHSOp, RHSOp); 8458 if (FoldOp.getOpcode() != ISD::UNDEF && 8459 FoldOp.getOpcode() != ISD::Constant && 8460 FoldOp.getOpcode() != ISD::ConstantFP) 8461 break; 8462 Ops.push_back(FoldOp); 8463 AddToWorkList(FoldOp.getNode()); 8464 } 8465 8466 if (Ops.size() == LHS.getNumOperands()) 8467 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8468 LHS.getValueType(), &Ops[0], Ops.size()); 8469 } 8470 8471 return SDValue(); 8472} 8473 8474/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 8475SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 8476 // After legalize, the target may be depending on adds and other 8477 // binary ops to provide legal ways to construct constants or other 8478 // things. Simplifying them may result in a loss of legality. 8479 if (LegalOperations) return SDValue(); 8480 8481 assert(N->getValueType(0).isVector() && 8482 "SimplifyVUnaryOp only works on vectors!"); 8483 8484 SDValue N0 = N->getOperand(0); 8485 8486 if (N0.getOpcode() != ISD::BUILD_VECTOR) 8487 return SDValue(); 8488 8489 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 8490 SmallVector<SDValue, 8> Ops; 8491 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 8492 SDValue Op = N0.getOperand(i); 8493 if (Op.getOpcode() != ISD::UNDEF && 8494 Op.getOpcode() != ISD::ConstantFP) 8495 break; 8496 EVT EltVT = Op.getValueType(); 8497 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op); 8498 if (FoldOp.getOpcode() != ISD::UNDEF && 8499 FoldOp.getOpcode() != ISD::ConstantFP) 8500 break; 8501 Ops.push_back(FoldOp); 8502 AddToWorkList(FoldOp.getNode()); 8503 } 8504 8505 if (Ops.size() != N0.getNumOperands()) 8506 return SDValue(); 8507 8508 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8509 N0.getValueType(), &Ops[0], Ops.size()); 8510} 8511 8512SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 8513 SDValue N1, SDValue N2){ 8514 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 8515 8516 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 8517 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 8518 8519 // If we got a simplified select_cc node back from SimplifySelectCC, then 8520 // break it down into a new SETCC node, and a new SELECT node, and then return 8521 // the SELECT node, since we were called with a SELECT node. 8522 if (SCC.getNode()) { 8523 // Check to see if we got a select_cc back (to turn into setcc/select). 8524 // Otherwise, just return whatever node we got back, like fabs. 8525 if (SCC.getOpcode() == ISD::SELECT_CC) { 8526 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 8527 N0.getValueType(), 8528 SCC.getOperand(0), SCC.getOperand(1), 8529 SCC.getOperand(4)); 8530 AddToWorkList(SETCC.getNode()); 8531 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 8532 SCC.getOperand(2), SCC.getOperand(3), SETCC); 8533 } 8534 8535 return SCC; 8536 } 8537 return SDValue(); 8538} 8539 8540/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 8541/// are the two values being selected between, see if we can simplify the 8542/// select. Callers of this should assume that TheSelect is deleted if this 8543/// returns true. As such, they should return the appropriate thing (e.g. the 8544/// node) back to the top-level of the DAG combiner loop to avoid it being 8545/// looked at. 8546bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 8547 SDValue RHS) { 8548 8549 // Cannot simplify select with vector condition 8550 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 8551 8552 // If this is a select from two identical things, try to pull the operation 8553 // through the select. 8554 if (LHS.getOpcode() != RHS.getOpcode() || 8555 !LHS.hasOneUse() || !RHS.hasOneUse()) 8556 return false; 8557 8558 // If this is a load and the token chain is identical, replace the select 8559 // of two loads with a load through a select of the address to load from. 8560 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 8561 // constants have been dropped into the constant pool. 8562 if (LHS.getOpcode() == ISD::LOAD) { 8563 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 8564 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 8565 8566 // Token chains must be identical. 8567 if (LHS.getOperand(0) != RHS.getOperand(0) || 8568 // Do not let this transformation reduce the number of volatile loads. 8569 LLD->isVolatile() || RLD->isVolatile() || 8570 // If this is an EXTLOAD, the VT's must match. 8571 LLD->getMemoryVT() != RLD->getMemoryVT() || 8572 // If this is an EXTLOAD, the kind of extension must match. 8573 (LLD->getExtensionType() != RLD->getExtensionType() && 8574 // The only exception is if one of the extensions is anyext. 8575 LLD->getExtensionType() != ISD::EXTLOAD && 8576 RLD->getExtensionType() != ISD::EXTLOAD) || 8577 // FIXME: this discards src value information. This is 8578 // over-conservative. It would be beneficial to be able to remember 8579 // both potential memory locations. Since we are discarding 8580 // src value info, don't do the transformation if the memory 8581 // locations are not in the default address space. 8582 LLD->getPointerInfo().getAddrSpace() != 0 || 8583 RLD->getPointerInfo().getAddrSpace() != 0) 8584 return false; 8585 8586 // Check that the select condition doesn't reach either load. If so, 8587 // folding this will induce a cycle into the DAG. If not, this is safe to 8588 // xform, so create a select of the addresses. 8589 SDValue Addr; 8590 if (TheSelect->getOpcode() == ISD::SELECT) { 8591 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 8592 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 8593 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 8594 return false; 8595 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 8596 LLD->getBasePtr().getValueType(), 8597 TheSelect->getOperand(0), LLD->getBasePtr(), 8598 RLD->getBasePtr()); 8599 } else { // Otherwise SELECT_CC 8600 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 8601 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 8602 8603 if ((LLD->hasAnyUseOfValue(1) && 8604 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 8605 (RLD->hasAnyUseOfValue(1) && 8606 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 8607 return false; 8608 8609 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 8610 LLD->getBasePtr().getValueType(), 8611 TheSelect->getOperand(0), 8612 TheSelect->getOperand(1), 8613 LLD->getBasePtr(), RLD->getBasePtr(), 8614 TheSelect->getOperand(4)); 8615 } 8616 8617 SDValue Load; 8618 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 8619 Load = DAG.getLoad(TheSelect->getValueType(0), 8620 TheSelect->getDebugLoc(), 8621 // FIXME: Discards pointer info. 8622 LLD->getChain(), Addr, MachinePointerInfo(), 8623 LLD->isVolatile(), LLD->isNonTemporal(), 8624 LLD->isInvariant(), LLD->getAlignment()); 8625 } else { 8626 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 8627 RLD->getExtensionType() : LLD->getExtensionType(), 8628 TheSelect->getDebugLoc(), 8629 TheSelect->getValueType(0), 8630 // FIXME: Discards pointer info. 8631 LLD->getChain(), Addr, MachinePointerInfo(), 8632 LLD->getMemoryVT(), LLD->isVolatile(), 8633 LLD->isNonTemporal(), LLD->getAlignment()); 8634 } 8635 8636 // Users of the select now use the result of the load. 8637 CombineTo(TheSelect, Load); 8638 8639 // Users of the old loads now use the new load's chain. We know the 8640 // old-load value is dead now. 8641 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 8642 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 8643 return true; 8644 } 8645 8646 return false; 8647} 8648 8649/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 8650/// where 'cond' is the comparison specified by CC. 8651SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 8652 SDValue N2, SDValue N3, 8653 ISD::CondCode CC, bool NotExtCompare) { 8654 // (x ? y : y) -> y. 8655 if (N2 == N3) return N2; 8656 8657 EVT VT = N2.getValueType(); 8658 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 8659 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 8660 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 8661 8662 // Determine if the condition we're dealing with is constant 8663 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 8664 N0, N1, CC, DL, false); 8665 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 8666 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 8667 8668 // fold select_cc true, x, y -> x 8669 if (SCCC && !SCCC->isNullValue()) 8670 return N2; 8671 // fold select_cc false, x, y -> y 8672 if (SCCC && SCCC->isNullValue()) 8673 return N3; 8674 8675 // Check to see if we can simplify the select into an fabs node 8676 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 8677 // Allow either -0.0 or 0.0 8678 if (CFP->getValueAPF().isZero()) { 8679 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 8680 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 8681 N0 == N2 && N3.getOpcode() == ISD::FNEG && 8682 N2 == N3.getOperand(0)) 8683 return DAG.getNode(ISD::FABS, DL, VT, N0); 8684 8685 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 8686 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 8687 N0 == N3 && N2.getOpcode() == ISD::FNEG && 8688 N2.getOperand(0) == N3) 8689 return DAG.getNode(ISD::FABS, DL, VT, N3); 8690 } 8691 } 8692 8693 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 8694 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 8695 // in it. This is a win when the constant is not otherwise available because 8696 // it replaces two constant pool loads with one. We only do this if the FP 8697 // type is known to be legal, because if it isn't, then we are before legalize 8698 // types an we want the other legalization to happen first (e.g. to avoid 8699 // messing with soft float) and if the ConstantFP is not legal, because if 8700 // it is legal, we may not need to store the FP constant in a constant pool. 8701 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 8702 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 8703 if (TLI.isTypeLegal(N2.getValueType()) && 8704 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 8705 TargetLowering::Legal) && 8706 // If both constants have multiple uses, then we won't need to do an 8707 // extra load, they are likely around in registers for other users. 8708 (TV->hasOneUse() || FV->hasOneUse())) { 8709 Constant *Elts[] = { 8710 const_cast<ConstantFP*>(FV->getConstantFPValue()), 8711 const_cast<ConstantFP*>(TV->getConstantFPValue()) 8712 }; 8713 Type *FPTy = Elts[0]->getType(); 8714 const TargetData &TD = *TLI.getTargetData(); 8715 8716 // Create a ConstantArray of the two constants. 8717 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 8718 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 8719 TD.getPrefTypeAlignment(FPTy)); 8720 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8721 8722 // Get the offsets to the 0 and 1 element of the array so that we can 8723 // select between them. 8724 SDValue Zero = DAG.getIntPtrConstant(0); 8725 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 8726 SDValue One = DAG.getIntPtrConstant(EltSize); 8727 8728 SDValue Cond = DAG.getSetCC(DL, 8729 TLI.getSetCCResultType(N0.getValueType()), 8730 N0, N1, CC); 8731 AddToWorkList(Cond.getNode()); 8732 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 8733 Cond, One, Zero); 8734 AddToWorkList(CstOffset.getNode()); 8735 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 8736 CstOffset); 8737 AddToWorkList(CPIdx.getNode()); 8738 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 8739 MachinePointerInfo::getConstantPool(), false, 8740 false, false, Alignment); 8741 8742 } 8743 } 8744 8745 // Check to see if we can perform the "gzip trick", transforming 8746 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 8747 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 8748 (N1C->isNullValue() || // (a < 0) ? b : 0 8749 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 8750 EVT XType = N0.getValueType(); 8751 EVT AType = N2.getValueType(); 8752 if (XType.bitsGE(AType)) { 8753 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 8754 // single-bit constant. 8755 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 8756 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 8757 ShCtV = XType.getSizeInBits()-ShCtV-1; 8758 SDValue ShCt = DAG.getConstant(ShCtV, 8759 getShiftAmountTy(N0.getValueType())); 8760 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 8761 XType, N0, ShCt); 8762 AddToWorkList(Shift.getNode()); 8763 8764 if (XType.bitsGT(AType)) { 8765 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8766 AddToWorkList(Shift.getNode()); 8767 } 8768 8769 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8770 } 8771 8772 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 8773 XType, N0, 8774 DAG.getConstant(XType.getSizeInBits()-1, 8775 getShiftAmountTy(N0.getValueType()))); 8776 AddToWorkList(Shift.getNode()); 8777 8778 if (XType.bitsGT(AType)) { 8779 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8780 AddToWorkList(Shift.getNode()); 8781 } 8782 8783 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8784 } 8785 } 8786 8787 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 8788 // where y is has a single bit set. 8789 // A plaintext description would be, we can turn the SELECT_CC into an AND 8790 // when the condition can be materialized as an all-ones register. Any 8791 // single bit-test can be materialized as an all-ones register with 8792 // shift-left and shift-right-arith. 8793 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 8794 N0->getValueType(0) == VT && 8795 N1C && N1C->isNullValue() && 8796 N2C && N2C->isNullValue()) { 8797 SDValue AndLHS = N0->getOperand(0); 8798 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 8799 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 8800 // Shift the tested bit over the sign bit. 8801 APInt AndMask = ConstAndRHS->getAPIntValue(); 8802 SDValue ShlAmt = 8803 DAG.getConstant(AndMask.countLeadingZeros(), 8804 getShiftAmountTy(AndLHS.getValueType())); 8805 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 8806 8807 // Now arithmetic right shift it all the way over, so the result is either 8808 // all-ones, or zero. 8809 SDValue ShrAmt = 8810 DAG.getConstant(AndMask.getBitWidth()-1, 8811 getShiftAmountTy(Shl.getValueType())); 8812 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 8813 8814 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 8815 } 8816 } 8817 8818 // fold select C, 16, 0 -> shl C, 4 8819 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 8820 TLI.getBooleanContents(N0.getValueType().isVector()) == 8821 TargetLowering::ZeroOrOneBooleanContent) { 8822 8823 // If the caller doesn't want us to simplify this into a zext of a compare, 8824 // don't do it. 8825 if (NotExtCompare && N2C->getAPIntValue() == 1) 8826 return SDValue(); 8827 8828 // Get a SetCC of the condition 8829 // FIXME: Should probably make sure that setcc is legal if we ever have a 8830 // target where it isn't. 8831 SDValue Temp, SCC; 8832 // cast from setcc result type to select result type 8833 if (LegalTypes) { 8834 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 8835 N0, N1, CC); 8836 if (N2.getValueType().bitsLT(SCC.getValueType())) 8837 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 8838 else 8839 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8840 N2.getValueType(), SCC); 8841 } else { 8842 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 8843 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8844 N2.getValueType(), SCC); 8845 } 8846 8847 AddToWorkList(SCC.getNode()); 8848 AddToWorkList(Temp.getNode()); 8849 8850 if (N2C->getAPIntValue() == 1) 8851 return Temp; 8852 8853 // shl setcc result by log2 n2c 8854 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 8855 DAG.getConstant(N2C->getAPIntValue().logBase2(), 8856 getShiftAmountTy(Temp.getValueType()))); 8857 } 8858 8859 // Check to see if this is the equivalent of setcc 8860 // FIXME: Turn all of these into setcc if setcc if setcc is legal 8861 // otherwise, go ahead with the folds. 8862 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 8863 EVT XType = N0.getValueType(); 8864 if (!LegalOperations || 8865 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 8866 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 8867 if (Res.getValueType() != VT) 8868 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 8869 return Res; 8870 } 8871 8872 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 8873 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 8874 (!LegalOperations || 8875 TLI.isOperationLegal(ISD::CTLZ, XType))) { 8876 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 8877 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 8878 DAG.getConstant(Log2_32(XType.getSizeInBits()), 8879 getShiftAmountTy(Ctlz.getValueType()))); 8880 } 8881 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 8882 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 8883 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 8884 XType, DAG.getConstant(0, XType), N0); 8885 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 8886 return DAG.getNode(ISD::SRL, DL, XType, 8887 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 8888 DAG.getConstant(XType.getSizeInBits()-1, 8889 getShiftAmountTy(XType))); 8890 } 8891 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 8892 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 8893 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 8894 DAG.getConstant(XType.getSizeInBits()-1, 8895 getShiftAmountTy(N0.getValueType()))); 8896 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 8897 } 8898 } 8899 8900 // Check to see if this is an integer abs. 8901 // select_cc setg[te] X, 0, X, -X -> 8902 // select_cc setgt X, -1, X, -X -> 8903 // select_cc setl[te] X, 0, -X, X -> 8904 // select_cc setlt X, 1, -X, X -> 8905 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 8906 if (N1C) { 8907 ConstantSDNode *SubC = NULL; 8908 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8909 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 8910 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 8911 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 8912 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 8913 (N1C->isOne() && CC == ISD::SETLT)) && 8914 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 8915 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 8916 8917 EVT XType = N0.getValueType(); 8918 if (SubC && SubC->isNullValue() && XType.isInteger()) { 8919 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 8920 N0, 8921 DAG.getConstant(XType.getSizeInBits()-1, 8922 getShiftAmountTy(N0.getValueType()))); 8923 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 8924 XType, N0, Shift); 8925 AddToWorkList(Shift.getNode()); 8926 AddToWorkList(Add.getNode()); 8927 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 8928 } 8929 } 8930 8931 return SDValue(); 8932} 8933 8934/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8935SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8936 SDValue N1, ISD::CondCode Cond, 8937 DebugLoc DL, bool foldBooleans) { 8938 TargetLowering::DAGCombinerInfo 8939 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8940 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8941} 8942 8943/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8944/// return a DAG expression to select that will generate the same value by 8945/// multiplying by a magic number. See: 8946/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8947SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8948 std::vector<SDNode*> Built; 8949 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8950 8951 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8952 ii != ee; ++ii) 8953 AddToWorkList(*ii); 8954 return S; 8955} 8956 8957/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8958/// return a DAG expression to select that will generate the same value by 8959/// multiplying by a magic number. See: 8960/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8961SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8962 std::vector<SDNode*> Built; 8963 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8964 8965 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8966 ii != ee; ++ii) 8967 AddToWorkList(*ii); 8968 return S; 8969} 8970 8971/// FindBaseOffset - Return true if base is a frame index, which is known not 8972// to alias with anything but itself. Provides base object and offset as 8973// results. 8974static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8975 const GlobalValue *&GV, const void *&CV) { 8976 // Assume it is a primitive operation. 8977 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8978 8979 // If it's an adding a simple constant then integrate the offset. 8980 if (Base.getOpcode() == ISD::ADD) { 8981 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8982 Base = Base.getOperand(0); 8983 Offset += C->getZExtValue(); 8984 } 8985 } 8986 8987 // Return the underlying GlobalValue, and update the Offset. Return false 8988 // for GlobalAddressSDNode since the same GlobalAddress may be represented 8989 // by multiple nodes with different offsets. 8990 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 8991 GV = G->getGlobal(); 8992 Offset += G->getOffset(); 8993 return false; 8994 } 8995 8996 // Return the underlying Constant value, and update the Offset. Return false 8997 // for ConstantSDNodes since the same constant pool entry may be represented 8998 // by multiple nodes with different offsets. 8999 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 9000 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 9001 : (const void *)C->getConstVal(); 9002 Offset += C->getOffset(); 9003 return false; 9004 } 9005 // If it's any of the following then it can't alias with anything but itself. 9006 return isa<FrameIndexSDNode>(Base); 9007} 9008 9009/// isAlias - Return true if there is any possibility that the two addresses 9010/// overlap. 9011bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 9012 const Value *SrcValue1, int SrcValueOffset1, 9013 unsigned SrcValueAlign1, 9014 const MDNode *TBAAInfo1, 9015 SDValue Ptr2, int64_t Size2, 9016 const Value *SrcValue2, int SrcValueOffset2, 9017 unsigned SrcValueAlign2, 9018 const MDNode *TBAAInfo2) const { 9019 // If they are the same then they must be aliases. 9020 if (Ptr1 == Ptr2) return true; 9021 9022 // Gather base node and offset information. 9023 SDValue Base1, Base2; 9024 int64_t Offset1, Offset2; 9025 const GlobalValue *GV1, *GV2; 9026 const void *CV1, *CV2; 9027 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 9028 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 9029 9030 // If they have a same base address then check to see if they overlap. 9031 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 9032 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9033 9034 // It is possible for different frame indices to alias each other, mostly 9035 // when tail call optimization reuses return address slots for arguments. 9036 // To catch this case, look up the actual index of frame indices to compute 9037 // the real alias relationship. 9038 if (isFrameIndex1 && isFrameIndex2) { 9039 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9040 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 9041 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 9042 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9043 } 9044 9045 // Otherwise, if we know what the bases are, and they aren't identical, then 9046 // we know they cannot alias. 9047 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 9048 return false; 9049 9050 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 9051 // compared to the size and offset of the access, we may be able to prove they 9052 // do not alias. This check is conservative for now to catch cases created by 9053 // splitting vector types. 9054 if ((SrcValueAlign1 == SrcValueAlign2) && 9055 (SrcValueOffset1 != SrcValueOffset2) && 9056 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 9057 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 9058 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 9059 9060 // There is no overlap between these relatively aligned accesses of similar 9061 // size, return no alias. 9062 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 9063 return false; 9064 } 9065 9066 if (CombinerGlobalAA) { 9067 // Use alias analysis information. 9068 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 9069 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 9070 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 9071 AliasAnalysis::AliasResult AAResult = 9072 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 9073 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 9074 if (AAResult == AliasAnalysis::NoAlias) 9075 return false; 9076 } 9077 9078 // Otherwise we have to assume they alias. 9079 return true; 9080} 9081 9082/// FindAliasInfo - Extracts the relevant alias information from the memory 9083/// node. Returns true if the operand was a load. 9084bool DAGCombiner::FindAliasInfo(SDNode *N, 9085 SDValue &Ptr, int64_t &Size, 9086 const Value *&SrcValue, 9087 int &SrcValueOffset, 9088 unsigned &SrcValueAlign, 9089 const MDNode *&TBAAInfo) const { 9090 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 9091 9092 Ptr = LS->getBasePtr(); 9093 Size = LS->getMemoryVT().getSizeInBits() >> 3; 9094 SrcValue = LS->getSrcValue(); 9095 SrcValueOffset = LS->getSrcValueOffset(); 9096 SrcValueAlign = LS->getOriginalAlignment(); 9097 TBAAInfo = LS->getTBAAInfo(); 9098 return isa<LoadSDNode>(LS); 9099} 9100 9101/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 9102/// looking for aliasing nodes and adding them to the Aliases vector. 9103void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 9104 SmallVector<SDValue, 8> &Aliases) { 9105 SmallVector<SDValue, 8> Chains; // List of chains to visit. 9106 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 9107 9108 // Get alias information for node. 9109 SDValue Ptr; 9110 int64_t Size; 9111 const Value *SrcValue; 9112 int SrcValueOffset; 9113 unsigned SrcValueAlign; 9114 const MDNode *SrcTBAAInfo; 9115 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 9116 SrcValueAlign, SrcTBAAInfo); 9117 9118 // Starting off. 9119 Chains.push_back(OriginalChain); 9120 unsigned Depth = 0; 9121 9122 // Look at each chain and determine if it is an alias. If so, add it to the 9123 // aliases list. If not, then continue up the chain looking for the next 9124 // candidate. 9125 while (!Chains.empty()) { 9126 SDValue Chain = Chains.back(); 9127 Chains.pop_back(); 9128 9129 // For TokenFactor nodes, look at each operand and only continue up the 9130 // chain until we find two aliases. If we've seen two aliases, assume we'll 9131 // find more and revert to original chain since the xform is unlikely to be 9132 // profitable. 9133 // 9134 // FIXME: The depth check could be made to return the last non-aliasing 9135 // chain we found before we hit a tokenfactor rather than the original 9136 // chain. 9137 if (Depth > 6 || Aliases.size() == 2) { 9138 Aliases.clear(); 9139 Aliases.push_back(OriginalChain); 9140 break; 9141 } 9142 9143 // Don't bother if we've been before. 9144 if (!Visited.insert(Chain.getNode())) 9145 continue; 9146 9147 switch (Chain.getOpcode()) { 9148 case ISD::EntryToken: 9149 // Entry token is ideal chain operand, but handled in FindBetterChain. 9150 break; 9151 9152 case ISD::LOAD: 9153 case ISD::STORE: { 9154 // Get alias information for Chain. 9155 SDValue OpPtr; 9156 int64_t OpSize; 9157 const Value *OpSrcValue; 9158 int OpSrcValueOffset; 9159 unsigned OpSrcValueAlign; 9160 const MDNode *OpSrcTBAAInfo; 9161 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 9162 OpSrcValue, OpSrcValueOffset, 9163 OpSrcValueAlign, 9164 OpSrcTBAAInfo); 9165 9166 // If chain is alias then stop here. 9167 if (!(IsLoad && IsOpLoad) && 9168 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 9169 SrcTBAAInfo, 9170 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 9171 OpSrcValueAlign, OpSrcTBAAInfo)) { 9172 Aliases.push_back(Chain); 9173 } else { 9174 // Look further up the chain. 9175 Chains.push_back(Chain.getOperand(0)); 9176 ++Depth; 9177 } 9178 break; 9179 } 9180 9181 case ISD::TokenFactor: 9182 // We have to check each of the operands of the token factor for "small" 9183 // token factors, so we queue them up. Adding the operands to the queue 9184 // (stack) in reverse order maintains the original order and increases the 9185 // likelihood that getNode will find a matching token factor (CSE.) 9186 if (Chain.getNumOperands() > 16) { 9187 Aliases.push_back(Chain); 9188 break; 9189 } 9190 for (unsigned n = Chain.getNumOperands(); n;) 9191 Chains.push_back(Chain.getOperand(--n)); 9192 ++Depth; 9193 break; 9194 9195 default: 9196 // For all other instructions we will just have to take what we can get. 9197 Aliases.push_back(Chain); 9198 break; 9199 } 9200 } 9201} 9202 9203/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 9204/// for a better chain (aliasing node.) 9205SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 9206 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 9207 9208 // Accumulate all the aliases to this node. 9209 GatherAllAliases(N, OldChain, Aliases); 9210 9211 // If no operands then chain to entry token. 9212 if (Aliases.size() == 0) 9213 return DAG.getEntryNode(); 9214 9215 // If a single operand then chain to it. We don't need to revisit it. 9216 if (Aliases.size() == 1) 9217 return Aliases[0]; 9218 9219 // Construct a custom tailored token factor. 9220 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 9221 &Aliases[0], Aliases.size()); 9222} 9223 9224// SelectionDAG::Combine - This is the entry point for the file. 9225// 9226void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 9227 CodeGenOpt::Level OptLevel) { 9228 /// run - This is the main entry point to this class. 9229 /// 9230 DAGCombiner(*this, AA, OptLevel).Run(Level); 9231} 9232