DAGCombiner.cpp revision 59f1e97ef3940840e023ae1d6226c9b416222d2d
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/CodeGen/SelectionDAG.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/Target/TargetData.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include "llvm/ADT/Statistic.h" 40#include "llvm/Support/Compiler.h" 41#include "llvm/Support/CommandLine.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Support/MathExtras.h" 44#include <algorithm> 45using namespace llvm; 46 47STATISTIC(NodesCombined , "Number of dag nodes combined"); 48STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 49STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 50 51namespace { 52#ifndef NDEBUG 53 static cl::opt<bool> 54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 55 cl::desc("Pop up a window to show dags before the first " 56 "dag combine pass")); 57 static cl::opt<bool> 58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 59 cl::desc("Pop up a window to show dags before the second " 60 "dag combine pass")); 61#else 62 static const bool ViewDAGCombine1 = false; 63 static const bool ViewDAGCombine2 = false; 64#endif 65 66 static cl::opt<bool> 67 CombinerAA("combiner-alias-analysis", cl::Hidden, 68 cl::desc("Turn on alias analysis during testing")); 69 70 static cl::opt<bool> 71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 72 cl::desc("Include global information in alias analysis")); 73 74//------------------------------ DAGCombiner ---------------------------------// 75 76 class VISIBILITY_HIDDEN DAGCombiner { 77 SelectionDAG &DAG; 78 TargetLowering &TLI; 79 bool AfterLegalize; 80 81 // Worklist of all of the nodes that need to be simplified. 82 std::vector<SDNode*> WorkList; 83 84 // AA - Used for DAG load/store alias analysis. 85 AliasAnalysis &AA; 86 87 /// AddUsersToWorkList - When an instruction is simplified, add all users of 88 /// the instruction to the work lists because they might get more simplified 89 /// now. 90 /// 91 void AddUsersToWorkList(SDNode *N) { 92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 93 UI != UE; ++UI) 94 AddToWorkList(*UI); 95 } 96 97 /// removeFromWorkList - remove all instances of N from the worklist. 98 /// 99 void removeFromWorkList(SDNode *N) { 100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 101 WorkList.end()); 102 } 103 104 /// visit - call the node-specific routine that knows how to fold each 105 /// particular type of node. 106 SDOperand visit(SDNode *N); 107 108 public: 109 /// AddToWorkList - Add to the work list making sure it's instance is at the 110 /// the back (next to be processed.) 111 void AddToWorkList(SDNode *N) { 112 removeFromWorkList(N); 113 WorkList.push_back(N); 114 } 115 116 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 117 bool AddTo = true) { 118 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 119 ++NodesCombined; 120 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 121 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 122 DOUT << " and " << NumTo-1 << " other values\n"; 123 std::vector<SDNode*> NowDead; 124 DAG.ReplaceAllUsesWith(N, To, &NowDead); 125 126 if (AddTo) { 127 // Push the new nodes and any users onto the worklist 128 for (unsigned i = 0, e = NumTo; i != e; ++i) { 129 AddToWorkList(To[i].Val); 130 AddUsersToWorkList(To[i].Val); 131 } 132 } 133 134 // Nodes can be reintroduced into the worklist. Make sure we do not 135 // process a node that has been replaced. 136 removeFromWorkList(N); 137 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 138 removeFromWorkList(NowDead[i]); 139 140 // Finally, since the node is now dead, remove it from the graph. 141 DAG.DeleteNode(N); 142 return SDOperand(N, 0); 143 } 144 145 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 146 return CombineTo(N, &Res, 1, AddTo); 147 } 148 149 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 150 bool AddTo = true) { 151 SDOperand To[] = { Res0, Res1 }; 152 return CombineTo(N, To, 2, AddTo); 153 } 154 private: 155 156 /// SimplifyDemandedBits - Check the specified integer node value to see if 157 /// it can be simplified or if things it uses can be simplified by bit 158 /// propagation. If so, return true. 159 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) { 160 TargetLowering::TargetLoweringOpt TLO(DAG); 161 uint64_t KnownZero, KnownOne; 162 Demanded &= MVT::getIntVTBitMask(Op.getValueType()); 163 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 164 return false; 165 166 // Revisit the node. 167 AddToWorkList(Op.Val); 168 169 // Replace the old value with the new one. 170 ++NodesCombined; 171 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 172 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 173 DOUT << '\n'; 174 175 std::vector<SDNode*> NowDead; 176 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead); 177 178 // Push the new node and any (possibly new) users onto the worklist. 179 AddToWorkList(TLO.New.Val); 180 AddUsersToWorkList(TLO.New.Val); 181 182 // Nodes can end up on the worklist more than once. Make sure we do 183 // not process a node that has been replaced. 184 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 185 removeFromWorkList(NowDead[i]); 186 187 // Finally, if the node is now dead, remove it from the graph. The node 188 // may not be dead if the replacement process recursively simplified to 189 // something else needing this node. 190 if (TLO.Old.Val->use_empty()) { 191 removeFromWorkList(TLO.Old.Val); 192 193 // If the operands of this node are only used by the node, they will now 194 // be dead. Make sure to visit them first to delete dead nodes early. 195 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 196 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 197 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 198 199 DAG.DeleteNode(TLO.Old.Val); 200 } 201 return true; 202 } 203 204 bool CombineToPreIndexedLoadStore(SDNode *N); 205 bool CombineToPostIndexedLoadStore(SDNode *N); 206 207 208 /// combine - call the node-specific routine that knows how to fold each 209 /// particular type of node. If that doesn't do anything, try the 210 /// target-specific DAG combines. 211 SDOperand combine(SDNode *N); 212 213 // Visitation implementation - Implement dag node combining for different 214 // node types. The semantics are as follows: 215 // Return Value: 216 // SDOperand.Val == 0 - No change was made 217 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 218 // otherwise - N should be replaced by the returned Operand. 219 // 220 SDOperand visitTokenFactor(SDNode *N); 221 SDOperand visitADD(SDNode *N); 222 SDOperand visitSUB(SDNode *N); 223 SDOperand visitADDC(SDNode *N); 224 SDOperand visitADDE(SDNode *N); 225 SDOperand visitMUL(SDNode *N); 226 SDOperand visitSDIV(SDNode *N); 227 SDOperand visitUDIV(SDNode *N); 228 SDOperand visitSREM(SDNode *N); 229 SDOperand visitUREM(SDNode *N); 230 SDOperand visitMULHU(SDNode *N); 231 SDOperand visitMULHS(SDNode *N); 232 SDOperand visitSMUL_LOHI(SDNode *N); 233 SDOperand visitUMUL_LOHI(SDNode *N); 234 SDOperand visitSDIVREM(SDNode *N); 235 SDOperand visitUDIVREM(SDNode *N); 236 SDOperand visitAND(SDNode *N); 237 SDOperand visitOR(SDNode *N); 238 SDOperand visitXOR(SDNode *N); 239 SDOperand SimplifyVBinOp(SDNode *N); 240 SDOperand visitSHL(SDNode *N); 241 SDOperand visitSRA(SDNode *N); 242 SDOperand visitSRL(SDNode *N); 243 SDOperand visitCTLZ(SDNode *N); 244 SDOperand visitCTTZ(SDNode *N); 245 SDOperand visitCTPOP(SDNode *N); 246 SDOperand visitSELECT(SDNode *N); 247 SDOperand visitSELECT_CC(SDNode *N); 248 SDOperand visitSETCC(SDNode *N); 249 SDOperand visitSIGN_EXTEND(SDNode *N); 250 SDOperand visitZERO_EXTEND(SDNode *N); 251 SDOperand visitANY_EXTEND(SDNode *N); 252 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 253 SDOperand visitTRUNCATE(SDNode *N); 254 SDOperand visitBIT_CONVERT(SDNode *N); 255 SDOperand visitFADD(SDNode *N); 256 SDOperand visitFSUB(SDNode *N); 257 SDOperand visitFMUL(SDNode *N); 258 SDOperand visitFDIV(SDNode *N); 259 SDOperand visitFREM(SDNode *N); 260 SDOperand visitFCOPYSIGN(SDNode *N); 261 SDOperand visitSINT_TO_FP(SDNode *N); 262 SDOperand visitUINT_TO_FP(SDNode *N); 263 SDOperand visitFP_TO_SINT(SDNode *N); 264 SDOperand visitFP_TO_UINT(SDNode *N); 265 SDOperand visitFP_ROUND(SDNode *N); 266 SDOperand visitFP_ROUND_INREG(SDNode *N); 267 SDOperand visitFP_EXTEND(SDNode *N); 268 SDOperand visitFNEG(SDNode *N); 269 SDOperand visitFABS(SDNode *N); 270 SDOperand visitBRCOND(SDNode *N); 271 SDOperand visitBR_CC(SDNode *N); 272 SDOperand visitLOAD(SDNode *N); 273 SDOperand visitSTORE(SDNode *N); 274 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 275 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 276 SDOperand visitBUILD_VECTOR(SDNode *N); 277 SDOperand visitCONCAT_VECTORS(SDNode *N); 278 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 279 280 SDOperand XformToShuffleWithZero(SDNode *N); 281 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 282 283 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 284 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 285 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 286 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 287 SDOperand N3, ISD::CondCode CC, 288 bool NotExtCompare = false); 289 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 290 ISD::CondCode Cond, bool foldBooleans = true); 291 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp); 292 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 293 SDOperand BuildSDIV(SDNode *N); 294 SDOperand BuildUDIV(SDNode *N); 295 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 296 SDOperand ReduceLoadWidth(SDNode *N); 297 298 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask); 299 300 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 301 /// looking for aliasing nodes and adding them to the Aliases vector. 302 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 303 SmallVector<SDOperand, 8> &Aliases); 304 305 /// isAlias - Return true if there is any possibility that the two addresses 306 /// overlap. 307 bool isAlias(SDOperand Ptr1, int64_t Size1, 308 const Value *SrcValue1, int SrcValueOffset1, 309 SDOperand Ptr2, int64_t Size2, 310 const Value *SrcValue2, int SrcValueOffset2); 311 312 /// FindAliasInfo - Extracts the relevant alias information from the memory 313 /// node. Returns true if the operand was a load. 314 bool FindAliasInfo(SDNode *N, 315 SDOperand &Ptr, int64_t &Size, 316 const Value *&SrcValue, int &SrcValueOffset); 317 318 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 319 /// looking for a better chain (aliasing node.) 320 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 321 322public: 323 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 324 : DAG(D), 325 TLI(D.getTargetLoweringInfo()), 326 AfterLegalize(false), 327 AA(A) {} 328 329 /// Run - runs the dag combiner on all nodes in the work list 330 void Run(bool RunningAfterLegalize); 331 }; 332} 333 334//===----------------------------------------------------------------------===// 335// TargetLowering::DAGCombinerInfo implementation 336//===----------------------------------------------------------------------===// 337 338void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 339 ((DAGCombiner*)DC)->AddToWorkList(N); 340} 341 342SDOperand TargetLowering::DAGCombinerInfo:: 343CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 344 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 345} 346 347SDOperand TargetLowering::DAGCombinerInfo:: 348CombineTo(SDNode *N, SDOperand Res) { 349 return ((DAGCombiner*)DC)->CombineTo(N, Res); 350} 351 352 353SDOperand TargetLowering::DAGCombinerInfo:: 354CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 355 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 356} 357 358 359//===----------------------------------------------------------------------===// 360// Helper Functions 361//===----------------------------------------------------------------------===// 362 363/// isNegatibleForFree - Return 1 if we can compute the negated form of the 364/// specified expression for the same cost as the expression itself, or 2 if we 365/// can compute the negated form more cheaply than the expression itself. 366static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 367 // No compile time optimizations on this type. 368 if (Op.getValueType() == MVT::ppcf128) 369 return 0; 370 371 // fneg is removable even if it has multiple uses. 372 if (Op.getOpcode() == ISD::FNEG) return 2; 373 374 // Don't allow anything with multiple uses. 375 if (!Op.hasOneUse()) return 0; 376 377 // Don't recurse exponentially. 378 if (Depth > 6) return 0; 379 380 switch (Op.getOpcode()) { 381 default: return false; 382 case ISD::ConstantFP: 383 return 1; 384 case ISD::FADD: 385 // FIXME: determine better conditions for this xform. 386 if (!UnsafeFPMath) return 0; 387 388 // -(A+B) -> -A - B 389 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 390 return V; 391 // -(A+B) -> -B - A 392 return isNegatibleForFree(Op.getOperand(1), Depth+1); 393 case ISD::FSUB: 394 // We can't turn -(A-B) into B-A when we honor signed zeros. 395 if (!UnsafeFPMath) return 0; 396 397 // -(A-B) -> B-A 398 return 1; 399 400 case ISD::FMUL: 401 case ISD::FDIV: 402 if (HonorSignDependentRoundingFPMath()) return 0; 403 404 // -(X*Y) -> (-X * Y) or (X*-Y) 405 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 406 return V; 407 408 return isNegatibleForFree(Op.getOperand(1), Depth+1); 409 410 case ISD::FP_EXTEND: 411 case ISD::FP_ROUND: 412 case ISD::FSIN: 413 return isNegatibleForFree(Op.getOperand(0), Depth+1); 414 } 415} 416 417/// GetNegatedExpression - If isNegatibleForFree returns true, this function 418/// returns the newly negated expression. 419static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 420 unsigned Depth = 0) { 421 // fneg is removable even if it has multiple uses. 422 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 423 424 // Don't allow anything with multiple uses. 425 assert(Op.hasOneUse() && "Unknown reuse!"); 426 427 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 428 switch (Op.getOpcode()) { 429 default: assert(0 && "Unknown code"); 430 case ISD::ConstantFP: { 431 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 432 V.changeSign(); 433 return DAG.getConstantFP(V, Op.getValueType()); 434 } 435 case ISD::FADD: 436 // FIXME: determine better conditions for this xform. 437 assert(UnsafeFPMath); 438 439 // -(A+B) -> -A - B 440 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 441 return DAG.getNode(ISD::FSUB, Op.getValueType(), 442 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 443 Op.getOperand(1)); 444 // -(A+B) -> -B - A 445 return DAG.getNode(ISD::FSUB, Op.getValueType(), 446 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 447 Op.getOperand(0)); 448 case ISD::FSUB: 449 // We can't turn -(A-B) into B-A when we honor signed zeros. 450 assert(UnsafeFPMath); 451 452 // -(0-B) -> B 453 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 454 if (N0CFP->getValueAPF().isZero()) 455 return Op.getOperand(1); 456 457 // -(A-B) -> B-A 458 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 459 Op.getOperand(0)); 460 461 case ISD::FMUL: 462 case ISD::FDIV: 463 assert(!HonorSignDependentRoundingFPMath()); 464 465 // -(X*Y) -> -X * Y 466 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 467 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 468 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 469 Op.getOperand(1)); 470 471 // -(X*Y) -> X * -Y 472 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 473 Op.getOperand(0), 474 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 475 476 case ISD::FP_EXTEND: 477 case ISD::FP_ROUND: 478 case ISD::FSIN: 479 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 480 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 481 } 482} 483 484 485// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 486// that selects between the values 1 and 0, making it equivalent to a setcc. 487// Also, set the incoming LHS, RHS, and CC references to the appropriate 488// nodes based on the type of node we are checking. This simplifies life a 489// bit for the callers. 490static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 491 SDOperand &CC) { 492 if (N.getOpcode() == ISD::SETCC) { 493 LHS = N.getOperand(0); 494 RHS = N.getOperand(1); 495 CC = N.getOperand(2); 496 return true; 497 } 498 if (N.getOpcode() == ISD::SELECT_CC && 499 N.getOperand(2).getOpcode() == ISD::Constant && 500 N.getOperand(3).getOpcode() == ISD::Constant && 501 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 502 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 503 LHS = N.getOperand(0); 504 RHS = N.getOperand(1); 505 CC = N.getOperand(4); 506 return true; 507 } 508 return false; 509} 510 511// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 512// one use. If this is true, it allows the users to invert the operation for 513// free when it is profitable to do so. 514static bool isOneUseSetCC(SDOperand N) { 515 SDOperand N0, N1, N2; 516 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 517 return true; 518 return false; 519} 520 521SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 522 MVT::ValueType VT = N0.getValueType(); 523 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 524 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 525 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 526 if (isa<ConstantSDNode>(N1)) { 527 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 528 AddToWorkList(OpNode.Val); 529 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 530 } else if (N0.hasOneUse()) { 531 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 532 AddToWorkList(OpNode.Val); 533 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 534 } 535 } 536 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 537 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 538 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 539 if (isa<ConstantSDNode>(N0)) { 540 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 541 AddToWorkList(OpNode.Val); 542 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 543 } else if (N1.hasOneUse()) { 544 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 545 AddToWorkList(OpNode.Val); 546 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 547 } 548 } 549 return SDOperand(); 550} 551 552//===----------------------------------------------------------------------===// 553// Main DAG Combiner implementation 554//===----------------------------------------------------------------------===// 555 556void DAGCombiner::Run(bool RunningAfterLegalize) { 557 // set the instance variable, so that the various visit routines may use it. 558 AfterLegalize = RunningAfterLegalize; 559 560 // Add all the dag nodes to the worklist. 561 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 562 E = DAG.allnodes_end(); I != E; ++I) 563 WorkList.push_back(I); 564 565 // Create a dummy node (which is not added to allnodes), that adds a reference 566 // to the root node, preventing it from being deleted, and tracking any 567 // changes of the root. 568 HandleSDNode Dummy(DAG.getRoot()); 569 570 // The root of the dag may dangle to deleted nodes until the dag combiner is 571 // done. Set it to null to avoid confusion. 572 DAG.setRoot(SDOperand()); 573 574 // while the worklist isn't empty, inspect the node on the end of it and 575 // try and combine it. 576 while (!WorkList.empty()) { 577 SDNode *N = WorkList.back(); 578 WorkList.pop_back(); 579 580 // If N has no uses, it is dead. Make sure to revisit all N's operands once 581 // N is deleted from the DAG, since they too may now be dead or may have a 582 // reduced number of uses, allowing other xforms. 583 if (N->use_empty() && N != &Dummy) { 584 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 585 AddToWorkList(N->getOperand(i).Val); 586 587 DAG.DeleteNode(N); 588 continue; 589 } 590 591 SDOperand RV = combine(N); 592 593 if (RV.Val) { 594 ++NodesCombined; 595 // If we get back the same node we passed in, rather than a new node or 596 // zero, we know that the node must have defined multiple values and 597 // CombineTo was used. Since CombineTo takes care of the worklist 598 // mechanics for us, we have no work to do in this case. 599 if (RV.Val != N) { 600 assert(N->getOpcode() != ISD::DELETED_NODE && 601 RV.Val->getOpcode() != ISD::DELETED_NODE && 602 "Node was deleted but visit returned new node!"); 603 604 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 605 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 606 DOUT << '\n'; 607 std::vector<SDNode*> NowDead; 608 if (N->getNumValues() == RV.Val->getNumValues()) 609 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 610 else { 611 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 612 SDOperand OpV = RV; 613 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 614 } 615 616 // Push the new node and any users onto the worklist 617 AddToWorkList(RV.Val); 618 AddUsersToWorkList(RV.Val); 619 620 // Nodes can be reintroduced into the worklist. Make sure we do not 621 // process a node that has been replaced. 622 removeFromWorkList(N); 623 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 624 removeFromWorkList(NowDead[i]); 625 626 // Finally, since the node is now dead, remove it from the graph. 627 DAG.DeleteNode(N); 628 } 629 } 630 } 631 632 // If the root changed (e.g. it was a dead load, update the root). 633 DAG.setRoot(Dummy.getValue()); 634} 635 636SDOperand DAGCombiner::visit(SDNode *N) { 637 switch(N->getOpcode()) { 638 default: break; 639 case ISD::TokenFactor: return visitTokenFactor(N); 640 case ISD::ADD: return visitADD(N); 641 case ISD::SUB: return visitSUB(N); 642 case ISD::ADDC: return visitADDC(N); 643 case ISD::ADDE: return visitADDE(N); 644 case ISD::MUL: return visitMUL(N); 645 case ISD::SDIV: return visitSDIV(N); 646 case ISD::UDIV: return visitUDIV(N); 647 case ISD::SREM: return visitSREM(N); 648 case ISD::UREM: return visitUREM(N); 649 case ISD::MULHU: return visitMULHU(N); 650 case ISD::MULHS: return visitMULHS(N); 651 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 652 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 653 case ISD::SDIVREM: return visitSDIVREM(N); 654 case ISD::UDIVREM: return visitUDIVREM(N); 655 case ISD::AND: return visitAND(N); 656 case ISD::OR: return visitOR(N); 657 case ISD::XOR: return visitXOR(N); 658 case ISD::SHL: return visitSHL(N); 659 case ISD::SRA: return visitSRA(N); 660 case ISD::SRL: return visitSRL(N); 661 case ISD::CTLZ: return visitCTLZ(N); 662 case ISD::CTTZ: return visitCTTZ(N); 663 case ISD::CTPOP: return visitCTPOP(N); 664 case ISD::SELECT: return visitSELECT(N); 665 case ISD::SELECT_CC: return visitSELECT_CC(N); 666 case ISD::SETCC: return visitSETCC(N); 667 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 668 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 669 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 670 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 671 case ISD::TRUNCATE: return visitTRUNCATE(N); 672 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 673 case ISD::FADD: return visitFADD(N); 674 case ISD::FSUB: return visitFSUB(N); 675 case ISD::FMUL: return visitFMUL(N); 676 case ISD::FDIV: return visitFDIV(N); 677 case ISD::FREM: return visitFREM(N); 678 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 679 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 680 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 681 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 682 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 683 case ISD::FP_ROUND: return visitFP_ROUND(N); 684 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 685 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 686 case ISD::FNEG: return visitFNEG(N); 687 case ISD::FABS: return visitFABS(N); 688 case ISD::BRCOND: return visitBRCOND(N); 689 case ISD::BR_CC: return visitBR_CC(N); 690 case ISD::LOAD: return visitLOAD(N); 691 case ISD::STORE: return visitSTORE(N); 692 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 693 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 694 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 695 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 696 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 697 } 698 return SDOperand(); 699} 700 701SDOperand DAGCombiner::combine(SDNode *N) { 702 703 SDOperand RV = visit(N); 704 705 // If nothing happened, try a target-specific DAG combine. 706 if (RV.Val == 0) { 707 assert(N->getOpcode() != ISD::DELETED_NODE && 708 "Node was deleted but visit returned NULL!"); 709 710 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 711 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 712 713 // Expose the DAG combiner to the target combiner impls. 714 TargetLowering::DAGCombinerInfo 715 DagCombineInfo(DAG, !AfterLegalize, false, this); 716 717 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 718 } 719 } 720 721 return RV; 722} 723 724/// getInputChainForNode - Given a node, return its input chain if it has one, 725/// otherwise return a null sd operand. 726static SDOperand getInputChainForNode(SDNode *N) { 727 if (unsigned NumOps = N->getNumOperands()) { 728 if (N->getOperand(0).getValueType() == MVT::Other) 729 return N->getOperand(0); 730 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 731 return N->getOperand(NumOps-1); 732 for (unsigned i = 1; i < NumOps-1; ++i) 733 if (N->getOperand(i).getValueType() == MVT::Other) 734 return N->getOperand(i); 735 } 736 return SDOperand(0, 0); 737} 738 739SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 740 // If N has two operands, where one has an input chain equal to the other, 741 // the 'other' chain is redundant. 742 if (N->getNumOperands() == 2) { 743 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 744 return N->getOperand(0); 745 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 746 return N->getOperand(1); 747 } 748 749 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 750 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 751 SmallPtrSet<SDNode*, 16> SeenOps; 752 bool Changed = false; // If we should replace this token factor. 753 754 // Start out with this token factor. 755 TFs.push_back(N); 756 757 // Iterate through token factors. The TFs grows when new token factors are 758 // encountered. 759 for (unsigned i = 0; i < TFs.size(); ++i) { 760 SDNode *TF = TFs[i]; 761 762 // Check each of the operands. 763 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 764 SDOperand Op = TF->getOperand(i); 765 766 switch (Op.getOpcode()) { 767 case ISD::EntryToken: 768 // Entry tokens don't need to be added to the list. They are 769 // rededundant. 770 Changed = true; 771 break; 772 773 case ISD::TokenFactor: 774 if ((CombinerAA || Op.hasOneUse()) && 775 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 776 // Queue up for processing. 777 TFs.push_back(Op.Val); 778 // Clean up in case the token factor is removed. 779 AddToWorkList(Op.Val); 780 Changed = true; 781 break; 782 } 783 // Fall thru 784 785 default: 786 // Only add if it isn't already in the list. 787 if (SeenOps.insert(Op.Val)) 788 Ops.push_back(Op); 789 else 790 Changed = true; 791 break; 792 } 793 } 794 } 795 796 SDOperand Result; 797 798 // If we've change things around then replace token factor. 799 if (Changed) { 800 if (Ops.size() == 0) { 801 // The entry token is the only possible outcome. 802 Result = DAG.getEntryNode(); 803 } else { 804 // New and improved token factor. 805 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 806 } 807 808 // Don't add users to work list. 809 return CombineTo(N, Result, false); 810 } 811 812 return Result; 813} 814 815static 816SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 817 MVT::ValueType VT = N0.getValueType(); 818 SDOperand N00 = N0.getOperand(0); 819 SDOperand N01 = N0.getOperand(1); 820 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 821 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 822 isa<ConstantSDNode>(N00.getOperand(1))) { 823 N0 = DAG.getNode(ISD::ADD, VT, 824 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 825 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 826 return DAG.getNode(ISD::ADD, VT, N0, N1); 827 } 828 return SDOperand(); 829} 830 831static 832SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 833 SelectionDAG &DAG) { 834 MVT::ValueType VT = N->getValueType(0); 835 unsigned Opc = N->getOpcode(); 836 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 837 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 838 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 839 ISD::CondCode CC = ISD::SETCC_INVALID; 840 if (isSlctCC) 841 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 842 else { 843 SDOperand CCOp = Slct.getOperand(0); 844 if (CCOp.getOpcode() == ISD::SETCC) 845 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 846 } 847 848 bool DoXform = false; 849 bool InvCC = false; 850 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 851 "Bad input!"); 852 if (LHS.getOpcode() == ISD::Constant && 853 cast<ConstantSDNode>(LHS)->isNullValue()) 854 DoXform = true; 855 else if (CC != ISD::SETCC_INVALID && 856 RHS.getOpcode() == ISD::Constant && 857 cast<ConstantSDNode>(RHS)->isNullValue()) { 858 std::swap(LHS, RHS); 859 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType() 860 : Slct.getOperand(0).getOperand(0).getValueType()); 861 CC = ISD::getSetCCInverse(CC, isInt); 862 DoXform = true; 863 InvCC = true; 864 } 865 866 if (DoXform) { 867 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 868 if (isSlctCC) 869 return DAG.getSelectCC(OtherOp, Result, 870 Slct.getOperand(0), Slct.getOperand(1), CC); 871 SDOperand CCOp = Slct.getOperand(0); 872 if (InvCC) 873 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 874 CCOp.getOperand(1), CC); 875 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 876 } 877 return SDOperand(); 878} 879 880SDOperand DAGCombiner::visitADD(SDNode *N) { 881 SDOperand N0 = N->getOperand(0); 882 SDOperand N1 = N->getOperand(1); 883 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 884 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 885 MVT::ValueType VT = N0.getValueType(); 886 887 // fold vector ops 888 if (MVT::isVector(VT)) { 889 SDOperand FoldedVOp = SimplifyVBinOp(N); 890 if (FoldedVOp.Val) return FoldedVOp; 891 } 892 893 // fold (add x, undef) -> undef 894 if (N0.getOpcode() == ISD::UNDEF) 895 return N0; 896 if (N1.getOpcode() == ISD::UNDEF) 897 return N1; 898 // fold (add c1, c2) -> c1+c2 899 if (N0C && N1C) 900 return DAG.getNode(ISD::ADD, VT, N0, N1); 901 // canonicalize constant to RHS 902 if (N0C && !N1C) 903 return DAG.getNode(ISD::ADD, VT, N1, N0); 904 // fold (add x, 0) -> x 905 if (N1C && N1C->isNullValue()) 906 return N0; 907 // fold ((c1-A)+c2) -> (c1+c2)-A 908 if (N1C && N0.getOpcode() == ISD::SUB) 909 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 910 return DAG.getNode(ISD::SUB, VT, 911 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 912 N0.getOperand(1)); 913 // reassociate add 914 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 915 if (RADD.Val != 0) 916 return RADD; 917 // fold ((0-A) + B) -> B-A 918 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 919 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 920 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 921 // fold (A + (0-B)) -> A-B 922 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 923 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 924 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 925 // fold (A+(B-A)) -> B 926 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 927 return N1.getOperand(0); 928 929 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 930 return SDOperand(N, 0); 931 932 // fold (a+b) -> (a|b) iff a and b share no bits. 933 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 934 uint64_t LHSZero, LHSOne; 935 uint64_t RHSZero, RHSOne; 936 uint64_t Mask = MVT::getIntVTBitMask(VT); 937 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 938 if (LHSZero) { 939 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 940 941 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 942 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 943 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 944 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 945 return DAG.getNode(ISD::OR, VT, N0, N1); 946 } 947 } 948 949 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 950 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 951 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 952 if (Result.Val) return Result; 953 } 954 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 955 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 956 if (Result.Val) return Result; 957 } 958 959 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 960 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 961 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 962 if (Result.Val) return Result; 963 } 964 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 965 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 966 if (Result.Val) return Result; 967 } 968 969 return SDOperand(); 970} 971 972SDOperand DAGCombiner::visitADDC(SDNode *N) { 973 SDOperand N0 = N->getOperand(0); 974 SDOperand N1 = N->getOperand(1); 975 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 976 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 977 MVT::ValueType VT = N0.getValueType(); 978 979 // If the flag result is dead, turn this into an ADD. 980 if (N->hasNUsesOfValue(0, 1)) 981 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 982 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 983 984 // canonicalize constant to RHS. 985 if (N0C && !N1C) { 986 SDOperand Ops[] = { N1, N0 }; 987 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 988 } 989 990 // fold (addc x, 0) -> x + no carry out 991 if (N1C && N1C->isNullValue()) 992 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 993 994 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 995 uint64_t LHSZero, LHSOne; 996 uint64_t RHSZero, RHSOne; 997 uint64_t Mask = MVT::getIntVTBitMask(VT); 998 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 999 if (LHSZero) { 1000 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1001 1002 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1003 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1004 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1005 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1006 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1007 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1008 } 1009 1010 return SDOperand(); 1011} 1012 1013SDOperand DAGCombiner::visitADDE(SDNode *N) { 1014 SDOperand N0 = N->getOperand(0); 1015 SDOperand N1 = N->getOperand(1); 1016 SDOperand CarryIn = N->getOperand(2); 1017 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1018 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1019 //MVT::ValueType VT = N0.getValueType(); 1020 1021 // canonicalize constant to RHS 1022 if (N0C && !N1C) { 1023 SDOperand Ops[] = { N1, N0, CarryIn }; 1024 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1025 } 1026 1027 // fold (adde x, y, false) -> (addc x, y) 1028 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1029 SDOperand Ops[] = { N1, N0 }; 1030 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1031 } 1032 1033 return SDOperand(); 1034} 1035 1036 1037 1038SDOperand DAGCombiner::visitSUB(SDNode *N) { 1039 SDOperand N0 = N->getOperand(0); 1040 SDOperand N1 = N->getOperand(1); 1041 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1042 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1043 MVT::ValueType VT = N0.getValueType(); 1044 1045 // fold vector ops 1046 if (MVT::isVector(VT)) { 1047 SDOperand FoldedVOp = SimplifyVBinOp(N); 1048 if (FoldedVOp.Val) return FoldedVOp; 1049 } 1050 1051 // fold (sub x, x) -> 0 1052 if (N0 == N1) 1053 return DAG.getConstant(0, N->getValueType(0)); 1054 // fold (sub c1, c2) -> c1-c2 1055 if (N0C && N1C) 1056 return DAG.getNode(ISD::SUB, VT, N0, N1); 1057 // fold (sub x, c) -> (add x, -c) 1058 if (N1C) 1059 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1060 // fold (A+B)-A -> B 1061 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1062 return N0.getOperand(1); 1063 // fold (A+B)-B -> A 1064 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1065 return N0.getOperand(0); 1066 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1067 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1068 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1069 if (Result.Val) return Result; 1070 } 1071 // If either operand of a sub is undef, the result is undef 1072 if (N0.getOpcode() == ISD::UNDEF) 1073 return N0; 1074 if (N1.getOpcode() == ISD::UNDEF) 1075 return N1; 1076 1077 return SDOperand(); 1078} 1079 1080SDOperand DAGCombiner::visitMUL(SDNode *N) { 1081 SDOperand N0 = N->getOperand(0); 1082 SDOperand N1 = N->getOperand(1); 1083 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1085 MVT::ValueType VT = N0.getValueType(); 1086 1087 // fold vector ops 1088 if (MVT::isVector(VT)) { 1089 SDOperand FoldedVOp = SimplifyVBinOp(N); 1090 if (FoldedVOp.Val) return FoldedVOp; 1091 } 1092 1093 // fold (mul x, undef) -> 0 1094 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1095 return DAG.getConstant(0, VT); 1096 // fold (mul c1, c2) -> c1*c2 1097 if (N0C && N1C) 1098 return DAG.getNode(ISD::MUL, VT, N0, N1); 1099 // canonicalize constant to RHS 1100 if (N0C && !N1C) 1101 return DAG.getNode(ISD::MUL, VT, N1, N0); 1102 // fold (mul x, 0) -> 0 1103 if (N1C && N1C->isNullValue()) 1104 return N1; 1105 // fold (mul x, -1) -> 0-x 1106 if (N1C && N1C->isAllOnesValue()) 1107 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1108 // fold (mul x, (1 << c)) -> x << c 1109 if (N1C && isPowerOf2_64(N1C->getValue())) 1110 return DAG.getNode(ISD::SHL, VT, N0, 1111 DAG.getConstant(Log2_64(N1C->getValue()), 1112 TLI.getShiftAmountTy())); 1113 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1114 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1115 // FIXME: If the input is something that is easily negated (e.g. a 1116 // single-use add), we should put the negate there. 1117 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1118 DAG.getNode(ISD::SHL, VT, N0, 1119 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1120 TLI.getShiftAmountTy()))); 1121 } 1122 1123 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1124 if (N1C && N0.getOpcode() == ISD::SHL && 1125 isa<ConstantSDNode>(N0.getOperand(1))) { 1126 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1127 AddToWorkList(C3.Val); 1128 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1129 } 1130 1131 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1132 // use. 1133 { 1134 SDOperand Sh(0,0), Y(0,0); 1135 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1136 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1137 N0.Val->hasOneUse()) { 1138 Sh = N0; Y = N1; 1139 } else if (N1.getOpcode() == ISD::SHL && 1140 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1141 Sh = N1; Y = N0; 1142 } 1143 if (Sh.Val) { 1144 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1145 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1146 } 1147 } 1148 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1149 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1150 isa<ConstantSDNode>(N0.getOperand(1))) { 1151 return DAG.getNode(ISD::ADD, VT, 1152 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1153 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1154 } 1155 1156 // reassociate mul 1157 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1158 if (RMUL.Val != 0) 1159 return RMUL; 1160 1161 return SDOperand(); 1162} 1163 1164SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1165 SDOperand N0 = N->getOperand(0); 1166 SDOperand N1 = N->getOperand(1); 1167 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1168 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1169 MVT::ValueType VT = N->getValueType(0); 1170 1171 // fold vector ops 1172 if (MVT::isVector(VT)) { 1173 SDOperand FoldedVOp = SimplifyVBinOp(N); 1174 if (FoldedVOp.Val) return FoldedVOp; 1175 } 1176 1177 // fold (sdiv c1, c2) -> c1/c2 1178 if (N0C && N1C && !N1C->isNullValue()) 1179 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1180 // fold (sdiv X, 1) -> X 1181 if (N1C && N1C->getSignExtended() == 1LL) 1182 return N0; 1183 // fold (sdiv X, -1) -> 0-X 1184 if (N1C && N1C->isAllOnesValue()) 1185 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1186 // If we know the sign bits of both operands are zero, strength reduce to a 1187 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1188 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1189 if (DAG.MaskedValueIsZero(N1, SignBit) && 1190 DAG.MaskedValueIsZero(N0, SignBit)) 1191 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1192 // fold (sdiv X, pow2) -> simple ops after legalize 1193 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1194 (isPowerOf2_64(N1C->getSignExtended()) || 1195 isPowerOf2_64(-N1C->getSignExtended()))) { 1196 // If dividing by powers of two is cheap, then don't perform the following 1197 // fold. 1198 if (TLI.isPow2DivCheap()) 1199 return SDOperand(); 1200 int64_t pow2 = N1C->getSignExtended(); 1201 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1202 unsigned lg2 = Log2_64(abs2); 1203 // Splat the sign bit into the register 1204 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1205 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1206 TLI.getShiftAmountTy())); 1207 AddToWorkList(SGN.Val); 1208 // Add (N0 < 0) ? abs2 - 1 : 0; 1209 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1210 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1211 TLI.getShiftAmountTy())); 1212 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1213 AddToWorkList(SRL.Val); 1214 AddToWorkList(ADD.Val); // Divide by pow2 1215 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1216 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1217 // If we're dividing by a positive value, we're done. Otherwise, we must 1218 // negate the result. 1219 if (pow2 > 0) 1220 return SRA; 1221 AddToWorkList(SRA.Val); 1222 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1223 } 1224 // if integer divide is expensive and we satisfy the requirements, emit an 1225 // alternate sequence. 1226 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1227 !TLI.isIntDivCheap()) { 1228 SDOperand Op = BuildSDIV(N); 1229 if (Op.Val) return Op; 1230 } 1231 1232 // undef / X -> 0 1233 if (N0.getOpcode() == ISD::UNDEF) 1234 return DAG.getConstant(0, VT); 1235 // X / undef -> undef 1236 if (N1.getOpcode() == ISD::UNDEF) 1237 return N1; 1238 1239 return SDOperand(); 1240} 1241 1242SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1243 SDOperand N0 = N->getOperand(0); 1244 SDOperand N1 = N->getOperand(1); 1245 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1246 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1247 MVT::ValueType VT = N->getValueType(0); 1248 1249 // fold vector ops 1250 if (MVT::isVector(VT)) { 1251 SDOperand FoldedVOp = SimplifyVBinOp(N); 1252 if (FoldedVOp.Val) return FoldedVOp; 1253 } 1254 1255 // fold (udiv c1, c2) -> c1/c2 1256 if (N0C && N1C && !N1C->isNullValue()) 1257 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1258 // fold (udiv x, (1 << c)) -> x >>u c 1259 if (N1C && isPowerOf2_64(N1C->getValue())) 1260 return DAG.getNode(ISD::SRL, VT, N0, 1261 DAG.getConstant(Log2_64(N1C->getValue()), 1262 TLI.getShiftAmountTy())); 1263 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1264 if (N1.getOpcode() == ISD::SHL) { 1265 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1266 if (isPowerOf2_64(SHC->getValue())) { 1267 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1268 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1269 DAG.getConstant(Log2_64(SHC->getValue()), 1270 ADDVT)); 1271 AddToWorkList(Add.Val); 1272 return DAG.getNode(ISD::SRL, VT, N0, Add); 1273 } 1274 } 1275 } 1276 // fold (udiv x, c) -> alternate 1277 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1278 SDOperand Op = BuildUDIV(N); 1279 if (Op.Val) return Op; 1280 } 1281 1282 // undef / X -> 0 1283 if (N0.getOpcode() == ISD::UNDEF) 1284 return DAG.getConstant(0, VT); 1285 // X / undef -> undef 1286 if (N1.getOpcode() == ISD::UNDEF) 1287 return N1; 1288 1289 return SDOperand(); 1290} 1291 1292SDOperand DAGCombiner::visitSREM(SDNode *N) { 1293 SDOperand N0 = N->getOperand(0); 1294 SDOperand N1 = N->getOperand(1); 1295 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1296 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1297 MVT::ValueType VT = N->getValueType(0); 1298 1299 // fold (srem c1, c2) -> c1%c2 1300 if (N0C && N1C && !N1C->isNullValue()) 1301 return DAG.getNode(ISD::SREM, VT, N0, N1); 1302 // If we know the sign bits of both operands are zero, strength reduce to a 1303 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1304 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1305 if (DAG.MaskedValueIsZero(N1, SignBit) && 1306 DAG.MaskedValueIsZero(N0, SignBit)) 1307 return DAG.getNode(ISD::UREM, VT, N0, N1); 1308 1309 // If X/C can be simplified by the division-by-constant logic, lower 1310 // X%C to the equivalent of X-X/C*C. 1311 if (N1C && !N1C->isNullValue()) { 1312 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1313 SDOperand OptimizedDiv = combine(Div.Val); 1314 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1315 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1316 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1317 AddToWorkList(Mul.Val); 1318 return Sub; 1319 } 1320 } 1321 1322 // undef % X -> 0 1323 if (N0.getOpcode() == ISD::UNDEF) 1324 return DAG.getConstant(0, VT); 1325 // X % undef -> undef 1326 if (N1.getOpcode() == ISD::UNDEF) 1327 return N1; 1328 1329 return SDOperand(); 1330} 1331 1332SDOperand DAGCombiner::visitUREM(SDNode *N) { 1333 SDOperand N0 = N->getOperand(0); 1334 SDOperand N1 = N->getOperand(1); 1335 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1336 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1337 MVT::ValueType VT = N->getValueType(0); 1338 1339 // fold (urem c1, c2) -> c1%c2 1340 if (N0C && N1C && !N1C->isNullValue()) 1341 return DAG.getNode(ISD::UREM, VT, N0, N1); 1342 // fold (urem x, pow2) -> (and x, pow2-1) 1343 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1344 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1345 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1346 if (N1.getOpcode() == ISD::SHL) { 1347 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1348 if (isPowerOf2_64(SHC->getValue())) { 1349 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1350 AddToWorkList(Add.Val); 1351 return DAG.getNode(ISD::AND, VT, N0, Add); 1352 } 1353 } 1354 } 1355 1356 // If X/C can be simplified by the division-by-constant logic, lower 1357 // X%C to the equivalent of X-X/C*C. 1358 if (N1C && !N1C->isNullValue()) { 1359 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1360 SDOperand OptimizedDiv = combine(Div.Val); 1361 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1362 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1363 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1364 AddToWorkList(Mul.Val); 1365 return Sub; 1366 } 1367 } 1368 1369 // undef % X -> 0 1370 if (N0.getOpcode() == ISD::UNDEF) 1371 return DAG.getConstant(0, VT); 1372 // X % undef -> undef 1373 if (N1.getOpcode() == ISD::UNDEF) 1374 return N1; 1375 1376 return SDOperand(); 1377} 1378 1379SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1380 SDOperand N0 = N->getOperand(0); 1381 SDOperand N1 = N->getOperand(1); 1382 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1383 MVT::ValueType VT = N->getValueType(0); 1384 1385 // fold (mulhs x, 0) -> 0 1386 if (N1C && N1C->isNullValue()) 1387 return N1; 1388 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1389 if (N1C && N1C->getValue() == 1) 1390 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1391 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1392 TLI.getShiftAmountTy())); 1393 // fold (mulhs x, undef) -> 0 1394 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1395 return DAG.getConstant(0, VT); 1396 1397 return SDOperand(); 1398} 1399 1400SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1401 SDOperand N0 = N->getOperand(0); 1402 SDOperand N1 = N->getOperand(1); 1403 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1404 MVT::ValueType VT = N->getValueType(0); 1405 1406 // fold (mulhu x, 0) -> 0 1407 if (N1C && N1C->isNullValue()) 1408 return N1; 1409 // fold (mulhu x, 1) -> 0 1410 if (N1C && N1C->getValue() == 1) 1411 return DAG.getConstant(0, N0.getValueType()); 1412 // fold (mulhu x, undef) -> 0 1413 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1414 return DAG.getConstant(0, VT); 1415 1416 return SDOperand(); 1417} 1418 1419/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1420/// compute two values. LoOp and HiOp give the opcodes for the two computations 1421/// that are being performed. Return true if a simplification was made. 1422/// 1423bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, 1424 unsigned LoOp, unsigned HiOp) { 1425 // If the high half is not needed, just compute the low half. 1426 bool HiExists = N->hasAnyUseOfValue(1); 1427 if (!HiExists && 1428 (!AfterLegalize || 1429 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1430 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), 1431 DAG.getNode(LoOp, N->getValueType(0), 1432 N->op_begin(), 1433 N->getNumOperands())); 1434 return true; 1435 } 1436 1437 // If the low half is not needed, just compute the high half. 1438 bool LoExists = N->hasAnyUseOfValue(0); 1439 if (!LoExists && 1440 (!AfterLegalize || 1441 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1442 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 1443 DAG.getNode(HiOp, N->getValueType(1), 1444 N->op_begin(), 1445 N->getNumOperands())); 1446 return true; 1447 } 1448 1449 // If both halves are used, return as it is. 1450 if (LoExists && HiExists) 1451 return false; 1452 1453 // If the two computed results can be simplified separately, separate them. 1454 bool RetVal = false; 1455 if (LoExists) { 1456 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1457 N->op_begin(), N->getNumOperands()); 1458 SDOperand LoOpt = combine(Lo.Val); 1459 if (LoOpt.Val && LoOpt != Lo && 1460 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) { 1461 RetVal = true; 1462 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt); 1463 } 1464 } 1465 1466 if (HiExists) { 1467 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1468 N->op_begin(), N->getNumOperands()); 1469 SDOperand HiOpt = combine(Hi.Val); 1470 if (HiOpt.Val && HiOpt != Hi && 1471 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) { 1472 RetVal = true; 1473 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt); 1474 } 1475 } 1476 1477 return RetVal; 1478} 1479 1480SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1481 1482 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS)) 1483 return SDOperand(); 1484 1485 return SDOperand(); 1486} 1487 1488SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1489 1490 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU)) 1491 return SDOperand(); 1492 1493 return SDOperand(); 1494} 1495 1496SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1497 1498 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM)) 1499 return SDOperand(); 1500 1501 return SDOperand(); 1502} 1503 1504SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1505 1506 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM)) 1507 return SDOperand(); 1508 1509 return SDOperand(); 1510} 1511 1512/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1513/// two operands of the same opcode, try to simplify it. 1514SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1515 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1516 MVT::ValueType VT = N0.getValueType(); 1517 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1518 1519 // For each of OP in AND/OR/XOR: 1520 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1521 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1522 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1523 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1524 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1525 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1526 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1527 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1528 N0.getOperand(0).getValueType(), 1529 N0.getOperand(0), N1.getOperand(0)); 1530 AddToWorkList(ORNode.Val); 1531 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1532 } 1533 1534 // For each of OP in SHL/SRL/SRA/AND... 1535 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1536 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1537 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1538 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1539 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1540 N0.getOperand(1) == N1.getOperand(1)) { 1541 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1542 N0.getOperand(0).getValueType(), 1543 N0.getOperand(0), N1.getOperand(0)); 1544 AddToWorkList(ORNode.Val); 1545 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1546 } 1547 1548 return SDOperand(); 1549} 1550 1551SDOperand DAGCombiner::visitAND(SDNode *N) { 1552 SDOperand N0 = N->getOperand(0); 1553 SDOperand N1 = N->getOperand(1); 1554 SDOperand LL, LR, RL, RR, CC0, CC1; 1555 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1556 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1557 MVT::ValueType VT = N1.getValueType(); 1558 1559 // fold vector ops 1560 if (MVT::isVector(VT)) { 1561 SDOperand FoldedVOp = SimplifyVBinOp(N); 1562 if (FoldedVOp.Val) return FoldedVOp; 1563 } 1564 1565 // fold (and x, undef) -> 0 1566 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1567 return DAG.getConstant(0, VT); 1568 // fold (and c1, c2) -> c1&c2 1569 if (N0C && N1C) 1570 return DAG.getNode(ISD::AND, VT, N0, N1); 1571 // canonicalize constant to RHS 1572 if (N0C && !N1C) 1573 return DAG.getNode(ISD::AND, VT, N1, N0); 1574 // fold (and x, -1) -> x 1575 if (N1C && N1C->isAllOnesValue()) 1576 return N0; 1577 // if (and x, c) is known to be zero, return 0 1578 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1579 return DAG.getConstant(0, VT); 1580 // reassociate and 1581 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1582 if (RAND.Val != 0) 1583 return RAND; 1584 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1585 if (N1C && N0.getOpcode() == ISD::OR) 1586 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1587 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1588 return N1; 1589 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1590 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1591 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1592 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1593 ~N1C->getValue() & InMask)) { 1594 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1595 N0.getOperand(0)); 1596 1597 // Replace uses of the AND with uses of the Zero extend node. 1598 CombineTo(N, Zext); 1599 1600 // We actually want to replace all uses of the any_extend with the 1601 // zero_extend, to avoid duplicating things. This will later cause this 1602 // AND to be folded. 1603 CombineTo(N0.Val, Zext); 1604 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1605 } 1606 } 1607 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1608 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1609 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1610 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1611 1612 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1613 MVT::isInteger(LL.getValueType())) { 1614 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1615 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1616 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1617 AddToWorkList(ORNode.Val); 1618 return DAG.getSetCC(VT, ORNode, LR, Op1); 1619 } 1620 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1621 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1622 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1623 AddToWorkList(ANDNode.Val); 1624 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1625 } 1626 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1627 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1628 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1629 AddToWorkList(ORNode.Val); 1630 return DAG.getSetCC(VT, ORNode, LR, Op1); 1631 } 1632 } 1633 // canonicalize equivalent to ll == rl 1634 if (LL == RR && LR == RL) { 1635 Op1 = ISD::getSetCCSwappedOperands(Op1); 1636 std::swap(RL, RR); 1637 } 1638 if (LL == RL && LR == RR) { 1639 bool isInteger = MVT::isInteger(LL.getValueType()); 1640 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1641 if (Result != ISD::SETCC_INVALID) 1642 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1643 } 1644 } 1645 1646 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1647 if (N0.getOpcode() == N1.getOpcode()) { 1648 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1649 if (Tmp.Val) return Tmp; 1650 } 1651 1652 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1653 // fold (and (sra)) -> (and (srl)) when possible. 1654 if (!MVT::isVector(VT) && 1655 SimplifyDemandedBits(SDOperand(N, 0))) 1656 return SDOperand(N, 0); 1657 // fold (zext_inreg (extload x)) -> (zextload x) 1658 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1659 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1660 MVT::ValueType EVT = LN0->getLoadedVT(); 1661 // If we zero all the possible extended bits, then we can turn this into 1662 // a zextload if we are running before legalize or the operation is legal. 1663 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1664 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1665 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1666 LN0->getBasePtr(), LN0->getSrcValue(), 1667 LN0->getSrcValueOffset(), EVT, 1668 LN0->isVolatile(), 1669 LN0->getAlignment()); 1670 AddToWorkList(N); 1671 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1672 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1673 } 1674 } 1675 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1676 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1677 N0.hasOneUse()) { 1678 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1679 MVT::ValueType EVT = LN0->getLoadedVT(); 1680 // If we zero all the possible extended bits, then we can turn this into 1681 // a zextload if we are running before legalize or the operation is legal. 1682 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1683 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1684 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1685 LN0->getBasePtr(), LN0->getSrcValue(), 1686 LN0->getSrcValueOffset(), EVT, 1687 LN0->isVolatile(), 1688 LN0->getAlignment()); 1689 AddToWorkList(N); 1690 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1691 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1692 } 1693 } 1694 1695 // fold (and (load x), 255) -> (zextload x, i8) 1696 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1697 if (N1C && N0.getOpcode() == ISD::LOAD) { 1698 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1699 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1700 LN0->getAddressingMode() == ISD::UNINDEXED && 1701 N0.hasOneUse()) { 1702 MVT::ValueType EVT, LoadedVT; 1703 if (N1C->getValue() == 255) 1704 EVT = MVT::i8; 1705 else if (N1C->getValue() == 65535) 1706 EVT = MVT::i16; 1707 else if (N1C->getValue() == ~0U) 1708 EVT = MVT::i32; 1709 else 1710 EVT = MVT::Other; 1711 1712 LoadedVT = LN0->getLoadedVT(); 1713 if (EVT != MVT::Other && LoadedVT > EVT && 1714 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1715 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1716 // For big endian targets, we need to add an offset to the pointer to 1717 // load the correct bytes. For little endian systems, we merely need to 1718 // read fewer bytes from the same pointer. 1719 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1720 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1721 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1722 unsigned Alignment = LN0->getAlignment(); 1723 SDOperand NewPtr = LN0->getBasePtr(); 1724 if (!TLI.isLittleEndian()) { 1725 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1726 DAG.getConstant(PtrOff, PtrType)); 1727 Alignment = MinAlign(Alignment, PtrOff); 1728 } 1729 AddToWorkList(NewPtr.Val); 1730 SDOperand Load = 1731 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1732 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1733 LN0->isVolatile(), Alignment); 1734 AddToWorkList(N); 1735 CombineTo(N0.Val, Load, Load.getValue(1)); 1736 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1737 } 1738 } 1739 } 1740 1741 return SDOperand(); 1742} 1743 1744SDOperand DAGCombiner::visitOR(SDNode *N) { 1745 SDOperand N0 = N->getOperand(0); 1746 SDOperand N1 = N->getOperand(1); 1747 SDOperand LL, LR, RL, RR, CC0, CC1; 1748 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1749 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1750 MVT::ValueType VT = N1.getValueType(); 1751 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1752 1753 // fold vector ops 1754 if (MVT::isVector(VT)) { 1755 SDOperand FoldedVOp = SimplifyVBinOp(N); 1756 if (FoldedVOp.Val) return FoldedVOp; 1757 } 1758 1759 // fold (or x, undef) -> -1 1760 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1761 return DAG.getConstant(~0ULL, VT); 1762 // fold (or c1, c2) -> c1|c2 1763 if (N0C && N1C) 1764 return DAG.getNode(ISD::OR, VT, N0, N1); 1765 // canonicalize constant to RHS 1766 if (N0C && !N1C) 1767 return DAG.getNode(ISD::OR, VT, N1, N0); 1768 // fold (or x, 0) -> x 1769 if (N1C && N1C->isNullValue()) 1770 return N0; 1771 // fold (or x, -1) -> -1 1772 if (N1C && N1C->isAllOnesValue()) 1773 return N1; 1774 // fold (or x, c) -> c iff (x & ~c) == 0 1775 if (N1C && 1776 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1777 return N1; 1778 // reassociate or 1779 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1780 if (ROR.Val != 0) 1781 return ROR; 1782 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1783 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1784 isa<ConstantSDNode>(N0.getOperand(1))) { 1785 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1786 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1787 N1), 1788 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1789 } 1790 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1791 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1792 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1793 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1794 1795 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1796 MVT::isInteger(LL.getValueType())) { 1797 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1798 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1799 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1800 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1801 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1802 AddToWorkList(ORNode.Val); 1803 return DAG.getSetCC(VT, ORNode, LR, Op1); 1804 } 1805 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1806 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1807 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1808 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1809 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1810 AddToWorkList(ANDNode.Val); 1811 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1812 } 1813 } 1814 // canonicalize equivalent to ll == rl 1815 if (LL == RR && LR == RL) { 1816 Op1 = ISD::getSetCCSwappedOperands(Op1); 1817 std::swap(RL, RR); 1818 } 1819 if (LL == RL && LR == RR) { 1820 bool isInteger = MVT::isInteger(LL.getValueType()); 1821 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1822 if (Result != ISD::SETCC_INVALID) 1823 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1824 } 1825 } 1826 1827 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1828 if (N0.getOpcode() == N1.getOpcode()) { 1829 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1830 if (Tmp.Val) return Tmp; 1831 } 1832 1833 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1834 if (N0.getOpcode() == ISD::AND && 1835 N1.getOpcode() == ISD::AND && 1836 N0.getOperand(1).getOpcode() == ISD::Constant && 1837 N1.getOperand(1).getOpcode() == ISD::Constant && 1838 // Don't increase # computations. 1839 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1840 // We can only do this xform if we know that bits from X that are set in C2 1841 // but not in C1 are already zero. Likewise for Y. 1842 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1843 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1844 1845 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1846 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1847 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1848 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1849 } 1850 } 1851 1852 1853 // See if this is some rotate idiom. 1854 if (SDNode *Rot = MatchRotate(N0, N1)) 1855 return SDOperand(Rot, 0); 1856 1857 return SDOperand(); 1858} 1859 1860 1861/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1862static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1863 if (Op.getOpcode() == ISD::AND) { 1864 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1865 Mask = Op.getOperand(1); 1866 Op = Op.getOperand(0); 1867 } else { 1868 return false; 1869 } 1870 } 1871 1872 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1873 Shift = Op; 1874 return true; 1875 } 1876 return false; 1877} 1878 1879 1880// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1881// idioms for rotate, and if the target supports rotation instructions, generate 1882// a rot[lr]. 1883SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1884 // Must be a legal type. Expanded an promoted things won't work with rotates. 1885 MVT::ValueType VT = LHS.getValueType(); 1886 if (!TLI.isTypeLegal(VT)) return 0; 1887 1888 // The target must have at least one rotate flavor. 1889 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1890 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1891 if (!HasROTL && !HasROTR) return 0; 1892 1893 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1894 SDOperand LHSShift; // The shift. 1895 SDOperand LHSMask; // AND value if any. 1896 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1897 return 0; // Not part of a rotate. 1898 1899 SDOperand RHSShift; // The shift. 1900 SDOperand RHSMask; // AND value if any. 1901 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1902 return 0; // Not part of a rotate. 1903 1904 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1905 return 0; // Not shifting the same value. 1906 1907 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1908 return 0; // Shifts must disagree. 1909 1910 // Canonicalize shl to left side in a shl/srl pair. 1911 if (RHSShift.getOpcode() == ISD::SHL) { 1912 std::swap(LHS, RHS); 1913 std::swap(LHSShift, RHSShift); 1914 std::swap(LHSMask , RHSMask ); 1915 } 1916 1917 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1918 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1919 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1920 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1921 1922 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1923 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1924 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1925 RHSShiftAmt.getOpcode() == ISD::Constant) { 1926 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1927 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1928 if ((LShVal + RShVal) != OpSizeInBits) 1929 return 0; 1930 1931 SDOperand Rot; 1932 if (HasROTL) 1933 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1934 else 1935 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1936 1937 // If there is an AND of either shifted operand, apply it to the result. 1938 if (LHSMask.Val || RHSMask.Val) { 1939 uint64_t Mask = MVT::getIntVTBitMask(VT); 1940 1941 if (LHSMask.Val) { 1942 uint64_t RHSBits = (1ULL << LShVal)-1; 1943 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1944 } 1945 if (RHSMask.Val) { 1946 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1947 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1948 } 1949 1950 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1951 } 1952 1953 return Rot.Val; 1954 } 1955 1956 // If there is a mask here, and we have a variable shift, we can't be sure 1957 // that we're masking out the right stuff. 1958 if (LHSMask.Val || RHSMask.Val) 1959 return 0; 1960 1961 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1962 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1963 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1964 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1965 if (ConstantSDNode *SUBC = 1966 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1967 if (SUBC->getValue() == OpSizeInBits) 1968 if (HasROTL) 1969 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1970 else 1971 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1972 } 1973 } 1974 1975 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1976 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1977 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1978 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1979 if (ConstantSDNode *SUBC = 1980 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1981 if (SUBC->getValue() == OpSizeInBits) 1982 if (HasROTL) 1983 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1984 else 1985 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1986 } 1987 } 1988 1989 // Look for sign/zext/any-extended cases: 1990 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1991 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1992 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1993 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1994 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1995 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1996 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1997 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1998 if (RExtOp0.getOpcode() == ISD::SUB && 1999 RExtOp0.getOperand(1) == LExtOp0) { 2000 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2001 // (rotr x, y) 2002 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2003 // (rotl x, (sub 32, y)) 2004 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2005 if (SUBC->getValue() == OpSizeInBits) { 2006 if (HasROTL) 2007 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2008 else 2009 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2010 } 2011 } 2012 } else if (LExtOp0.getOpcode() == ISD::SUB && 2013 RExtOp0 == LExtOp0.getOperand(1)) { 2014 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2015 // (rotl x, y) 2016 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2017 // (rotr x, (sub 32, y)) 2018 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2019 if (SUBC->getValue() == OpSizeInBits) { 2020 if (HasROTL) 2021 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2022 else 2023 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2024 } 2025 } 2026 } 2027 } 2028 2029 return 0; 2030} 2031 2032 2033SDOperand DAGCombiner::visitXOR(SDNode *N) { 2034 SDOperand N0 = N->getOperand(0); 2035 SDOperand N1 = N->getOperand(1); 2036 SDOperand LHS, RHS, CC; 2037 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2038 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2039 MVT::ValueType VT = N0.getValueType(); 2040 2041 // fold vector ops 2042 if (MVT::isVector(VT)) { 2043 SDOperand FoldedVOp = SimplifyVBinOp(N); 2044 if (FoldedVOp.Val) return FoldedVOp; 2045 } 2046 2047 // fold (xor x, undef) -> undef 2048 if (N0.getOpcode() == ISD::UNDEF) 2049 return N0; 2050 if (N1.getOpcode() == ISD::UNDEF) 2051 return N1; 2052 // fold (xor c1, c2) -> c1^c2 2053 if (N0C && N1C) 2054 return DAG.getNode(ISD::XOR, VT, N0, N1); 2055 // canonicalize constant to RHS 2056 if (N0C && !N1C) 2057 return DAG.getNode(ISD::XOR, VT, N1, N0); 2058 // fold (xor x, 0) -> x 2059 if (N1C && N1C->isNullValue()) 2060 return N0; 2061 // reassociate xor 2062 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2063 if (RXOR.Val != 0) 2064 return RXOR; 2065 // fold !(x cc y) -> (x !cc y) 2066 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2067 bool isInt = MVT::isInteger(LHS.getValueType()); 2068 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2069 isInt); 2070 if (N0.getOpcode() == ISD::SETCC) 2071 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2072 if (N0.getOpcode() == ISD::SELECT_CC) 2073 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2074 assert(0 && "Unhandled SetCC Equivalent!"); 2075 abort(); 2076 } 2077 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2078 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2079 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2080 SDOperand V = N0.getOperand(0); 2081 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2082 DAG.getConstant(1, V.getValueType())); 2083 AddToWorkList(V.Val); 2084 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2085 } 2086 2087 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2088 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2089 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2090 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2091 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2092 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2093 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2094 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2095 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2096 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2097 } 2098 } 2099 // fold !(x or y) -> (!x and !y) iff x or y are constants 2100 if (N1C && N1C->isAllOnesValue() && 2101 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2102 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2103 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2104 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2105 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2106 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2107 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2108 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2109 } 2110 } 2111 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2112 if (N1C && N0.getOpcode() == ISD::XOR) { 2113 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2114 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2115 if (N00C) 2116 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2117 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2118 if (N01C) 2119 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2120 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2121 } 2122 // fold (xor x, x) -> 0 2123 if (N0 == N1) { 2124 if (!MVT::isVector(VT)) { 2125 return DAG.getConstant(0, VT); 2126 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2127 // Produce a vector of zeros. 2128 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2129 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2130 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2131 } 2132 } 2133 2134 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2135 if (N0.getOpcode() == N1.getOpcode()) { 2136 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2137 if (Tmp.Val) return Tmp; 2138 } 2139 2140 // Simplify the expression using non-local knowledge. 2141 if (!MVT::isVector(VT) && 2142 SimplifyDemandedBits(SDOperand(N, 0))) 2143 return SDOperand(N, 0); 2144 2145 return SDOperand(); 2146} 2147 2148SDOperand DAGCombiner::visitSHL(SDNode *N) { 2149 SDOperand N0 = N->getOperand(0); 2150 SDOperand N1 = N->getOperand(1); 2151 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2152 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2153 MVT::ValueType VT = N0.getValueType(); 2154 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2155 2156 // fold (shl c1, c2) -> c1<<c2 2157 if (N0C && N1C) 2158 return DAG.getNode(ISD::SHL, VT, N0, N1); 2159 // fold (shl 0, x) -> 0 2160 if (N0C && N0C->isNullValue()) 2161 return N0; 2162 // fold (shl x, c >= size(x)) -> undef 2163 if (N1C && N1C->getValue() >= OpSizeInBits) 2164 return DAG.getNode(ISD::UNDEF, VT); 2165 // fold (shl x, 0) -> x 2166 if (N1C && N1C->isNullValue()) 2167 return N0; 2168 // if (shl x, c) is known to be zero, return 0 2169 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2170 return DAG.getConstant(0, VT); 2171 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2172 return SDOperand(N, 0); 2173 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2174 if (N1C && N0.getOpcode() == ISD::SHL && 2175 N0.getOperand(1).getOpcode() == ISD::Constant) { 2176 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2177 uint64_t c2 = N1C->getValue(); 2178 if (c1 + c2 > OpSizeInBits) 2179 return DAG.getConstant(0, VT); 2180 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2181 DAG.getConstant(c1 + c2, N1.getValueType())); 2182 } 2183 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2184 // (srl (and x, -1 << c1), c1-c2) 2185 if (N1C && N0.getOpcode() == ISD::SRL && 2186 N0.getOperand(1).getOpcode() == ISD::Constant) { 2187 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2188 uint64_t c2 = N1C->getValue(); 2189 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2190 DAG.getConstant(~0ULL << c1, VT)); 2191 if (c2 > c1) 2192 return DAG.getNode(ISD::SHL, VT, Mask, 2193 DAG.getConstant(c2-c1, N1.getValueType())); 2194 else 2195 return DAG.getNode(ISD::SRL, VT, Mask, 2196 DAG.getConstant(c1-c2, N1.getValueType())); 2197 } 2198 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2199 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2200 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2201 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2202 return SDOperand(); 2203} 2204 2205SDOperand DAGCombiner::visitSRA(SDNode *N) { 2206 SDOperand N0 = N->getOperand(0); 2207 SDOperand N1 = N->getOperand(1); 2208 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2209 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2210 MVT::ValueType VT = N0.getValueType(); 2211 2212 // fold (sra c1, c2) -> c1>>c2 2213 if (N0C && N1C) 2214 return DAG.getNode(ISD::SRA, VT, N0, N1); 2215 // fold (sra 0, x) -> 0 2216 if (N0C && N0C->isNullValue()) 2217 return N0; 2218 // fold (sra -1, x) -> -1 2219 if (N0C && N0C->isAllOnesValue()) 2220 return N0; 2221 // fold (sra x, c >= size(x)) -> undef 2222 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2223 return DAG.getNode(ISD::UNDEF, VT); 2224 // fold (sra x, 0) -> x 2225 if (N1C && N1C->isNullValue()) 2226 return N0; 2227 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2228 // sext_inreg. 2229 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2230 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2231 MVT::ValueType EVT; 2232 switch (LowBits) { 2233 default: EVT = MVT::Other; break; 2234 case 1: EVT = MVT::i1; break; 2235 case 8: EVT = MVT::i8; break; 2236 case 16: EVT = MVT::i16; break; 2237 case 32: EVT = MVT::i32; break; 2238 } 2239 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2240 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2241 DAG.getValueType(EVT)); 2242 } 2243 2244 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2245 if (N1C && N0.getOpcode() == ISD::SRA) { 2246 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2247 unsigned Sum = N1C->getValue() + C1->getValue(); 2248 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2249 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2250 DAG.getConstant(Sum, N1C->getValueType(0))); 2251 } 2252 } 2253 2254 // Simplify, based on bits shifted out of the LHS. 2255 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2256 return SDOperand(N, 0); 2257 2258 2259 // If the sign bit is known to be zero, switch this to a SRL. 2260 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2261 return DAG.getNode(ISD::SRL, VT, N0, N1); 2262 return SDOperand(); 2263} 2264 2265SDOperand DAGCombiner::visitSRL(SDNode *N) { 2266 SDOperand N0 = N->getOperand(0); 2267 SDOperand N1 = N->getOperand(1); 2268 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2269 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2270 MVT::ValueType VT = N0.getValueType(); 2271 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2272 2273 // fold (srl c1, c2) -> c1 >>u c2 2274 if (N0C && N1C) 2275 return DAG.getNode(ISD::SRL, VT, N0, N1); 2276 // fold (srl 0, x) -> 0 2277 if (N0C && N0C->isNullValue()) 2278 return N0; 2279 // fold (srl x, c >= size(x)) -> undef 2280 if (N1C && N1C->getValue() >= OpSizeInBits) 2281 return DAG.getNode(ISD::UNDEF, VT); 2282 // fold (srl x, 0) -> x 2283 if (N1C && N1C->isNullValue()) 2284 return N0; 2285 // if (srl x, c) is known to be zero, return 0 2286 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2287 return DAG.getConstant(0, VT); 2288 2289 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2290 if (N1C && N0.getOpcode() == ISD::SRL && 2291 N0.getOperand(1).getOpcode() == ISD::Constant) { 2292 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2293 uint64_t c2 = N1C->getValue(); 2294 if (c1 + c2 > OpSizeInBits) 2295 return DAG.getConstant(0, VT); 2296 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2297 DAG.getConstant(c1 + c2, N1.getValueType())); 2298 } 2299 2300 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2301 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2302 // Shifting in all undef bits? 2303 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2304 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2305 return DAG.getNode(ISD::UNDEF, VT); 2306 2307 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2308 AddToWorkList(SmallShift.Val); 2309 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2310 } 2311 2312 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2313 // bit, which is unmodified by sra. 2314 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2315 if (N0.getOpcode() == ISD::SRA) 2316 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2317 } 2318 2319 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2320 if (N1C && N0.getOpcode() == ISD::CTLZ && 2321 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2322 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2323 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2324 2325 // If any of the input bits are KnownOne, then the input couldn't be all 2326 // zeros, thus the result of the srl will always be zero. 2327 if (KnownOne) return DAG.getConstant(0, VT); 2328 2329 // If all of the bits input the to ctlz node are known to be zero, then 2330 // the result of the ctlz is "32" and the result of the shift is one. 2331 uint64_t UnknownBits = ~KnownZero & Mask; 2332 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2333 2334 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2335 if ((UnknownBits & (UnknownBits-1)) == 0) { 2336 // Okay, we know that only that the single bit specified by UnknownBits 2337 // could be set on input to the CTLZ node. If this bit is set, the SRL 2338 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2339 // to an SRL,XOR pair, which is likely to simplify more. 2340 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2341 SDOperand Op = N0.getOperand(0); 2342 if (ShAmt) { 2343 Op = DAG.getNode(ISD::SRL, VT, Op, 2344 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2345 AddToWorkList(Op.Val); 2346 } 2347 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2348 } 2349 } 2350 2351 // fold operands of srl based on knowledge that the low bits are not 2352 // demanded. 2353 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2354 return SDOperand(N, 0); 2355 2356 return SDOperand(); 2357} 2358 2359SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2360 SDOperand N0 = N->getOperand(0); 2361 MVT::ValueType VT = N->getValueType(0); 2362 2363 // fold (ctlz c1) -> c2 2364 if (isa<ConstantSDNode>(N0)) 2365 return DAG.getNode(ISD::CTLZ, VT, N0); 2366 return SDOperand(); 2367} 2368 2369SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2370 SDOperand N0 = N->getOperand(0); 2371 MVT::ValueType VT = N->getValueType(0); 2372 2373 // fold (cttz c1) -> c2 2374 if (isa<ConstantSDNode>(N0)) 2375 return DAG.getNode(ISD::CTTZ, VT, N0); 2376 return SDOperand(); 2377} 2378 2379SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2380 SDOperand N0 = N->getOperand(0); 2381 MVT::ValueType VT = N->getValueType(0); 2382 2383 // fold (ctpop c1) -> c2 2384 if (isa<ConstantSDNode>(N0)) 2385 return DAG.getNode(ISD::CTPOP, VT, N0); 2386 return SDOperand(); 2387} 2388 2389SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2390 SDOperand N0 = N->getOperand(0); 2391 SDOperand N1 = N->getOperand(1); 2392 SDOperand N2 = N->getOperand(2); 2393 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2394 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2395 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2396 MVT::ValueType VT = N->getValueType(0); 2397 MVT::ValueType VT0 = N0.getValueType(); 2398 2399 2400 // Some targets have SETCC types bigger than 1 bit, but do not set all the 2401 // bits to 1; identified by getSetCCResultContents. Watch out for these. 2402 2403 // fold select C, X, X -> X 2404 if (N1 == N2) 2405 return N1; 2406 // fold select true, X, Y -> X 2407 if (N0C && !N0C->isNullValue()) 2408 return N1; 2409 // fold select false, X, Y -> Y 2410 if (N0C && N0C->isNullValue()) 2411 return N2; 2412 // fold select C, 1, X -> C | X 2413 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2414 return DAG.getNode(ISD::OR, VT, N0, N2); 2415 // fold select C, 0, 1 -> ~C 2416 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2417 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2418 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2419 if (VT == VT0) 2420 return XORNode; 2421 AddToWorkList(XORNode.Val); 2422 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2423 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2424 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2425 } 2426 // fold select C, 0, X -> ~C & X 2427 if (VT == VT0 && N1C && N1C->isNullValue() && 2428 (N0.Val->getOpcode()!=ISD::SETCC || VT==MVT::i1 || 2429 TLI.getSetCCResultContents()== 2430 TargetLowering::ZeroOrNegativeOneSetCCResult)) { 2431 SDOperand XORNode; 2432 XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(~0UL, VT)); 2433 AddToWorkList(XORNode.Val); 2434 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2435 } 2436 // fold select C, X, 1 -> ~C | X 2437 if (VT == VT0 && N2C && N2C->getValue() == 1 && 2438 (N0.Val->getOpcode()!=ISD::SETCC || VT==MVT::i1 || 2439 TLI.getSetCCResultContents()== 2440 TargetLowering::ZeroOrNegativeOneSetCCResult)) { 2441 SDOperand XORNode; 2442 XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(~0UL, VT)); 2443 AddToWorkList(XORNode.Val); 2444 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2445 } 2446 // fold select C, X, 0 -> C & X 2447 // FIXME: this should check for C type == X type, not i1? 2448 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2449 return DAG.getNode(ISD::AND, VT, N0, N1); 2450 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2451 if (MVT::i1 == VT && N0 == N1) 2452 return DAG.getNode(ISD::OR, VT, N0, N2); 2453 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2454 if (MVT::i1 == VT && N0 == N2) 2455 return DAG.getNode(ISD::AND, VT, N0, N1); 2456 2457 // If we can fold this based on the true/false value, do so. 2458 if (SimplifySelectOps(N, N1, N2)) 2459 return SDOperand(N, 0); // Don't revisit N. 2460 2461 // fold selects based on a setcc into other things, such as min/max/abs 2462 if (N0.getOpcode() == ISD::SETCC) 2463 // FIXME: 2464 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2465 // having to say they don't support SELECT_CC on every type the DAG knows 2466 // about, since there is no way to mark an opcode illegal at all value types 2467 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2468 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2469 N1, N2, N0.getOperand(2)); 2470 else 2471 return SimplifySelect(N0, N1, N2); 2472 return SDOperand(); 2473} 2474 2475SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2476 SDOperand N0 = N->getOperand(0); 2477 SDOperand N1 = N->getOperand(1); 2478 SDOperand N2 = N->getOperand(2); 2479 SDOperand N3 = N->getOperand(3); 2480 SDOperand N4 = N->getOperand(4); 2481 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2482 2483 // fold select_cc lhs, rhs, x, x, cc -> x 2484 if (N2 == N3) 2485 return N2; 2486 2487 // Determine if the condition we're dealing with is constant 2488 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2489 if (SCC.Val) AddToWorkList(SCC.Val); 2490 2491 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2492 if (SCCC->getValue()) 2493 return N2; // cond always true -> true val 2494 else 2495 return N3; // cond always false -> false val 2496 } 2497 2498 // Fold to a simpler select_cc 2499 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2500 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2501 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2502 SCC.getOperand(2)); 2503 2504 // If we can fold this based on the true/false value, do so. 2505 if (SimplifySelectOps(N, N2, N3)) 2506 return SDOperand(N, 0); // Don't revisit N. 2507 2508 // fold select_cc into other things, such as min/max/abs 2509 return SimplifySelectCC(N0, N1, N2, N3, CC); 2510} 2511 2512SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2513 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2514 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2515} 2516 2517// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2518// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2519// transformation. Returns true if extension are possible and the above 2520// mentioned transformation is profitable. 2521static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2522 unsigned ExtOpc, 2523 SmallVector<SDNode*, 4> &ExtendNodes, 2524 TargetLowering &TLI) { 2525 bool HasCopyToRegUses = false; 2526 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2527 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2528 UI != UE; ++UI) { 2529 SDNode *User = *UI; 2530 if (User == N) 2531 continue; 2532 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2533 if (User->getOpcode() == ISD::SETCC) { 2534 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2535 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2536 // Sign bits will be lost after a zext. 2537 return false; 2538 bool Add = false; 2539 for (unsigned i = 0; i != 2; ++i) { 2540 SDOperand UseOp = User->getOperand(i); 2541 if (UseOp == N0) 2542 continue; 2543 if (!isa<ConstantSDNode>(UseOp)) 2544 return false; 2545 Add = true; 2546 } 2547 if (Add) 2548 ExtendNodes.push_back(User); 2549 } else { 2550 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2551 SDOperand UseOp = User->getOperand(i); 2552 if (UseOp == N0) { 2553 // If truncate from extended type to original load type is free 2554 // on this target, then it's ok to extend a CopyToReg. 2555 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2556 HasCopyToRegUses = true; 2557 else 2558 return false; 2559 } 2560 } 2561 } 2562 } 2563 2564 if (HasCopyToRegUses) { 2565 bool BothLiveOut = false; 2566 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2567 UI != UE; ++UI) { 2568 SDNode *User = *UI; 2569 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2570 SDOperand UseOp = User->getOperand(i); 2571 if (UseOp.Val == N && UseOp.ResNo == 0) { 2572 BothLiveOut = true; 2573 break; 2574 } 2575 } 2576 } 2577 if (BothLiveOut) 2578 // Both unextended and extended values are live out. There had better be 2579 // good a reason for the transformation. 2580 return ExtendNodes.size(); 2581 } 2582 return true; 2583} 2584 2585SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2586 SDOperand N0 = N->getOperand(0); 2587 MVT::ValueType VT = N->getValueType(0); 2588 2589 // fold (sext c1) -> c1 2590 if (isa<ConstantSDNode>(N0)) 2591 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2592 2593 // fold (sext (sext x)) -> (sext x) 2594 // fold (sext (aext x)) -> (sext x) 2595 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2596 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2597 2598 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2599 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2600 if (N0.getOpcode() == ISD::TRUNCATE) { 2601 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2602 if (NarrowLoad.Val) { 2603 if (NarrowLoad.Val != N0.Val) 2604 CombineTo(N0.Val, NarrowLoad); 2605 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2606 } 2607 } 2608 2609 // See if the value being truncated is already sign extended. If so, just 2610 // eliminate the trunc/sext pair. 2611 if (N0.getOpcode() == ISD::TRUNCATE) { 2612 SDOperand Op = N0.getOperand(0); 2613 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2614 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2615 unsigned DestBits = MVT::getSizeInBits(VT); 2616 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2617 2618 if (OpBits == DestBits) { 2619 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2620 // bits, it is already ready. 2621 if (NumSignBits > DestBits-MidBits) 2622 return Op; 2623 } else if (OpBits < DestBits) { 2624 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2625 // bits, just sext from i32. 2626 if (NumSignBits > OpBits-MidBits) 2627 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2628 } else { 2629 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2630 // bits, just truncate to i32. 2631 if (NumSignBits > OpBits-MidBits) 2632 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2633 } 2634 2635 // fold (sext (truncate x)) -> (sextinreg x). 2636 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2637 N0.getValueType())) { 2638 if (Op.getValueType() < VT) 2639 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2640 else if (Op.getValueType() > VT) 2641 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2642 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2643 DAG.getValueType(N0.getValueType())); 2644 } 2645 } 2646 2647 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2648 if (ISD::isNON_EXTLoad(N0.Val) && 2649 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2650 bool DoXform = true; 2651 SmallVector<SDNode*, 4> SetCCs; 2652 if (!N0.hasOneUse()) 2653 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2654 if (DoXform) { 2655 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2656 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2657 LN0->getBasePtr(), LN0->getSrcValue(), 2658 LN0->getSrcValueOffset(), 2659 N0.getValueType(), 2660 LN0->isVolatile(), 2661 LN0->getAlignment()); 2662 CombineTo(N, ExtLoad); 2663 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2664 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2665 // Extend SetCC uses if necessary. 2666 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2667 SDNode *SetCC = SetCCs[i]; 2668 SmallVector<SDOperand, 4> Ops; 2669 for (unsigned j = 0; j != 2; ++j) { 2670 SDOperand SOp = SetCC->getOperand(j); 2671 if (SOp == Trunc) 2672 Ops.push_back(ExtLoad); 2673 else 2674 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2675 } 2676 Ops.push_back(SetCC->getOperand(2)); 2677 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2678 &Ops[0], Ops.size())); 2679 } 2680 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2681 } 2682 } 2683 2684 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2685 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2686 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2687 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2688 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2689 MVT::ValueType EVT = LN0->getLoadedVT(); 2690 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2691 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2692 LN0->getBasePtr(), LN0->getSrcValue(), 2693 LN0->getSrcValueOffset(), EVT, 2694 LN0->isVolatile(), 2695 LN0->getAlignment()); 2696 CombineTo(N, ExtLoad); 2697 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2698 ExtLoad.getValue(1)); 2699 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2700 } 2701 } 2702 2703 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2704 if (N0.getOpcode() == ISD::SETCC) { 2705 SDOperand SCC = 2706 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2707 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2708 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2709 if (SCC.Val) return SCC; 2710 } 2711 2712 return SDOperand(); 2713} 2714 2715SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2716 SDOperand N0 = N->getOperand(0); 2717 MVT::ValueType VT = N->getValueType(0); 2718 2719 // fold (zext c1) -> c1 2720 if (isa<ConstantSDNode>(N0)) 2721 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2722 // fold (zext (zext x)) -> (zext x) 2723 // fold (zext (aext x)) -> (zext x) 2724 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2725 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2726 2727 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2728 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2729 if (N0.getOpcode() == ISD::TRUNCATE) { 2730 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2731 if (NarrowLoad.Val) { 2732 if (NarrowLoad.Val != N0.Val) 2733 CombineTo(N0.Val, NarrowLoad); 2734 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2735 } 2736 } 2737 2738 // fold (zext (truncate x)) -> (and x, mask) 2739 if (N0.getOpcode() == ISD::TRUNCATE && 2740 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2741 SDOperand Op = N0.getOperand(0); 2742 if (Op.getValueType() < VT) { 2743 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2744 } else if (Op.getValueType() > VT) { 2745 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2746 } 2747 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2748 } 2749 2750 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2751 if (N0.getOpcode() == ISD::AND && 2752 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2753 N0.getOperand(1).getOpcode() == ISD::Constant) { 2754 SDOperand X = N0.getOperand(0).getOperand(0); 2755 if (X.getValueType() < VT) { 2756 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2757 } else if (X.getValueType() > VT) { 2758 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2759 } 2760 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2761 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2762 } 2763 2764 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2765 if (ISD::isNON_EXTLoad(N0.Val) && 2766 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2767 bool DoXform = true; 2768 SmallVector<SDNode*, 4> SetCCs; 2769 if (!N0.hasOneUse()) 2770 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2771 if (DoXform) { 2772 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2773 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2774 LN0->getBasePtr(), LN0->getSrcValue(), 2775 LN0->getSrcValueOffset(), 2776 N0.getValueType(), 2777 LN0->isVolatile(), 2778 LN0->getAlignment()); 2779 CombineTo(N, ExtLoad); 2780 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2781 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2782 // Extend SetCC uses if necessary. 2783 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2784 SDNode *SetCC = SetCCs[i]; 2785 SmallVector<SDOperand, 4> Ops; 2786 for (unsigned j = 0; j != 2; ++j) { 2787 SDOperand SOp = SetCC->getOperand(j); 2788 if (SOp == Trunc) 2789 Ops.push_back(ExtLoad); 2790 else 2791 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2792 } 2793 Ops.push_back(SetCC->getOperand(2)); 2794 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2795 &Ops[0], Ops.size())); 2796 } 2797 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2798 } 2799 } 2800 2801 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2802 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2803 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2804 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2805 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2806 MVT::ValueType EVT = LN0->getLoadedVT(); 2807 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2808 LN0->getBasePtr(), LN0->getSrcValue(), 2809 LN0->getSrcValueOffset(), EVT, 2810 LN0->isVolatile(), 2811 LN0->getAlignment()); 2812 CombineTo(N, ExtLoad); 2813 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2814 ExtLoad.getValue(1)); 2815 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2816 } 2817 2818 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2819 if (N0.getOpcode() == ISD::SETCC) { 2820 SDOperand SCC = 2821 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2822 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2823 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2824 if (SCC.Val) return SCC; 2825 } 2826 2827 return SDOperand(); 2828} 2829 2830SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2831 SDOperand N0 = N->getOperand(0); 2832 MVT::ValueType VT = N->getValueType(0); 2833 2834 // fold (aext c1) -> c1 2835 if (isa<ConstantSDNode>(N0)) 2836 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2837 // fold (aext (aext x)) -> (aext x) 2838 // fold (aext (zext x)) -> (zext x) 2839 // fold (aext (sext x)) -> (sext x) 2840 if (N0.getOpcode() == ISD::ANY_EXTEND || 2841 N0.getOpcode() == ISD::ZERO_EXTEND || 2842 N0.getOpcode() == ISD::SIGN_EXTEND) 2843 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2844 2845 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2846 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2847 if (N0.getOpcode() == ISD::TRUNCATE) { 2848 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2849 if (NarrowLoad.Val) { 2850 if (NarrowLoad.Val != N0.Val) 2851 CombineTo(N0.Val, NarrowLoad); 2852 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2853 } 2854 } 2855 2856 // fold (aext (truncate x)) 2857 if (N0.getOpcode() == ISD::TRUNCATE) { 2858 SDOperand TruncOp = N0.getOperand(0); 2859 if (TruncOp.getValueType() == VT) 2860 return TruncOp; // x iff x size == zext size. 2861 if (TruncOp.getValueType() > VT) 2862 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2863 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2864 } 2865 2866 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2867 if (N0.getOpcode() == ISD::AND && 2868 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2869 N0.getOperand(1).getOpcode() == ISD::Constant) { 2870 SDOperand X = N0.getOperand(0).getOperand(0); 2871 if (X.getValueType() < VT) { 2872 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2873 } else if (X.getValueType() > VT) { 2874 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2875 } 2876 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2877 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2878 } 2879 2880 // fold (aext (load x)) -> (aext (truncate (extload x))) 2881 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2882 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2883 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2884 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2885 LN0->getBasePtr(), LN0->getSrcValue(), 2886 LN0->getSrcValueOffset(), 2887 N0.getValueType(), 2888 LN0->isVolatile(), 2889 LN0->getAlignment()); 2890 CombineTo(N, ExtLoad); 2891 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2892 ExtLoad.getValue(1)); 2893 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2894 } 2895 2896 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2897 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2898 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2899 if (N0.getOpcode() == ISD::LOAD && 2900 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2901 N0.hasOneUse()) { 2902 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2903 MVT::ValueType EVT = LN0->getLoadedVT(); 2904 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2905 LN0->getChain(), LN0->getBasePtr(), 2906 LN0->getSrcValue(), 2907 LN0->getSrcValueOffset(), EVT, 2908 LN0->isVolatile(), 2909 LN0->getAlignment()); 2910 CombineTo(N, ExtLoad); 2911 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2912 ExtLoad.getValue(1)); 2913 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2914 } 2915 2916 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2917 if (N0.getOpcode() == ISD::SETCC) { 2918 SDOperand SCC = 2919 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2920 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2921 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2922 if (SCC.Val) 2923 return SCC; 2924 } 2925 2926 return SDOperand(); 2927} 2928 2929/// GetDemandedBits - See if the specified operand can be simplified with the 2930/// knowledge that only the bits specified by Mask are used. If so, return the 2931/// simpler operand, otherwise return a null SDOperand. 2932SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) { 2933 switch (V.getOpcode()) { 2934 default: break; 2935 case ISD::OR: 2936 case ISD::XOR: 2937 // If the LHS or RHS don't contribute bits to the or, drop them. 2938 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 2939 return V.getOperand(1); 2940 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 2941 return V.getOperand(0); 2942 break; 2943 case ISD::SRL: 2944 // Only look at single-use SRLs. 2945 if (!V.Val->hasOneUse()) 2946 break; 2947 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 2948 // See if we can recursively simplify the LHS. 2949 unsigned Amt = RHSC->getValue(); 2950 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType()); 2951 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask); 2952 if (SimplifyLHS.Val) { 2953 return DAG.getNode(ISD::SRL, V.getValueType(), 2954 SimplifyLHS, V.getOperand(1)); 2955 } 2956 } 2957 } 2958 return SDOperand(); 2959} 2960 2961/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2962/// bits and then truncated to a narrower type and where N is a multiple 2963/// of number of bits of the narrower type, transform it to a narrower load 2964/// from address + N / num of bits of new type. If the result is to be 2965/// extended, also fold the extension to form a extending load. 2966SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2967 unsigned Opc = N->getOpcode(); 2968 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2969 SDOperand N0 = N->getOperand(0); 2970 MVT::ValueType VT = N->getValueType(0); 2971 MVT::ValueType EVT = N->getValueType(0); 2972 2973 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2974 // extended to VT. 2975 if (Opc == ISD::SIGN_EXTEND_INREG) { 2976 ExtType = ISD::SEXTLOAD; 2977 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2978 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2979 return SDOperand(); 2980 } 2981 2982 unsigned EVTBits = MVT::getSizeInBits(EVT); 2983 unsigned ShAmt = 0; 2984 bool CombineSRL = false; 2985 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2986 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2987 ShAmt = N01->getValue(); 2988 // Is the shift amount a multiple of size of VT? 2989 if ((ShAmt & (EVTBits-1)) == 0) { 2990 N0 = N0.getOperand(0); 2991 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2992 return SDOperand(); 2993 CombineSRL = true; 2994 } 2995 } 2996 } 2997 2998 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2999 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3000 // zero extended form: by shrinking the load, we lose track of the fact 3001 // that it is already zero extended. 3002 // FIXME: This should be reevaluated. 3003 VT != MVT::i1) { 3004 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3005 "Cannot truncate to larger type!"); 3006 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3007 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3008 // For big endian targets, we need to adjust the offset to the pointer to 3009 // load the correct bytes. 3010 if (!TLI.isLittleEndian()) { 3011 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3012 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3013 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3014 } 3015 uint64_t PtrOff = ShAmt / 8; 3016 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3017 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3018 DAG.getConstant(PtrOff, PtrType)); 3019 AddToWorkList(NewPtr.Val); 3020 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3021 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3022 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3023 LN0->isVolatile(), NewAlign) 3024 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3025 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3026 LN0->isVolatile(), NewAlign); 3027 AddToWorkList(N); 3028 if (CombineSRL) { 3029 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 3030 CombineTo(N->getOperand(0).Val, Load); 3031 } else 3032 CombineTo(N0.Val, Load, Load.getValue(1)); 3033 if (ShAmt) { 3034 if (Opc == ISD::SIGN_EXTEND_INREG) 3035 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3036 else 3037 return DAG.getNode(Opc, VT, Load); 3038 } 3039 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3040 } 3041 3042 return SDOperand(); 3043} 3044 3045 3046SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3047 SDOperand N0 = N->getOperand(0); 3048 SDOperand N1 = N->getOperand(1); 3049 MVT::ValueType VT = N->getValueType(0); 3050 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3051 unsigned EVTBits = MVT::getSizeInBits(EVT); 3052 3053 // fold (sext_in_reg c1) -> c1 3054 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3055 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3056 3057 // If the input is already sign extended, just drop the extension. 3058 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3059 return N0; 3060 3061 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3062 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3063 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3064 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3065 } 3066 3067 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3068 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 3069 return DAG.getZeroExtendInReg(N0, EVT); 3070 3071 // fold operands of sext_in_reg based on knowledge that the top bits are not 3072 // demanded. 3073 if (SimplifyDemandedBits(SDOperand(N, 0))) 3074 return SDOperand(N, 0); 3075 3076 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3077 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3078 SDOperand NarrowLoad = ReduceLoadWidth(N); 3079 if (NarrowLoad.Val) 3080 return NarrowLoad; 3081 3082 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3083 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3084 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3085 if (N0.getOpcode() == ISD::SRL) { 3086 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3087 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3088 // We can turn this into an SRA iff the input to the SRL is already sign 3089 // extended enough. 3090 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3091 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3092 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3093 } 3094 } 3095 3096 // fold (sext_inreg (extload x)) -> (sextload x) 3097 if (ISD::isEXTLoad(N0.Val) && 3098 ISD::isUNINDEXEDLoad(N0.Val) && 3099 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3100 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3101 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3102 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3103 LN0->getBasePtr(), LN0->getSrcValue(), 3104 LN0->getSrcValueOffset(), EVT, 3105 LN0->isVolatile(), 3106 LN0->getAlignment()); 3107 CombineTo(N, ExtLoad); 3108 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3109 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3110 } 3111 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3112 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3113 N0.hasOneUse() && 3114 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3115 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3116 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3117 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3118 LN0->getBasePtr(), LN0->getSrcValue(), 3119 LN0->getSrcValueOffset(), EVT, 3120 LN0->isVolatile(), 3121 LN0->getAlignment()); 3122 CombineTo(N, ExtLoad); 3123 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3124 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3125 } 3126 return SDOperand(); 3127} 3128 3129SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3130 SDOperand N0 = N->getOperand(0); 3131 MVT::ValueType VT = N->getValueType(0); 3132 3133 // noop truncate 3134 if (N0.getValueType() == N->getValueType(0)) 3135 return N0; 3136 // fold (truncate c1) -> c1 3137 if (isa<ConstantSDNode>(N0)) 3138 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3139 // fold (truncate (truncate x)) -> (truncate x) 3140 if (N0.getOpcode() == ISD::TRUNCATE) 3141 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3142 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3143 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3144 N0.getOpcode() == ISD::ANY_EXTEND) { 3145 if (N0.getOperand(0).getValueType() < VT) 3146 // if the source is smaller than the dest, we still need an extend 3147 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3148 else if (N0.getOperand(0).getValueType() > VT) 3149 // if the source is larger than the dest, than we just need the truncate 3150 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3151 else 3152 // if the source and dest are the same type, we can drop both the extend 3153 // and the truncate 3154 return N0.getOperand(0); 3155 } 3156 3157 // See if we can simplify the input to this truncate through knowledge that 3158 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3159 // -> trunc y 3160 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT)); 3161 if (Shorter.Val) 3162 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3163 3164 // fold (truncate (load x)) -> (smaller load x) 3165 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3166 return ReduceLoadWidth(N); 3167} 3168 3169SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3170 SDOperand N0 = N->getOperand(0); 3171 MVT::ValueType VT = N->getValueType(0); 3172 3173 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3174 // Only do this before legalize, since afterward the target may be depending 3175 // on the bitconvert. 3176 // First check to see if this is all constant. 3177 if (!AfterLegalize && 3178 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3179 MVT::isVector(VT)) { 3180 bool isSimple = true; 3181 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3182 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3183 N0.getOperand(i).getOpcode() != ISD::Constant && 3184 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3185 isSimple = false; 3186 break; 3187 } 3188 3189 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3190 assert(!MVT::isVector(DestEltVT) && 3191 "Element type of vector ValueType must not be vector!"); 3192 if (isSimple) { 3193 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3194 } 3195 } 3196 3197 // If the input is a constant, let getNode() fold it. 3198 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3199 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3200 if (Res.Val != N) return Res; 3201 } 3202 3203 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3204 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3205 3206 // fold (conv (load x)) -> (load (conv*)x) 3207 // If the resultant load doesn't need a higher alignment than the original! 3208 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3209 TLI.isOperationLegal(ISD::LOAD, VT)) { 3210 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3211 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3212 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3213 unsigned OrigAlign = LN0->getAlignment(); 3214 if (Align <= OrigAlign) { 3215 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3216 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3217 LN0->isVolatile(), Align); 3218 AddToWorkList(N); 3219 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3220 Load.getValue(1)); 3221 return Load; 3222 } 3223 } 3224 3225 return SDOperand(); 3226} 3227 3228/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3229/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3230/// destination element value type. 3231SDOperand DAGCombiner:: 3232ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3233 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3234 3235 // If this is already the right type, we're done. 3236 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3237 3238 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3239 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3240 3241 // If this is a conversion of N elements of one type to N elements of another 3242 // type, convert each element. This handles FP<->INT cases. 3243 if (SrcBitSize == DstBitSize) { 3244 SmallVector<SDOperand, 8> Ops; 3245 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3246 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3247 AddToWorkList(Ops.back().Val); 3248 } 3249 MVT::ValueType VT = 3250 MVT::getVectorType(DstEltVT, 3251 MVT::getVectorNumElements(BV->getValueType(0))); 3252 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3253 } 3254 3255 // Otherwise, we're growing or shrinking the elements. To avoid having to 3256 // handle annoying details of growing/shrinking FP values, we convert them to 3257 // int first. 3258 if (MVT::isFloatingPoint(SrcEltVT)) { 3259 // Convert the input float vector to a int vector where the elements are the 3260 // same sizes. 3261 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3262 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3263 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3264 SrcEltVT = IntVT; 3265 } 3266 3267 // Now we know the input is an integer vector. If the output is a FP type, 3268 // convert to integer first, then to FP of the right size. 3269 if (MVT::isFloatingPoint(DstEltVT)) { 3270 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3271 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3272 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3273 3274 // Next, convert to FP elements of the same size. 3275 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3276 } 3277 3278 // Okay, we know the src/dst types are both integers of differing types. 3279 // Handling growing first. 3280 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3281 if (SrcBitSize < DstBitSize) { 3282 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3283 3284 SmallVector<SDOperand, 8> Ops; 3285 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3286 i += NumInputsPerOutput) { 3287 bool isLE = TLI.isLittleEndian(); 3288 uint64_t NewBits = 0; 3289 bool EltIsUndef = true; 3290 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3291 // Shift the previously computed bits over. 3292 NewBits <<= SrcBitSize; 3293 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3294 if (Op.getOpcode() == ISD::UNDEF) continue; 3295 EltIsUndef = false; 3296 3297 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3298 } 3299 3300 if (EltIsUndef) 3301 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3302 else 3303 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3304 } 3305 3306 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3307 Ops.size()); 3308 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3309 } 3310 3311 // Finally, this must be the case where we are shrinking elements: each input 3312 // turns into multiple outputs. 3313 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3314 SmallVector<SDOperand, 8> Ops; 3315 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3316 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3317 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3318 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3319 continue; 3320 } 3321 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3322 3323 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3324 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3325 OpVal >>= DstBitSize; 3326 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3327 } 3328 3329 // For big endian targets, swap the order of the pieces of each element. 3330 if (!TLI.isLittleEndian()) 3331 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3332 } 3333 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3334 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3335} 3336 3337 3338 3339SDOperand DAGCombiner::visitFADD(SDNode *N) { 3340 SDOperand N0 = N->getOperand(0); 3341 SDOperand N1 = N->getOperand(1); 3342 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3343 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3344 MVT::ValueType VT = N->getValueType(0); 3345 3346 // fold vector ops 3347 if (MVT::isVector(VT)) { 3348 SDOperand FoldedVOp = SimplifyVBinOp(N); 3349 if (FoldedVOp.Val) return FoldedVOp; 3350 } 3351 3352 // fold (fadd c1, c2) -> c1+c2 3353 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3354 return DAG.getNode(ISD::FADD, VT, N0, N1); 3355 // canonicalize constant to RHS 3356 if (N0CFP && !N1CFP) 3357 return DAG.getNode(ISD::FADD, VT, N1, N0); 3358 // fold (A + (-B)) -> A-B 3359 if (isNegatibleForFree(N1) == 2) 3360 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3361 // fold ((-A) + B) -> B-A 3362 if (isNegatibleForFree(N0) == 2) 3363 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3364 3365 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3366 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3367 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3368 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3369 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3370 3371 return SDOperand(); 3372} 3373 3374SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3375 SDOperand N0 = N->getOperand(0); 3376 SDOperand N1 = N->getOperand(1); 3377 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3378 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3379 MVT::ValueType VT = N->getValueType(0); 3380 3381 // fold vector ops 3382 if (MVT::isVector(VT)) { 3383 SDOperand FoldedVOp = SimplifyVBinOp(N); 3384 if (FoldedVOp.Val) return FoldedVOp; 3385 } 3386 3387 // fold (fsub c1, c2) -> c1-c2 3388 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3389 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3390 // fold (0-B) -> -B 3391 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3392 if (isNegatibleForFree(N1)) 3393 return GetNegatedExpression(N1, DAG); 3394 return DAG.getNode(ISD::FNEG, VT, N1); 3395 } 3396 // fold (A-(-B)) -> A+B 3397 if (isNegatibleForFree(N1)) 3398 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3399 3400 return SDOperand(); 3401} 3402 3403SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3404 SDOperand N0 = N->getOperand(0); 3405 SDOperand N1 = N->getOperand(1); 3406 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3407 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3408 MVT::ValueType VT = N->getValueType(0); 3409 3410 // fold vector ops 3411 if (MVT::isVector(VT)) { 3412 SDOperand FoldedVOp = SimplifyVBinOp(N); 3413 if (FoldedVOp.Val) return FoldedVOp; 3414 } 3415 3416 // fold (fmul c1, c2) -> c1*c2 3417 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3418 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3419 // canonicalize constant to RHS 3420 if (N0CFP && !N1CFP) 3421 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3422 // fold (fmul X, 2.0) -> (fadd X, X) 3423 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3424 return DAG.getNode(ISD::FADD, VT, N0, N0); 3425 // fold (fmul X, -1.0) -> (fneg X) 3426 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3427 return DAG.getNode(ISD::FNEG, VT, N0); 3428 3429 // -X * -Y -> X*Y 3430 if (char LHSNeg = isNegatibleForFree(N0)) { 3431 if (char RHSNeg = isNegatibleForFree(N1)) { 3432 // Both can be negated for free, check to see if at least one is cheaper 3433 // negated. 3434 if (LHSNeg == 2 || RHSNeg == 2) 3435 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3436 GetNegatedExpression(N1, DAG)); 3437 } 3438 } 3439 3440 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3441 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3442 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3443 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3444 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3445 3446 return SDOperand(); 3447} 3448 3449SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3450 SDOperand N0 = N->getOperand(0); 3451 SDOperand N1 = N->getOperand(1); 3452 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3453 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3454 MVT::ValueType VT = N->getValueType(0); 3455 3456 // fold vector ops 3457 if (MVT::isVector(VT)) { 3458 SDOperand FoldedVOp = SimplifyVBinOp(N); 3459 if (FoldedVOp.Val) return FoldedVOp; 3460 } 3461 3462 // fold (fdiv c1, c2) -> c1/c2 3463 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3464 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3465 3466 3467 // -X / -Y -> X*Y 3468 if (char LHSNeg = isNegatibleForFree(N0)) { 3469 if (char RHSNeg = isNegatibleForFree(N1)) { 3470 // Both can be negated for free, check to see if at least one is cheaper 3471 // negated. 3472 if (LHSNeg == 2 || RHSNeg == 2) 3473 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3474 GetNegatedExpression(N1, DAG)); 3475 } 3476 } 3477 3478 return SDOperand(); 3479} 3480 3481SDOperand DAGCombiner::visitFREM(SDNode *N) { 3482 SDOperand N0 = N->getOperand(0); 3483 SDOperand N1 = N->getOperand(1); 3484 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3485 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3486 MVT::ValueType VT = N->getValueType(0); 3487 3488 // fold (frem c1, c2) -> fmod(c1,c2) 3489 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3490 return DAG.getNode(ISD::FREM, VT, N0, N1); 3491 3492 return SDOperand(); 3493} 3494 3495SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3496 SDOperand N0 = N->getOperand(0); 3497 SDOperand N1 = N->getOperand(1); 3498 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3499 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3500 MVT::ValueType VT = N->getValueType(0); 3501 3502 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3503 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3504 3505 if (N1CFP) { 3506 const APFloat& V = N1CFP->getValueAPF(); 3507 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3508 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3509 if (!V.isNegative()) 3510 return DAG.getNode(ISD::FABS, VT, N0); 3511 else 3512 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3513 } 3514 3515 // copysign(fabs(x), y) -> copysign(x, y) 3516 // copysign(fneg(x), y) -> copysign(x, y) 3517 // copysign(copysign(x,z), y) -> copysign(x, y) 3518 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3519 N0.getOpcode() == ISD::FCOPYSIGN) 3520 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3521 3522 // copysign(x, abs(y)) -> abs(x) 3523 if (N1.getOpcode() == ISD::FABS) 3524 return DAG.getNode(ISD::FABS, VT, N0); 3525 3526 // copysign(x, copysign(y,z)) -> copysign(x, z) 3527 if (N1.getOpcode() == ISD::FCOPYSIGN) 3528 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3529 3530 // copysign(x, fp_extend(y)) -> copysign(x, y) 3531 // copysign(x, fp_round(y)) -> copysign(x, y) 3532 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3533 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3534 3535 return SDOperand(); 3536} 3537 3538 3539 3540SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3541 SDOperand N0 = N->getOperand(0); 3542 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3543 MVT::ValueType VT = N->getValueType(0); 3544 3545 // fold (sint_to_fp c1) -> c1fp 3546 if (N0C && N0.getValueType() != MVT::ppcf128) 3547 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3548 return SDOperand(); 3549} 3550 3551SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3552 SDOperand N0 = N->getOperand(0); 3553 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3554 MVT::ValueType VT = N->getValueType(0); 3555 3556 // fold (uint_to_fp c1) -> c1fp 3557 if (N0C && N0.getValueType() != MVT::ppcf128) 3558 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3559 return SDOperand(); 3560} 3561 3562SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3563 SDOperand N0 = N->getOperand(0); 3564 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3565 MVT::ValueType VT = N->getValueType(0); 3566 3567 // fold (fp_to_sint c1fp) -> c1 3568 if (N0CFP) 3569 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3570 return SDOperand(); 3571} 3572 3573SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3574 SDOperand N0 = N->getOperand(0); 3575 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3576 MVT::ValueType VT = N->getValueType(0); 3577 3578 // fold (fp_to_uint c1fp) -> c1 3579 if (N0CFP && VT != MVT::ppcf128) 3580 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3581 return SDOperand(); 3582} 3583 3584SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3585 SDOperand N0 = N->getOperand(0); 3586 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3587 MVT::ValueType VT = N->getValueType(0); 3588 3589 // fold (fp_round c1fp) -> c1fp 3590 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3591 return DAG.getNode(ISD::FP_ROUND, VT, N0); 3592 3593 // fold (fp_round (fp_extend x)) -> x 3594 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3595 return N0.getOperand(0); 3596 3597 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3598 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3599 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 3600 AddToWorkList(Tmp.Val); 3601 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3602 } 3603 3604 return SDOperand(); 3605} 3606 3607SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3608 SDOperand N0 = N->getOperand(0); 3609 MVT::ValueType VT = N->getValueType(0); 3610 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3611 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3612 3613 // fold (fp_round_inreg c1fp) -> c1fp 3614 if (N0CFP) { 3615 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3616 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3617 } 3618 return SDOperand(); 3619} 3620 3621SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3622 SDOperand N0 = N->getOperand(0); 3623 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3624 MVT::ValueType VT = N->getValueType(0); 3625 3626 // fold (fp_extend c1fp) -> c1fp 3627 if (N0CFP && VT != MVT::ppcf128) 3628 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3629 3630 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 3631 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3632 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3633 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3634 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3635 LN0->getBasePtr(), LN0->getSrcValue(), 3636 LN0->getSrcValueOffset(), 3637 N0.getValueType(), 3638 LN0->isVolatile(), 3639 LN0->getAlignment()); 3640 CombineTo(N, ExtLoad); 3641 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 3642 ExtLoad.getValue(1)); 3643 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3644 } 3645 3646 3647 return SDOperand(); 3648} 3649 3650SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3651 SDOperand N0 = N->getOperand(0); 3652 3653 if (isNegatibleForFree(N0)) 3654 return GetNegatedExpression(N0, DAG); 3655 3656 return SDOperand(); 3657} 3658 3659SDOperand DAGCombiner::visitFABS(SDNode *N) { 3660 SDOperand N0 = N->getOperand(0); 3661 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3662 MVT::ValueType VT = N->getValueType(0); 3663 3664 // fold (fabs c1) -> fabs(c1) 3665 if (N0CFP && VT != MVT::ppcf128) 3666 return DAG.getNode(ISD::FABS, VT, N0); 3667 // fold (fabs (fabs x)) -> (fabs x) 3668 if (N0.getOpcode() == ISD::FABS) 3669 return N->getOperand(0); 3670 // fold (fabs (fneg x)) -> (fabs x) 3671 // fold (fabs (fcopysign x, y)) -> (fabs x) 3672 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3673 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3674 3675 return SDOperand(); 3676} 3677 3678SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3679 SDOperand Chain = N->getOperand(0); 3680 SDOperand N1 = N->getOperand(1); 3681 SDOperand N2 = N->getOperand(2); 3682 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3683 3684 // never taken branch, fold to chain 3685 if (N1C && N1C->isNullValue()) 3686 return Chain; 3687 // unconditional branch 3688 if (N1C && N1C->getValue() == 1) 3689 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3690 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3691 // on the target. 3692 if (N1.getOpcode() == ISD::SETCC && 3693 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3694 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3695 N1.getOperand(0), N1.getOperand(1), N2); 3696 } 3697 return SDOperand(); 3698} 3699 3700// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3701// 3702SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3703 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3704 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3705 3706 // Use SimplifySetCC to simplify SETCC's. 3707 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3708 if (Simp.Val) AddToWorkList(Simp.Val); 3709 3710 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3711 3712 // fold br_cc true, dest -> br dest (unconditional branch) 3713 if (SCCC && SCCC->getValue()) 3714 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3715 N->getOperand(4)); 3716 // fold br_cc false, dest -> unconditional fall through 3717 if (SCCC && SCCC->isNullValue()) 3718 return N->getOperand(0); 3719 3720 // fold to a simpler setcc 3721 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3722 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3723 Simp.getOperand(2), Simp.getOperand(0), 3724 Simp.getOperand(1), N->getOperand(4)); 3725 return SDOperand(); 3726} 3727 3728 3729/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3730/// pre-indexed load / store when the base pointer is a add or subtract 3731/// and it has other uses besides the load / store. After the 3732/// transformation, the new indexed load / store has effectively folded 3733/// the add / subtract in and all of its other uses are redirected to the 3734/// new load / store. 3735bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3736 if (!AfterLegalize) 3737 return false; 3738 3739 bool isLoad = true; 3740 SDOperand Ptr; 3741 MVT::ValueType VT; 3742 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3743 if (LD->getAddressingMode() != ISD::UNINDEXED) 3744 return false; 3745 VT = LD->getLoadedVT(); 3746 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3747 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3748 return false; 3749 Ptr = LD->getBasePtr(); 3750 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3751 if (ST->getAddressingMode() != ISD::UNINDEXED) 3752 return false; 3753 VT = ST->getStoredVT(); 3754 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3755 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3756 return false; 3757 Ptr = ST->getBasePtr(); 3758 isLoad = false; 3759 } else 3760 return false; 3761 3762 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3763 // out. There is no reason to make this a preinc/predec. 3764 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3765 Ptr.Val->hasOneUse()) 3766 return false; 3767 3768 // Ask the target to do addressing mode selection. 3769 SDOperand BasePtr; 3770 SDOperand Offset; 3771 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3772 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3773 return false; 3774 // Don't create a indexed load / store with zero offset. 3775 if (isa<ConstantSDNode>(Offset) && 3776 cast<ConstantSDNode>(Offset)->getValue() == 0) 3777 return false; 3778 3779 // Try turning it into a pre-indexed load / store except when: 3780 // 1) The new base ptr is a frame index. 3781 // 2) If N is a store and the new base ptr is either the same as or is a 3782 // predecessor of the value being stored. 3783 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3784 // that would create a cycle. 3785 // 4) All uses are load / store ops that use it as old base ptr. 3786 3787 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3788 // (plus the implicit offset) to a register to preinc anyway. 3789 if (isa<FrameIndexSDNode>(BasePtr)) 3790 return false; 3791 3792 // Check #2. 3793 if (!isLoad) { 3794 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3795 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3796 return false; 3797 } 3798 3799 // Now check for #3 and #4. 3800 bool RealUse = false; 3801 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3802 E = Ptr.Val->use_end(); I != E; ++I) { 3803 SDNode *Use = *I; 3804 if (Use == N) 3805 continue; 3806 if (Use->isPredecessor(N)) 3807 return false; 3808 3809 if (!((Use->getOpcode() == ISD::LOAD && 3810 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3811 (Use->getOpcode() == ISD::STORE) && 3812 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3813 RealUse = true; 3814 } 3815 if (!RealUse) 3816 return false; 3817 3818 SDOperand Result; 3819 if (isLoad) 3820 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3821 else 3822 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3823 ++PreIndexedNodes; 3824 ++NodesCombined; 3825 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 3826 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3827 DOUT << '\n'; 3828 std::vector<SDNode*> NowDead; 3829 if (isLoad) { 3830 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3831 &NowDead); 3832 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3833 &NowDead); 3834 } else { 3835 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3836 &NowDead); 3837 } 3838 3839 // Nodes can end up on the worklist more than once. Make sure we do 3840 // not process a node that has been replaced. 3841 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3842 removeFromWorkList(NowDead[i]); 3843 // Finally, since the node is now dead, remove it from the graph. 3844 DAG.DeleteNode(N); 3845 3846 // Replace the uses of Ptr with uses of the updated base value. 3847 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3848 &NowDead); 3849 removeFromWorkList(Ptr.Val); 3850 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3851 removeFromWorkList(NowDead[i]); 3852 DAG.DeleteNode(Ptr.Val); 3853 3854 return true; 3855} 3856 3857/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3858/// add / sub of the base pointer node into a post-indexed load / store. 3859/// The transformation folded the add / subtract into the new indexed 3860/// load / store effectively and all of its uses are redirected to the 3861/// new load / store. 3862bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3863 if (!AfterLegalize) 3864 return false; 3865 3866 bool isLoad = true; 3867 SDOperand Ptr; 3868 MVT::ValueType VT; 3869 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3870 if (LD->getAddressingMode() != ISD::UNINDEXED) 3871 return false; 3872 VT = LD->getLoadedVT(); 3873 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3874 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3875 return false; 3876 Ptr = LD->getBasePtr(); 3877 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3878 if (ST->getAddressingMode() != ISD::UNINDEXED) 3879 return false; 3880 VT = ST->getStoredVT(); 3881 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3882 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3883 return false; 3884 Ptr = ST->getBasePtr(); 3885 isLoad = false; 3886 } else 3887 return false; 3888 3889 if (Ptr.Val->hasOneUse()) 3890 return false; 3891 3892 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3893 E = Ptr.Val->use_end(); I != E; ++I) { 3894 SDNode *Op = *I; 3895 if (Op == N || 3896 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3897 continue; 3898 3899 SDOperand BasePtr; 3900 SDOperand Offset; 3901 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3902 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3903 if (Ptr == Offset) 3904 std::swap(BasePtr, Offset); 3905 if (Ptr != BasePtr) 3906 continue; 3907 // Don't create a indexed load / store with zero offset. 3908 if (isa<ConstantSDNode>(Offset) && 3909 cast<ConstantSDNode>(Offset)->getValue() == 0) 3910 continue; 3911 3912 // Try turning it into a post-indexed load / store except when 3913 // 1) All uses are load / store ops that use it as base ptr. 3914 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3915 // nor a successor of N. Otherwise, if Op is folded that would 3916 // create a cycle. 3917 3918 // Check for #1. 3919 bool TryNext = false; 3920 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3921 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3922 SDNode *Use = *II; 3923 if (Use == Ptr.Val) 3924 continue; 3925 3926 // If all the uses are load / store addresses, then don't do the 3927 // transformation. 3928 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3929 bool RealUse = false; 3930 for (SDNode::use_iterator III = Use->use_begin(), 3931 EEE = Use->use_end(); III != EEE; ++III) { 3932 SDNode *UseUse = *III; 3933 if (!((UseUse->getOpcode() == ISD::LOAD && 3934 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3935 (UseUse->getOpcode() == ISD::STORE) && 3936 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3937 RealUse = true; 3938 } 3939 3940 if (!RealUse) { 3941 TryNext = true; 3942 break; 3943 } 3944 } 3945 } 3946 if (TryNext) 3947 continue; 3948 3949 // Check for #2 3950 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3951 SDOperand Result = isLoad 3952 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3953 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3954 ++PostIndexedNodes; 3955 ++NodesCombined; 3956 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 3957 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3958 DOUT << '\n'; 3959 std::vector<SDNode*> NowDead; 3960 if (isLoad) { 3961 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3962 &NowDead); 3963 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3964 &NowDead); 3965 } else { 3966 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3967 &NowDead); 3968 } 3969 3970 // Nodes can end up on the worklist more than once. Make sure we do 3971 // not process a node that has been replaced. 3972 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3973 removeFromWorkList(NowDead[i]); 3974 // Finally, since the node is now dead, remove it from the graph. 3975 DAG.DeleteNode(N); 3976 3977 // Replace the uses of Use with uses of the updated base value. 3978 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3979 Result.getValue(isLoad ? 1 : 0), 3980 &NowDead); 3981 removeFromWorkList(Op); 3982 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3983 removeFromWorkList(NowDead[i]); 3984 DAG.DeleteNode(Op); 3985 3986 return true; 3987 } 3988 } 3989 } 3990 return false; 3991} 3992 3993 3994SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3995 LoadSDNode *LD = cast<LoadSDNode>(N); 3996 SDOperand Chain = LD->getChain(); 3997 SDOperand Ptr = LD->getBasePtr(); 3998 3999 // If load is not volatile and there are no uses of the loaded value (and 4000 // the updated indexed value in case of indexed loads), change uses of the 4001 // chain value into uses of the chain input (i.e. delete the dead load). 4002 if (!LD->isVolatile()) { 4003 if (N->getValueType(1) == MVT::Other) { 4004 // Unindexed loads. 4005 if (N->hasNUsesOfValue(0, 0)) 4006 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 4007 } else { 4008 // Indexed loads. 4009 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4010 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4011 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4012 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1)); 4013 SDOperand To[] = { Undef0, Undef1, Chain }; 4014 return CombineTo(N, To, 3); 4015 } 4016 } 4017 } 4018 4019 // If this load is directly stored, replace the load value with the stored 4020 // value. 4021 // TODO: Handle store large -> read small portion. 4022 // TODO: Handle TRUNCSTORE/LOADEXT 4023 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4024 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4025 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4026 if (PrevST->getBasePtr() == Ptr && 4027 PrevST->getValue().getValueType() == N->getValueType(0)) 4028 return CombineTo(N, Chain.getOperand(1), Chain); 4029 } 4030 } 4031 4032 if (CombinerAA) { 4033 // Walk up chain skipping non-aliasing memory nodes. 4034 SDOperand BetterChain = FindBetterChain(N, Chain); 4035 4036 // If there is a better chain. 4037 if (Chain != BetterChain) { 4038 SDOperand ReplLoad; 4039 4040 // Replace the chain to void dependency. 4041 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4042 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4043 LD->getSrcValue(), LD->getSrcValueOffset(), 4044 LD->isVolatile(), LD->getAlignment()); 4045 } else { 4046 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4047 LD->getValueType(0), 4048 BetterChain, Ptr, LD->getSrcValue(), 4049 LD->getSrcValueOffset(), 4050 LD->getLoadedVT(), 4051 LD->isVolatile(), 4052 LD->getAlignment()); 4053 } 4054 4055 // Create token factor to keep old chain connected. 4056 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4057 Chain, ReplLoad.getValue(1)); 4058 4059 // Replace uses with load result and token factor. Don't add users 4060 // to work list. 4061 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4062 } 4063 } 4064 4065 // Try transforming N to an indexed load. 4066 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4067 return SDOperand(N, 0); 4068 4069 return SDOperand(); 4070} 4071 4072SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4073 StoreSDNode *ST = cast<StoreSDNode>(N); 4074 SDOperand Chain = ST->getChain(); 4075 SDOperand Value = ST->getValue(); 4076 SDOperand Ptr = ST->getBasePtr(); 4077 4078 // If this is a store of a bit convert, store the input value if the 4079 // resultant store does not need a higher alignment than the original. 4080 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4081 ST->getAddressingMode() == ISD::UNINDEXED) { 4082 unsigned Align = ST->getAlignment(); 4083 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4084 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4085 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4086 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4087 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4088 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4089 } 4090 4091 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4092 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4093 if (Value.getOpcode() != ISD::TargetConstantFP) { 4094 SDOperand Tmp; 4095 switch (CFP->getValueType(0)) { 4096 default: assert(0 && "Unknown FP type"); 4097 case MVT::f80: // We don't do this for these yet. 4098 case MVT::f128: 4099 case MVT::ppcf128: 4100 break; 4101 case MVT::f32: 4102 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4103 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4104 convertToAPInt().getZExtValue(), MVT::i32); 4105 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4106 ST->getSrcValueOffset(), ST->isVolatile(), 4107 ST->getAlignment()); 4108 } 4109 break; 4110 case MVT::f64: 4111 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4112 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4113 getZExtValue(), MVT::i64); 4114 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4115 ST->getSrcValueOffset(), ST->isVolatile(), 4116 ST->getAlignment()); 4117 } else if (TLI.isTypeLegal(MVT::i32)) { 4118 // Many FP stores are not made apparent until after legalize, e.g. for 4119 // argument passing. Since this is so common, custom legalize the 4120 // 64-bit integer store into two 32-bit stores. 4121 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4122 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4123 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4124 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 4125 4126 int SVOffset = ST->getSrcValueOffset(); 4127 unsigned Alignment = ST->getAlignment(); 4128 bool isVolatile = ST->isVolatile(); 4129 4130 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4131 ST->getSrcValueOffset(), 4132 isVolatile, ST->getAlignment()); 4133 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4134 DAG.getConstant(4, Ptr.getValueType())); 4135 SVOffset += 4; 4136 Alignment = MinAlign(Alignment, 4U); 4137 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4138 SVOffset, isVolatile, Alignment); 4139 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4140 } 4141 break; 4142 } 4143 } 4144 } 4145 4146 if (CombinerAA) { 4147 // Walk up chain skipping non-aliasing memory nodes. 4148 SDOperand BetterChain = FindBetterChain(N, Chain); 4149 4150 // If there is a better chain. 4151 if (Chain != BetterChain) { 4152 // Replace the chain to avoid dependency. 4153 SDOperand ReplStore; 4154 if (ST->isTruncatingStore()) { 4155 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4156 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(), 4157 ST->isVolatile(), ST->getAlignment()); 4158 } else { 4159 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4160 ST->getSrcValue(), ST->getSrcValueOffset(), 4161 ST->isVolatile(), ST->getAlignment()); 4162 } 4163 4164 // Create token to keep both nodes around. 4165 SDOperand Token = 4166 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4167 4168 // Don't add users to work list. 4169 return CombineTo(N, Token, false); 4170 } 4171 } 4172 4173 // Try transforming N to an indexed store. 4174 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4175 return SDOperand(N, 0); 4176 4177 // FIXME: is there such a think as a truncating indexed store? 4178 if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED && 4179 MVT::isInteger(Value.getValueType())) { 4180 // See if we can simplify the input to this truncstore with knowledge that 4181 // only the low bits are being used. For example: 4182 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4183 SDOperand Shorter = 4184 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())); 4185 AddToWorkList(Value.Val); 4186 if (Shorter.Val) 4187 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4188 ST->getSrcValueOffset(), ST->getStoredVT(), 4189 ST->isVolatile(), ST->getAlignment()); 4190 4191 // Otherwise, see if we can simplify the operation with 4192 // SimplifyDemandedBits, which only works if the value has a single use. 4193 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()))) 4194 return SDOperand(N, 0); 4195 } 4196 4197 return SDOperand(); 4198} 4199 4200SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4201 SDOperand InVec = N->getOperand(0); 4202 SDOperand InVal = N->getOperand(1); 4203 SDOperand EltNo = N->getOperand(2); 4204 4205 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4206 // vector with the inserted element. 4207 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4208 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4209 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4210 if (Elt < Ops.size()) 4211 Ops[Elt] = InVal; 4212 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4213 &Ops[0], Ops.size()); 4214 } 4215 4216 return SDOperand(); 4217} 4218 4219SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4220 SDOperand InVec = N->getOperand(0); 4221 SDOperand EltNo = N->getOperand(1); 4222 4223 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4224 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4225 if (isa<ConstantSDNode>(EltNo)) { 4226 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4227 bool NewLoad = false; 4228 if (Elt == 0) { 4229 MVT::ValueType VT = InVec.getValueType(); 4230 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4231 MVT::ValueType LVT = EVT; 4232 unsigned NumElts = MVT::getVectorNumElements(VT); 4233 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4234 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4235 if (!MVT::isVector(BCVT) || 4236 NumElts != MVT::getVectorNumElements(BCVT)) 4237 return SDOperand(); 4238 InVec = InVec.getOperand(0); 4239 EVT = MVT::getVectorElementType(BCVT); 4240 NewLoad = true; 4241 } 4242 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4243 InVec.getOperand(0).getValueType() == EVT && 4244 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4245 InVec.getOperand(0).hasOneUse()) { 4246 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4247 unsigned Align = LN0->getAlignment(); 4248 if (NewLoad) { 4249 // Check the resultant load doesn't need a higher alignment than the 4250 // original load. 4251 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4252 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4253 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4254 return SDOperand(); 4255 Align = NewAlign; 4256 } 4257 4258 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4259 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4260 LN0->isVolatile(), Align); 4261 } 4262 } 4263 } 4264 return SDOperand(); 4265} 4266 4267 4268SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4269 unsigned NumInScalars = N->getNumOperands(); 4270 MVT::ValueType VT = N->getValueType(0); 4271 unsigned NumElts = MVT::getVectorNumElements(VT); 4272 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4273 4274 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4275 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4276 // at most two distinct vectors, turn this into a shuffle node. 4277 SDOperand VecIn1, VecIn2; 4278 for (unsigned i = 0; i != NumInScalars; ++i) { 4279 // Ignore undef inputs. 4280 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4281 4282 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4283 // constant index, bail out. 4284 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4285 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4286 VecIn1 = VecIn2 = SDOperand(0, 0); 4287 break; 4288 } 4289 4290 // If the input vector type disagrees with the result of the build_vector, 4291 // we can't make a shuffle. 4292 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4293 if (ExtractedFromVec.getValueType() != VT) { 4294 VecIn1 = VecIn2 = SDOperand(0, 0); 4295 break; 4296 } 4297 4298 // Otherwise, remember this. We allow up to two distinct input vectors. 4299 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4300 continue; 4301 4302 if (VecIn1.Val == 0) { 4303 VecIn1 = ExtractedFromVec; 4304 } else if (VecIn2.Val == 0) { 4305 VecIn2 = ExtractedFromVec; 4306 } else { 4307 // Too many inputs. 4308 VecIn1 = VecIn2 = SDOperand(0, 0); 4309 break; 4310 } 4311 } 4312 4313 // If everything is good, we can make a shuffle operation. 4314 if (VecIn1.Val) { 4315 SmallVector<SDOperand, 8> BuildVecIndices; 4316 for (unsigned i = 0; i != NumInScalars; ++i) { 4317 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4318 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4319 continue; 4320 } 4321 4322 SDOperand Extract = N->getOperand(i); 4323 4324 // If extracting from the first vector, just use the index directly. 4325 if (Extract.getOperand(0) == VecIn1) { 4326 BuildVecIndices.push_back(Extract.getOperand(1)); 4327 continue; 4328 } 4329 4330 // Otherwise, use InIdx + VecSize 4331 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4332 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 4333 TLI.getPointerTy())); 4334 } 4335 4336 // Add count and size info. 4337 MVT::ValueType BuildVecVT = 4338 MVT::getVectorType(TLI.getPointerTy(), NumElts); 4339 4340 // Return the new VECTOR_SHUFFLE node. 4341 SDOperand Ops[5]; 4342 Ops[0] = VecIn1; 4343 if (VecIn2.Val) { 4344 Ops[1] = VecIn2; 4345 } else { 4346 // Use an undef build_vector as input for the second operand. 4347 std::vector<SDOperand> UnOps(NumInScalars, 4348 DAG.getNode(ISD::UNDEF, 4349 EltType)); 4350 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4351 &UnOps[0], UnOps.size()); 4352 AddToWorkList(Ops[1].Val); 4353 } 4354 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4355 &BuildVecIndices[0], BuildVecIndices.size()); 4356 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4357 } 4358 4359 return SDOperand(); 4360} 4361 4362SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4363 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4364 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4365 // inputs come from at most two distinct vectors, turn this into a shuffle 4366 // node. 4367 4368 // If we only have one input vector, we don't need to do any concatenation. 4369 if (N->getNumOperands() == 1) { 4370 return N->getOperand(0); 4371 } 4372 4373 return SDOperand(); 4374} 4375 4376SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4377 SDOperand ShufMask = N->getOperand(2); 4378 unsigned NumElts = ShufMask.getNumOperands(); 4379 4380 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4381 bool isIdentity = true; 4382 for (unsigned i = 0; i != NumElts; ++i) { 4383 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4384 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4385 isIdentity = false; 4386 break; 4387 } 4388 } 4389 if (isIdentity) return N->getOperand(0); 4390 4391 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4392 isIdentity = true; 4393 for (unsigned i = 0; i != NumElts; ++i) { 4394 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4395 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4396 isIdentity = false; 4397 break; 4398 } 4399 } 4400 if (isIdentity) return N->getOperand(1); 4401 4402 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4403 // needed at all. 4404 bool isUnary = true; 4405 bool isSplat = true; 4406 int VecNum = -1; 4407 unsigned BaseIdx = 0; 4408 for (unsigned i = 0; i != NumElts; ++i) 4409 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4410 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4411 int V = (Idx < NumElts) ? 0 : 1; 4412 if (VecNum == -1) { 4413 VecNum = V; 4414 BaseIdx = Idx; 4415 } else { 4416 if (BaseIdx != Idx) 4417 isSplat = false; 4418 if (VecNum != V) { 4419 isUnary = false; 4420 break; 4421 } 4422 } 4423 } 4424 4425 SDOperand N0 = N->getOperand(0); 4426 SDOperand N1 = N->getOperand(1); 4427 // Normalize unary shuffle so the RHS is undef. 4428 if (isUnary && VecNum == 1) 4429 std::swap(N0, N1); 4430 4431 // If it is a splat, check if the argument vector is a build_vector with 4432 // all scalar elements the same. 4433 if (isSplat) { 4434 SDNode *V = N0.Val; 4435 4436 // If this is a bit convert that changes the element type of the vector but 4437 // not the number of vector elements, look through it. Be careful not to 4438 // look though conversions that change things like v4f32 to v2f64. 4439 if (V->getOpcode() == ISD::BIT_CONVERT) { 4440 SDOperand ConvInput = V->getOperand(0); 4441 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4442 V = ConvInput.Val; 4443 } 4444 4445 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4446 unsigned NumElems = V->getNumOperands(); 4447 if (NumElems > BaseIdx) { 4448 SDOperand Base; 4449 bool AllSame = true; 4450 for (unsigned i = 0; i != NumElems; ++i) { 4451 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4452 Base = V->getOperand(i); 4453 break; 4454 } 4455 } 4456 // Splat of <u, u, u, u>, return <u, u, u, u> 4457 if (!Base.Val) 4458 return N0; 4459 for (unsigned i = 0; i != NumElems; ++i) { 4460 if (V->getOperand(i) != Base) { 4461 AllSame = false; 4462 break; 4463 } 4464 } 4465 // Splat of <x, x, x, x>, return <x, x, x, x> 4466 if (AllSame) 4467 return N0; 4468 } 4469 } 4470 } 4471 4472 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4473 // into an undef. 4474 if (isUnary || N0 == N1) { 4475 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4476 // first operand. 4477 SmallVector<SDOperand, 8> MappedOps; 4478 for (unsigned i = 0; i != NumElts; ++i) { 4479 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4480 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4481 MappedOps.push_back(ShufMask.getOperand(i)); 4482 } else { 4483 unsigned NewIdx = 4484 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4485 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4486 } 4487 } 4488 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4489 &MappedOps[0], MappedOps.size()); 4490 AddToWorkList(ShufMask.Val); 4491 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4492 N0, 4493 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4494 ShufMask); 4495 } 4496 4497 return SDOperand(); 4498} 4499 4500/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4501/// an AND to a vector_shuffle with the destination vector and a zero vector. 4502/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4503/// vector_shuffle V, Zero, <0, 4, 2, 4> 4504SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4505 SDOperand LHS = N->getOperand(0); 4506 SDOperand RHS = N->getOperand(1); 4507 if (N->getOpcode() == ISD::AND) { 4508 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4509 RHS = RHS.getOperand(0); 4510 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4511 std::vector<SDOperand> IdxOps; 4512 unsigned NumOps = RHS.getNumOperands(); 4513 unsigned NumElts = NumOps; 4514 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4515 for (unsigned i = 0; i != NumElts; ++i) { 4516 SDOperand Elt = RHS.getOperand(i); 4517 if (!isa<ConstantSDNode>(Elt)) 4518 return SDOperand(); 4519 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4520 IdxOps.push_back(DAG.getConstant(i, EVT)); 4521 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4522 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4523 else 4524 return SDOperand(); 4525 } 4526 4527 // Let's see if the target supports this vector_shuffle. 4528 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4529 return SDOperand(); 4530 4531 // Return the new VECTOR_SHUFFLE node. 4532 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4533 std::vector<SDOperand> Ops; 4534 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4535 Ops.push_back(LHS); 4536 AddToWorkList(LHS.Val); 4537 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4538 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4539 &ZeroOps[0], ZeroOps.size())); 4540 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4541 &IdxOps[0], IdxOps.size())); 4542 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4543 &Ops[0], Ops.size()); 4544 if (VT != LHS.getValueType()) { 4545 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4546 } 4547 return Result; 4548 } 4549 } 4550 return SDOperand(); 4551} 4552 4553/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4554SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4555 // After legalize, the target may be depending on adds and other 4556 // binary ops to provide legal ways to construct constants or other 4557 // things. Simplifying them may result in a loss of legality. 4558 if (AfterLegalize) return SDOperand(); 4559 4560 MVT::ValueType VT = N->getValueType(0); 4561 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4562 4563 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4564 SDOperand LHS = N->getOperand(0); 4565 SDOperand RHS = N->getOperand(1); 4566 SDOperand Shuffle = XformToShuffleWithZero(N); 4567 if (Shuffle.Val) return Shuffle; 4568 4569 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4570 // this operation. 4571 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4572 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4573 SmallVector<SDOperand, 8> Ops; 4574 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4575 SDOperand LHSOp = LHS.getOperand(i); 4576 SDOperand RHSOp = RHS.getOperand(i); 4577 // If these two elements can't be folded, bail out. 4578 if ((LHSOp.getOpcode() != ISD::UNDEF && 4579 LHSOp.getOpcode() != ISD::Constant && 4580 LHSOp.getOpcode() != ISD::ConstantFP) || 4581 (RHSOp.getOpcode() != ISD::UNDEF && 4582 RHSOp.getOpcode() != ISD::Constant && 4583 RHSOp.getOpcode() != ISD::ConstantFP)) 4584 break; 4585 // Can't fold divide by zero. 4586 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4587 N->getOpcode() == ISD::FDIV) { 4588 if ((RHSOp.getOpcode() == ISD::Constant && 4589 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4590 (RHSOp.getOpcode() == ISD::ConstantFP && 4591 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4592 break; 4593 } 4594 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4595 AddToWorkList(Ops.back().Val); 4596 assert((Ops.back().getOpcode() == ISD::UNDEF || 4597 Ops.back().getOpcode() == ISD::Constant || 4598 Ops.back().getOpcode() == ISD::ConstantFP) && 4599 "Scalar binop didn't fold!"); 4600 } 4601 4602 if (Ops.size() == LHS.getNumOperands()) { 4603 MVT::ValueType VT = LHS.getValueType(); 4604 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4605 } 4606 } 4607 4608 return SDOperand(); 4609} 4610 4611SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4612 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4613 4614 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4615 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4616 // If we got a simplified select_cc node back from SimplifySelectCC, then 4617 // break it down into a new SETCC node, and a new SELECT node, and then return 4618 // the SELECT node, since we were called with a SELECT node. 4619 if (SCC.Val) { 4620 // Check to see if we got a select_cc back (to turn into setcc/select). 4621 // Otherwise, just return whatever node we got back, like fabs. 4622 if (SCC.getOpcode() == ISD::SELECT_CC) { 4623 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4624 SCC.getOperand(0), SCC.getOperand(1), 4625 SCC.getOperand(4)); 4626 AddToWorkList(SETCC.Val); 4627 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4628 SCC.getOperand(3), SETCC); 4629 } 4630 return SCC; 4631 } 4632 return SDOperand(); 4633} 4634 4635/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4636/// are the two values being selected between, see if we can simplify the 4637/// select. Callers of this should assume that TheSelect is deleted if this 4638/// returns true. As such, they should return the appropriate thing (e.g. the 4639/// node) back to the top-level of the DAG combiner loop to avoid it being 4640/// looked at. 4641/// 4642bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4643 SDOperand RHS) { 4644 4645 // If this is a select from two identical things, try to pull the operation 4646 // through the select. 4647 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4648 // If this is a load and the token chain is identical, replace the select 4649 // of two loads with a load through a select of the address to load from. 4650 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4651 // constants have been dropped into the constant pool. 4652 if (LHS.getOpcode() == ISD::LOAD && 4653 // Token chains must be identical. 4654 LHS.getOperand(0) == RHS.getOperand(0)) { 4655 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4656 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4657 4658 // If this is an EXTLOAD, the VT's must match. 4659 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4660 // FIXME: this conflates two src values, discarding one. This is not 4661 // the right thing to do, but nothing uses srcvalues now. When they do, 4662 // turn SrcValue into a list of locations. 4663 SDOperand Addr; 4664 if (TheSelect->getOpcode() == ISD::SELECT) { 4665 // Check that the condition doesn't reach either load. If so, folding 4666 // this will induce a cycle into the DAG. 4667 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4668 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4669 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4670 TheSelect->getOperand(0), LLD->getBasePtr(), 4671 RLD->getBasePtr()); 4672 } 4673 } else { 4674 // Check that the condition doesn't reach either load. If so, folding 4675 // this will induce a cycle into the DAG. 4676 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4677 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4678 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4679 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4680 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4681 TheSelect->getOperand(0), 4682 TheSelect->getOperand(1), 4683 LLD->getBasePtr(), RLD->getBasePtr(), 4684 TheSelect->getOperand(4)); 4685 } 4686 } 4687 4688 if (Addr.Val) { 4689 SDOperand Load; 4690 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4691 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4692 Addr,LLD->getSrcValue(), 4693 LLD->getSrcValueOffset(), 4694 LLD->isVolatile(), 4695 LLD->getAlignment()); 4696 else { 4697 Load = DAG.getExtLoad(LLD->getExtensionType(), 4698 TheSelect->getValueType(0), 4699 LLD->getChain(), Addr, LLD->getSrcValue(), 4700 LLD->getSrcValueOffset(), 4701 LLD->getLoadedVT(), 4702 LLD->isVolatile(), 4703 LLD->getAlignment()); 4704 } 4705 // Users of the select now use the result of the load. 4706 CombineTo(TheSelect, Load); 4707 4708 // Users of the old loads now use the new load's chain. We know the 4709 // old-load value is dead now. 4710 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4711 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4712 return true; 4713 } 4714 } 4715 } 4716 } 4717 4718 return false; 4719} 4720 4721SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4722 SDOperand N2, SDOperand N3, 4723 ISD::CondCode CC, bool NotExtCompare) { 4724 4725 MVT::ValueType VT = N2.getValueType(); 4726 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4727 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4728 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4729 4730 // Determine if the condition we're dealing with is constant 4731 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4732 if (SCC.Val) AddToWorkList(SCC.Val); 4733 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4734 4735 // fold select_cc true, x, y -> x 4736 if (SCCC && SCCC->getValue()) 4737 return N2; 4738 // fold select_cc false, x, y -> y 4739 if (SCCC && SCCC->getValue() == 0) 4740 return N3; 4741 4742 // Check to see if we can simplify the select into an fabs node 4743 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4744 // Allow either -0.0 or 0.0 4745 if (CFP->getValueAPF().isZero()) { 4746 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4747 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4748 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4749 N2 == N3.getOperand(0)) 4750 return DAG.getNode(ISD::FABS, VT, N0); 4751 4752 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4753 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4754 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4755 N2.getOperand(0) == N3) 4756 return DAG.getNode(ISD::FABS, VT, N3); 4757 } 4758 } 4759 4760 // Check to see if we can perform the "gzip trick", transforming 4761 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4762 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4763 MVT::isInteger(N0.getValueType()) && 4764 MVT::isInteger(N2.getValueType()) && 4765 (N1C->isNullValue() || // (a < 0) ? b : 0 4766 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4767 MVT::ValueType XType = N0.getValueType(); 4768 MVT::ValueType AType = N2.getValueType(); 4769 if (XType >= AType) { 4770 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4771 // single-bit constant. 4772 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4773 unsigned ShCtV = Log2_64(N2C->getValue()); 4774 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4775 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4776 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4777 AddToWorkList(Shift.Val); 4778 if (XType > AType) { 4779 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4780 AddToWorkList(Shift.Val); 4781 } 4782 return DAG.getNode(ISD::AND, AType, Shift, N2); 4783 } 4784 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4785 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4786 TLI.getShiftAmountTy())); 4787 AddToWorkList(Shift.Val); 4788 if (XType > AType) { 4789 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4790 AddToWorkList(Shift.Val); 4791 } 4792 return DAG.getNode(ISD::AND, AType, Shift, N2); 4793 } 4794 } 4795 4796 // fold select C, 16, 0 -> shl C, 4 4797 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4798 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4799 4800 // If the caller doesn't want us to simplify this into a zext of a compare, 4801 // don't do it. 4802 if (NotExtCompare && N2C->getValue() == 1) 4803 return SDOperand(); 4804 4805 // Get a SetCC of the condition 4806 // FIXME: Should probably make sure that setcc is legal if we ever have a 4807 // target where it isn't. 4808 SDOperand Temp, SCC; 4809 // cast from setcc result type to select result type 4810 if (AfterLegalize) { 4811 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4812 if (N2.getValueType() < SCC.getValueType()) 4813 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4814 else 4815 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4816 } else { 4817 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4818 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4819 } 4820 AddToWorkList(SCC.Val); 4821 AddToWorkList(Temp.Val); 4822 4823 if (N2C->getValue() == 1) 4824 return Temp; 4825 // shl setcc result by log2 n2c 4826 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4827 DAG.getConstant(Log2_64(N2C->getValue()), 4828 TLI.getShiftAmountTy())); 4829 } 4830 4831 // Check to see if this is the equivalent of setcc 4832 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4833 // otherwise, go ahead with the folds. 4834 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4835 MVT::ValueType XType = N0.getValueType(); 4836 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4837 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4838 if (Res.getValueType() != VT) 4839 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4840 return Res; 4841 } 4842 4843 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4844 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4845 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4846 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4847 return DAG.getNode(ISD::SRL, XType, Ctlz, 4848 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4849 TLI.getShiftAmountTy())); 4850 } 4851 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4852 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4853 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4854 N0); 4855 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4856 DAG.getConstant(~0ULL, XType)); 4857 return DAG.getNode(ISD::SRL, XType, 4858 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4859 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4860 TLI.getShiftAmountTy())); 4861 } 4862 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4863 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4864 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4865 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4866 TLI.getShiftAmountTy())); 4867 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4868 } 4869 } 4870 4871 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4872 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4873 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4874 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4875 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4876 MVT::ValueType XType = N0.getValueType(); 4877 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4878 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4879 TLI.getShiftAmountTy())); 4880 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4881 AddToWorkList(Shift.Val); 4882 AddToWorkList(Add.Val); 4883 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4884 } 4885 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4886 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4887 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4888 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4889 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4890 MVT::ValueType XType = N0.getValueType(); 4891 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4892 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4893 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4894 TLI.getShiftAmountTy())); 4895 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4896 AddToWorkList(Shift.Val); 4897 AddToWorkList(Add.Val); 4898 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4899 } 4900 } 4901 } 4902 4903 return SDOperand(); 4904} 4905 4906/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4907SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4908 SDOperand N1, ISD::CondCode Cond, 4909 bool foldBooleans) { 4910 TargetLowering::DAGCombinerInfo 4911 DagCombineInfo(DAG, !AfterLegalize, false, this); 4912 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4913} 4914 4915/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4916/// return a DAG expression to select that will generate the same value by 4917/// multiplying by a magic number. See: 4918/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4919SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4920 std::vector<SDNode*> Built; 4921 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4922 4923 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4924 ii != ee; ++ii) 4925 AddToWorkList(*ii); 4926 return S; 4927} 4928 4929/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4930/// return a DAG expression to select that will generate the same value by 4931/// multiplying by a magic number. See: 4932/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4933SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4934 std::vector<SDNode*> Built; 4935 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4936 4937 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4938 ii != ee; ++ii) 4939 AddToWorkList(*ii); 4940 return S; 4941} 4942 4943/// FindBaseOffset - Return true if base is known not to alias with anything 4944/// but itself. Provides base object and offset as results. 4945static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4946 // Assume it is a primitive operation. 4947 Base = Ptr; Offset = 0; 4948 4949 // If it's an adding a simple constant then integrate the offset. 4950 if (Base.getOpcode() == ISD::ADD) { 4951 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4952 Base = Base.getOperand(0); 4953 Offset += C->getValue(); 4954 } 4955 } 4956 4957 // If it's any of the following then it can't alias with anything but itself. 4958 return isa<FrameIndexSDNode>(Base) || 4959 isa<ConstantPoolSDNode>(Base) || 4960 isa<GlobalAddressSDNode>(Base); 4961} 4962 4963/// isAlias - Return true if there is any possibility that the two addresses 4964/// overlap. 4965bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4966 const Value *SrcValue1, int SrcValueOffset1, 4967 SDOperand Ptr2, int64_t Size2, 4968 const Value *SrcValue2, int SrcValueOffset2) 4969{ 4970 // If they are the same then they must be aliases. 4971 if (Ptr1 == Ptr2) return true; 4972 4973 // Gather base node and offset information. 4974 SDOperand Base1, Base2; 4975 int64_t Offset1, Offset2; 4976 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4977 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4978 4979 // If they have a same base address then... 4980 if (Base1 == Base2) { 4981 // Check to see if the addresses overlap. 4982 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4983 } 4984 4985 // If we know both bases then they can't alias. 4986 if (KnownBase1 && KnownBase2) return false; 4987 4988 if (CombinerGlobalAA) { 4989 // Use alias analysis information. 4990 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 4991 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 4992 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 4993 AliasAnalysis::AliasResult AAResult = 4994 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4995 if (AAResult == AliasAnalysis::NoAlias) 4996 return false; 4997 } 4998 4999 // Otherwise we have to assume they alias. 5000 return true; 5001} 5002 5003/// FindAliasInfo - Extracts the relevant alias information from the memory 5004/// node. Returns true if the operand was a load. 5005bool DAGCombiner::FindAliasInfo(SDNode *N, 5006 SDOperand &Ptr, int64_t &Size, 5007 const Value *&SrcValue, int &SrcValueOffset) { 5008 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5009 Ptr = LD->getBasePtr(); 5010 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 5011 SrcValue = LD->getSrcValue(); 5012 SrcValueOffset = LD->getSrcValueOffset(); 5013 return true; 5014 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5015 Ptr = ST->getBasePtr(); 5016 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 5017 SrcValue = ST->getSrcValue(); 5018 SrcValueOffset = ST->getSrcValueOffset(); 5019 } else { 5020 assert(0 && "FindAliasInfo expected a memory operand"); 5021 } 5022 5023 return false; 5024} 5025 5026/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5027/// looking for aliasing nodes and adding them to the Aliases vector. 5028void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5029 SmallVector<SDOperand, 8> &Aliases) { 5030 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5031 std::set<SDNode *> Visited; // Visited node set. 5032 5033 // Get alias information for node. 5034 SDOperand Ptr; 5035 int64_t Size; 5036 const Value *SrcValue; 5037 int SrcValueOffset; 5038 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5039 5040 // Starting off. 5041 Chains.push_back(OriginalChain); 5042 5043 // Look at each chain and determine if it is an alias. If so, add it to the 5044 // aliases list. If not, then continue up the chain looking for the next 5045 // candidate. 5046 while (!Chains.empty()) { 5047 SDOperand Chain = Chains.back(); 5048 Chains.pop_back(); 5049 5050 // Don't bother if we've been before. 5051 if (Visited.find(Chain.Val) != Visited.end()) continue; 5052 Visited.insert(Chain.Val); 5053 5054 switch (Chain.getOpcode()) { 5055 case ISD::EntryToken: 5056 // Entry token is ideal chain operand, but handled in FindBetterChain. 5057 break; 5058 5059 case ISD::LOAD: 5060 case ISD::STORE: { 5061 // Get alias information for Chain. 5062 SDOperand OpPtr; 5063 int64_t OpSize; 5064 const Value *OpSrcValue; 5065 int OpSrcValueOffset; 5066 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5067 OpSrcValue, OpSrcValueOffset); 5068 5069 // If chain is alias then stop here. 5070 if (!(IsLoad && IsOpLoad) && 5071 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5072 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5073 Aliases.push_back(Chain); 5074 } else { 5075 // Look further up the chain. 5076 Chains.push_back(Chain.getOperand(0)); 5077 // Clean up old chain. 5078 AddToWorkList(Chain.Val); 5079 } 5080 break; 5081 } 5082 5083 case ISD::TokenFactor: 5084 // We have to check each of the operands of the token factor, so we queue 5085 // then up. Adding the operands to the queue (stack) in reverse order 5086 // maintains the original order and increases the likelihood that getNode 5087 // will find a matching token factor (CSE.) 5088 for (unsigned n = Chain.getNumOperands(); n;) 5089 Chains.push_back(Chain.getOperand(--n)); 5090 // Eliminate the token factor if we can. 5091 AddToWorkList(Chain.Val); 5092 break; 5093 5094 default: 5095 // For all other instructions we will just have to take what we can get. 5096 Aliases.push_back(Chain); 5097 break; 5098 } 5099 } 5100} 5101 5102/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5103/// for a better chain (aliasing node.) 5104SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5105 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5106 5107 // Accumulate all the aliases to this node. 5108 GatherAllAliases(N, OldChain, Aliases); 5109 5110 if (Aliases.size() == 0) { 5111 // If no operands then chain to entry token. 5112 return DAG.getEntryNode(); 5113 } else if (Aliases.size() == 1) { 5114 // If a single operand then chain to it. We don't need to revisit it. 5115 return Aliases[0]; 5116 } 5117 5118 // Construct a custom tailored token factor. 5119 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5120 &Aliases[0], Aliases.size()); 5121 5122 // Make sure the old chain gets cleaned up. 5123 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5124 5125 return NewChain; 5126} 5127 5128// SelectionDAG::Combine - This is the entry point for the file. 5129// 5130void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5131 if (!RunningAfterLegalize && ViewDAGCombine1) 5132 viewGraph(); 5133 if (RunningAfterLegalize && ViewDAGCombine2) 5134 viewGraph(); 5135 /// run - This is the main entry point to this class. 5136 /// 5137 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5138} 5139