DAGCombiner.cpp revision 5f42a240ba5c6199d2d78fb1238938da2c073755
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/CodeGen/SelectionDAG.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Target/TargetLowering.h" 37#include "llvm/Support/Compiler.h" 38#include <algorithm> 39#include <cmath> 40#include <iostream> 41using namespace llvm; 42 43namespace { 44 static Statistic<> NodesCombined ("dagcombiner", 45 "Number of dag nodes combined"); 46 47 class VISIBILITY_HIDDEN DAGCombiner { 48 SelectionDAG &DAG; 49 TargetLowering &TLI; 50 bool AfterLegalize; 51 52 // Worklist of all of the nodes that need to be simplified. 53 std::vector<SDNode*> WorkList; 54 55 /// AddUsersToWorkList - When an instruction is simplified, add all users of 56 /// the instruction to the work lists because they might get more simplified 57 /// now. 58 /// 59 void AddUsersToWorkList(SDNode *N) { 60 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 61 UI != UE; ++UI) 62 WorkList.push_back(*UI); 63 } 64 65 /// removeFromWorkList - remove all instances of N from the worklist. 66 /// 67 void removeFromWorkList(SDNode *N) { 68 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 69 WorkList.end()); 70 } 71 72 public: 73 void AddToWorkList(SDNode *N) { 74 WorkList.push_back(N); 75 } 76 77 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo) { 78 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 79 ++NodesCombined; 80 DEBUG(std::cerr << "\nReplacing "; N->dump(); 81 std::cerr << "\nWith: "; To[0].Val->dump(&DAG); 82 std::cerr << " and " << NumTo-1 << " other values\n"); 83 std::vector<SDNode*> NowDead; 84 DAG.ReplaceAllUsesWith(N, To, &NowDead); 85 86 // Push the new nodes and any users onto the worklist 87 for (unsigned i = 0, e = NumTo; i != e; ++i) { 88 WorkList.push_back(To[i].Val); 89 AddUsersToWorkList(To[i].Val); 90 } 91 92 // Nodes can end up on the worklist more than once. Make sure we do 93 // not process a node that has been replaced. 94 removeFromWorkList(N); 95 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 96 removeFromWorkList(NowDead[i]); 97 98 // Finally, since the node is now dead, remove it from the graph. 99 DAG.DeleteNode(N); 100 return SDOperand(N, 0); 101 } 102 103 SDOperand CombineTo(SDNode *N, SDOperand Res) { 104 return CombineTo(N, &Res, 1); 105 } 106 107 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 108 SDOperand To[] = { Res0, Res1 }; 109 return CombineTo(N, To, 2); 110 } 111 private: 112 113 /// SimplifyDemandedBits - Check the specified integer node value to see if 114 /// it can be simplified or if things it uses can be simplified by bit 115 /// propagation. If so, return true. 116 bool SimplifyDemandedBits(SDOperand Op) { 117 TargetLowering::TargetLoweringOpt TLO(DAG); 118 uint64_t KnownZero, KnownOne; 119 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 120 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 121 return false; 122 123 // Revisit the node. 124 WorkList.push_back(Op.Val); 125 126 // Replace the old value with the new one. 127 ++NodesCombined; 128 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 129 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG)); 130 131 std::vector<SDNode*> NowDead; 132 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 133 134 // Push the new node and any (possibly new) users onto the worklist. 135 WorkList.push_back(TLO.New.Val); 136 AddUsersToWorkList(TLO.New.Val); 137 138 // Nodes can end up on the worklist more than once. Make sure we do 139 // not process a node that has been replaced. 140 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 141 removeFromWorkList(NowDead[i]); 142 143 // Finally, if the node is now dead, remove it from the graph. The node 144 // may not be dead if the replacement process recursively simplified to 145 // something else needing this node. 146 if (TLO.Old.Val->use_empty()) { 147 removeFromWorkList(TLO.Old.Val); 148 DAG.DeleteNode(TLO.Old.Val); 149 } 150 return true; 151 } 152 153 /// visit - call the node-specific routine that knows how to fold each 154 /// particular type of node. 155 SDOperand visit(SDNode *N); 156 157 // Visitation implementation - Implement dag node combining for different 158 // node types. The semantics are as follows: 159 // Return Value: 160 // SDOperand.Val == 0 - No change was made 161 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 162 // otherwise - N should be replaced by the returned Operand. 163 // 164 SDOperand visitTokenFactor(SDNode *N); 165 SDOperand visitADD(SDNode *N); 166 SDOperand visitSUB(SDNode *N); 167 SDOperand visitMUL(SDNode *N); 168 SDOperand visitSDIV(SDNode *N); 169 SDOperand visitUDIV(SDNode *N); 170 SDOperand visitSREM(SDNode *N); 171 SDOperand visitUREM(SDNode *N); 172 SDOperand visitMULHU(SDNode *N); 173 SDOperand visitMULHS(SDNode *N); 174 SDOperand visitAND(SDNode *N); 175 SDOperand visitOR(SDNode *N); 176 SDOperand visitXOR(SDNode *N); 177 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 178 SDOperand visitSHL(SDNode *N); 179 SDOperand visitSRA(SDNode *N); 180 SDOperand visitSRL(SDNode *N); 181 SDOperand visitCTLZ(SDNode *N); 182 SDOperand visitCTTZ(SDNode *N); 183 SDOperand visitCTPOP(SDNode *N); 184 SDOperand visitSELECT(SDNode *N); 185 SDOperand visitSELECT_CC(SDNode *N); 186 SDOperand visitSETCC(SDNode *N); 187 SDOperand visitSIGN_EXTEND(SDNode *N); 188 SDOperand visitZERO_EXTEND(SDNode *N); 189 SDOperand visitANY_EXTEND(SDNode *N); 190 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 191 SDOperand visitTRUNCATE(SDNode *N); 192 SDOperand visitBIT_CONVERT(SDNode *N); 193 SDOperand visitVBIT_CONVERT(SDNode *N); 194 SDOperand visitFADD(SDNode *N); 195 SDOperand visitFSUB(SDNode *N); 196 SDOperand visitFMUL(SDNode *N); 197 SDOperand visitFDIV(SDNode *N); 198 SDOperand visitFREM(SDNode *N); 199 SDOperand visitFCOPYSIGN(SDNode *N); 200 SDOperand visitSINT_TO_FP(SDNode *N); 201 SDOperand visitUINT_TO_FP(SDNode *N); 202 SDOperand visitFP_TO_SINT(SDNode *N); 203 SDOperand visitFP_TO_UINT(SDNode *N); 204 SDOperand visitFP_ROUND(SDNode *N); 205 SDOperand visitFP_ROUND_INREG(SDNode *N); 206 SDOperand visitFP_EXTEND(SDNode *N); 207 SDOperand visitFNEG(SDNode *N); 208 SDOperand visitFABS(SDNode *N); 209 SDOperand visitBRCOND(SDNode *N); 210 SDOperand visitBR_CC(SDNode *N); 211 SDOperand visitLOAD(SDNode *N); 212 SDOperand visitXEXTLOAD(SDNode *N); 213 SDOperand visitSTORE(SDNode *N); 214 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 215 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 216 SDOperand visitVBUILD_VECTOR(SDNode *N); 217 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 218 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 219 220 SDOperand XformToShuffleWithZero(SDNode *N); 221 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 222 223 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 224 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 225 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 226 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 227 SDOperand N3, ISD::CondCode CC); 228 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 229 ISD::CondCode Cond, bool foldBooleans = true); 230 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 231 SDOperand BuildSDIV(SDNode *N); 232 SDOperand BuildUDIV(SDNode *N); 233 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 234public: 235 DAGCombiner(SelectionDAG &D) 236 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 237 238 /// Run - runs the dag combiner on all nodes in the work list 239 void Run(bool RunningAfterLegalize); 240 }; 241} 242 243//===----------------------------------------------------------------------===// 244// TargetLowering::DAGCombinerInfo implementation 245//===----------------------------------------------------------------------===// 246 247void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 248 ((DAGCombiner*)DC)->AddToWorkList(N); 249} 250 251SDOperand TargetLowering::DAGCombinerInfo:: 252CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 253 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 254} 255 256SDOperand TargetLowering::DAGCombinerInfo:: 257CombineTo(SDNode *N, SDOperand Res) { 258 return ((DAGCombiner*)DC)->CombineTo(N, Res); 259} 260 261 262SDOperand TargetLowering::DAGCombinerInfo:: 263CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 264 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 265} 266 267 268 269 270//===----------------------------------------------------------------------===// 271 272 273// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 274// that selects between the values 1 and 0, making it equivalent to a setcc. 275// Also, set the incoming LHS, RHS, and CC references to the appropriate 276// nodes based on the type of node we are checking. This simplifies life a 277// bit for the callers. 278static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 279 SDOperand &CC) { 280 if (N.getOpcode() == ISD::SETCC) { 281 LHS = N.getOperand(0); 282 RHS = N.getOperand(1); 283 CC = N.getOperand(2); 284 return true; 285 } 286 if (N.getOpcode() == ISD::SELECT_CC && 287 N.getOperand(2).getOpcode() == ISD::Constant && 288 N.getOperand(3).getOpcode() == ISD::Constant && 289 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 290 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 291 LHS = N.getOperand(0); 292 RHS = N.getOperand(1); 293 CC = N.getOperand(4); 294 return true; 295 } 296 return false; 297} 298 299// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 300// one use. If this is true, it allows the users to invert the operation for 301// free when it is profitable to do so. 302static bool isOneUseSetCC(SDOperand N) { 303 SDOperand N0, N1, N2; 304 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 305 return true; 306 return false; 307} 308 309SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 310 MVT::ValueType VT = N0.getValueType(); 311 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 312 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 313 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 314 if (isa<ConstantSDNode>(N1)) { 315 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 316 AddToWorkList(OpNode.Val); 317 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 318 } else if (N0.hasOneUse()) { 319 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 320 AddToWorkList(OpNode.Val); 321 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 322 } 323 } 324 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 325 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 326 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 327 if (isa<ConstantSDNode>(N0)) { 328 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 329 AddToWorkList(OpNode.Val); 330 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 331 } else if (N1.hasOneUse()) { 332 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 333 AddToWorkList(OpNode.Val); 334 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 335 } 336 } 337 return SDOperand(); 338} 339 340void DAGCombiner::Run(bool RunningAfterLegalize) { 341 // set the instance variable, so that the various visit routines may use it. 342 AfterLegalize = RunningAfterLegalize; 343 344 // Add all the dag nodes to the worklist. 345 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 346 E = DAG.allnodes_end(); I != E; ++I) 347 WorkList.push_back(I); 348 349 // Create a dummy node (which is not added to allnodes), that adds a reference 350 // to the root node, preventing it from being deleted, and tracking any 351 // changes of the root. 352 HandleSDNode Dummy(DAG.getRoot()); 353 354 355 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 356 TargetLowering::DAGCombinerInfo 357 DagCombineInfo(DAG, !RunningAfterLegalize, this); 358 359 // while the worklist isn't empty, inspect the node on the end of it and 360 // try and combine it. 361 while (!WorkList.empty()) { 362 SDNode *N = WorkList.back(); 363 WorkList.pop_back(); 364 365 // If N has no uses, it is dead. Make sure to revisit all N's operands once 366 // N is deleted from the DAG, since they too may now be dead or may have a 367 // reduced number of uses, allowing other xforms. 368 if (N->use_empty() && N != &Dummy) { 369 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 370 WorkList.push_back(N->getOperand(i).Val); 371 372 removeFromWorkList(N); 373 DAG.DeleteNode(N); 374 continue; 375 } 376 377 SDOperand RV = visit(N); 378 379 // If nothing happened, try a target-specific DAG combine. 380 if (RV.Val == 0) { 381 assert(N->getOpcode() != ISD::DELETED_NODE && 382 "Node was deleted but visit returned NULL!"); 383 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 384 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 385 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 386 } 387 388 if (RV.Val) { 389 ++NodesCombined; 390 // If we get back the same node we passed in, rather than a new node or 391 // zero, we know that the node must have defined multiple values and 392 // CombineTo was used. Since CombineTo takes care of the worklist 393 // mechanics for us, we have no work to do in this case. 394 if (RV.Val != N) { 395 assert(N->getOpcode() != ISD::DELETED_NODE && 396 RV.Val->getOpcode() != ISD::DELETED_NODE && 397 "Node was deleted but visit returned new node!"); 398 399 DEBUG(std::cerr << "\nReplacing "; N->dump(); 400 std::cerr << "\nWith: "; RV.Val->dump(&DAG); 401 std::cerr << '\n'); 402 std::vector<SDNode*> NowDead; 403 SDOperand OpV = RV; 404 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 405 406 // Push the new node and any users onto the worklist 407 WorkList.push_back(RV.Val); 408 AddUsersToWorkList(RV.Val); 409 410 // Nodes can end up on the worklist more than once. Make sure we do 411 // not process a node that has been replaced. 412 removeFromWorkList(N); 413 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 414 removeFromWorkList(NowDead[i]); 415 416 // Finally, since the node is now dead, remove it from the graph. 417 DAG.DeleteNode(N); 418 } 419 } 420 } 421 422 // If the root changed (e.g. it was a dead load, update the root). 423 DAG.setRoot(Dummy.getValue()); 424} 425 426SDOperand DAGCombiner::visit(SDNode *N) { 427 switch(N->getOpcode()) { 428 default: break; 429 case ISD::TokenFactor: return visitTokenFactor(N); 430 case ISD::ADD: return visitADD(N); 431 case ISD::SUB: return visitSUB(N); 432 case ISD::MUL: return visitMUL(N); 433 case ISD::SDIV: return visitSDIV(N); 434 case ISD::UDIV: return visitUDIV(N); 435 case ISD::SREM: return visitSREM(N); 436 case ISD::UREM: return visitUREM(N); 437 case ISD::MULHU: return visitMULHU(N); 438 case ISD::MULHS: return visitMULHS(N); 439 case ISD::AND: return visitAND(N); 440 case ISD::OR: return visitOR(N); 441 case ISD::XOR: return visitXOR(N); 442 case ISD::SHL: return visitSHL(N); 443 case ISD::SRA: return visitSRA(N); 444 case ISD::SRL: return visitSRL(N); 445 case ISD::CTLZ: return visitCTLZ(N); 446 case ISD::CTTZ: return visitCTTZ(N); 447 case ISD::CTPOP: return visitCTPOP(N); 448 case ISD::SELECT: return visitSELECT(N); 449 case ISD::SELECT_CC: return visitSELECT_CC(N); 450 case ISD::SETCC: return visitSETCC(N); 451 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 452 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 453 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 454 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 455 case ISD::TRUNCATE: return visitTRUNCATE(N); 456 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 457 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 458 case ISD::FADD: return visitFADD(N); 459 case ISD::FSUB: return visitFSUB(N); 460 case ISD::FMUL: return visitFMUL(N); 461 case ISD::FDIV: return visitFDIV(N); 462 case ISD::FREM: return visitFREM(N); 463 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 464 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 465 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 466 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 467 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 468 case ISD::FP_ROUND: return visitFP_ROUND(N); 469 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 470 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 471 case ISD::FNEG: return visitFNEG(N); 472 case ISD::FABS: return visitFABS(N); 473 case ISD::BRCOND: return visitBRCOND(N); 474 case ISD::BR_CC: return visitBR_CC(N); 475 case ISD::LOAD: return visitLOAD(N); 476 case ISD::EXTLOAD: 477 case ISD::SEXTLOAD: 478 case ISD::ZEXTLOAD: return visitXEXTLOAD(N); 479 case ISD::STORE: return visitSTORE(N); 480 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 481 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 482 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 483 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 484 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 485 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 486 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 487 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 488 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 489 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 490 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 491 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 492 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 493 } 494 return SDOperand(); 495} 496 497SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 498 SmallVector<SDOperand, 8> Ops; 499 bool Changed = false; 500 501 // If the token factor has two operands and one is the entry token, replace 502 // the token factor with the other operand. 503 if (N->getNumOperands() == 2) { 504 if (N->getOperand(0).getOpcode() == ISD::EntryToken || 505 N->getOperand(0) == N->getOperand(1)) 506 return N->getOperand(1); 507 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 508 return N->getOperand(0); 509 } 510 511 // fold (tokenfactor (tokenfactor)) -> tokenfactor 512 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 513 SDOperand Op = N->getOperand(i); 514 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 515 AddToWorkList(Op.Val); // Remove dead node. 516 Changed = true; 517 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 518 Ops.push_back(Op.getOperand(j)); 519 } else if (i == 0 || N->getOperand(i) != N->getOperand(i-1)) { 520 Ops.push_back(Op); 521 } else { 522 // Deleted an operand that was the same as the last one. 523 Changed = true; 524 } 525 } 526 if (Changed) 527 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 528 return SDOperand(); 529} 530 531SDOperand DAGCombiner::visitADD(SDNode *N) { 532 SDOperand N0 = N->getOperand(0); 533 SDOperand N1 = N->getOperand(1); 534 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 535 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 536 MVT::ValueType VT = N0.getValueType(); 537 538 // fold (add c1, c2) -> c1+c2 539 if (N0C && N1C) 540 return DAG.getNode(ISD::ADD, VT, N0, N1); 541 // canonicalize constant to RHS 542 if (N0C && !N1C) 543 return DAG.getNode(ISD::ADD, VT, N1, N0); 544 // fold (add x, 0) -> x 545 if (N1C && N1C->isNullValue()) 546 return N0; 547 // fold ((c1-A)+c2) -> (c1+c2)-A 548 if (N1C && N0.getOpcode() == ISD::SUB) 549 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 550 return DAG.getNode(ISD::SUB, VT, 551 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 552 N0.getOperand(1)); 553 // reassociate add 554 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 555 if (RADD.Val != 0) 556 return RADD; 557 // fold ((0-A) + B) -> B-A 558 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 559 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 560 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 561 // fold (A + (0-B)) -> A-B 562 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 563 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 564 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 565 // fold (A+(B-A)) -> B 566 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 567 return N1.getOperand(0); 568 569 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 570 return SDOperand(N, 0); 571 572 // fold (a+b) -> (a|b) iff a and b share no bits. 573 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 574 uint64_t LHSZero, LHSOne; 575 uint64_t RHSZero, RHSOne; 576 uint64_t Mask = MVT::getIntVTBitMask(VT); 577 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 578 if (LHSZero) { 579 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 580 581 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 582 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 583 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 584 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 585 return DAG.getNode(ISD::OR, VT, N0, N1); 586 } 587 } 588 589 return SDOperand(); 590} 591 592SDOperand DAGCombiner::visitSUB(SDNode *N) { 593 SDOperand N0 = N->getOperand(0); 594 SDOperand N1 = N->getOperand(1); 595 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 596 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 597 MVT::ValueType VT = N0.getValueType(); 598 599 // fold (sub x, x) -> 0 600 if (N0 == N1) 601 return DAG.getConstant(0, N->getValueType(0)); 602 // fold (sub c1, c2) -> c1-c2 603 if (N0C && N1C) 604 return DAG.getNode(ISD::SUB, VT, N0, N1); 605 // fold (sub x, c) -> (add x, -c) 606 if (N1C) 607 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 608 // fold (A+B)-A -> B 609 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 610 return N0.getOperand(1); 611 // fold (A+B)-B -> A 612 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 613 return N0.getOperand(0); 614 return SDOperand(); 615} 616 617SDOperand DAGCombiner::visitMUL(SDNode *N) { 618 SDOperand N0 = N->getOperand(0); 619 SDOperand N1 = N->getOperand(1); 620 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 621 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 622 MVT::ValueType VT = N0.getValueType(); 623 624 // fold (mul c1, c2) -> c1*c2 625 if (N0C && N1C) 626 return DAG.getNode(ISD::MUL, VT, N0, N1); 627 // canonicalize constant to RHS 628 if (N0C && !N1C) 629 return DAG.getNode(ISD::MUL, VT, N1, N0); 630 // fold (mul x, 0) -> 0 631 if (N1C && N1C->isNullValue()) 632 return N1; 633 // fold (mul x, -1) -> 0-x 634 if (N1C && N1C->isAllOnesValue()) 635 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 636 // fold (mul x, (1 << c)) -> x << c 637 if (N1C && isPowerOf2_64(N1C->getValue())) 638 return DAG.getNode(ISD::SHL, VT, N0, 639 DAG.getConstant(Log2_64(N1C->getValue()), 640 TLI.getShiftAmountTy())); 641 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 642 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 643 // FIXME: If the input is something that is easily negated (e.g. a 644 // single-use add), we should put the negate there. 645 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 646 DAG.getNode(ISD::SHL, VT, N0, 647 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 648 TLI.getShiftAmountTy()))); 649 } 650 651 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 652 if (N1C && N0.getOpcode() == ISD::SHL && 653 isa<ConstantSDNode>(N0.getOperand(1))) { 654 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 655 AddToWorkList(C3.Val); 656 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 657 } 658 659 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 660 // use. 661 { 662 SDOperand Sh(0,0), Y(0,0); 663 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 664 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 665 N0.Val->hasOneUse()) { 666 Sh = N0; Y = N1; 667 } else if (N1.getOpcode() == ISD::SHL && 668 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 669 Sh = N1; Y = N0; 670 } 671 if (Sh.Val) { 672 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 673 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 674 } 675 } 676 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 677 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 678 isa<ConstantSDNode>(N0.getOperand(1))) { 679 return DAG.getNode(ISD::ADD, VT, 680 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 681 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 682 } 683 684 // reassociate mul 685 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 686 if (RMUL.Val != 0) 687 return RMUL; 688 return SDOperand(); 689} 690 691SDOperand DAGCombiner::visitSDIV(SDNode *N) { 692 SDOperand N0 = N->getOperand(0); 693 SDOperand N1 = N->getOperand(1); 694 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 695 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 696 MVT::ValueType VT = N->getValueType(0); 697 698 // fold (sdiv c1, c2) -> c1/c2 699 if (N0C && N1C && !N1C->isNullValue()) 700 return DAG.getNode(ISD::SDIV, VT, N0, N1); 701 // fold (sdiv X, 1) -> X 702 if (N1C && N1C->getSignExtended() == 1LL) 703 return N0; 704 // fold (sdiv X, -1) -> 0-X 705 if (N1C && N1C->isAllOnesValue()) 706 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 707 // If we know the sign bits of both operands are zero, strength reduce to a 708 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 709 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 710 if (TLI.MaskedValueIsZero(N1, SignBit) && 711 TLI.MaskedValueIsZero(N0, SignBit)) 712 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 713 // fold (sdiv X, pow2) -> simple ops after legalize 714 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 715 (isPowerOf2_64(N1C->getSignExtended()) || 716 isPowerOf2_64(-N1C->getSignExtended()))) { 717 // If dividing by powers of two is cheap, then don't perform the following 718 // fold. 719 if (TLI.isPow2DivCheap()) 720 return SDOperand(); 721 int64_t pow2 = N1C->getSignExtended(); 722 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 723 unsigned lg2 = Log2_64(abs2); 724 // Splat the sign bit into the register 725 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 726 DAG.getConstant(MVT::getSizeInBits(VT)-1, 727 TLI.getShiftAmountTy())); 728 AddToWorkList(SGN.Val); 729 // Add (N0 < 0) ? abs2 - 1 : 0; 730 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 731 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 732 TLI.getShiftAmountTy())); 733 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 734 AddToWorkList(SRL.Val); 735 AddToWorkList(ADD.Val); // Divide by pow2 736 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 737 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 738 // If we're dividing by a positive value, we're done. Otherwise, we must 739 // negate the result. 740 if (pow2 > 0) 741 return SRA; 742 AddToWorkList(SRA.Val); 743 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 744 } 745 // if integer divide is expensive and we satisfy the requirements, emit an 746 // alternate sequence. 747 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 748 !TLI.isIntDivCheap()) { 749 SDOperand Op = BuildSDIV(N); 750 if (Op.Val) return Op; 751 } 752 return SDOperand(); 753} 754 755SDOperand DAGCombiner::visitUDIV(SDNode *N) { 756 SDOperand N0 = N->getOperand(0); 757 SDOperand N1 = N->getOperand(1); 758 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 759 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 760 MVT::ValueType VT = N->getValueType(0); 761 762 // fold (udiv c1, c2) -> c1/c2 763 if (N0C && N1C && !N1C->isNullValue()) 764 return DAG.getNode(ISD::UDIV, VT, N0, N1); 765 // fold (udiv x, (1 << c)) -> x >>u c 766 if (N1C && isPowerOf2_64(N1C->getValue())) 767 return DAG.getNode(ISD::SRL, VT, N0, 768 DAG.getConstant(Log2_64(N1C->getValue()), 769 TLI.getShiftAmountTy())); 770 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 771 if (N1.getOpcode() == ISD::SHL) { 772 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 773 if (isPowerOf2_64(SHC->getValue())) { 774 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 775 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 776 DAG.getConstant(Log2_64(SHC->getValue()), 777 ADDVT)); 778 AddToWorkList(Add.Val); 779 return DAG.getNode(ISD::SRL, VT, N0, Add); 780 } 781 } 782 } 783 // fold (udiv x, c) -> alternate 784 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 785 SDOperand Op = BuildUDIV(N); 786 if (Op.Val) return Op; 787 } 788 return SDOperand(); 789} 790 791SDOperand DAGCombiner::visitSREM(SDNode *N) { 792 SDOperand N0 = N->getOperand(0); 793 SDOperand N1 = N->getOperand(1); 794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 796 MVT::ValueType VT = N->getValueType(0); 797 798 // fold (srem c1, c2) -> c1%c2 799 if (N0C && N1C && !N1C->isNullValue()) 800 return DAG.getNode(ISD::SREM, VT, N0, N1); 801 // If we know the sign bits of both operands are zero, strength reduce to a 802 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 803 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 804 if (TLI.MaskedValueIsZero(N1, SignBit) && 805 TLI.MaskedValueIsZero(N0, SignBit)) 806 return DAG.getNode(ISD::UREM, VT, N0, N1); 807 return SDOperand(); 808} 809 810SDOperand DAGCombiner::visitUREM(SDNode *N) { 811 SDOperand N0 = N->getOperand(0); 812 SDOperand N1 = N->getOperand(1); 813 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 814 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 815 MVT::ValueType VT = N->getValueType(0); 816 817 // fold (urem c1, c2) -> c1%c2 818 if (N0C && N1C && !N1C->isNullValue()) 819 return DAG.getNode(ISD::UREM, VT, N0, N1); 820 // fold (urem x, pow2) -> (and x, pow2-1) 821 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 822 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 823 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 824 if (N1.getOpcode() == ISD::SHL) { 825 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 826 if (isPowerOf2_64(SHC->getValue())) { 827 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 828 AddToWorkList(Add.Val); 829 return DAG.getNode(ISD::AND, VT, N0, Add); 830 } 831 } 832 } 833 return SDOperand(); 834} 835 836SDOperand DAGCombiner::visitMULHS(SDNode *N) { 837 SDOperand N0 = N->getOperand(0); 838 SDOperand N1 = N->getOperand(1); 839 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 840 841 // fold (mulhs x, 0) -> 0 842 if (N1C && N1C->isNullValue()) 843 return N1; 844 // fold (mulhs x, 1) -> (sra x, size(x)-1) 845 if (N1C && N1C->getValue() == 1) 846 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 847 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 848 TLI.getShiftAmountTy())); 849 return SDOperand(); 850} 851 852SDOperand DAGCombiner::visitMULHU(SDNode *N) { 853 SDOperand N0 = N->getOperand(0); 854 SDOperand N1 = N->getOperand(1); 855 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 856 857 // fold (mulhu x, 0) -> 0 858 if (N1C && N1C->isNullValue()) 859 return N1; 860 // fold (mulhu x, 1) -> 0 861 if (N1C && N1C->getValue() == 1) 862 return DAG.getConstant(0, N0.getValueType()); 863 return SDOperand(); 864} 865 866/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 867/// two operands of the same opcode, try to simplify it. 868SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 869 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 870 MVT::ValueType VT = N0.getValueType(); 871 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 872 873 // For each of OP in AND/OR/XOR: 874 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 875 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 876 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 877 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 878 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 879 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 880 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 881 SDOperand ORNode = DAG.getNode(N->getOpcode(), 882 N0.getOperand(0).getValueType(), 883 N0.getOperand(0), N1.getOperand(0)); 884 AddToWorkList(ORNode.Val); 885 return DAG.getNode(N0.getOpcode(), VT, ORNode); 886 } 887 888 // For each of OP in SHL/SRL/SRA/AND... 889 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 890 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 891 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 892 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 893 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 894 N0.getOperand(1) == N1.getOperand(1)) { 895 SDOperand ORNode = DAG.getNode(N->getOpcode(), 896 N0.getOperand(0).getValueType(), 897 N0.getOperand(0), N1.getOperand(0)); 898 AddToWorkList(ORNode.Val); 899 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 900 } 901 902 return SDOperand(); 903} 904 905SDOperand DAGCombiner::visitAND(SDNode *N) { 906 SDOperand N0 = N->getOperand(0); 907 SDOperand N1 = N->getOperand(1); 908 SDOperand LL, LR, RL, RR, CC0, CC1; 909 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 910 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 911 MVT::ValueType VT = N1.getValueType(); 912 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 913 914 // fold (and c1, c2) -> c1&c2 915 if (N0C && N1C) 916 return DAG.getNode(ISD::AND, VT, N0, N1); 917 // canonicalize constant to RHS 918 if (N0C && !N1C) 919 return DAG.getNode(ISD::AND, VT, N1, N0); 920 // fold (and x, -1) -> x 921 if (N1C && N1C->isAllOnesValue()) 922 return N0; 923 // if (and x, c) is known to be zero, return 0 924 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 925 return DAG.getConstant(0, VT); 926 // reassociate and 927 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 928 if (RAND.Val != 0) 929 return RAND; 930 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 931 if (N1C && N0.getOpcode() == ISD::OR) 932 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 933 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 934 return N1; 935 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 936 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 937 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 938 if (TLI.MaskedValueIsZero(N0.getOperand(0), 939 ~N1C->getValue() & InMask)) { 940 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 941 N0.getOperand(0)); 942 943 // Replace uses of the AND with uses of the Zero extend node. 944 CombineTo(N, Zext); 945 946 // We actually want to replace all uses of the any_extend with the 947 // zero_extend, to avoid duplicating things. This will later cause this 948 // AND to be folded. 949 CombineTo(N0.Val, Zext); 950 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 951 } 952 } 953 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 954 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 955 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 956 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 957 958 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 959 MVT::isInteger(LL.getValueType())) { 960 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 961 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 962 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 963 AddToWorkList(ORNode.Val); 964 return DAG.getSetCC(VT, ORNode, LR, Op1); 965 } 966 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 967 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 968 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 969 AddToWorkList(ANDNode.Val); 970 return DAG.getSetCC(VT, ANDNode, LR, Op1); 971 } 972 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 973 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 974 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 975 AddToWorkList(ORNode.Val); 976 return DAG.getSetCC(VT, ORNode, LR, Op1); 977 } 978 } 979 // canonicalize equivalent to ll == rl 980 if (LL == RR && LR == RL) { 981 Op1 = ISD::getSetCCSwappedOperands(Op1); 982 std::swap(RL, RR); 983 } 984 if (LL == RL && LR == RR) { 985 bool isInteger = MVT::isInteger(LL.getValueType()); 986 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 987 if (Result != ISD::SETCC_INVALID) 988 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 989 } 990 } 991 992 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 993 if (N0.getOpcode() == N1.getOpcode()) { 994 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 995 if (Tmp.Val) return Tmp; 996 } 997 998 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 999 // fold (and (sra)) -> (and (srl)) when possible. 1000 if (!MVT::isVector(VT) && 1001 SimplifyDemandedBits(SDOperand(N, 0))) 1002 return SDOperand(N, 0); 1003 // fold (zext_inreg (extload x)) -> (zextload x) 1004 if (N0.getOpcode() == ISD::EXTLOAD) { 1005 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1006 // If we zero all the possible extended bits, then we can turn this into 1007 // a zextload if we are running before legalize or the operation is legal. 1008 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1009 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1010 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1011 N0.getOperand(1), N0.getOperand(2), 1012 EVT); 1013 AddToWorkList(N); 1014 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1015 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1016 } 1017 } 1018 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1019 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1020 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1021 // If we zero all the possible extended bits, then we can turn this into 1022 // a zextload if we are running before legalize or the operation is legal. 1023 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1024 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1025 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1026 N0.getOperand(1), N0.getOperand(2), 1027 EVT); 1028 AddToWorkList(N); 1029 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1030 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1031 } 1032 } 1033 1034 // fold (and (load x), 255) -> (zextload x, i8) 1035 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1036 if (N1C && 1037 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD || 1038 N0.getOpcode() == ISD::ZEXTLOAD) && 1039 N0.hasOneUse()) { 1040 MVT::ValueType EVT, LoadedVT; 1041 if (N1C->getValue() == 255) 1042 EVT = MVT::i8; 1043 else if (N1C->getValue() == 65535) 1044 EVT = MVT::i16; 1045 else if (N1C->getValue() == ~0U) 1046 EVT = MVT::i32; 1047 else 1048 EVT = MVT::Other; 1049 1050 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : 1051 cast<VTSDNode>(N0.getOperand(3))->getVT(); 1052 if (EVT != MVT::Other && LoadedVT > EVT && 1053 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1054 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1055 // For big endian targets, we need to add an offset to the pointer to load 1056 // the correct bytes. For little endian systems, we merely need to read 1057 // fewer bytes from the same pointer. 1058 unsigned PtrOff = 1059 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1060 SDOperand NewPtr = N0.getOperand(1); 1061 if (!TLI.isLittleEndian()) 1062 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1063 DAG.getConstant(PtrOff, PtrType)); 1064 AddToWorkList(NewPtr.Val); 1065 SDOperand Load = 1066 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr, 1067 N0.getOperand(2), EVT); 1068 AddToWorkList(N); 1069 CombineTo(N0.Val, Load, Load.getValue(1)); 1070 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1071 } 1072 } 1073 1074 return SDOperand(); 1075} 1076 1077SDOperand DAGCombiner::visitOR(SDNode *N) { 1078 SDOperand N0 = N->getOperand(0); 1079 SDOperand N1 = N->getOperand(1); 1080 SDOperand LL, LR, RL, RR, CC0, CC1; 1081 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1082 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1083 MVT::ValueType VT = N1.getValueType(); 1084 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1085 1086 // fold (or c1, c2) -> c1|c2 1087 if (N0C && N1C) 1088 return DAG.getNode(ISD::OR, VT, N0, N1); 1089 // canonicalize constant to RHS 1090 if (N0C && !N1C) 1091 return DAG.getNode(ISD::OR, VT, N1, N0); 1092 // fold (or x, 0) -> x 1093 if (N1C && N1C->isNullValue()) 1094 return N0; 1095 // fold (or x, -1) -> -1 1096 if (N1C && N1C->isAllOnesValue()) 1097 return N1; 1098 // fold (or x, c) -> c iff (x & ~c) == 0 1099 if (N1C && 1100 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1101 return N1; 1102 // reassociate or 1103 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1104 if (ROR.Val != 0) 1105 return ROR; 1106 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1107 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1108 isa<ConstantSDNode>(N0.getOperand(1))) { 1109 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1110 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1111 N1), 1112 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1113 } 1114 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1115 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1116 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1117 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1118 1119 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1120 MVT::isInteger(LL.getValueType())) { 1121 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1122 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1123 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1124 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1125 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1126 AddToWorkList(ORNode.Val); 1127 return DAG.getSetCC(VT, ORNode, LR, Op1); 1128 } 1129 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1130 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1131 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1132 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1133 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1134 AddToWorkList(ANDNode.Val); 1135 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1136 } 1137 } 1138 // canonicalize equivalent to ll == rl 1139 if (LL == RR && LR == RL) { 1140 Op1 = ISD::getSetCCSwappedOperands(Op1); 1141 std::swap(RL, RR); 1142 } 1143 if (LL == RL && LR == RR) { 1144 bool isInteger = MVT::isInteger(LL.getValueType()); 1145 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1146 if (Result != ISD::SETCC_INVALID) 1147 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1148 } 1149 } 1150 1151 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1152 if (N0.getOpcode() == N1.getOpcode()) { 1153 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1154 if (Tmp.Val) return Tmp; 1155 } 1156 1157 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1158 if (N0.getOpcode() == ISD::AND && 1159 N1.getOpcode() == ISD::AND && 1160 N0.getOperand(1).getOpcode() == ISD::Constant && 1161 N1.getOperand(1).getOpcode() == ISD::Constant && 1162 // Don't increase # computations. 1163 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1164 // We can only do this xform if we know that bits from X that are set in C2 1165 // but not in C1 are already zero. Likewise for Y. 1166 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1167 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1168 1169 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1170 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1171 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1172 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1173 } 1174 } 1175 1176 1177 // See if this is some rotate idiom. 1178 if (SDNode *Rot = MatchRotate(N0, N1)) 1179 return SDOperand(Rot, 0); 1180 1181 return SDOperand(); 1182} 1183 1184 1185/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1186static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1187 if (Op.getOpcode() == ISD::AND) { 1188 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1189 Mask = Op.getOperand(1); 1190 Op = Op.getOperand(0); 1191 } else { 1192 return false; 1193 } 1194 } 1195 1196 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1197 Shift = Op; 1198 return true; 1199 } 1200 return false; 1201} 1202 1203 1204// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1205// idioms for rotate, and if the target supports rotation instructions, generate 1206// a rot[lr]. 1207SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1208 // Must be a legal type. Expanded an promoted things won't work with rotates. 1209 MVT::ValueType VT = LHS.getValueType(); 1210 if (!TLI.isTypeLegal(VT)) return 0; 1211 1212 // The target must have at least one rotate flavor. 1213 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1214 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1215 if (!HasROTL && !HasROTR) return 0; 1216 1217 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1218 SDOperand LHSShift; // The shift. 1219 SDOperand LHSMask; // AND value if any. 1220 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1221 return 0; // Not part of a rotate. 1222 1223 SDOperand RHSShift; // The shift. 1224 SDOperand RHSMask; // AND value if any. 1225 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1226 return 0; // Not part of a rotate. 1227 1228 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1229 return 0; // Not shifting the same value. 1230 1231 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1232 return 0; // Shifts must disagree. 1233 1234 // Canonicalize shl to left side in a shl/srl pair. 1235 if (RHSShift.getOpcode() == ISD::SHL) { 1236 std::swap(LHS, RHS); 1237 std::swap(LHSShift, RHSShift); 1238 std::swap(LHSMask , RHSMask ); 1239 } 1240 1241 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1242 1243 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1244 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1245 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant && 1246 RHSShift.getOperand(1).getOpcode() == ISD::Constant) { 1247 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue(); 1248 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue(); 1249 if ((LShVal + RShVal) != OpSizeInBits) 1250 return 0; 1251 1252 SDOperand Rot; 1253 if (HasROTL) 1254 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1255 LHSShift.getOperand(1)); 1256 else 1257 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1258 RHSShift.getOperand(1)); 1259 1260 // If there is an AND of either shifted operand, apply it to the result. 1261 if (LHSMask.Val || RHSMask.Val) { 1262 uint64_t Mask = MVT::getIntVTBitMask(VT); 1263 1264 if (LHSMask.Val) { 1265 uint64_t RHSBits = (1ULL << LShVal)-1; 1266 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1267 } 1268 if (RHSMask.Val) { 1269 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1270 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1271 } 1272 1273 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1274 } 1275 1276 return Rot.Val; 1277 } 1278 1279 // If there is a mask here, and we have a variable shift, we can't be sure 1280 // that we're masking out the right stuff. 1281 if (LHSMask.Val || RHSMask.Val) 1282 return 0; 1283 1284 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1285 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1286 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB && 1287 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) { 1288 if (ConstantSDNode *SUBC = 1289 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) { 1290 if (SUBC->getValue() == OpSizeInBits) 1291 if (HasROTL) 1292 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1293 LHSShift.getOperand(1)).Val; 1294 else 1295 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1296 LHSShift.getOperand(1)).Val; 1297 } 1298 } 1299 1300 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1301 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1302 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB && 1303 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) { 1304 if (ConstantSDNode *SUBC = 1305 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) { 1306 if (SUBC->getValue() == OpSizeInBits) 1307 if (HasROTL) 1308 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1309 LHSShift.getOperand(1)).Val; 1310 else 1311 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1312 RHSShift.getOperand(1)).Val; 1313 } 1314 } 1315 1316 return 0; 1317} 1318 1319 1320SDOperand DAGCombiner::visitXOR(SDNode *N) { 1321 SDOperand N0 = N->getOperand(0); 1322 SDOperand N1 = N->getOperand(1); 1323 SDOperand LHS, RHS, CC; 1324 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1325 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1326 MVT::ValueType VT = N0.getValueType(); 1327 1328 // fold (xor c1, c2) -> c1^c2 1329 if (N0C && N1C) 1330 return DAG.getNode(ISD::XOR, VT, N0, N1); 1331 // canonicalize constant to RHS 1332 if (N0C && !N1C) 1333 return DAG.getNode(ISD::XOR, VT, N1, N0); 1334 // fold (xor x, 0) -> x 1335 if (N1C && N1C->isNullValue()) 1336 return N0; 1337 // reassociate xor 1338 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1339 if (RXOR.Val != 0) 1340 return RXOR; 1341 // fold !(x cc y) -> (x !cc y) 1342 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1343 bool isInt = MVT::isInteger(LHS.getValueType()); 1344 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1345 isInt); 1346 if (N0.getOpcode() == ISD::SETCC) 1347 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1348 if (N0.getOpcode() == ISD::SELECT_CC) 1349 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1350 assert(0 && "Unhandled SetCC Equivalent!"); 1351 abort(); 1352 } 1353 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1354 if (N1C && N1C->getValue() == 1 && 1355 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1356 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1357 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1358 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1359 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1360 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1361 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1362 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1363 } 1364 } 1365 // fold !(x or y) -> (!x and !y) iff x or y are constants 1366 if (N1C && N1C->isAllOnesValue() && 1367 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1368 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1369 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1370 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1371 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1372 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1373 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1374 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1375 } 1376 } 1377 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1378 if (N1C && N0.getOpcode() == ISD::XOR) { 1379 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1380 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1381 if (N00C) 1382 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1383 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1384 if (N01C) 1385 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1386 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1387 } 1388 // fold (xor x, x) -> 0 1389 if (N0 == N1) { 1390 if (!MVT::isVector(VT)) { 1391 return DAG.getConstant(0, VT); 1392 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1393 // Produce a vector of zeros. 1394 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1395 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1396 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1397 } 1398 } 1399 1400 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1401 if (N0.getOpcode() == N1.getOpcode()) { 1402 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1403 if (Tmp.Val) return Tmp; 1404 } 1405 1406 // Simplify the expression using non-local knowledge. 1407 if (!MVT::isVector(VT) && 1408 SimplifyDemandedBits(SDOperand(N, 0))) 1409 return SDOperand(N, 0); 1410 1411 return SDOperand(); 1412} 1413 1414SDOperand DAGCombiner::visitSHL(SDNode *N) { 1415 SDOperand N0 = N->getOperand(0); 1416 SDOperand N1 = N->getOperand(1); 1417 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1418 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1419 MVT::ValueType VT = N0.getValueType(); 1420 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1421 1422 // fold (shl c1, c2) -> c1<<c2 1423 if (N0C && N1C) 1424 return DAG.getNode(ISD::SHL, VT, N0, N1); 1425 // fold (shl 0, x) -> 0 1426 if (N0C && N0C->isNullValue()) 1427 return N0; 1428 // fold (shl x, c >= size(x)) -> undef 1429 if (N1C && N1C->getValue() >= OpSizeInBits) 1430 return DAG.getNode(ISD::UNDEF, VT); 1431 // fold (shl x, 0) -> x 1432 if (N1C && N1C->isNullValue()) 1433 return N0; 1434 // if (shl x, c) is known to be zero, return 0 1435 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1436 return DAG.getConstant(0, VT); 1437 if (SimplifyDemandedBits(SDOperand(N, 0))) 1438 return SDOperand(N, 0); 1439 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1440 if (N1C && N0.getOpcode() == ISD::SHL && 1441 N0.getOperand(1).getOpcode() == ISD::Constant) { 1442 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1443 uint64_t c2 = N1C->getValue(); 1444 if (c1 + c2 > OpSizeInBits) 1445 return DAG.getConstant(0, VT); 1446 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1447 DAG.getConstant(c1 + c2, N1.getValueType())); 1448 } 1449 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1450 // (srl (and x, -1 << c1), c1-c2) 1451 if (N1C && N0.getOpcode() == ISD::SRL && 1452 N0.getOperand(1).getOpcode() == ISD::Constant) { 1453 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1454 uint64_t c2 = N1C->getValue(); 1455 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1456 DAG.getConstant(~0ULL << c1, VT)); 1457 if (c2 > c1) 1458 return DAG.getNode(ISD::SHL, VT, Mask, 1459 DAG.getConstant(c2-c1, N1.getValueType())); 1460 else 1461 return DAG.getNode(ISD::SRL, VT, Mask, 1462 DAG.getConstant(c1-c2, N1.getValueType())); 1463 } 1464 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1465 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1466 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1467 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1468 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) 1469 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1470 isa<ConstantSDNode>(N0.getOperand(1))) { 1471 return DAG.getNode(ISD::ADD, VT, 1472 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1), 1473 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1)); 1474 } 1475 return SDOperand(); 1476} 1477 1478SDOperand DAGCombiner::visitSRA(SDNode *N) { 1479 SDOperand N0 = N->getOperand(0); 1480 SDOperand N1 = N->getOperand(1); 1481 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1482 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1483 MVT::ValueType VT = N0.getValueType(); 1484 1485 // fold (sra c1, c2) -> c1>>c2 1486 if (N0C && N1C) 1487 return DAG.getNode(ISD::SRA, VT, N0, N1); 1488 // fold (sra 0, x) -> 0 1489 if (N0C && N0C->isNullValue()) 1490 return N0; 1491 // fold (sra -1, x) -> -1 1492 if (N0C && N0C->isAllOnesValue()) 1493 return N0; 1494 // fold (sra x, c >= size(x)) -> undef 1495 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1496 return DAG.getNode(ISD::UNDEF, VT); 1497 // fold (sra x, 0) -> x 1498 if (N1C && N1C->isNullValue()) 1499 return N0; 1500 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1501 // sext_inreg. 1502 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1503 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1504 MVT::ValueType EVT; 1505 switch (LowBits) { 1506 default: EVT = MVT::Other; break; 1507 case 1: EVT = MVT::i1; break; 1508 case 8: EVT = MVT::i8; break; 1509 case 16: EVT = MVT::i16; break; 1510 case 32: EVT = MVT::i32; break; 1511 } 1512 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1513 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1514 DAG.getValueType(EVT)); 1515 } 1516 1517 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1518 if (N1C && N0.getOpcode() == ISD::SRA) { 1519 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1520 unsigned Sum = N1C->getValue() + C1->getValue(); 1521 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1522 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1523 DAG.getConstant(Sum, N1C->getValueType(0))); 1524 } 1525 } 1526 1527 // Simplify, based on bits shifted out of the LHS. 1528 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1529 return SDOperand(N, 0); 1530 1531 1532 // If the sign bit is known to be zero, switch this to a SRL. 1533 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1534 return DAG.getNode(ISD::SRL, VT, N0, N1); 1535 return SDOperand(); 1536} 1537 1538SDOperand DAGCombiner::visitSRL(SDNode *N) { 1539 SDOperand N0 = N->getOperand(0); 1540 SDOperand N1 = N->getOperand(1); 1541 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1542 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1543 MVT::ValueType VT = N0.getValueType(); 1544 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1545 1546 // fold (srl c1, c2) -> c1 >>u c2 1547 if (N0C && N1C) 1548 return DAG.getNode(ISD::SRL, VT, N0, N1); 1549 // fold (srl 0, x) -> 0 1550 if (N0C && N0C->isNullValue()) 1551 return N0; 1552 // fold (srl x, c >= size(x)) -> undef 1553 if (N1C && N1C->getValue() >= OpSizeInBits) 1554 return DAG.getNode(ISD::UNDEF, VT); 1555 // fold (srl x, 0) -> x 1556 if (N1C && N1C->isNullValue()) 1557 return N0; 1558 // if (srl x, c) is known to be zero, return 0 1559 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1560 return DAG.getConstant(0, VT); 1561 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1562 if (N1C && N0.getOpcode() == ISD::SRL && 1563 N0.getOperand(1).getOpcode() == ISD::Constant) { 1564 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1565 uint64_t c2 = N1C->getValue(); 1566 if (c1 + c2 > OpSizeInBits) 1567 return DAG.getConstant(0, VT); 1568 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1569 DAG.getConstant(c1 + c2, N1.getValueType())); 1570 } 1571 1572 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1573 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1574 // Shifting in all undef bits? 1575 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1576 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1577 return DAG.getNode(ISD::UNDEF, VT); 1578 1579 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1580 AddToWorkList(SmallShift.Val); 1581 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1582 } 1583 1584 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1585 if (N1C && N0.getOpcode() == ISD::CTLZ && 1586 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1587 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1588 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1589 1590 // If any of the input bits are KnownOne, then the input couldn't be all 1591 // zeros, thus the result of the srl will always be zero. 1592 if (KnownOne) return DAG.getConstant(0, VT); 1593 1594 // If all of the bits input the to ctlz node are known to be zero, then 1595 // the result of the ctlz is "32" and the result of the shift is one. 1596 uint64_t UnknownBits = ~KnownZero & Mask; 1597 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1598 1599 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1600 if ((UnknownBits & (UnknownBits-1)) == 0) { 1601 // Okay, we know that only that the single bit specified by UnknownBits 1602 // could be set on input to the CTLZ node. If this bit is set, the SRL 1603 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1604 // to an SRL,XOR pair, which is likely to simplify more. 1605 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1606 SDOperand Op = N0.getOperand(0); 1607 if (ShAmt) { 1608 Op = DAG.getNode(ISD::SRL, VT, Op, 1609 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1610 AddToWorkList(Op.Val); 1611 } 1612 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1613 } 1614 } 1615 1616 return SDOperand(); 1617} 1618 1619SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1620 SDOperand N0 = N->getOperand(0); 1621 MVT::ValueType VT = N->getValueType(0); 1622 1623 // fold (ctlz c1) -> c2 1624 if (isa<ConstantSDNode>(N0)) 1625 return DAG.getNode(ISD::CTLZ, VT, N0); 1626 return SDOperand(); 1627} 1628 1629SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1630 SDOperand N0 = N->getOperand(0); 1631 MVT::ValueType VT = N->getValueType(0); 1632 1633 // fold (cttz c1) -> c2 1634 if (isa<ConstantSDNode>(N0)) 1635 return DAG.getNode(ISD::CTTZ, VT, N0); 1636 return SDOperand(); 1637} 1638 1639SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1640 SDOperand N0 = N->getOperand(0); 1641 MVT::ValueType VT = N->getValueType(0); 1642 1643 // fold (ctpop c1) -> c2 1644 if (isa<ConstantSDNode>(N0)) 1645 return DAG.getNode(ISD::CTPOP, VT, N0); 1646 return SDOperand(); 1647} 1648 1649SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1650 SDOperand N0 = N->getOperand(0); 1651 SDOperand N1 = N->getOperand(1); 1652 SDOperand N2 = N->getOperand(2); 1653 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1654 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1655 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1656 MVT::ValueType VT = N->getValueType(0); 1657 1658 // fold select C, X, X -> X 1659 if (N1 == N2) 1660 return N1; 1661 // fold select true, X, Y -> X 1662 if (N0C && !N0C->isNullValue()) 1663 return N1; 1664 // fold select false, X, Y -> Y 1665 if (N0C && N0C->isNullValue()) 1666 return N2; 1667 // fold select C, 1, X -> C | X 1668 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1669 return DAG.getNode(ISD::OR, VT, N0, N2); 1670 // fold select C, 0, X -> ~C & X 1671 // FIXME: this should check for C type == X type, not i1? 1672 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1673 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1674 AddToWorkList(XORNode.Val); 1675 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1676 } 1677 // fold select C, X, 1 -> ~C | X 1678 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1679 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1680 AddToWorkList(XORNode.Val); 1681 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1682 } 1683 // fold select C, X, 0 -> C & X 1684 // FIXME: this should check for C type == X type, not i1? 1685 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1686 return DAG.getNode(ISD::AND, VT, N0, N1); 1687 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1688 if (MVT::i1 == VT && N0 == N1) 1689 return DAG.getNode(ISD::OR, VT, N0, N2); 1690 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1691 if (MVT::i1 == VT && N0 == N2) 1692 return DAG.getNode(ISD::AND, VT, N0, N1); 1693 1694 // If we can fold this based on the true/false value, do so. 1695 if (SimplifySelectOps(N, N1, N2)) 1696 return SDOperand(N, 0); // Don't revisit N. 1697 1698 // fold selects based on a setcc into other things, such as min/max/abs 1699 if (N0.getOpcode() == ISD::SETCC) 1700 // FIXME: 1701 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1702 // having to say they don't support SELECT_CC on every type the DAG knows 1703 // about, since there is no way to mark an opcode illegal at all value types 1704 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1705 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1706 N1, N2, N0.getOperand(2)); 1707 else 1708 return SimplifySelect(N0, N1, N2); 1709 return SDOperand(); 1710} 1711 1712SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1713 SDOperand N0 = N->getOperand(0); 1714 SDOperand N1 = N->getOperand(1); 1715 SDOperand N2 = N->getOperand(2); 1716 SDOperand N3 = N->getOperand(3); 1717 SDOperand N4 = N->getOperand(4); 1718 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1719 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1720 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1721 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1722 1723 // fold select_cc lhs, rhs, x, x, cc -> x 1724 if (N2 == N3) 1725 return N2; 1726 1727 // Determine if the condition we're dealing with is constant 1728 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1729 1730 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 1731 if (SCCC->getValue()) 1732 return N2; // cond always true -> true val 1733 else 1734 return N3; // cond always false -> false val 1735 } 1736 1737 // Fold to a simpler select_cc 1738 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 1739 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 1740 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 1741 SCC.getOperand(2)); 1742 1743 // If we can fold this based on the true/false value, do so. 1744 if (SimplifySelectOps(N, N2, N3)) 1745 return SDOperand(N, 0); // Don't revisit N. 1746 1747 // fold select_cc into other things, such as min/max/abs 1748 return SimplifySelectCC(N0, N1, N2, N3, CC); 1749} 1750 1751SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1752 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1753 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1754} 1755 1756SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1757 SDOperand N0 = N->getOperand(0); 1758 MVT::ValueType VT = N->getValueType(0); 1759 1760 // fold (sext c1) -> c1 1761 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 1762 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1763 1764 // fold (sext (sext x)) -> (sext x) 1765 // fold (sext (aext x)) -> (sext x) 1766 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1767 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1768 1769 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1770 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1771 (!AfterLegalize || 1772 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1773 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1774 DAG.getValueType(N0.getValueType())); 1775 1776 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1777 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1778 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1779 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1780 N0.getOperand(1), N0.getOperand(2), 1781 N0.getValueType()); 1782 CombineTo(N, ExtLoad); 1783 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1784 ExtLoad.getValue(1)); 1785 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1786 } 1787 1788 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1789 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1790 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1791 N0.hasOneUse()) { 1792 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1793 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1794 N0.getOperand(1), N0.getOperand(2), EVT); 1795 CombineTo(N, ExtLoad); 1796 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1797 ExtLoad.getValue(1)); 1798 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1799 } 1800 1801 return SDOperand(); 1802} 1803 1804SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1805 SDOperand N0 = N->getOperand(0); 1806 MVT::ValueType VT = N->getValueType(0); 1807 1808 // fold (zext c1) -> c1 1809 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 1810 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1811 // fold (zext (zext x)) -> (zext x) 1812 // fold (zext (aext x)) -> (zext x) 1813 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1814 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1815 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1816 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1817 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1818 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1819 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1820 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1821 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1822 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1823 N0.getOperand(1), N0.getOperand(2), 1824 N0.getValueType()); 1825 CombineTo(N, ExtLoad); 1826 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1827 ExtLoad.getValue(1)); 1828 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1829 } 1830 1831 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1832 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1833 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1834 N0.hasOneUse()) { 1835 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1836 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1837 N0.getOperand(1), N0.getOperand(2), EVT); 1838 CombineTo(N, ExtLoad); 1839 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1840 ExtLoad.getValue(1)); 1841 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1842 } 1843 return SDOperand(); 1844} 1845 1846SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 1847 SDOperand N0 = N->getOperand(0); 1848 MVT::ValueType VT = N->getValueType(0); 1849 1850 // fold (aext c1) -> c1 1851 if (isa<ConstantSDNode>(N0)) 1852 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 1853 // fold (aext (aext x)) -> (aext x) 1854 // fold (aext (zext x)) -> (zext x) 1855 // fold (aext (sext x)) -> (sext x) 1856 if (N0.getOpcode() == ISD::ANY_EXTEND || 1857 N0.getOpcode() == ISD::ZERO_EXTEND || 1858 N0.getOpcode() == ISD::SIGN_EXTEND) 1859 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1860 1861 // fold (aext (truncate x)) -> x iff x size == zext size. 1862 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT) 1863 return N0.getOperand(0); 1864 // fold (aext (load x)) -> (aext (truncate (extload x))) 1865 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1866 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 1867 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 1868 N0.getOperand(1), N0.getOperand(2), 1869 N0.getValueType()); 1870 CombineTo(N, ExtLoad); 1871 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1872 ExtLoad.getValue(1)); 1873 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1874 } 1875 1876 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 1877 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 1878 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 1879 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD || 1880 N0.getOpcode() == ISD::SEXTLOAD) && 1881 N0.hasOneUse()) { 1882 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1883 SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0), 1884 N0.getOperand(1), N0.getOperand(2), EVT); 1885 CombineTo(N, ExtLoad); 1886 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1887 ExtLoad.getValue(1)); 1888 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1889 } 1890 return SDOperand(); 1891} 1892 1893 1894SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1895 SDOperand N0 = N->getOperand(0); 1896 SDOperand N1 = N->getOperand(1); 1897 MVT::ValueType VT = N->getValueType(0); 1898 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1899 unsigned EVTBits = MVT::getSizeInBits(EVT); 1900 1901 // fold (sext_in_reg c1) -> c1 1902 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 1903 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 1904 1905 // If the input is already sign extended, just drop the extension. 1906 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 1907 return N0; 1908 1909 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1910 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1911 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1912 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1913 } 1914 1915 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1916 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1917 return DAG.getZeroExtendInReg(N0, EVT); 1918 1919 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 1920 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 1921 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 1922 if (N0.getOpcode() == ISD::SRL) { 1923 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1924 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 1925 // We can turn this into an SRA iff the input to the SRL is already sign 1926 // extended enough. 1927 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 1928 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 1929 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 1930 } 1931 } 1932 1933 // fold (sext_inreg (extload x)) -> (sextload x) 1934 if (N0.getOpcode() == ISD::EXTLOAD && 1935 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1936 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1937 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1938 N0.getOperand(1), N0.getOperand(2), 1939 EVT); 1940 CombineTo(N, ExtLoad); 1941 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1942 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1943 } 1944 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1945 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1946 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1947 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1948 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1949 N0.getOperand(1), N0.getOperand(2), 1950 EVT); 1951 CombineTo(N, ExtLoad); 1952 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1953 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1954 } 1955 return SDOperand(); 1956} 1957 1958SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1959 SDOperand N0 = N->getOperand(0); 1960 MVT::ValueType VT = N->getValueType(0); 1961 1962 // noop truncate 1963 if (N0.getValueType() == N->getValueType(0)) 1964 return N0; 1965 // fold (truncate c1) -> c1 1966 if (isa<ConstantSDNode>(N0)) 1967 return DAG.getNode(ISD::TRUNCATE, VT, N0); 1968 // fold (truncate (truncate x)) -> (truncate x) 1969 if (N0.getOpcode() == ISD::TRUNCATE) 1970 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1971 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1972 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 1973 N0.getOpcode() == ISD::ANY_EXTEND) { 1974 if (N0.getValueType() < VT) 1975 // if the source is smaller than the dest, we still need an extend 1976 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1977 else if (N0.getValueType() > VT) 1978 // if the source is larger than the dest, than we just need the truncate 1979 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1980 else 1981 // if the source and dest are the same type, we can drop both the extend 1982 // and the truncate 1983 return N0.getOperand(0); 1984 } 1985 // fold (truncate (load x)) -> (smaller load x) 1986 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1987 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1988 "Cannot truncate to larger type!"); 1989 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1990 // For big endian targets, we need to add an offset to the pointer to load 1991 // the correct bytes. For little endian systems, we merely need to read 1992 // fewer bytes from the same pointer. 1993 uint64_t PtrOff = 1994 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1995 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1996 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1997 DAG.getConstant(PtrOff, PtrType)); 1998 AddToWorkList(NewPtr.Val); 1999 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 2000 AddToWorkList(N); 2001 CombineTo(N0.Val, Load, Load.getValue(1)); 2002 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2003 } 2004 return SDOperand(); 2005} 2006 2007SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2008 SDOperand N0 = N->getOperand(0); 2009 MVT::ValueType VT = N->getValueType(0); 2010 2011 // If the input is a constant, let getNode() fold it. 2012 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2013 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2014 if (Res.Val != N) return Res; 2015 } 2016 2017 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2018 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2019 2020 // fold (conv (load x)) -> (load (conv*)x) 2021 // FIXME: These xforms need to know that the resultant load doesn't need a 2022 // higher alignment than the original! 2023 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 2024 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 2025 N0.getOperand(2)); 2026 AddToWorkList(N); 2027 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2028 Load.getValue(1)); 2029 return Load; 2030 } 2031 2032 return SDOperand(); 2033} 2034 2035SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2036 SDOperand N0 = N->getOperand(0); 2037 MVT::ValueType VT = N->getValueType(0); 2038 2039 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2040 // First check to see if this is all constant. 2041 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2042 VT == MVT::Vector) { 2043 bool isSimple = true; 2044 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2045 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2046 N0.getOperand(i).getOpcode() != ISD::Constant && 2047 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2048 isSimple = false; 2049 break; 2050 } 2051 2052 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2053 if (isSimple && !MVT::isVector(DestEltVT)) { 2054 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2055 } 2056 } 2057 2058 return SDOperand(); 2059} 2060 2061/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2062/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2063/// destination element value type. 2064SDOperand DAGCombiner:: 2065ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2066 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2067 2068 // If this is already the right type, we're done. 2069 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2070 2071 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2072 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2073 2074 // If this is a conversion of N elements of one type to N elements of another 2075 // type, convert each element. This handles FP<->INT cases. 2076 if (SrcBitSize == DstBitSize) { 2077 SmallVector<SDOperand, 8> Ops; 2078 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2079 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2080 AddToWorkList(Ops.back().Val); 2081 } 2082 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2083 Ops.push_back(DAG.getValueType(DstEltVT)); 2084 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2085 } 2086 2087 // Otherwise, we're growing or shrinking the elements. To avoid having to 2088 // handle annoying details of growing/shrinking FP values, we convert them to 2089 // int first. 2090 if (MVT::isFloatingPoint(SrcEltVT)) { 2091 // Convert the input float vector to a int vector where the elements are the 2092 // same sizes. 2093 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2094 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2095 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2096 SrcEltVT = IntVT; 2097 } 2098 2099 // Now we know the input is an integer vector. If the output is a FP type, 2100 // convert to integer first, then to FP of the right size. 2101 if (MVT::isFloatingPoint(DstEltVT)) { 2102 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2103 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2104 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2105 2106 // Next, convert to FP elements of the same size. 2107 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2108 } 2109 2110 // Okay, we know the src/dst types are both integers of differing types. 2111 // Handling growing first. 2112 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2113 if (SrcBitSize < DstBitSize) { 2114 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2115 2116 SmallVector<SDOperand, 8> Ops; 2117 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2118 i += NumInputsPerOutput) { 2119 bool isLE = TLI.isLittleEndian(); 2120 uint64_t NewBits = 0; 2121 bool EltIsUndef = true; 2122 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2123 // Shift the previously computed bits over. 2124 NewBits <<= SrcBitSize; 2125 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2126 if (Op.getOpcode() == ISD::UNDEF) continue; 2127 EltIsUndef = false; 2128 2129 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2130 } 2131 2132 if (EltIsUndef) 2133 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2134 else 2135 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2136 } 2137 2138 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2139 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2140 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2141 } 2142 2143 // Finally, this must be the case where we are shrinking elements: each input 2144 // turns into multiple outputs. 2145 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2146 SmallVector<SDOperand, 8> Ops; 2147 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2148 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2149 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2150 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2151 continue; 2152 } 2153 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2154 2155 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2156 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2157 OpVal >>= DstBitSize; 2158 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2159 } 2160 2161 // For big endian targets, swap the order of the pieces of each element. 2162 if (!TLI.isLittleEndian()) 2163 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2164 } 2165 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2166 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2167 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2168} 2169 2170 2171 2172SDOperand DAGCombiner::visitFADD(SDNode *N) { 2173 SDOperand N0 = N->getOperand(0); 2174 SDOperand N1 = N->getOperand(1); 2175 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2176 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2177 MVT::ValueType VT = N->getValueType(0); 2178 2179 // fold (fadd c1, c2) -> c1+c2 2180 if (N0CFP && N1CFP) 2181 return DAG.getNode(ISD::FADD, VT, N0, N1); 2182 // canonicalize constant to RHS 2183 if (N0CFP && !N1CFP) 2184 return DAG.getNode(ISD::FADD, VT, N1, N0); 2185 // fold (A + (-B)) -> A-B 2186 if (N1.getOpcode() == ISD::FNEG) 2187 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2188 // fold ((-A) + B) -> B-A 2189 if (N0.getOpcode() == ISD::FNEG) 2190 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2191 return SDOperand(); 2192} 2193 2194SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2195 SDOperand N0 = N->getOperand(0); 2196 SDOperand N1 = N->getOperand(1); 2197 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2198 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2199 MVT::ValueType VT = N->getValueType(0); 2200 2201 // fold (fsub c1, c2) -> c1-c2 2202 if (N0CFP && N1CFP) 2203 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2204 // fold (A-(-B)) -> A+B 2205 if (N1.getOpcode() == ISD::FNEG) 2206 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2207 return SDOperand(); 2208} 2209 2210SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2211 SDOperand N0 = N->getOperand(0); 2212 SDOperand N1 = N->getOperand(1); 2213 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2214 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2215 MVT::ValueType VT = N->getValueType(0); 2216 2217 // fold (fmul c1, c2) -> c1*c2 2218 if (N0CFP && N1CFP) 2219 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2220 // canonicalize constant to RHS 2221 if (N0CFP && !N1CFP) 2222 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2223 // fold (fmul X, 2.0) -> (fadd X, X) 2224 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2225 return DAG.getNode(ISD::FADD, VT, N0, N0); 2226 return SDOperand(); 2227} 2228 2229SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2230 SDOperand N0 = N->getOperand(0); 2231 SDOperand N1 = N->getOperand(1); 2232 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2233 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2234 MVT::ValueType VT = N->getValueType(0); 2235 2236 // fold (fdiv c1, c2) -> c1/c2 2237 if (N0CFP && N1CFP) 2238 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2239 return SDOperand(); 2240} 2241 2242SDOperand DAGCombiner::visitFREM(SDNode *N) { 2243 SDOperand N0 = N->getOperand(0); 2244 SDOperand N1 = N->getOperand(1); 2245 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2246 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2247 MVT::ValueType VT = N->getValueType(0); 2248 2249 // fold (frem c1, c2) -> fmod(c1,c2) 2250 if (N0CFP && N1CFP) 2251 return DAG.getNode(ISD::FREM, VT, N0, N1); 2252 return SDOperand(); 2253} 2254 2255SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2256 SDOperand N0 = N->getOperand(0); 2257 SDOperand N1 = N->getOperand(1); 2258 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2259 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2260 MVT::ValueType VT = N->getValueType(0); 2261 2262 if (N0CFP && N1CFP) // Constant fold 2263 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2264 2265 if (N1CFP) { 2266 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2267 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2268 union { 2269 double d; 2270 int64_t i; 2271 } u; 2272 u.d = N1CFP->getValue(); 2273 if (u.i >= 0) 2274 return DAG.getNode(ISD::FABS, VT, N0); 2275 else 2276 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2277 } 2278 2279 // copysign(fabs(x), y) -> copysign(x, y) 2280 // copysign(fneg(x), y) -> copysign(x, y) 2281 // copysign(copysign(x,z), y) -> copysign(x, y) 2282 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2283 N0.getOpcode() == ISD::FCOPYSIGN) 2284 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2285 2286 // copysign(x, abs(y)) -> abs(x) 2287 if (N1.getOpcode() == ISD::FABS) 2288 return DAG.getNode(ISD::FABS, VT, N0); 2289 2290 // copysign(x, copysign(y,z)) -> copysign(x, z) 2291 if (N1.getOpcode() == ISD::FCOPYSIGN) 2292 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2293 2294 // copysign(x, fp_extend(y)) -> copysign(x, y) 2295 // copysign(x, fp_round(y)) -> copysign(x, y) 2296 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2297 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2298 2299 return SDOperand(); 2300} 2301 2302 2303 2304SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2305 SDOperand N0 = N->getOperand(0); 2306 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2307 MVT::ValueType VT = N->getValueType(0); 2308 2309 // fold (sint_to_fp c1) -> c1fp 2310 if (N0C) 2311 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2312 return SDOperand(); 2313} 2314 2315SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2316 SDOperand N0 = N->getOperand(0); 2317 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2318 MVT::ValueType VT = N->getValueType(0); 2319 2320 // fold (uint_to_fp c1) -> c1fp 2321 if (N0C) 2322 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2323 return SDOperand(); 2324} 2325 2326SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2327 SDOperand N0 = N->getOperand(0); 2328 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2329 MVT::ValueType VT = N->getValueType(0); 2330 2331 // fold (fp_to_sint c1fp) -> c1 2332 if (N0CFP) 2333 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2334 return SDOperand(); 2335} 2336 2337SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2338 SDOperand N0 = N->getOperand(0); 2339 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2340 MVT::ValueType VT = N->getValueType(0); 2341 2342 // fold (fp_to_uint c1fp) -> c1 2343 if (N0CFP) 2344 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2345 return SDOperand(); 2346} 2347 2348SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2349 SDOperand N0 = N->getOperand(0); 2350 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2351 MVT::ValueType VT = N->getValueType(0); 2352 2353 // fold (fp_round c1fp) -> c1fp 2354 if (N0CFP) 2355 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2356 2357 // fold (fp_round (fp_extend x)) -> x 2358 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2359 return N0.getOperand(0); 2360 2361 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2362 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2363 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2364 AddToWorkList(Tmp.Val); 2365 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2366 } 2367 2368 return SDOperand(); 2369} 2370 2371SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2372 SDOperand N0 = N->getOperand(0); 2373 MVT::ValueType VT = N->getValueType(0); 2374 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2375 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2376 2377 // fold (fp_round_inreg c1fp) -> c1fp 2378 if (N0CFP) { 2379 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2380 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2381 } 2382 return SDOperand(); 2383} 2384 2385SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2386 SDOperand N0 = N->getOperand(0); 2387 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2388 MVT::ValueType VT = N->getValueType(0); 2389 2390 // fold (fp_extend c1fp) -> c1fp 2391 if (N0CFP) 2392 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2393 2394 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2395 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 2396 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 2397 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 2398 N0.getOperand(1), N0.getOperand(2), 2399 N0.getValueType()); 2400 CombineTo(N, ExtLoad); 2401 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2402 ExtLoad.getValue(1)); 2403 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2404 } 2405 2406 2407 return SDOperand(); 2408} 2409 2410SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2411 SDOperand N0 = N->getOperand(0); 2412 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2413 MVT::ValueType VT = N->getValueType(0); 2414 2415 // fold (fneg c1) -> -c1 2416 if (N0CFP) 2417 return DAG.getNode(ISD::FNEG, VT, N0); 2418 // fold (fneg (sub x, y)) -> (sub y, x) 2419 if (N0.getOpcode() == ISD::SUB) 2420 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2421 // fold (fneg (fneg x)) -> x 2422 if (N0.getOpcode() == ISD::FNEG) 2423 return N0.getOperand(0); 2424 return SDOperand(); 2425} 2426 2427SDOperand DAGCombiner::visitFABS(SDNode *N) { 2428 SDOperand N0 = N->getOperand(0); 2429 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2430 MVT::ValueType VT = N->getValueType(0); 2431 2432 // fold (fabs c1) -> fabs(c1) 2433 if (N0CFP) 2434 return DAG.getNode(ISD::FABS, VT, N0); 2435 // fold (fabs (fabs x)) -> (fabs x) 2436 if (N0.getOpcode() == ISD::FABS) 2437 return N->getOperand(0); 2438 // fold (fabs (fneg x)) -> (fabs x) 2439 // fold (fabs (fcopysign x, y)) -> (fabs x) 2440 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2441 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2442 2443 return SDOperand(); 2444} 2445 2446SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2447 SDOperand Chain = N->getOperand(0); 2448 SDOperand N1 = N->getOperand(1); 2449 SDOperand N2 = N->getOperand(2); 2450 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2451 2452 // never taken branch, fold to chain 2453 if (N1C && N1C->isNullValue()) 2454 return Chain; 2455 // unconditional branch 2456 if (N1C && N1C->getValue() == 1) 2457 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2458 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2459 // on the target. 2460 if (N1.getOpcode() == ISD::SETCC && 2461 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2462 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2463 N1.getOperand(0), N1.getOperand(1), N2); 2464 } 2465 return SDOperand(); 2466} 2467 2468// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2469// 2470SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2471 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2472 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2473 2474 // Use SimplifySetCC to simplify SETCC's. 2475 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2476 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2477 2478 // fold br_cc true, dest -> br dest (unconditional branch) 2479 if (SCCC && SCCC->getValue()) 2480 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2481 N->getOperand(4)); 2482 // fold br_cc false, dest -> unconditional fall through 2483 if (SCCC && SCCC->isNullValue()) 2484 return N->getOperand(0); 2485 // fold to a simpler setcc 2486 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2487 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2488 Simp.getOperand(2), Simp.getOperand(0), 2489 Simp.getOperand(1), N->getOperand(4)); 2490 return SDOperand(); 2491} 2492 2493SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2494 SDOperand Chain = N->getOperand(0); 2495 SDOperand Ptr = N->getOperand(1); 2496 SDOperand SrcValue = N->getOperand(2); 2497 2498 // If there are no uses of the loaded value, change uses of the chain value 2499 // into uses of the chain input (i.e. delete the dead load). 2500 if (N->hasNUsesOfValue(0, 0)) 2501 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2502 2503 // If this load is directly stored, replace the load value with the stored 2504 // value. 2505 // TODO: Handle store large -> read small portion. 2506 // TODO: Handle TRUNCSTORE/EXTLOAD 2507 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2508 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2509 return CombineTo(N, Chain.getOperand(1), Chain); 2510 2511 return SDOperand(); 2512} 2513 2514/// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD. 2515SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) { 2516 SDOperand Chain = N->getOperand(0); 2517 SDOperand Ptr = N->getOperand(1); 2518 SDOperand SrcValue = N->getOperand(2); 2519 SDOperand EVT = N->getOperand(3); 2520 2521 // If there are no uses of the loaded value, change uses of the chain value 2522 // into uses of the chain input (i.e. delete the dead load). 2523 if (N->hasNUsesOfValue(0, 0)) 2524 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2525 2526 return SDOperand(); 2527} 2528 2529SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2530 SDOperand Chain = N->getOperand(0); 2531 SDOperand Value = N->getOperand(1); 2532 SDOperand Ptr = N->getOperand(2); 2533 SDOperand SrcValue = N->getOperand(3); 2534 2535 // If this is a store that kills a previous store, remove the previous store. 2536 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2537 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2538 // Make sure that these stores are the same value type: 2539 // FIXME: we really care that the second store is >= size of the first. 2540 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2541 // Create a new store of Value that replaces both stores. 2542 SDNode *PrevStore = Chain.Val; 2543 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2544 return Chain; 2545 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2546 PrevStore->getOperand(0), Value, Ptr, 2547 SrcValue); 2548 CombineTo(N, NewStore); // Nuke this store. 2549 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2550 return SDOperand(N, 0); 2551 } 2552 2553 // If this is a store of a bit convert, store the input value. 2554 // FIXME: This needs to know that the resultant store does not need a 2555 // higher alignment than the original. 2556 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2557 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2558 Ptr, SrcValue); 2559 2560 return SDOperand(); 2561} 2562 2563SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 2564 SDOperand InVec = N->getOperand(0); 2565 SDOperand InVal = N->getOperand(1); 2566 SDOperand EltNo = N->getOperand(2); 2567 2568 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 2569 // vector with the inserted element. 2570 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2571 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2572 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2573 if (Elt < Ops.size()) 2574 Ops[Elt] = InVal; 2575 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 2576 &Ops[0], Ops.size()); 2577 } 2578 2579 return SDOperand(); 2580} 2581 2582SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 2583 SDOperand InVec = N->getOperand(0); 2584 SDOperand InVal = N->getOperand(1); 2585 SDOperand EltNo = N->getOperand(2); 2586 SDOperand NumElts = N->getOperand(3); 2587 SDOperand EltType = N->getOperand(4); 2588 2589 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 2590 // vector with the inserted element. 2591 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2592 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2593 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2594 if (Elt < Ops.size()-2) 2595 Ops[Elt] = InVal; 2596 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), 2597 &Ops[0], Ops.size()); 2598 } 2599 2600 return SDOperand(); 2601} 2602 2603SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 2604 unsigned NumInScalars = N->getNumOperands()-2; 2605 SDOperand NumElts = N->getOperand(NumInScalars); 2606 SDOperand EltType = N->getOperand(NumInScalars+1); 2607 2608 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 2609 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 2610 // two distinct vectors, turn this into a shuffle node. 2611 SDOperand VecIn1, VecIn2; 2612 for (unsigned i = 0; i != NumInScalars; ++i) { 2613 // Ignore undef inputs. 2614 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 2615 2616 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 2617 // constant index, bail out. 2618 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 2619 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 2620 VecIn1 = VecIn2 = SDOperand(0, 0); 2621 break; 2622 } 2623 2624 // If the input vector type disagrees with the result of the vbuild_vector, 2625 // we can't make a shuffle. 2626 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 2627 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 2628 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 2629 VecIn1 = VecIn2 = SDOperand(0, 0); 2630 break; 2631 } 2632 2633 // Otherwise, remember this. We allow up to two distinct input vectors. 2634 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 2635 continue; 2636 2637 if (VecIn1.Val == 0) { 2638 VecIn1 = ExtractedFromVec; 2639 } else if (VecIn2.Val == 0) { 2640 VecIn2 = ExtractedFromVec; 2641 } else { 2642 // Too many inputs. 2643 VecIn1 = VecIn2 = SDOperand(0, 0); 2644 break; 2645 } 2646 } 2647 2648 // If everything is good, we can make a shuffle operation. 2649 if (VecIn1.Val) { 2650 SmallVector<SDOperand, 8> BuildVecIndices; 2651 for (unsigned i = 0; i != NumInScalars; ++i) { 2652 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 2653 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 2654 continue; 2655 } 2656 2657 SDOperand Extract = N->getOperand(i); 2658 2659 // If extracting from the first vector, just use the index directly. 2660 if (Extract.getOperand(0) == VecIn1) { 2661 BuildVecIndices.push_back(Extract.getOperand(1)); 2662 continue; 2663 } 2664 2665 // Otherwise, use InIdx + VecSize 2666 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 2667 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32)); 2668 } 2669 2670 // Add count and size info. 2671 BuildVecIndices.push_back(NumElts); 2672 BuildVecIndices.push_back(DAG.getValueType(MVT::i32)); 2673 2674 // Return the new VVECTOR_SHUFFLE node. 2675 SDOperand Ops[5]; 2676 Ops[0] = VecIn1; 2677 if (VecIn2.Val) { 2678 Ops[1] = VecIn2; 2679 } else { 2680 // Use an undef vbuild_vector as input for the second operand. 2681 std::vector<SDOperand> UnOps(NumInScalars, 2682 DAG.getNode(ISD::UNDEF, 2683 cast<VTSDNode>(EltType)->getVT())); 2684 UnOps.push_back(NumElts); 2685 UnOps.push_back(EltType); 2686 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 2687 &UnOps[0], UnOps.size()); 2688 AddToWorkList(Ops[1].Val); 2689 } 2690 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 2691 &BuildVecIndices[0], BuildVecIndices.size()); 2692 Ops[3] = NumElts; 2693 Ops[4] = EltType; 2694 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5); 2695 } 2696 2697 return SDOperand(); 2698} 2699 2700SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 2701 SDOperand ShufMask = N->getOperand(2); 2702 unsigned NumElts = ShufMask.getNumOperands(); 2703 2704 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2705 bool isIdentity = true; 2706 for (unsigned i = 0; i != NumElts; ++i) { 2707 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2708 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2709 isIdentity = false; 2710 break; 2711 } 2712 } 2713 if (isIdentity) return N->getOperand(0); 2714 2715 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2716 isIdentity = true; 2717 for (unsigned i = 0; i != NumElts; ++i) { 2718 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2719 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2720 isIdentity = false; 2721 break; 2722 } 2723 } 2724 if (isIdentity) return N->getOperand(1); 2725 2726 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 2727 // needed at all. 2728 bool isUnary = true; 2729 bool isSplat = true; 2730 int VecNum = -1; 2731 unsigned BaseIdx = 0; 2732 for (unsigned i = 0; i != NumElts; ++i) 2733 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 2734 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 2735 int V = (Idx < NumElts) ? 0 : 1; 2736 if (VecNum == -1) { 2737 VecNum = V; 2738 BaseIdx = Idx; 2739 } else { 2740 if (BaseIdx != Idx) 2741 isSplat = false; 2742 if (VecNum != V) { 2743 isUnary = false; 2744 break; 2745 } 2746 } 2747 } 2748 2749 SDOperand N0 = N->getOperand(0); 2750 SDOperand N1 = N->getOperand(1); 2751 // Normalize unary shuffle so the RHS is undef. 2752 if (isUnary && VecNum == 1) 2753 std::swap(N0, N1); 2754 2755 // If it is a splat, check if the argument vector is a build_vector with 2756 // all scalar elements the same. 2757 if (isSplat) { 2758 SDNode *V = N0.Val; 2759 if (V->getOpcode() == ISD::BIT_CONVERT) 2760 V = V->getOperand(0).Val; 2761 if (V->getOpcode() == ISD::BUILD_VECTOR) { 2762 unsigned NumElems = V->getNumOperands()-2; 2763 if (NumElems > BaseIdx) { 2764 SDOperand Base; 2765 bool AllSame = true; 2766 for (unsigned i = 0; i != NumElems; ++i) { 2767 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 2768 Base = V->getOperand(i); 2769 break; 2770 } 2771 } 2772 // Splat of <u, u, u, u>, return <u, u, u, u> 2773 if (!Base.Val) 2774 return N0; 2775 for (unsigned i = 0; i != NumElems; ++i) { 2776 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 2777 V->getOperand(i) != Base) { 2778 AllSame = false; 2779 break; 2780 } 2781 } 2782 // Splat of <x, x, x, x>, return <x, x, x, x> 2783 if (AllSame) 2784 return N0; 2785 } 2786 } 2787 } 2788 2789 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 2790 // into an undef. 2791 if (isUnary || N0 == N1) { 2792 if (N0.getOpcode() == ISD::UNDEF) 2793 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 2794 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 2795 // first operand. 2796 SmallVector<SDOperand, 8> MappedOps; 2797 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 2798 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 2799 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 2800 MappedOps.push_back(ShufMask.getOperand(i)); 2801 } else { 2802 unsigned NewIdx = 2803 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 2804 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 2805 } 2806 } 2807 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 2808 &MappedOps[0], MappedOps.size()); 2809 AddToWorkList(ShufMask.Val); 2810 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 2811 N0, 2812 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 2813 ShufMask); 2814 } 2815 2816 return SDOperand(); 2817} 2818 2819SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 2820 SDOperand ShufMask = N->getOperand(2); 2821 unsigned NumElts = ShufMask.getNumOperands()-2; 2822 2823 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2824 bool isIdentity = true; 2825 for (unsigned i = 0; i != NumElts; ++i) { 2826 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2827 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2828 isIdentity = false; 2829 break; 2830 } 2831 } 2832 if (isIdentity) return N->getOperand(0); 2833 2834 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2835 isIdentity = true; 2836 for (unsigned i = 0; i != NumElts; ++i) { 2837 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2838 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2839 isIdentity = false; 2840 break; 2841 } 2842 } 2843 if (isIdentity) return N->getOperand(1); 2844 2845 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 2846 // needed at all. 2847 bool isUnary = true; 2848 bool isSplat = true; 2849 int VecNum = -1; 2850 unsigned BaseIdx = 0; 2851 for (unsigned i = 0; i != NumElts; ++i) 2852 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 2853 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 2854 int V = (Idx < NumElts) ? 0 : 1; 2855 if (VecNum == -1) { 2856 VecNum = V; 2857 BaseIdx = Idx; 2858 } else { 2859 if (BaseIdx != Idx) 2860 isSplat = false; 2861 if (VecNum != V) { 2862 isUnary = false; 2863 break; 2864 } 2865 } 2866 } 2867 2868 SDOperand N0 = N->getOperand(0); 2869 SDOperand N1 = N->getOperand(1); 2870 // Normalize unary shuffle so the RHS is undef. 2871 if (isUnary && VecNum == 1) 2872 std::swap(N0, N1); 2873 2874 // If it is a splat, check if the argument vector is a build_vector with 2875 // all scalar elements the same. 2876 if (isSplat) { 2877 SDNode *V = N0.Val; 2878 if (V->getOpcode() == ISD::VBIT_CONVERT) 2879 V = V->getOperand(0).Val; 2880 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 2881 unsigned NumElems = V->getNumOperands()-2; 2882 if (NumElems > BaseIdx) { 2883 SDOperand Base; 2884 bool AllSame = true; 2885 for (unsigned i = 0; i != NumElems; ++i) { 2886 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 2887 Base = V->getOperand(i); 2888 break; 2889 } 2890 } 2891 // Splat of <u, u, u, u>, return <u, u, u, u> 2892 if (!Base.Val) 2893 return N0; 2894 for (unsigned i = 0; i != NumElems; ++i) { 2895 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 2896 V->getOperand(i) != Base) { 2897 AllSame = false; 2898 break; 2899 } 2900 } 2901 // Splat of <x, x, x, x>, return <x, x, x, x> 2902 if (AllSame) 2903 return N0; 2904 } 2905 } 2906 } 2907 2908 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 2909 // into an undef. 2910 if (isUnary || N0 == N1) { 2911 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 2912 // first operand. 2913 SmallVector<SDOperand, 8> MappedOps; 2914 for (unsigned i = 0; i != NumElts; ++i) { 2915 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 2916 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 2917 MappedOps.push_back(ShufMask.getOperand(i)); 2918 } else { 2919 unsigned NewIdx = 2920 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 2921 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 2922 } 2923 } 2924 // Add the type/#elts values. 2925 MappedOps.push_back(ShufMask.getOperand(NumElts)); 2926 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 2927 2928 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 2929 &MappedOps[0], MappedOps.size()); 2930 AddToWorkList(ShufMask.Val); 2931 2932 // Build the undef vector. 2933 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 2934 for (unsigned i = 0; i != NumElts; ++i) 2935 MappedOps[i] = UDVal; 2936 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 2937 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 2938 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 2939 &MappedOps[0], MappedOps.size()); 2940 2941 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 2942 N0, UDVal, ShufMask, 2943 MappedOps[NumElts], MappedOps[NumElts+1]); 2944 } 2945 2946 return SDOperand(); 2947} 2948 2949/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 2950/// a VAND to a vector_shuffle with the destination vector and a zero vector. 2951/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 2952/// vector_shuffle V, Zero, <0, 4, 2, 4> 2953SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 2954 SDOperand LHS = N->getOperand(0); 2955 SDOperand RHS = N->getOperand(1); 2956 if (N->getOpcode() == ISD::VAND) { 2957 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 2958 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 2959 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 2960 RHS = RHS.getOperand(0); 2961 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 2962 std::vector<SDOperand> IdxOps; 2963 unsigned NumOps = RHS.getNumOperands(); 2964 unsigned NumElts = NumOps-2; 2965 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 2966 for (unsigned i = 0; i != NumElts; ++i) { 2967 SDOperand Elt = RHS.getOperand(i); 2968 if (!isa<ConstantSDNode>(Elt)) 2969 return SDOperand(); 2970 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 2971 IdxOps.push_back(DAG.getConstant(i, EVT)); 2972 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 2973 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 2974 else 2975 return SDOperand(); 2976 } 2977 2978 // Let's see if the target supports this vector_shuffle. 2979 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 2980 return SDOperand(); 2981 2982 // Return the new VVECTOR_SHUFFLE node. 2983 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 2984 SDOperand EVTNode = DAG.getValueType(EVT); 2985 std::vector<SDOperand> Ops; 2986 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, 2987 EVTNode); 2988 Ops.push_back(LHS); 2989 AddToWorkList(LHS.Val); 2990 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 2991 ZeroOps.push_back(NumEltsNode); 2992 ZeroOps.push_back(EVTNode); 2993 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 2994 &ZeroOps[0], ZeroOps.size())); 2995 IdxOps.push_back(NumEltsNode); 2996 IdxOps.push_back(EVTNode); 2997 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 2998 &IdxOps[0], IdxOps.size())); 2999 Ops.push_back(NumEltsNode); 3000 Ops.push_back(EVTNode); 3001 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3002 &Ops[0], Ops.size()); 3003 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 3004 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 3005 DstVecSize, DstVecEVT); 3006 } 3007 return Result; 3008 } 3009 } 3010 return SDOperand(); 3011} 3012 3013/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 3014/// the scalar operation of the vop if it is operating on an integer vector 3015/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 3016SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 3017 ISD::NodeType FPOp) { 3018 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 3019 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 3020 SDOperand LHS = N->getOperand(0); 3021 SDOperand RHS = N->getOperand(1); 3022 SDOperand Shuffle = XformToShuffleWithZero(N); 3023 if (Shuffle.Val) return Shuffle; 3024 3025 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 3026 // this operation. 3027 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 3028 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3029 SmallVector<SDOperand, 8> Ops; 3030 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 3031 SDOperand LHSOp = LHS.getOperand(i); 3032 SDOperand RHSOp = RHS.getOperand(i); 3033 // If these two elements can't be folded, bail out. 3034 if ((LHSOp.getOpcode() != ISD::UNDEF && 3035 LHSOp.getOpcode() != ISD::Constant && 3036 LHSOp.getOpcode() != ISD::ConstantFP) || 3037 (RHSOp.getOpcode() != ISD::UNDEF && 3038 RHSOp.getOpcode() != ISD::Constant && 3039 RHSOp.getOpcode() != ISD::ConstantFP)) 3040 break; 3041 // Can't fold divide by zero. 3042 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 3043 if ((RHSOp.getOpcode() == ISD::Constant && 3044 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 3045 (RHSOp.getOpcode() == ISD::ConstantFP && 3046 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 3047 break; 3048 } 3049 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 3050 AddToWorkList(Ops.back().Val); 3051 assert((Ops.back().getOpcode() == ISD::UNDEF || 3052 Ops.back().getOpcode() == ISD::Constant || 3053 Ops.back().getOpcode() == ISD::ConstantFP) && 3054 "Scalar binop didn't fold!"); 3055 } 3056 3057 if (Ops.size() == LHS.getNumOperands()-2) { 3058 Ops.push_back(*(LHS.Val->op_end()-2)); 3059 Ops.push_back(*(LHS.Val->op_end()-1)); 3060 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 3061 } 3062 } 3063 3064 return SDOperand(); 3065} 3066 3067SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 3068 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 3069 3070 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 3071 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3072 // If we got a simplified select_cc node back from SimplifySelectCC, then 3073 // break it down into a new SETCC node, and a new SELECT node, and then return 3074 // the SELECT node, since we were called with a SELECT node. 3075 if (SCC.Val) { 3076 // Check to see if we got a select_cc back (to turn into setcc/select). 3077 // Otherwise, just return whatever node we got back, like fabs. 3078 if (SCC.getOpcode() == ISD::SELECT_CC) { 3079 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 3080 SCC.getOperand(0), SCC.getOperand(1), 3081 SCC.getOperand(4)); 3082 AddToWorkList(SETCC.Val); 3083 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 3084 SCC.getOperand(3), SETCC); 3085 } 3086 return SCC; 3087 } 3088 return SDOperand(); 3089} 3090 3091/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 3092/// are the two values being selected between, see if we can simplify the 3093/// select. Callers of this should assume that TheSelect is deleted if this 3094/// returns true. As such, they should return the appropriate thing (e.g. the 3095/// node) back to the top-level of the DAG combiner loop to avoid it being 3096/// looked at. 3097/// 3098bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 3099 SDOperand RHS) { 3100 3101 // If this is a select from two identical things, try to pull the operation 3102 // through the select. 3103 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 3104#if 0 3105 std::cerr << "SELECT: ["; LHS.Val->dump(); 3106 std::cerr << "] ["; RHS.Val->dump(); 3107 std::cerr << "]\n"; 3108#endif 3109 3110 // If this is a load and the token chain is identical, replace the select 3111 // of two loads with a load through a select of the address to load from. 3112 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 3113 // constants have been dropped into the constant pool. 3114 if ((LHS.getOpcode() == ISD::LOAD || 3115 LHS.getOpcode() == ISD::EXTLOAD || 3116 LHS.getOpcode() == ISD::ZEXTLOAD || 3117 LHS.getOpcode() == ISD::SEXTLOAD) && 3118 // Token chains must be identical. 3119 LHS.getOperand(0) == RHS.getOperand(0) && 3120 // If this is an EXTLOAD, the VT's must match. 3121 (LHS.getOpcode() == ISD::LOAD || 3122 LHS.getOperand(3) == RHS.getOperand(3))) { 3123 // FIXME: this conflates two src values, discarding one. This is not 3124 // the right thing to do, but nothing uses srcvalues now. When they do, 3125 // turn SrcValue into a list of locations. 3126 SDOperand Addr; 3127 if (TheSelect->getOpcode() == ISD::SELECT) 3128 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 3129 TheSelect->getOperand(0), LHS.getOperand(1), 3130 RHS.getOperand(1)); 3131 else 3132 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 3133 TheSelect->getOperand(0), 3134 TheSelect->getOperand(1), 3135 LHS.getOperand(1), RHS.getOperand(1), 3136 TheSelect->getOperand(4)); 3137 3138 SDOperand Load; 3139 if (LHS.getOpcode() == ISD::LOAD) 3140 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 3141 Addr, LHS.getOperand(2)); 3142 else 3143 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 3144 LHS.getOperand(0), Addr, LHS.getOperand(2), 3145 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 3146 // Users of the select now use the result of the load. 3147 CombineTo(TheSelect, Load); 3148 3149 // Users of the old loads now use the new load's chain. We know the 3150 // old-load value is dead now. 3151 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 3152 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 3153 return true; 3154 } 3155 } 3156 3157 return false; 3158} 3159 3160SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 3161 SDOperand N2, SDOperand N3, 3162 ISD::CondCode CC) { 3163 3164 MVT::ValueType VT = N2.getValueType(); 3165 //ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 3166 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 3167 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 3168 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 3169 3170 // Determine if the condition we're dealing with is constant 3171 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 3172 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 3173 3174 // fold select_cc true, x, y -> x 3175 if (SCCC && SCCC->getValue()) 3176 return N2; 3177 // fold select_cc false, x, y -> y 3178 if (SCCC && SCCC->getValue() == 0) 3179 return N3; 3180 3181 // Check to see if we can simplify the select into an fabs node 3182 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 3183 // Allow either -0.0 or 0.0 3184 if (CFP->getValue() == 0.0) { 3185 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 3186 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 3187 N0 == N2 && N3.getOpcode() == ISD::FNEG && 3188 N2 == N3.getOperand(0)) 3189 return DAG.getNode(ISD::FABS, VT, N0); 3190 3191 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 3192 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 3193 N0 == N3 && N2.getOpcode() == ISD::FNEG && 3194 N2.getOperand(0) == N3) 3195 return DAG.getNode(ISD::FABS, VT, N3); 3196 } 3197 } 3198 3199 // Check to see if we can perform the "gzip trick", transforming 3200 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 3201 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 3202 MVT::isInteger(N0.getValueType()) && 3203 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 3204 MVT::ValueType XType = N0.getValueType(); 3205 MVT::ValueType AType = N2.getValueType(); 3206 if (XType >= AType) { 3207 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 3208 // single-bit constant. 3209 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 3210 unsigned ShCtV = Log2_64(N2C->getValue()); 3211 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 3212 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 3213 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 3214 AddToWorkList(Shift.Val); 3215 if (XType > AType) { 3216 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3217 AddToWorkList(Shift.Val); 3218 } 3219 return DAG.getNode(ISD::AND, AType, Shift, N2); 3220 } 3221 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3222 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3223 TLI.getShiftAmountTy())); 3224 AddToWorkList(Shift.Val); 3225 if (XType > AType) { 3226 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3227 AddToWorkList(Shift.Val); 3228 } 3229 return DAG.getNode(ISD::AND, AType, Shift, N2); 3230 } 3231 } 3232 3233 // fold select C, 16, 0 -> shl C, 4 3234 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 3235 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 3236 // Get a SetCC of the condition 3237 // FIXME: Should probably make sure that setcc is legal if we ever have a 3238 // target where it isn't. 3239 SDOperand Temp, SCC; 3240 // cast from setcc result type to select result type 3241 if (AfterLegalize) { 3242 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3243 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 3244 } else { 3245 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 3246 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 3247 } 3248 AddToWorkList(SCC.Val); 3249 AddToWorkList(Temp.Val); 3250 // shl setcc result by log2 n2c 3251 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 3252 DAG.getConstant(Log2_64(N2C->getValue()), 3253 TLI.getShiftAmountTy())); 3254 } 3255 3256 // Check to see if this is the equivalent of setcc 3257 // FIXME: Turn all of these into setcc if setcc if setcc is legal 3258 // otherwise, go ahead with the folds. 3259 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 3260 MVT::ValueType XType = N0.getValueType(); 3261 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 3262 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3263 if (Res.getValueType() != VT) 3264 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 3265 return Res; 3266 } 3267 3268 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 3269 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 3270 TLI.isOperationLegal(ISD::CTLZ, XType)) { 3271 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 3272 return DAG.getNode(ISD::SRL, XType, Ctlz, 3273 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 3274 TLI.getShiftAmountTy())); 3275 } 3276 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 3277 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 3278 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 3279 N0); 3280 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 3281 DAG.getConstant(~0ULL, XType)); 3282 return DAG.getNode(ISD::SRL, XType, 3283 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 3284 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3285 TLI.getShiftAmountTy())); 3286 } 3287 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 3288 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 3289 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 3290 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3291 TLI.getShiftAmountTy())); 3292 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 3293 } 3294 } 3295 3296 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 3297 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 3298 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 3299 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 3300 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 3301 MVT::ValueType XType = N0.getValueType(); 3302 if (SubC->isNullValue() && MVT::isInteger(XType)) { 3303 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3304 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3305 TLI.getShiftAmountTy())); 3306 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 3307 AddToWorkList(Shift.Val); 3308 AddToWorkList(Add.Val); 3309 return DAG.getNode(ISD::XOR, XType, Add, Shift); 3310 } 3311 } 3312 } 3313 3314 return SDOperand(); 3315} 3316 3317SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 3318 SDOperand N1, ISD::CondCode Cond, 3319 bool foldBooleans) { 3320 // These setcc operations always fold. 3321 switch (Cond) { 3322 default: break; 3323 case ISD::SETFALSE: 3324 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 3325 case ISD::SETTRUE: 3326 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 3327 } 3328 3329 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 3330 uint64_t C1 = N1C->getValue(); 3331 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 3332 uint64_t C0 = N0C->getValue(); 3333 3334 // Sign extend the operands if required 3335 if (ISD::isSignedIntSetCC(Cond)) { 3336 C0 = N0C->getSignExtended(); 3337 C1 = N1C->getSignExtended(); 3338 } 3339 3340 switch (Cond) { 3341 default: assert(0 && "Unknown integer setcc!"); 3342 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3343 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3344 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 3345 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 3346 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 3347 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 3348 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 3349 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 3350 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 3351 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 3352 } 3353 } else { 3354 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 3355 // equality comparison, then we're just comparing whether X itself is 3356 // zero. 3357 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 3358 N0.getOperand(0).getOpcode() == ISD::CTLZ && 3359 N0.getOperand(1).getOpcode() == ISD::Constant) { 3360 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 3361 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3362 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 3363 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 3364 // (srl (ctlz x), 5) == 0 -> X != 0 3365 // (srl (ctlz x), 5) != 1 -> X != 0 3366 Cond = ISD::SETNE; 3367 } else { 3368 // (srl (ctlz x), 5) != 0 -> X == 0 3369 // (srl (ctlz x), 5) == 1 -> X == 0 3370 Cond = ISD::SETEQ; 3371 } 3372 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 3373 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 3374 Zero, Cond); 3375 } 3376 } 3377 3378 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 3379 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 3380 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 3381 3382 // If the comparison constant has bits in the upper part, the 3383 // zero-extended value could never match. 3384 if (C1 & (~0ULL << InSize)) { 3385 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 3386 switch (Cond) { 3387 case ISD::SETUGT: 3388 case ISD::SETUGE: 3389 case ISD::SETEQ: return DAG.getConstant(0, VT); 3390 case ISD::SETULT: 3391 case ISD::SETULE: 3392 case ISD::SETNE: return DAG.getConstant(1, VT); 3393 case ISD::SETGT: 3394 case ISD::SETGE: 3395 // True if the sign bit of C1 is set. 3396 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 3397 case ISD::SETLT: 3398 case ISD::SETLE: 3399 // True if the sign bit of C1 isn't set. 3400 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 3401 default: 3402 break; 3403 } 3404 } 3405 3406 // Otherwise, we can perform the comparison with the low bits. 3407 switch (Cond) { 3408 case ISD::SETEQ: 3409 case ISD::SETNE: 3410 case ISD::SETUGT: 3411 case ISD::SETUGE: 3412 case ISD::SETULT: 3413 case ISD::SETULE: 3414 return DAG.getSetCC(VT, N0.getOperand(0), 3415 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 3416 Cond); 3417 default: 3418 break; // todo, be more careful with signed comparisons 3419 } 3420 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3421 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 3422 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 3423 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 3424 MVT::ValueType ExtDstTy = N0.getValueType(); 3425 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 3426 3427 // If the extended part has any inconsistent bits, it cannot ever 3428 // compare equal. In other words, they have to be all ones or all 3429 // zeros. 3430 uint64_t ExtBits = 3431 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 3432 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 3433 return DAG.getConstant(Cond == ISD::SETNE, VT); 3434 3435 SDOperand ZextOp; 3436 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 3437 if (Op0Ty == ExtSrcTy) { 3438 ZextOp = N0.getOperand(0); 3439 } else { 3440 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 3441 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 3442 DAG.getConstant(Imm, Op0Ty)); 3443 } 3444 AddToWorkList(ZextOp.Val); 3445 // Otherwise, make this a use of a zext. 3446 return DAG.getSetCC(VT, ZextOp, 3447 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 3448 ExtDstTy), 3449 Cond); 3450 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 3451 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3452 (N0.getOpcode() == ISD::XOR || 3453 (N0.getOpcode() == ISD::AND && 3454 N0.getOperand(0).getOpcode() == ISD::XOR && 3455 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 3456 isa<ConstantSDNode>(N0.getOperand(1)) && 3457 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 3458 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 3459 // only do this if the top bits are known zero. 3460 if (TLI.MaskedValueIsZero(N1, 3461 MVT::getIntVTBitMask(N0.getValueType())-1)) { 3462 // Okay, get the un-inverted input value. 3463 SDOperand Val; 3464 if (N0.getOpcode() == ISD::XOR) 3465 Val = N0.getOperand(0); 3466 else { 3467 assert(N0.getOpcode() == ISD::AND && 3468 N0.getOperand(0).getOpcode() == ISD::XOR); 3469 // ((X^1)&1)^1 -> X & 1 3470 Val = DAG.getNode(ISD::AND, N0.getValueType(), 3471 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 3472 } 3473 return DAG.getSetCC(VT, Val, N1, 3474 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 3475 } 3476 } 3477 3478 uint64_t MinVal, MaxVal; 3479 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 3480 if (ISD::isSignedIntSetCC(Cond)) { 3481 MinVal = 1ULL << (OperandBitSize-1); 3482 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 3483 MaxVal = ~0ULL >> (65-OperandBitSize); 3484 else 3485 MaxVal = 0; 3486 } else { 3487 MinVal = 0; 3488 MaxVal = ~0ULL >> (64-OperandBitSize); 3489 } 3490 3491 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 3492 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 3493 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 3494 --C1; // X >= C0 --> X > (C0-1) 3495 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3496 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 3497 } 3498 3499 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 3500 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 3501 ++C1; // X <= C0 --> X < (C0+1) 3502 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3503 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 3504 } 3505 3506 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 3507 return DAG.getConstant(0, VT); // X < MIN --> false 3508 3509 // Canonicalize setgt X, Min --> setne X, Min 3510 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 3511 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3512 // Canonicalize setlt X, Max --> setne X, Max 3513 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 3514 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3515 3516 // If we have setult X, 1, turn it into seteq X, 0 3517 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 3518 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 3519 ISD::SETEQ); 3520 // If we have setugt X, Max-1, turn it into seteq X, Max 3521 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 3522 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 3523 ISD::SETEQ); 3524 3525 // If we have "setcc X, C0", check to see if we can shrink the immediate 3526 // by changing cc. 3527 3528 // SETUGT X, SINTMAX -> SETLT X, 0 3529 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 3530 C1 == (~0ULL >> (65-OperandBitSize))) 3531 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 3532 ISD::SETLT); 3533 3534 // FIXME: Implement the rest of these. 3535 3536 // Fold bit comparisons when we can. 3537 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3538 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 3539 if (ConstantSDNode *AndRHS = 3540 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3541 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 3542 // Perform the xform if the AND RHS is a single bit. 3543 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 3544 return DAG.getNode(ISD::SRL, VT, N0, 3545 DAG.getConstant(Log2_64(AndRHS->getValue()), 3546 TLI.getShiftAmountTy())); 3547 } 3548 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 3549 // (X & 8) == 8 --> (X & 8) >> 3 3550 // Perform the xform if C1 is a single bit. 3551 if ((C1 & (C1-1)) == 0) { 3552 return DAG.getNode(ISD::SRL, VT, N0, 3553 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 3554 } 3555 } 3556 } 3557 } 3558 } else if (isa<ConstantSDNode>(N0.Val)) { 3559 // Ensure that the constant occurs on the RHS. 3560 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3561 } 3562 3563 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 3564 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 3565 double C0 = N0C->getValue(), C1 = N1C->getValue(); 3566 3567 switch (Cond) { 3568 default: break; // FIXME: Implement the rest of these! 3569 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3570 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3571 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 3572 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 3573 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 3574 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 3575 } 3576 } else { 3577 // Ensure that the constant occurs on the RHS. 3578 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3579 } 3580 3581 if (N0 == N1) { 3582 // We can always fold X == Y for integer setcc's. 3583 if (MVT::isInteger(N0.getValueType())) 3584 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3585 unsigned UOF = ISD::getUnorderedFlavor(Cond); 3586 if (UOF == 2) // FP operators that are undefined on NaNs. 3587 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3588 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 3589 return DAG.getConstant(UOF, VT); 3590 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 3591 // if it is not already. 3592 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 3593 if (NewCond != Cond) 3594 return DAG.getSetCC(VT, N0, N1, NewCond); 3595 } 3596 3597 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3598 MVT::isInteger(N0.getValueType())) { 3599 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 3600 N0.getOpcode() == ISD::XOR) { 3601 // Simplify (X+Y) == (X+Z) --> Y == Z 3602 if (N0.getOpcode() == N1.getOpcode()) { 3603 if (N0.getOperand(0) == N1.getOperand(0)) 3604 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 3605 if (N0.getOperand(1) == N1.getOperand(1)) 3606 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 3607 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 3608 // If X op Y == Y op X, try other combinations. 3609 if (N0.getOperand(0) == N1.getOperand(1)) 3610 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 3611 if (N0.getOperand(1) == N1.getOperand(0)) 3612 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 3613 } 3614 } 3615 3616 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 3617 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3618 // Turn (X+C1) == C2 --> X == C2-C1 3619 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 3620 return DAG.getSetCC(VT, N0.getOperand(0), 3621 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 3622 N0.getValueType()), Cond); 3623 } 3624 3625 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 3626 if (N0.getOpcode() == ISD::XOR) 3627 // If we know that all of the inverted bits are zero, don't bother 3628 // performing the inversion. 3629 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 3630 return DAG.getSetCC(VT, N0.getOperand(0), 3631 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 3632 N0.getValueType()), Cond); 3633 } 3634 3635 // Turn (C1-X) == C2 --> X == C1-C2 3636 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 3637 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 3638 return DAG.getSetCC(VT, N0.getOperand(1), 3639 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 3640 N0.getValueType()), Cond); 3641 } 3642 } 3643 } 3644 3645 // Simplify (X+Z) == X --> Z == 0 3646 if (N0.getOperand(0) == N1) 3647 return DAG.getSetCC(VT, N0.getOperand(1), 3648 DAG.getConstant(0, N0.getValueType()), Cond); 3649 if (N0.getOperand(1) == N1) { 3650 if (DAG.isCommutativeBinOp(N0.getOpcode())) 3651 return DAG.getSetCC(VT, N0.getOperand(0), 3652 DAG.getConstant(0, N0.getValueType()), Cond); 3653 else { 3654 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 3655 // (Z-X) == X --> Z == X<<1 3656 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 3657 N1, 3658 DAG.getConstant(1,TLI.getShiftAmountTy())); 3659 AddToWorkList(SH.Val); 3660 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 3661 } 3662 } 3663 } 3664 3665 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 3666 N1.getOpcode() == ISD::XOR) { 3667 // Simplify X == (X+Z) --> Z == 0 3668 if (N1.getOperand(0) == N0) { 3669 return DAG.getSetCC(VT, N1.getOperand(1), 3670 DAG.getConstant(0, N1.getValueType()), Cond); 3671 } else if (N1.getOperand(1) == N0) { 3672 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 3673 return DAG.getSetCC(VT, N1.getOperand(0), 3674 DAG.getConstant(0, N1.getValueType()), Cond); 3675 } else { 3676 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 3677 // X == (Z-X) --> X<<1 == Z 3678 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 3679 DAG.getConstant(1,TLI.getShiftAmountTy())); 3680 AddToWorkList(SH.Val); 3681 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 3682 } 3683 } 3684 } 3685 } 3686 3687 // Fold away ALL boolean setcc's. 3688 SDOperand Temp; 3689 if (N0.getValueType() == MVT::i1 && foldBooleans) { 3690 switch (Cond) { 3691 default: assert(0 && "Unknown integer setcc!"); 3692 case ISD::SETEQ: // X == Y -> (X^Y)^1 3693 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3694 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 3695 AddToWorkList(Temp.Val); 3696 break; 3697 case ISD::SETNE: // X != Y --> (X^Y) 3698 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3699 break; 3700 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 3701 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 3702 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3703 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 3704 AddToWorkList(Temp.Val); 3705 break; 3706 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 3707 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 3708 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3709 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 3710 AddToWorkList(Temp.Val); 3711 break; 3712 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 3713 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 3714 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3715 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 3716 AddToWorkList(Temp.Val); 3717 break; 3718 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 3719 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 3720 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3721 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 3722 break; 3723 } 3724 if (VT != MVT::i1) { 3725 AddToWorkList(N0.Val); 3726 // FIXME: If running after legalize, we probably can't do this. 3727 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3728 } 3729 return N0; 3730 } 3731 3732 // Could not fold it. 3733 return SDOperand(); 3734} 3735 3736/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3737/// return a DAG expression to select that will generate the same value by 3738/// multiplying by a magic number. See: 3739/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3740SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 3741 std::vector<SDNode*> Built; 3742 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 3743 3744 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 3745 ii != ee; ++ii) 3746 AddToWorkList(*ii); 3747 return S; 3748} 3749 3750/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3751/// return a DAG expression to select that will generate the same value by 3752/// multiplying by a magic number. See: 3753/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3754SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 3755 std::vector<SDNode*> Built; 3756 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 3757 3758 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 3759 ii != ee; ++ii) 3760 AddToWorkList(*ii); 3761 return S; 3762} 3763 3764// SelectionDAG::Combine - This is the entry point for the file. 3765// 3766void SelectionDAG::Combine(bool RunningAfterLegalize) { 3767 /// run - This is the main entry point to this class. 3768 /// 3769 DAGCombiner(*this).Run(RunningAfterLegalize); 3770} 3771