DAGCombiner.cpp revision 67a44cd3aa26003a6bc2cd755516c9cc12c36ca0
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: Should add a corresponding version of fold AND with 20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 21// we don't have yet. 22// 23// FIXME: select C, pow2, pow2 -> something smart 24// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 25// FIXME: (select C, load A, load B) -> load (select C, A, B) 26// FIXME: Dead stores -> nuke 27// FIXME: shr X, (and Y,31) -> shr X, Y 28// FIXME: TRUNC (LOAD) -> EXT_LOAD/LOAD(smaller) 29// FIXME: mul (x, const) -> shifts + adds 30// FIXME: undef values 31// FIXME: make truncate see through SIGN_EXTEND and AND 32// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 33// FIXME: verify that getNode can't return extends with an operand whose type 34// is >= to that of the extend. 35// FIXME: divide by zero is currently left unfolded. do we want to turn this 36// into an undef? 37// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 38// FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use 39// 40//===----------------------------------------------------------------------===// 41 42#define DEBUG_TYPE "dagcombine" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/MathExtras.h" 47#include "llvm/Target/TargetLowering.h" 48#include <algorithm> 49#include <cmath> 50using namespace llvm; 51 52namespace { 53 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 54 55 class DAGCombiner { 56 SelectionDAG &DAG; 57 TargetLowering &TLI; 58 bool AfterLegalize; 59 60 // Worklist of all of the nodes that need to be simplified. 61 std::vector<SDNode*> WorkList; 62 63 /// AddUsersToWorkList - When an instruction is simplified, add all users of 64 /// the instruction to the work lists because they might get more simplified 65 /// now. 66 /// 67 void AddUsersToWorkList(SDNode *N) { 68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 69 UI != UE; ++UI) 70 WorkList.push_back(*UI); 71 } 72 73 /// removeFromWorkList - remove all instances of N from the worklist. 74 void removeFromWorkList(SDNode *N) { 75 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 76 WorkList.end()); 77 } 78 79 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 80 ++NodesCombined; 81 DEBUG(std::cerr << "\nReplacing "; N->dump(); 82 std::cerr << "\nWith: "; To[0].Val->dump(); 83 std::cerr << " and " << To.size()-1 << " other values\n"); 84 std::vector<SDNode*> NowDead; 85 DAG.ReplaceAllUsesWith(N, To, &NowDead); 86 87 // Push the new nodes and any users onto the worklist 88 for (unsigned i = 0, e = To.size(); i != e; ++i) { 89 WorkList.push_back(To[i].Val); 90 AddUsersToWorkList(To[i].Val); 91 } 92 93 // Nodes can end up on the worklist more than once. Make sure we do 94 // not process a node that has been replaced. 95 removeFromWorkList(N); 96 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 97 removeFromWorkList(NowDead[i]); 98 99 // Finally, since the node is now dead, remove it from the graph. 100 DAG.DeleteNode(N); 101 return SDOperand(N, 0); 102 } 103 104 SDOperand CombineTo(SDNode *N, SDOperand Res) { 105 std::vector<SDOperand> To; 106 To.push_back(Res); 107 return CombineTo(N, To); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 111 std::vector<SDOperand> To; 112 To.push_back(Res0); 113 To.push_back(Res1); 114 return CombineTo(N, To); 115 } 116 117 /// visit - call the node-specific routine that knows how to fold each 118 /// particular type of node. 119 SDOperand visit(SDNode *N); 120 121 // Visitation implementation - Implement dag node combining for different 122 // node types. The semantics are as follows: 123 // Return Value: 124 // SDOperand.Val == 0 - No change was made 125 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 126 // otherwise - N should be replaced by the returned Operand. 127 // 128 SDOperand visitTokenFactor(SDNode *N); 129 SDOperand visitADD(SDNode *N); 130 SDOperand visitSUB(SDNode *N); 131 SDOperand visitMUL(SDNode *N); 132 SDOperand visitSDIV(SDNode *N); 133 SDOperand visitUDIV(SDNode *N); 134 SDOperand visitSREM(SDNode *N); 135 SDOperand visitUREM(SDNode *N); 136 SDOperand visitMULHU(SDNode *N); 137 SDOperand visitMULHS(SDNode *N); 138 SDOperand visitAND(SDNode *N); 139 SDOperand visitOR(SDNode *N); 140 SDOperand visitXOR(SDNode *N); 141 SDOperand visitSHL(SDNode *N); 142 SDOperand visitSRA(SDNode *N); 143 SDOperand visitSRL(SDNode *N); 144 SDOperand visitCTLZ(SDNode *N); 145 SDOperand visitCTTZ(SDNode *N); 146 SDOperand visitCTPOP(SDNode *N); 147 SDOperand visitSELECT(SDNode *N); 148 SDOperand visitSELECT_CC(SDNode *N); 149 SDOperand visitSETCC(SDNode *N); 150 SDOperand visitSIGN_EXTEND(SDNode *N); 151 SDOperand visitZERO_EXTEND(SDNode *N); 152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 153 SDOperand visitTRUNCATE(SDNode *N); 154 155 SDOperand visitFADD(SDNode *N); 156 SDOperand visitFSUB(SDNode *N); 157 SDOperand visitFMUL(SDNode *N); 158 SDOperand visitFDIV(SDNode *N); 159 SDOperand visitFREM(SDNode *N); 160 SDOperand visitSINT_TO_FP(SDNode *N); 161 SDOperand visitUINT_TO_FP(SDNode *N); 162 SDOperand visitFP_TO_SINT(SDNode *N); 163 SDOperand visitFP_TO_UINT(SDNode *N); 164 SDOperand visitFP_ROUND(SDNode *N); 165 SDOperand visitFP_ROUND_INREG(SDNode *N); 166 SDOperand visitFP_EXTEND(SDNode *N); 167 SDOperand visitFNEG(SDNode *N); 168 SDOperand visitFABS(SDNode *N); 169 SDOperand visitBRCOND(SDNode *N); 170 SDOperand visitBRCONDTWOWAY(SDNode *N); 171 SDOperand visitBR_CC(SDNode *N); 172 SDOperand visitBRTWOWAY_CC(SDNode *N); 173 174 SDOperand visitLOAD(SDNode *N); 175 SDOperand visitSTORE(SDNode *N); 176 177 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 178 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 179 SDOperand N3, ISD::CondCode CC); 180 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 181 ISD::CondCode Cond, bool foldBooleans = true); 182public: 183 DAGCombiner(SelectionDAG &D) 184 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 185 186 /// Run - runs the dag combiner on all nodes in the work list 187 void Run(bool RunningAfterLegalize); 188 }; 189} 190 191/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use 192/// this predicate to simplify operations downstream. Op and Mask are known to 193/// be the same type. 194static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 195 const TargetLowering &TLI) { 196 unsigned SrcBits; 197 if (Mask == 0) return true; 198 199 // If we know the result of a setcc has the top bits zero, use this info. 200 switch (Op.getOpcode()) { 201 case ISD::Constant: 202 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 203 case ISD::SETCC: 204 return ((Mask & 1) == 0) && 205 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 206 case ISD::ZEXTLOAD: 207 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 208 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 209 case ISD::ZERO_EXTEND: 210 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 211 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 212 case ISD::AssertZext: 213 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 214 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 215 case ISD::AND: 216 // If either of the operands has zero bits, the result will too. 217 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) || 218 MaskedValueIsZero(Op.getOperand(0), Mask, TLI)) 219 return true; 220 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 221 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 222 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 223 return false; 224 case ISD::OR: 225 case ISD::XOR: 226 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 227 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 228 case ISD::SELECT: 229 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 230 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 231 case ISD::SELECT_CC: 232 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 233 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 234 case ISD::SRL: 235 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 236 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 237 uint64_t NewVal = Mask << ShAmt->getValue(); 238 SrcBits = MVT::getSizeInBits(Op.getValueType()); 239 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 240 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 241 } 242 return false; 243 case ISD::SHL: 244 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 245 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 246 uint64_t NewVal = Mask >> ShAmt->getValue(); 247 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 248 } 249 return false; 250 case ISD::ADD: 251 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits. 252 if ((Mask&(Mask+1)) == 0) { // All low bits 253 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 254 MaskedValueIsZero(Op.getOperand(1), Mask, TLI)) 255 return true; 256 } 257 break; 258 case ISD::SUB: 259 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 260 // We know that the top bits of C-X are clear if X contains less bits 261 // than C (i.e. no wrap-around can happen). For example, 20-X is 262 // positive if we can prove that X is >= 0 and < 16. 263 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0)); 264 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear 265 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 266 uint64_t MaskV = (1ULL << (63-NLZ))-1; 267 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) { 268 // High bits are clear this value is known to be >= C. 269 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 270 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0) 271 return true; 272 } 273 } 274 } 275 break; 276 case ISD::CTTZ: 277 case ISD::CTLZ: 278 case ISD::CTPOP: 279 // Bit counting instructions can not set the high bits of the result 280 // register. The max number of bits sets depends on the input. 281 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 282 default: break; 283 } 284 return false; 285} 286 287// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 288// that selects between the values 1 and 0, making it equivalent to a setcc. 289// Also, set the incoming LHS, RHS, and CC references to the appropriate 290// nodes based on the type of node we are checking. This simplifies life a 291// bit for the callers. 292static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 293 SDOperand &CC) { 294 if (N.getOpcode() == ISD::SETCC) { 295 LHS = N.getOperand(0); 296 RHS = N.getOperand(1); 297 CC = N.getOperand(2); 298 return true; 299 } 300 if (N.getOpcode() == ISD::SELECT_CC && 301 N.getOperand(2).getOpcode() == ISD::Constant && 302 N.getOperand(3).getOpcode() == ISD::Constant && 303 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 304 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 305 LHS = N.getOperand(0); 306 RHS = N.getOperand(1); 307 CC = N.getOperand(4); 308 return true; 309 } 310 return false; 311} 312 313// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 314// one use. If this is true, it allows the users to invert the operation for 315// free when it is profitable to do so. 316static bool isOneUseSetCC(SDOperand N) { 317 SDOperand N0, N1, N2; 318 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 319 return true; 320 return false; 321} 322 323// FIXME: This should probably go in the ISD class rather than being duplicated 324// in several files. 325static bool isCommutativeBinOp(unsigned Opcode) { 326 switch (Opcode) { 327 case ISD::ADD: 328 case ISD::MUL: 329 case ISD::AND: 330 case ISD::OR: 331 case ISD::XOR: return true; 332 default: return false; // FIXME: Need commutative info for user ops! 333 } 334} 335 336void DAGCombiner::Run(bool RunningAfterLegalize) { 337 // set the instance variable, so that the various visit routines may use it. 338 AfterLegalize = RunningAfterLegalize; 339 340 // Add all the dag nodes to the worklist. 341 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end()); 342 343 // Create a dummy node (which is not added to allnodes), that adds a reference 344 // to the root node, preventing it from being deleted, and tracking any 345 // changes of the root. 346 HandleSDNode Dummy(DAG.getRoot()); 347 348 // while the worklist isn't empty, inspect the node on the end of it and 349 // try and combine it. 350 while (!WorkList.empty()) { 351 SDNode *N = WorkList.back(); 352 WorkList.pop_back(); 353 354 // If N has no uses, it is dead. Make sure to revisit all N's operands once 355 // N is deleted from the DAG, since they too may now be dead or may have a 356 // reduced number of uses, allowing other xforms. 357 if (N->use_empty() && N != &Dummy) { 358 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 359 WorkList.push_back(N->getOperand(i).Val); 360 361 removeFromWorkList(N); 362 DAG.DeleteNode(N); 363 continue; 364 } 365 366 SDOperand RV = visit(N); 367 if (RV.Val) { 368 ++NodesCombined; 369 // If we get back the same node we passed in, rather than a new node or 370 // zero, we know that the node must have defined multiple values and 371 // CombineTo was used. Since CombineTo takes care of the worklist 372 // mechanics for us, we have no work to do in this case. 373 if (RV.Val != N) { 374 DEBUG(std::cerr << "\nReplacing "; N->dump(); 375 std::cerr << "\nWith: "; RV.Val->dump(); 376 std::cerr << '\n'); 377 std::vector<SDNode*> NowDead; 378 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 379 380 // Push the new node and any users onto the worklist 381 WorkList.push_back(RV.Val); 382 AddUsersToWorkList(RV.Val); 383 384 // Nodes can end up on the worklist more than once. Make sure we do 385 // not process a node that has been replaced. 386 removeFromWorkList(N); 387 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 388 removeFromWorkList(NowDead[i]); 389 390 // Finally, since the node is now dead, remove it from the graph. 391 DAG.DeleteNode(N); 392 } 393 } 394 } 395 396 // If the root changed (e.g. it was a dead load, update the root). 397 DAG.setRoot(Dummy.getValue()); 398} 399 400SDOperand DAGCombiner::visit(SDNode *N) { 401 switch(N->getOpcode()) { 402 default: break; 403 case ISD::TokenFactor: return visitTokenFactor(N); 404 case ISD::ADD: return visitADD(N); 405 case ISD::SUB: return visitSUB(N); 406 case ISD::MUL: return visitMUL(N); 407 case ISD::SDIV: return visitSDIV(N); 408 case ISD::UDIV: return visitUDIV(N); 409 case ISD::SREM: return visitSREM(N); 410 case ISD::UREM: return visitUREM(N); 411 case ISD::MULHU: return visitMULHU(N); 412 case ISD::MULHS: return visitMULHS(N); 413 case ISD::AND: return visitAND(N); 414 case ISD::OR: return visitOR(N); 415 case ISD::XOR: return visitXOR(N); 416 case ISD::SHL: return visitSHL(N); 417 case ISD::SRA: return visitSRA(N); 418 case ISD::SRL: return visitSRL(N); 419 case ISD::CTLZ: return visitCTLZ(N); 420 case ISD::CTTZ: return visitCTTZ(N); 421 case ISD::CTPOP: return visitCTPOP(N); 422 case ISD::SELECT: return visitSELECT(N); 423 case ISD::SELECT_CC: return visitSELECT_CC(N); 424 case ISD::SETCC: return visitSETCC(N); 425 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 426 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 427 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 428 case ISD::TRUNCATE: return visitTRUNCATE(N); 429 case ISD::FADD: return visitFADD(N); 430 case ISD::FSUB: return visitFSUB(N); 431 case ISD::FMUL: return visitFMUL(N); 432 case ISD::FDIV: return visitFDIV(N); 433 case ISD::FREM: return visitFREM(N); 434 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 435 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 436 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 437 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 438 case ISD::FP_ROUND: return visitFP_ROUND(N); 439 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 440 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 441 case ISD::FNEG: return visitFNEG(N); 442 case ISD::FABS: return visitFABS(N); 443 case ISD::BRCOND: return visitBRCOND(N); 444 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 445 case ISD::BR_CC: return visitBR_CC(N); 446 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 447 case ISD::LOAD: return visitLOAD(N); 448 case ISD::STORE: return visitSTORE(N); 449 } 450 return SDOperand(); 451} 452 453SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 454 std::vector<SDOperand> Ops; 455 bool Changed = false; 456 457 // If the token factor has two operands and one is the entry token, replace 458 // the token factor with the other operand. 459 if (N->getNumOperands() == 2) { 460 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 461 return N->getOperand(1); 462 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 463 return N->getOperand(0); 464 } 465 // fold (tokenfactor (tokenfactor)) -> tokenfactor 466 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 467 SDOperand Op = N->getOperand(i); 468 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 469 Changed = true; 470 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 471 Ops.push_back(Op.getOperand(j)); 472 } else { 473 Ops.push_back(Op); 474 } 475 } 476 if (Changed) 477 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 478 return SDOperand(); 479} 480 481SDOperand DAGCombiner::visitADD(SDNode *N) { 482 SDOperand N0 = N->getOperand(0); 483 SDOperand N1 = N->getOperand(1); 484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 486 MVT::ValueType VT = N0.getValueType(); 487 488 // fold (add c1, c2) -> c1+c2 489 if (N0C && N1C) 490 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); 491 // canonicalize constant to RHS 492 if (N0C && !N1C) { 493 std::swap(N0, N1); 494 std::swap(N0C, N1C); 495 } 496 // fold (add x, 0) -> x 497 if (N1C && N1C->isNullValue()) 498 return N0; 499 // fold (add (add x, c1), c2) -> (add x, c1+c2) 500 if (N1C && N0.getOpcode() == ISD::ADD) { 501 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 502 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 503 if (N00C) 504 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1), 505 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT)); 506 if (N01C) 507 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0), 508 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT)); 509 } 510 // fold ((0-A) + B) -> B-A 511 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 512 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 513 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 514 // fold (A + (0-B)) -> A-B 515 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 516 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 517 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 518 // fold (A+(B-A)) -> B 519 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 520 return N1.getOperand(0); 521 return SDOperand(); 522} 523 524SDOperand DAGCombiner::visitSUB(SDNode *N) { 525 SDOperand N0 = N->getOperand(0); 526 SDOperand N1 = N->getOperand(1); 527 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 528 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 529 530 // fold (sub c1, c2) -> c1-c2 531 if (N0C && N1C) 532 return DAG.getConstant(N0C->getValue() - N1C->getValue(), 533 N->getValueType(0)); 534 // fold (sub x, c) -> (add x, -c) 535 if (N1C) 536 return DAG.getNode(ISD::ADD, N0.getValueType(), N0, 537 DAG.getConstant(-N1C->getValue(), N0.getValueType())); 538 539 // fold (A+B)-A -> B 540 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 541 return N0.getOperand(1); 542 // fold (A+B)-B -> A 543 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 544 return N0.getOperand(0); 545 return SDOperand(); 546} 547 548SDOperand DAGCombiner::visitMUL(SDNode *N) { 549 SDOperand N0 = N->getOperand(0); 550 SDOperand N1 = N->getOperand(1); 551 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 552 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 553 MVT::ValueType VT = N0.getValueType(); 554 555 // fold (mul c1, c2) -> c1*c2 556 if (N0C && N1C) 557 return DAG.getConstant(N0C->getValue() * N1C->getValue(), 558 N->getValueType(0)); 559 // canonicalize constant to RHS 560 if (N0C && !N1C) { 561 std::swap(N0, N1); 562 std::swap(N0C, N1C); 563 } 564 // fold (mul x, 0) -> 0 565 if (N1C && N1C->isNullValue()) 566 return N1; 567 // fold (mul x, -1) -> 0-x 568 if (N1C && N1C->isAllOnesValue()) 569 return DAG.getNode(ISD::SUB, N->getValueType(0), 570 DAG.getConstant(0, N->getValueType(0)), N0); 571 // fold (mul x, (1 << c)) -> x << c 572 if (N1C && isPowerOf2_64(N1C->getValue())) 573 return DAG.getNode(ISD::SHL, N->getValueType(0), N0, 574 DAG.getConstant(Log2_64(N1C->getValue()), 575 TLI.getShiftAmountTy())); 576 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2) 577 if (N1C && N0.getOpcode() == ISD::MUL) { 578 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 579 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 580 if (N00C) 581 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1), 582 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT)); 583 if (N01C) 584 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), 585 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT)); 586 } 587 return SDOperand(); 588} 589 590SDOperand DAGCombiner::visitSDIV(SDNode *N) { 591 SDOperand N0 = N->getOperand(0); 592 SDOperand N1 = N->getOperand(1); 593 MVT::ValueType VT = N->getValueType(0); 594 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 595 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 596 597 // fold (sdiv c1, c2) -> c1/c2 598 if (N0C && N1C && !N1C->isNullValue()) 599 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(), 600 N->getValueType(0)); 601 // If we know the sign bits of both operands are zero, strength reduce to a 602 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 603 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 604 if (MaskedValueIsZero(N1, SignBit, TLI) && 605 MaskedValueIsZero(N0, SignBit, TLI)) 606 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 607 return SDOperand(); 608} 609 610SDOperand DAGCombiner::visitUDIV(SDNode *N) { 611 SDOperand N0 = N->getOperand(0); 612 SDOperand N1 = N->getOperand(1); 613 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 614 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 615 616 // fold (udiv c1, c2) -> c1/c2 617 if (N0C && N1C && !N1C->isNullValue()) 618 return DAG.getConstant(N0C->getValue() / N1C->getValue(), 619 N->getValueType(0)); 620 // fold (udiv x, (1 << c)) -> x >>u c 621 if (N1C && isPowerOf2_64(N1C->getValue())) 622 return DAG.getNode(ISD::SRL, N->getValueType(0), N0, 623 DAG.getConstant(Log2_64(N1C->getValue()), 624 TLI.getShiftAmountTy())); 625 return SDOperand(); 626} 627 628SDOperand DAGCombiner::visitSREM(SDNode *N) { 629 SDOperand N0 = N->getOperand(0); 630 SDOperand N1 = N->getOperand(1); 631 MVT::ValueType VT = N->getValueType(0); 632 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 633 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 634 635 // fold (srem c1, c2) -> c1%c2 636 if (N0C && N1C && !N1C->isNullValue()) 637 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(), 638 N->getValueType(0)); 639 // If we know the sign bits of both operands are zero, strength reduce to a 640 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 641 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 642 if (MaskedValueIsZero(N1, SignBit, TLI) && 643 MaskedValueIsZero(N0, SignBit, TLI)) 644 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1); 645 return SDOperand(); 646} 647 648SDOperand DAGCombiner::visitUREM(SDNode *N) { 649 SDOperand N0 = N->getOperand(0); 650 SDOperand N1 = N->getOperand(1); 651 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 652 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 653 654 // fold (urem c1, c2) -> c1%c2 655 if (N0C && N1C && !N1C->isNullValue()) 656 return DAG.getConstant(N0C->getValue() % N1C->getValue(), 657 N->getValueType(0)); 658 // fold (urem x, pow2) -> (and x, pow2-1) 659 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 660 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 661 DAG.getConstant(N1C->getValue()-1, N1.getValueType())); 662 return SDOperand(); 663} 664 665SDOperand DAGCombiner::visitMULHS(SDNode *N) { 666 SDOperand N0 = N->getOperand(0); 667 SDOperand N1 = N->getOperand(1); 668 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 669 670 // fold (mulhs x, 0) -> 0 671 if (N1C && N1C->isNullValue()) 672 return N1; 673 // fold (mulhs x, 1) -> (sra x, size(x)-1) 674 if (N1C && N1C->getValue() == 1) 675 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 676 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 677 TLI.getShiftAmountTy())); 678 return SDOperand(); 679} 680 681SDOperand DAGCombiner::visitMULHU(SDNode *N) { 682 SDOperand N0 = N->getOperand(0); 683 SDOperand N1 = N->getOperand(1); 684 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 685 686 // fold (mulhu x, 0) -> 0 687 if (N1C && N1C->isNullValue()) 688 return N1; 689 // fold (mulhu x, 1) -> 0 690 if (N1C && N1C->getValue() == 1) 691 return DAG.getConstant(0, N0.getValueType()); 692 return SDOperand(); 693} 694 695SDOperand DAGCombiner::visitAND(SDNode *N) { 696 SDOperand N0 = N->getOperand(0); 697 SDOperand N1 = N->getOperand(1); 698 SDOperand LL, LR, RL, RR, CC0, CC1; 699 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 700 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 701 MVT::ValueType VT = N1.getValueType(); 702 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 703 704 // fold (and c1, c2) -> c1&c2 705 if (N0C && N1C) 706 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT); 707 // canonicalize constant to RHS 708 if (N0C && !N1C) { 709 std::swap(N0, N1); 710 std::swap(N0C, N1C); 711 } 712 // fold (and x, -1) -> x 713 if (N1C && N1C->isAllOnesValue()) 714 return N0; 715 // if (and x, c) is known to be zero, return 0 716 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 717 return DAG.getConstant(0, VT); 718 // fold (and x, c) -> x iff (x & ~c) == 0 719 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 720 TLI)) 721 return N0; 722 // fold (and (and x, c1), c2) -> (and x, c1^c2) 723 if (N1C && N0.getOpcode() == ISD::AND) { 724 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 725 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 726 if (N00C) 727 return DAG.getNode(ISD::AND, VT, N0.getOperand(1), 728 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT)); 729 if (N01C) 730 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 731 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT)); 732 } 733 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 734 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { 735 unsigned ExtendBits = 736 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT()); 737 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0) 738 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1); 739 } 740 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 741 if (N0.getOpcode() == ISD::OR && N1C) 742 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 743 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 744 return N1; 745 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 746 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 747 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 748 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 749 750 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 751 MVT::isInteger(LL.getValueType())) { 752 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 753 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 754 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 755 WorkList.push_back(ORNode.Val); 756 return DAG.getSetCC(VT, ORNode, LR, Op1); 757 } 758 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 759 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 760 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 761 WorkList.push_back(ANDNode.Val); 762 return DAG.getSetCC(VT, ANDNode, LR, Op1); 763 } 764 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 765 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 766 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 767 WorkList.push_back(ORNode.Val); 768 return DAG.getSetCC(VT, ORNode, LR, Op1); 769 } 770 } 771 // canonicalize equivalent to ll == rl 772 if (LL == RR && LR == RL) { 773 Op1 = ISD::getSetCCSwappedOperands(Op1); 774 std::swap(RL, RR); 775 } 776 if (LL == RL && LR == RR) { 777 bool isInteger = MVT::isInteger(LL.getValueType()); 778 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 779 if (Result != ISD::SETCC_INVALID) 780 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 781 } 782 } 783 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 784 if (N0.getOpcode() == ISD::ZERO_EXTEND && 785 N1.getOpcode() == ISD::ZERO_EXTEND && 786 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 787 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 788 N0.getOperand(0), N1.getOperand(0)); 789 WorkList.push_back(ANDNode.Val); 790 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 791 } 792 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y)) 793 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 794 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) && 795 N0.getOperand(1) == N1.getOperand(1)) { 796 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 797 N0.getOperand(0), N1.getOperand(0)); 798 WorkList.push_back(ANDNode.Val); 799 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 800 } 801 // fold (zext_inreg (extload x)) -> (zextload x) 802 if (N1C && N0.getOpcode() == ISD::EXTLOAD) { 803 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 804 // If the type of the zext_inreg and the extload match, and we're running 805 // before Legalize, or the resulting zextload is legal on the target, then 806 // go ahead and do the fold. 807 if ((N1C->getValue() == (1ULL << MVT::getSizeInBits(EVT))-1) && 808 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 809 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 810 N0.getOperand(1), N0.getOperand(2), 811 EVT); 812 WorkList.push_back(N); 813 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 814 return SDOperand(); 815 } 816 } 817 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 818 if (N1C && N0.getOpcode() == ISD::SEXTLOAD && N0.Val->hasNUsesOfValue(1, 0)) { 819 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 820 // If the type of the zext_inreg and the extload match, and we're running 821 // before Legalize, or the resulting zextload is legal on the target, then 822 // go ahead and do the fold. 823 if ((N1C->getValue() == (1ULL << MVT::getSizeInBits(EVT))-1) && 824 (!AfterLegalize || 825 TargetLowering::Legal == TLI.getOperationAction(ISD::ZEXTLOAD, EVT))) { 826 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 827 N0.getOperand(1), N0.getOperand(2), 828 EVT); 829 WorkList.push_back(N); 830 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 831 return SDOperand(); 832 } 833 } 834 return SDOperand(); 835} 836 837SDOperand DAGCombiner::visitOR(SDNode *N) { 838 SDOperand N0 = N->getOperand(0); 839 SDOperand N1 = N->getOperand(1); 840 SDOperand LL, LR, RL, RR, CC0, CC1; 841 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 842 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 843 MVT::ValueType VT = N1.getValueType(); 844 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 845 846 // fold (or c1, c2) -> c1|c2 847 if (N0C && N1C) 848 return DAG.getConstant(N0C->getValue() | N1C->getValue(), 849 N->getValueType(0)); 850 // canonicalize constant to RHS 851 if (N0C && !N1C) { 852 std::swap(N0, N1); 853 std::swap(N0C, N1C); 854 } 855 // fold (or x, 0) -> x 856 if (N1C && N1C->isNullValue()) 857 return N0; 858 // fold (or x, -1) -> -1 859 if (N1C && N1C->isAllOnesValue()) 860 return N1; 861 // fold (or x, c) -> c iff (x & ~c) == 0 862 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 863 TLI)) 864 return N1; 865 // fold (or (or x, c1), c2) -> (or x, c1|c2) 866 if (N1C && N0.getOpcode() == ISD::OR) { 867 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 868 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 869 if (N00C) 870 return DAG.getNode(ISD::OR, VT, N0.getOperand(1), 871 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT)); 872 if (N01C) 873 return DAG.getNode(ISD::OR, VT, N0.getOperand(0), 874 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT)); 875 } 876 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 877 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 878 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 879 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 880 881 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 882 MVT::isInteger(LL.getValueType())) { 883 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 884 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 885 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 886 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 887 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 888 WorkList.push_back(ORNode.Val); 889 return DAG.getSetCC(VT, ORNode, LR, Op1); 890 } 891 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 892 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 893 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 894 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 895 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 896 WorkList.push_back(ANDNode.Val); 897 return DAG.getSetCC(VT, ANDNode, LR, Op1); 898 } 899 } 900 // canonicalize equivalent to ll == rl 901 if (LL == RR && LR == RL) { 902 Op1 = ISD::getSetCCSwappedOperands(Op1); 903 std::swap(RL, RR); 904 } 905 if (LL == RL && LR == RR) { 906 bool isInteger = MVT::isInteger(LL.getValueType()); 907 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 908 if (Result != ISD::SETCC_INVALID) 909 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 910 } 911 } 912 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 913 if (N0.getOpcode() == ISD::ZERO_EXTEND && 914 N1.getOpcode() == ISD::ZERO_EXTEND && 915 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 916 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 917 N0.getOperand(0), N1.getOperand(0)); 918 WorkList.push_back(ORNode.Val); 919 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 920 } 921 return SDOperand(); 922} 923 924SDOperand DAGCombiner::visitXOR(SDNode *N) { 925 SDOperand N0 = N->getOperand(0); 926 SDOperand N1 = N->getOperand(1); 927 SDOperand LHS, RHS, CC; 928 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 929 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 930 MVT::ValueType VT = N0.getValueType(); 931 932 // fold (xor c1, c2) -> c1^c2 933 if (N0C && N1C) 934 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT); 935 // canonicalize constant to RHS 936 if (N0C && !N1C) { 937 std::swap(N0, N1); 938 std::swap(N0C, N1C); 939 } 940 // fold (xor x, 0) -> x 941 if (N1C && N1C->isNullValue()) 942 return N0; 943 // fold !(x cc y) -> (x !cc y) 944 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 945 bool isInt = MVT::isInteger(LHS.getValueType()); 946 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 947 isInt); 948 if (N0.getOpcode() == ISD::SETCC) 949 return DAG.getSetCC(VT, LHS, RHS, NotCC); 950 if (N0.getOpcode() == ISD::SELECT_CC) 951 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 952 assert(0 && "Unhandled SetCC Equivalent!"); 953 abort(); 954 } 955 // fold !(x or y) -> (!x and !y) iff x or y are setcc 956 if (N1C && N1C->getValue() == 1 && 957 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 958 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 959 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 960 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 961 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 962 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 963 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 964 return DAG.getNode(NewOpcode, VT, LHS, RHS); 965 } 966 } 967 // fold !(x or y) -> (!x and !y) iff x or y are constants 968 if (N1C && N1C->isAllOnesValue() && 969 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 970 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 971 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 972 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 973 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 974 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 975 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 976 return DAG.getNode(NewOpcode, VT, LHS, RHS); 977 } 978 } 979 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 980 if (N1C && N0.getOpcode() == ISD::XOR) { 981 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 982 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 983 if (N00C) 984 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 985 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 986 if (N01C) 987 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 988 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 989 } 990 // fold (xor x, x) -> 0 991 if (N0 == N1) 992 return DAG.getConstant(0, VT); 993 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 994 if (N0.getOpcode() == ISD::ZERO_EXTEND && 995 N1.getOpcode() == ISD::ZERO_EXTEND && 996 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 997 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 998 N0.getOperand(0), N1.getOperand(0)); 999 WorkList.push_back(XORNode.Val); 1000 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1001 } 1002 return SDOperand(); 1003} 1004 1005SDOperand DAGCombiner::visitSHL(SDNode *N) { 1006 SDOperand N0 = N->getOperand(0); 1007 SDOperand N1 = N->getOperand(1); 1008 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1009 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1010 MVT::ValueType VT = N0.getValueType(); 1011 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1012 1013 // fold (shl c1, c2) -> c1<<c2 1014 if (N0C && N1C) 1015 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT); 1016 // fold (shl 0, x) -> 0 1017 if (N0C && N0C->isNullValue()) 1018 return N0; 1019 // fold (shl x, c >= size(x)) -> undef 1020 if (N1C && N1C->getValue() >= OpSizeInBits) 1021 return DAG.getNode(ISD::UNDEF, VT); 1022 // fold (shl x, 0) -> x 1023 if (N1C && N1C->isNullValue()) 1024 return N0; 1025 // if (shl x, c) is known to be zero, return 0 1026 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1027 return DAG.getConstant(0, VT); 1028 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1029 if (N1C && N0.getOpcode() == ISD::SHL && 1030 N0.getOperand(1).getOpcode() == ISD::Constant) { 1031 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1032 uint64_t c2 = N1C->getValue(); 1033 if (c1 + c2 > OpSizeInBits) 1034 return DAG.getConstant(0, VT); 1035 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1036 DAG.getConstant(c1 + c2, N1.getValueType())); 1037 } 1038 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1039 // (srl (and x, -1 << c1), c1-c2) 1040 if (N1C && N0.getOpcode() == ISD::SRL && 1041 N0.getOperand(1).getOpcode() == ISD::Constant) { 1042 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1043 uint64_t c2 = N1C->getValue(); 1044 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1045 DAG.getConstant(~0ULL << c1, VT)); 1046 if (c2 > c1) 1047 return DAG.getNode(ISD::SHL, VT, Mask, 1048 DAG.getConstant(c2-c1, N1.getValueType())); 1049 else 1050 return DAG.getNode(ISD::SRL, VT, Mask, 1051 DAG.getConstant(c1-c2, N1.getValueType())); 1052 } 1053 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1054 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1055 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1056 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1057 return SDOperand(); 1058} 1059 1060SDOperand DAGCombiner::visitSRA(SDNode *N) { 1061 SDOperand N0 = N->getOperand(0); 1062 SDOperand N1 = N->getOperand(1); 1063 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1064 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1065 MVT::ValueType VT = N0.getValueType(); 1066 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1067 1068 // fold (sra c1, c2) -> c1>>c2 1069 if (N0C && N1C) 1070 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT); 1071 // fold (sra 0, x) -> 0 1072 if (N0C && N0C->isNullValue()) 1073 return N0; 1074 // fold (sra -1, x) -> -1 1075 if (N0C && N0C->isAllOnesValue()) 1076 return N0; 1077 // fold (sra x, c >= size(x)) -> undef 1078 if (N1C && N1C->getValue() >= OpSizeInBits) 1079 return DAG.getNode(ISD::UNDEF, VT); 1080 // fold (sra x, 0) -> x 1081 if (N1C && N1C->isNullValue()) 1082 return N0; 1083 // If the sign bit is known to be zero, switch this to a SRL. 1084 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI)) 1085 return DAG.getNode(ISD::SRL, VT, N0, N1); 1086 return SDOperand(); 1087} 1088 1089SDOperand DAGCombiner::visitSRL(SDNode *N) { 1090 SDOperand N0 = N->getOperand(0); 1091 SDOperand N1 = N->getOperand(1); 1092 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1093 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1094 MVT::ValueType VT = N0.getValueType(); 1095 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1096 1097 // fold (srl c1, c2) -> c1 >>u c2 1098 if (N0C && N1C) 1099 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT); 1100 // fold (srl 0, x) -> 0 1101 if (N0C && N0C->isNullValue()) 1102 return N0; 1103 // fold (srl x, c >= size(x)) -> undef 1104 if (N1C && N1C->getValue() >= OpSizeInBits) 1105 return DAG.getNode(ISD::UNDEF, VT); 1106 // fold (srl x, 0) -> x 1107 if (N1C && N1C->isNullValue()) 1108 return N0; 1109 // if (srl x, c) is known to be zero, return 0 1110 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1111 return DAG.getConstant(0, VT); 1112 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1113 if (N1C && N0.getOpcode() == ISD::SRL && 1114 N0.getOperand(1).getOpcode() == ISD::Constant) { 1115 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1116 uint64_t c2 = N1C->getValue(); 1117 if (c1 + c2 > OpSizeInBits) 1118 return DAG.getConstant(0, VT); 1119 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1120 DAG.getConstant(c1 + c2, N1.getValueType())); 1121 } 1122 return SDOperand(); 1123} 1124 1125SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1126 SDOperand N0 = N->getOperand(0); 1127 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1128 1129 // fold (ctlz c1) -> c2 1130 if (N0C) 1131 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()), 1132 N0.getValueType()); 1133 return SDOperand(); 1134} 1135 1136SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1137 SDOperand N0 = N->getOperand(0); 1138 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1139 1140 // fold (cttz c1) -> c2 1141 if (N0C) 1142 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()), 1143 N0.getValueType()); 1144 return SDOperand(); 1145} 1146 1147SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1148 SDOperand N0 = N->getOperand(0); 1149 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1150 1151 // fold (ctpop c1) -> c2 1152 if (N0C) 1153 return DAG.getConstant(CountPopulation_64(N0C->getValue()), 1154 N0.getValueType()); 1155 return SDOperand(); 1156} 1157 1158SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1159 SDOperand N0 = N->getOperand(0); 1160 SDOperand N1 = N->getOperand(1); 1161 SDOperand N2 = N->getOperand(2); 1162 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1163 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1164 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1165 MVT::ValueType VT = N->getValueType(0); 1166 1167 // fold select C, X, X -> X 1168 if (N1 == N2) 1169 return N1; 1170 // fold select true, X, Y -> X 1171 if (N0C && !N0C->isNullValue()) 1172 return N1; 1173 // fold select false, X, Y -> Y 1174 if (N0C && N0C->isNullValue()) 1175 return N2; 1176 // fold select C, 1, X -> C | X 1177 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1178 return DAG.getNode(ISD::OR, VT, N0, N2); 1179 // fold select C, 0, X -> ~C & X 1180 // FIXME: this should check for C type == X type, not i1? 1181 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1182 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1183 WorkList.push_back(XORNode.Val); 1184 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1185 } 1186 // fold select C, X, 1 -> ~C | X 1187 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1188 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1189 WorkList.push_back(XORNode.Val); 1190 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1191 } 1192 // fold select C, X, 0 -> C & X 1193 // FIXME: this should check for C type == X type, not i1? 1194 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1195 return DAG.getNode(ISD::AND, VT, N0, N1); 1196 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1197 if (MVT::i1 == VT && N0 == N1) 1198 return DAG.getNode(ISD::OR, VT, N0, N2); 1199 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1200 if (MVT::i1 == VT && N0 == N2) 1201 return DAG.getNode(ISD::AND, VT, N0, N1); 1202 // fold selects based on a setcc into other things, such as min/max/abs 1203 if (N0.getOpcode() == ISD::SETCC) 1204 return SimplifySelect(N0, N1, N2); 1205 return SDOperand(); 1206} 1207 1208SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1209 SDOperand N0 = N->getOperand(0); 1210 SDOperand N1 = N->getOperand(1); 1211 SDOperand N2 = N->getOperand(2); 1212 SDOperand N3 = N->getOperand(3); 1213 SDOperand N4 = N->getOperand(4); 1214 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1215 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1216 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1217 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1218 1219 // Determine if the condition we're dealing with is constant 1220 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1221 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1222 1223 // fold select_cc lhs, rhs, x, x, cc -> x 1224 if (N2 == N3) 1225 return N2; 1226 // fold select_cc into other things, such as min/max/abs 1227 return SimplifySelectCC(N0, N1, N2, N3, CC); 1228} 1229 1230SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1231 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1232 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1233} 1234 1235SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1236 SDOperand N0 = N->getOperand(0); 1237 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1238 MVT::ValueType VT = N->getValueType(0); 1239 1240 // fold (sext c1) -> c1 1241 if (N0C) 1242 return DAG.getConstant(N0C->getSignExtended(), VT); 1243 // fold (sext (sext x)) -> (sext x) 1244 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1245 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1246 // fold (sext (sextload x)) -> (sextload x) 1247 if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType()) 1248 return N0; 1249 // fold (sext (load x)) -> (sextload x) 1250 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) { 1251 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1252 N0.getOperand(1), N0.getOperand(2), 1253 N0.getValueType()); 1254 CombineTo(N0.Val, ExtLoad, ExtLoad.getOperand(0)); 1255 WorkList.push_back(N); 1256 return SDOperand(); 1257 } 1258 return SDOperand(); 1259} 1260 1261SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1262 SDOperand N0 = N->getOperand(0); 1263 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1264 MVT::ValueType VT = N->getValueType(0); 1265 1266 // fold (zext c1) -> c1 1267 if (N0C) 1268 return DAG.getConstant(N0C->getValue(), VT); 1269 // fold (zext (zext x)) -> (zext x) 1270 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1271 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1272 return SDOperand(); 1273} 1274 1275SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1276 SDOperand N0 = N->getOperand(0); 1277 SDOperand N1 = N->getOperand(1); 1278 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1279 MVT::ValueType VT = N->getValueType(0); 1280 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1281 unsigned EVTBits = MVT::getSizeInBits(EVT); 1282 1283 // fold (sext_in_reg c1) -> c1 1284 if (N0C) { 1285 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1286 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1287 } 1288 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1289 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1290 cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) { 1291 return N0; 1292 } 1293 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1294 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1295 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1296 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1297 } 1298 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1299 if (N0.getOpcode() == ISD::AssertSext && 1300 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1301 return N0; 1302 } 1303 // fold (sext_in_reg (sextload x)) -> (sextload x) 1304 if (N0.getOpcode() == ISD::SEXTLOAD && 1305 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1306 return N0; 1307 } 1308 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1309 if (N0.getOpcode() == ISD::SETCC && 1310 TLI.getSetCCResultContents() == 1311 TargetLowering::ZeroOrNegativeOneSetCCResult) 1312 return N0; 1313 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1314 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI)) 1315 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 1316 DAG.getConstant(~0ULL >> (64-EVTBits), VT)); 1317 // fold (sext_in_reg (srl x)) -> sra x 1318 if (N0.getOpcode() == ISD::SRL && 1319 N0.getOperand(1).getOpcode() == ISD::Constant && 1320 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1321 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1322 N0.getOperand(1)); 1323 } 1324 // fold (sext_inreg (extload x)) -> (sextload x) 1325 if (N0.getOpcode() == ISD::EXTLOAD && 1326 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1327 (!AfterLegalize || 1328 (TargetLowering::Legal == TLI.getOperationAction(ISD::SEXTLOAD, EVT)))) { 1329 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1330 N0.getOperand(1), N0.getOperand(2), 1331 EVT); 1332 CombineTo(N0.Val, ExtLoad, ExtLoad.getOperand(0)); 1333 WorkList.push_back(N); 1334 return SDOperand(); 1335 } 1336 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1337 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.Val->hasNUsesOfValue(1, 0) && 1338 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1339 (!AfterLegalize || 1340 (TargetLowering::Legal == TLI.getOperationAction(ISD::SEXTLOAD, EVT)))) { 1341 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1342 N0.getOperand(1), N0.getOperand(2), 1343 EVT); 1344 CombineTo(N0.Val, ExtLoad, ExtLoad.getOperand(0)); 1345 WorkList.push_back(N); 1346 return SDOperand(); 1347 } 1348 return SDOperand(); 1349} 1350 1351SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1352 SDOperand N0 = N->getOperand(0); 1353 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1354 MVT::ValueType VT = N->getValueType(0); 1355 1356 // noop truncate 1357 if (N0.getValueType() == N->getValueType(0)) 1358 return N0; 1359 // fold (truncate c1) -> c1 1360 if (N0C) 1361 return DAG.getConstant(N0C->getValue(), VT); 1362 // fold (truncate (truncate x)) -> (truncate x) 1363 if (N0.getOpcode() == ISD::TRUNCATE) 1364 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1365 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1366 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1367 if (N0.getValueType() < VT) 1368 // if the source is smaller than the dest, we still need an extend 1369 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1370 else if (N0.getValueType() > VT) 1371 // if the source is larger than the dest, than we just need the truncate 1372 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1373 else 1374 // if the source and dest are the same type, we can drop both the extend 1375 // and the truncate 1376 return N0.getOperand(0); 1377 } 1378 // fold (truncate (load x)) -> (smaller load x) 1379 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) { 1380 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1381 "Cannot truncate to larger type!"); 1382 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1383 // For big endian targets, we need to add an offset to the pointer to load 1384 // the correct bytes. For little endian systems, we merely need to read 1385 // fewer bytes from the same pointer. 1386 uint64_t PtrOff = 1387 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1388 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1389 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1390 DAG.getConstant(PtrOff, PtrType)); 1391 WorkList.push_back(NewPtr.Val); 1392 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1393 CombineTo(N0.Val, Load, Load.getOperand(0)); 1394 WorkList.push_back(N); 1395 return SDOperand(); 1396 } 1397 return SDOperand(); 1398} 1399 1400SDOperand DAGCombiner::visitFADD(SDNode *N) { 1401 SDOperand N0 = N->getOperand(0); 1402 SDOperand N1 = N->getOperand(1); 1403 MVT::ValueType VT = N->getValueType(0); 1404 1405 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1406 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1407 // fold floating point (fadd c1, c2) 1408 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), 1409 N->getValueType(0)); 1410 } 1411 // fold (A + (-B)) -> A-B 1412 if (N1.getOpcode() == ISD::FNEG) 1413 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1414 1415 // fold ((-A) + B) -> B-A 1416 if (N0.getOpcode() == ISD::FNEG) 1417 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1418 1419 return SDOperand(); 1420} 1421 1422SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1423 SDOperand N0 = N->getOperand(0); 1424 SDOperand N1 = N->getOperand(1); 1425 MVT::ValueType VT = N->getValueType(0); 1426 1427 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1428 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1429 // fold floating point (fsub c1, c2) 1430 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(), 1431 N->getValueType(0)); 1432 } 1433 // fold (A-(-B)) -> A+B 1434 if (N1.getOpcode() == ISD::FNEG) 1435 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0)); 1436 1437 return SDOperand(); 1438} 1439 1440SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1441 SDOperand N0 = N->getOperand(0); 1442 SDOperand N1 = N->getOperand(1); 1443 MVT::ValueType VT = N->getValueType(0); 1444 1445 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1446 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1447 // fold floating point (fmul c1, c2) 1448 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(), 1449 N->getValueType(0)); 1450 } 1451 return SDOperand(); 1452} 1453 1454SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1455 SDOperand N0 = N->getOperand(0); 1456 SDOperand N1 = N->getOperand(1); 1457 MVT::ValueType VT = N->getValueType(0); 1458 1459 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1460 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1461 // fold floating point (fdiv c1, c2) 1462 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(), 1463 N->getValueType(0)); 1464 } 1465 return SDOperand(); 1466} 1467 1468SDOperand DAGCombiner::visitFREM(SDNode *N) { 1469 SDOperand N0 = N->getOperand(0); 1470 SDOperand N1 = N->getOperand(1); 1471 MVT::ValueType VT = N->getValueType(0); 1472 1473 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1474 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1475 // fold floating point (frem c1, c2) -> fmod(c1, c2) 1476 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()), 1477 N->getValueType(0)); 1478 } 1479 return SDOperand(); 1480} 1481 1482 1483SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1484 SDOperand N0 = N->getOperand(0); 1485 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1486 1487 // fold (sint_to_fp c1) -> c1fp 1488 if (N0C) 1489 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0)); 1490 return SDOperand(); 1491} 1492 1493SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1494 SDOperand N0 = N->getOperand(0); 1495 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1496 1497 // fold (uint_to_fp c1) -> c1fp 1498 if (N0C) 1499 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0)); 1500 return SDOperand(); 1501} 1502 1503SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1504 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1505 1506 // fold (fp_to_sint c1fp) -> c1 1507 if (N0CFP) 1508 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0)); 1509 return SDOperand(); 1510} 1511 1512SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1513 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1514 1515 // fold (fp_to_uint c1fp) -> c1 1516 if (N0CFP) 1517 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0)); 1518 return SDOperand(); 1519} 1520 1521SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1522 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1523 1524 // fold (fp_round c1fp) -> c1fp 1525 if (N0CFP) 1526 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1527 return SDOperand(); 1528} 1529 1530SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1531 SDOperand N0 = N->getOperand(0); 1532 MVT::ValueType VT = N->getValueType(0); 1533 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1534 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1535 1536 // fold (fp_round_inreg c1fp) -> c1fp 1537 if (N0CFP) { 1538 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1539 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1540 } 1541 return SDOperand(); 1542} 1543 1544SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1545 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1546 1547 // fold (fp_extend c1fp) -> c1fp 1548 if (N0CFP) 1549 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1550 return SDOperand(); 1551} 1552 1553SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1554 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1555 // fold (neg c1) -> -c1 1556 if (N0CFP) 1557 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0)); 1558 // fold (neg (sub x, y)) -> (sub y, x) 1559 if (N->getOperand(0).getOpcode() == ISD::SUB) 1560 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1), 1561 N->getOperand(0)); 1562 // fold (neg (neg x)) -> x 1563 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1564 return N->getOperand(0).getOperand(0); 1565 return SDOperand(); 1566} 1567 1568SDOperand DAGCombiner::visitFABS(SDNode *N) { 1569 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1570 // fold (fabs c1) -> fabs(c1) 1571 if (N0CFP) 1572 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0)); 1573 // fold (fabs (fabs x)) -> (fabs x) 1574 if (N->getOperand(0).getOpcode() == ISD::FABS) 1575 return N->getOperand(0); 1576 // fold (fabs (fneg x)) -> (fabs x) 1577 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1578 return DAG.getNode(ISD::FABS, N->getValueType(0), 1579 N->getOperand(0).getOperand(0)); 1580 return SDOperand(); 1581} 1582 1583SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 1584 SDOperand Chain = N->getOperand(0); 1585 SDOperand N1 = N->getOperand(1); 1586 SDOperand N2 = N->getOperand(2); 1587 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1588 1589 // never taken branch, fold to chain 1590 if (N1C && N1C->isNullValue()) 1591 return Chain; 1592 // unconditional branch 1593 if (N1C && N1C->getValue() == 1) 1594 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1595 return SDOperand(); 1596} 1597 1598SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 1599 SDOperand Chain = N->getOperand(0); 1600 SDOperand N1 = N->getOperand(1); 1601 SDOperand N2 = N->getOperand(2); 1602 SDOperand N3 = N->getOperand(3); 1603 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1604 1605 // unconditional branch to true mbb 1606 if (N1C && N1C->getValue() == 1) 1607 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1608 // unconditional branch to false mbb 1609 if (N1C && N1C->isNullValue()) 1610 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 1611 return SDOperand(); 1612} 1613 1614// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 1615// 1616SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 1617 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 1618 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 1619 1620 // Use SimplifySetCC to simplify SETCC's. 1621 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 1622 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 1623 1624 // fold br_cc true, dest -> br dest (unconditional branch) 1625 if (SCCC && SCCC->getValue()) 1626 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 1627 N->getOperand(4)); 1628 // fold br_cc false, dest -> unconditional fall through 1629 if (SCCC && SCCC->isNullValue()) 1630 return N->getOperand(0); 1631 // fold to a simpler setcc 1632 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 1633 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 1634 Simp.getOperand(2), Simp.getOperand(0), 1635 Simp.getOperand(1), N->getOperand(4)); 1636 return SDOperand(); 1637} 1638 1639SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 1640 SDOperand Chain = N->getOperand(0); 1641 SDOperand CCN = N->getOperand(1); 1642 SDOperand LHS = N->getOperand(2); 1643 SDOperand RHS = N->getOperand(3); 1644 SDOperand N4 = N->getOperand(4); 1645 SDOperand N5 = N->getOperand(5); 1646 1647 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 1648 cast<CondCodeSDNode>(CCN)->get(), false); 1649 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1650 1651 // fold select_cc lhs, rhs, x, x, cc -> x 1652 if (N4 == N5) 1653 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1654 // fold select_cc true, x, y -> x 1655 if (SCCC && SCCC->getValue()) 1656 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1657 // fold select_cc false, x, y -> y 1658 if (SCCC && SCCC->isNullValue()) 1659 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 1660 // fold to a simpler setcc 1661 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 1662 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0), 1663 SCC.getOperand(1), N4, N5); 1664 return SDOperand(); 1665} 1666 1667SDOperand DAGCombiner::visitLOAD(SDNode *N) { 1668 SDOperand Chain = N->getOperand(0); 1669 SDOperand Ptr = N->getOperand(1); 1670 SDOperand SrcValue = N->getOperand(2); 1671 1672 // If this load is directly stored, replace the load value with the stored 1673 // value. 1674 // TODO: Handle store large -> read small portion. 1675 // TODO: Handle TRUNCSTORE/EXTLOAD 1676 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1677 Chain.getOperand(1).getValueType() == N->getValueType(0)) 1678 return CombineTo(N, Chain.getOperand(1), Chain); 1679 1680 return SDOperand(); 1681} 1682 1683SDOperand DAGCombiner::visitSTORE(SDNode *N) { 1684 SDOperand Chain = N->getOperand(0); 1685 SDOperand Value = N->getOperand(1); 1686 SDOperand Ptr = N->getOperand(2); 1687 SDOperand SrcValue = N->getOperand(3); 1688 1689 // If this is a store that kills a previous store, remove the previous store. 1690 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1691 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) { 1692 // Create a new store of Value that replaces both stores. 1693 SDNode *PrevStore = Chain.Val; 1694 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 1695 return Chain; 1696 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 1697 PrevStore->getOperand(0), Value, Ptr, 1698 SrcValue); 1699 CombineTo(N, NewStore); // Nuke this store. 1700 CombineTo(PrevStore, NewStore); // Nuke the previous store. 1701 return SDOperand(N, 0); 1702 } 1703 1704 return SDOperand(); 1705} 1706 1707SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 1708 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 1709 1710 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 1711 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 1712 // If we got a simplified select_cc node back from SimplifySelectCC, then 1713 // break it down into a new SETCC node, and a new SELECT node, and then return 1714 // the SELECT node, since we were called with a SELECT node. 1715 if (SCC.Val) { 1716 // Check to see if we got a select_cc back (to turn into setcc/select). 1717 // Otherwise, just return whatever node we got back, like fabs. 1718 if (SCC.getOpcode() == ISD::SELECT_CC) { 1719 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 1720 SCC.getOperand(0), SCC.getOperand(1), 1721 SCC.getOperand(4)); 1722 WorkList.push_back(SETCC.Val); 1723 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 1724 SCC.getOperand(3), SETCC); 1725 } 1726 return SCC; 1727 } 1728 return SDOperand(); 1729} 1730 1731SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 1732 SDOperand N2, SDOperand N3, 1733 ISD::CondCode CC) { 1734 1735 MVT::ValueType VT = N2.getValueType(); 1736 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1738 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1739 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1740 1741 // Determine if the condition we're dealing with is constant 1742 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1743 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1744 1745 // fold select_cc true, x, y -> x 1746 if (SCCC && SCCC->getValue()) 1747 return N2; 1748 // fold select_cc false, x, y -> y 1749 if (SCCC && SCCC->getValue() == 0) 1750 return N3; 1751 1752 // Check to see if we can simplify the select into an fabs node 1753 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1754 // Allow either -0.0 or 0.0 1755 if (CFP->getValue() == 0.0) { 1756 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 1757 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 1758 N0 == N2 && N3.getOpcode() == ISD::FNEG && 1759 N2 == N3.getOperand(0)) 1760 return DAG.getNode(ISD::FABS, VT, N0); 1761 1762 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 1763 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 1764 N0 == N3 && N2.getOpcode() == ISD::FNEG && 1765 N2.getOperand(0) == N3) 1766 return DAG.getNode(ISD::FABS, VT, N3); 1767 } 1768 } 1769 1770 // Check to see if we can perform the "gzip trick", transforming 1771 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 1772 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 1773 MVT::isInteger(N0.getValueType()) && 1774 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 1775 MVT::ValueType XType = N0.getValueType(); 1776 MVT::ValueType AType = N2.getValueType(); 1777 if (XType >= AType) { 1778 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 1779 // single-bit constant. 1780 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 1781 unsigned ShCtV = Log2_64(N2C->getValue()); 1782 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 1783 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 1784 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 1785 WorkList.push_back(Shift.Val); 1786 if (XType > AType) { 1787 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 1788 WorkList.push_back(Shift.Val); 1789 } 1790 return DAG.getNode(ISD::AND, AType, Shift, N2); 1791 } 1792 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 1793 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1794 TLI.getShiftAmountTy())); 1795 WorkList.push_back(Shift.Val); 1796 if (XType > AType) { 1797 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 1798 WorkList.push_back(Shift.Val); 1799 } 1800 return DAG.getNode(ISD::AND, AType, Shift, N2); 1801 } 1802 } 1803 1804 // fold select C, 16, 0 -> shl C, 4 1805 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 1806 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 1807 // Get a SetCC of the condition 1808 // FIXME: Should probably make sure that setcc is legal if we ever have a 1809 // target where it isn't. 1810 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 1811 WorkList.push_back(SCC.Val); 1812 // cast from setcc result type to select result type 1813 if (AfterLegalize) 1814 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 1815 else 1816 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 1817 WorkList.push_back(Temp.Val); 1818 // shl setcc result by log2 n2c 1819 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 1820 DAG.getConstant(Log2_64(N2C->getValue()), 1821 TLI.getShiftAmountTy())); 1822 } 1823 1824 // Check to see if this is the equivalent of setcc 1825 // FIXME: Turn all of these into setcc if setcc if setcc is legal 1826 // otherwise, go ahead with the folds. 1827 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 1828 MVT::ValueType XType = N0.getValueType(); 1829 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 1830 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 1831 if (Res.getValueType() != VT) 1832 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 1833 return Res; 1834 } 1835 1836 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 1837 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 1838 TLI.isOperationLegal(ISD::CTLZ, XType)) { 1839 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 1840 return DAG.getNode(ISD::SRL, XType, Ctlz, 1841 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 1842 TLI.getShiftAmountTy())); 1843 } 1844 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 1845 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 1846 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 1847 N0); 1848 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 1849 DAG.getConstant(~0ULL, XType)); 1850 return DAG.getNode(ISD::SRL, XType, 1851 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 1852 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1853 TLI.getShiftAmountTy())); 1854 } 1855 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 1856 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 1857 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 1858 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1859 TLI.getShiftAmountTy())); 1860 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 1861 } 1862 } 1863 1864 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 1865 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 1866 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 1867 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 1868 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 1869 MVT::ValueType XType = N0.getValueType(); 1870 if (SubC->isNullValue() && MVT::isInteger(XType)) { 1871 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 1872 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1873 TLI.getShiftAmountTy())); 1874 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 1875 WorkList.push_back(Shift.Val); 1876 WorkList.push_back(Add.Val); 1877 return DAG.getNode(ISD::XOR, XType, Add, Shift); 1878 } 1879 } 1880 } 1881 1882 return SDOperand(); 1883} 1884 1885SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 1886 SDOperand N1, ISD::CondCode Cond, 1887 bool foldBooleans) { 1888 // These setcc operations always fold. 1889 switch (Cond) { 1890 default: break; 1891 case ISD::SETFALSE: 1892 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1893 case ISD::SETTRUE: 1894 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1895 } 1896 1897 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1898 uint64_t C1 = N1C->getValue(); 1899 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 1900 uint64_t C0 = N0C->getValue(); 1901 1902 // Sign extend the operands if required 1903 if (ISD::isSignedIntSetCC(Cond)) { 1904 C0 = N0C->getSignExtended(); 1905 C1 = N1C->getSignExtended(); 1906 } 1907 1908 switch (Cond) { 1909 default: assert(0 && "Unknown integer setcc!"); 1910 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 1911 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 1912 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 1913 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 1914 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 1915 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 1916 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 1917 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 1918 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 1919 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 1920 } 1921 } else { 1922 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1923 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1924 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1925 1926 // If the comparison constant has bits in the upper part, the 1927 // zero-extended value could never match. 1928 if (C1 & (~0ULL << InSize)) { 1929 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 1930 switch (Cond) { 1931 case ISD::SETUGT: 1932 case ISD::SETUGE: 1933 case ISD::SETEQ: return DAG.getConstant(0, VT); 1934 case ISD::SETULT: 1935 case ISD::SETULE: 1936 case ISD::SETNE: return DAG.getConstant(1, VT); 1937 case ISD::SETGT: 1938 case ISD::SETGE: 1939 // True if the sign bit of C1 is set. 1940 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 1941 case ISD::SETLT: 1942 case ISD::SETLE: 1943 // True if the sign bit of C1 isn't set. 1944 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 1945 default: 1946 break; 1947 } 1948 } 1949 1950 // Otherwise, we can perform the comparison with the low bits. 1951 switch (Cond) { 1952 case ISD::SETEQ: 1953 case ISD::SETNE: 1954 case ISD::SETUGT: 1955 case ISD::SETUGE: 1956 case ISD::SETULT: 1957 case ISD::SETULE: 1958 return DAG.getSetCC(VT, N0.getOperand(0), 1959 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 1960 Cond); 1961 default: 1962 break; // todo, be more careful with signed comparisons 1963 } 1964 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1965 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1966 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1967 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1968 MVT::ValueType ExtDstTy = N0.getValueType(); 1969 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1970 1971 // If the extended part has any inconsistent bits, it cannot ever 1972 // compare equal. In other words, they have to be all ones or all 1973 // zeros. 1974 uint64_t ExtBits = 1975 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 1976 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1977 return DAG.getConstant(Cond == ISD::SETNE, VT); 1978 1979 SDOperand ZextOp; 1980 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1981 if (Op0Ty == ExtSrcTy) { 1982 ZextOp = N0.getOperand(0); 1983 } else { 1984 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 1985 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1986 DAG.getConstant(Imm, Op0Ty)); 1987 } 1988 WorkList.push_back(ZextOp.Val); 1989 // Otherwise, make this a use of a zext. 1990 return DAG.getSetCC(VT, ZextOp, 1991 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 1992 ExtDstTy), 1993 Cond); 1994 } 1995 1996 uint64_t MinVal, MaxVal; 1997 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1998 if (ISD::isSignedIntSetCC(Cond)) { 1999 MinVal = 1ULL << (OperandBitSize-1); 2000 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2001 MaxVal = ~0ULL >> (65-OperandBitSize); 2002 else 2003 MaxVal = 0; 2004 } else { 2005 MinVal = 0; 2006 MaxVal = ~0ULL >> (64-OperandBitSize); 2007 } 2008 2009 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2010 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2011 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2012 --C1; // X >= C0 --> X > (C0-1) 2013 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2014 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2015 } 2016 2017 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2018 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2019 ++C1; // X <= C0 --> X < (C0+1) 2020 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2021 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2022 } 2023 2024 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2025 return DAG.getConstant(0, VT); // X < MIN --> false 2026 2027 // Canonicalize setgt X, Min --> setne X, Min 2028 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2029 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2030 2031 // If we have setult X, 1, turn it into seteq X, 0 2032 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2033 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2034 ISD::SETEQ); 2035 // If we have setugt X, Max-1, turn it into seteq X, Max 2036 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2037 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2038 ISD::SETEQ); 2039 2040 // If we have "setcc X, C0", check to see if we can shrink the immediate 2041 // by changing cc. 2042 2043 // SETUGT X, SINTMAX -> SETLT X, 0 2044 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2045 C1 == (~0ULL >> (65-OperandBitSize))) 2046 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2047 ISD::SETLT); 2048 2049 // FIXME: Implement the rest of these. 2050 2051 // Fold bit comparisons when we can. 2052 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2053 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2054 if (ConstantSDNode *AndRHS = 2055 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2056 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2057 // Perform the xform if the AND RHS is a single bit. 2058 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2059 return DAG.getNode(ISD::SRL, VT, N0, 2060 DAG.getConstant(Log2_64(AndRHS->getValue()), 2061 TLI.getShiftAmountTy())); 2062 } 2063 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2064 // (X & 8) == 8 --> (X & 8) >> 3 2065 // Perform the xform if C1 is a single bit. 2066 if ((C1 & (C1-1)) == 0) { 2067 return DAG.getNode(ISD::SRL, VT, N0, 2068 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2069 } 2070 } 2071 } 2072 } 2073 } else if (isa<ConstantSDNode>(N0.Val)) { 2074 // Ensure that the constant occurs on the RHS. 2075 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2076 } 2077 2078 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2079 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2080 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2081 2082 switch (Cond) { 2083 default: break; // FIXME: Implement the rest of these! 2084 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2085 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2086 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2087 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2088 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2089 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2090 } 2091 } else { 2092 // Ensure that the constant occurs on the RHS. 2093 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2094 } 2095 2096 if (N0 == N1) { 2097 // We can always fold X == Y for integer setcc's. 2098 if (MVT::isInteger(N0.getValueType())) 2099 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2100 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2101 if (UOF == 2) // FP operators that are undefined on NaNs. 2102 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2103 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2104 return DAG.getConstant(UOF, VT); 2105 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2106 // if it is not already. 2107 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 2108 if (NewCond != Cond) 2109 return DAG.getSetCC(VT, N0, N1, NewCond); 2110 } 2111 2112 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2113 MVT::isInteger(N0.getValueType())) { 2114 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2115 N0.getOpcode() == ISD::XOR) { 2116 // Simplify (X+Y) == (X+Z) --> Y == Z 2117 if (N0.getOpcode() == N1.getOpcode()) { 2118 if (N0.getOperand(0) == N1.getOperand(0)) 2119 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2120 if (N0.getOperand(1) == N1.getOperand(1)) 2121 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2122 if (isCommutativeBinOp(N0.getOpcode())) { 2123 // If X op Y == Y op X, try other combinations. 2124 if (N0.getOperand(0) == N1.getOperand(1)) 2125 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2126 if (N0.getOperand(1) == N1.getOperand(0)) 2127 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2128 } 2129 } 2130 2131 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes. 2132 if (N0.getOpcode() == ISD::XOR) 2133 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2134 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2135 // If we know that all of the inverted bits are zero, don't bother 2136 // performing the inversion. 2137 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI)) 2138 return DAG.getSetCC(VT, N0.getOperand(0), 2139 DAG.getConstant(XORC->getValue()^RHSC->getValue(), 2140 N0.getValueType()), Cond); 2141 } 2142 2143 // Simplify (X+Z) == X --> Z == 0 2144 if (N0.getOperand(0) == N1) 2145 return DAG.getSetCC(VT, N0.getOperand(1), 2146 DAG.getConstant(0, N0.getValueType()), Cond); 2147 if (N0.getOperand(1) == N1) { 2148 if (isCommutativeBinOp(N0.getOpcode())) 2149 return DAG.getSetCC(VT, N0.getOperand(0), 2150 DAG.getConstant(0, N0.getValueType()), Cond); 2151 else { 2152 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2153 // (Z-X) == X --> Z == X<<1 2154 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2155 N1, 2156 DAG.getConstant(1,TLI.getShiftAmountTy())); 2157 WorkList.push_back(SH.Val); 2158 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2159 } 2160 } 2161 } 2162 2163 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2164 N1.getOpcode() == ISD::XOR) { 2165 // Simplify X == (X+Z) --> Z == 0 2166 if (N1.getOperand(0) == N0) { 2167 return DAG.getSetCC(VT, N1.getOperand(1), 2168 DAG.getConstant(0, N1.getValueType()), Cond); 2169 } else if (N1.getOperand(1) == N0) { 2170 if (isCommutativeBinOp(N1.getOpcode())) { 2171 return DAG.getSetCC(VT, N1.getOperand(0), 2172 DAG.getConstant(0, N1.getValueType()), Cond); 2173 } else { 2174 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2175 // X == (Z-X) --> X<<1 == Z 2176 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2177 DAG.getConstant(1,TLI.getShiftAmountTy())); 2178 WorkList.push_back(SH.Val); 2179 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2180 } 2181 } 2182 } 2183 } 2184 2185 // Fold away ALL boolean setcc's. 2186 SDOperand Temp; 2187 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2188 switch (Cond) { 2189 default: assert(0 && "Unknown integer setcc!"); 2190 case ISD::SETEQ: // X == Y -> (X^Y)^1 2191 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2192 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2193 WorkList.push_back(Temp.Val); 2194 break; 2195 case ISD::SETNE: // X != Y --> (X^Y) 2196 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2197 break; 2198 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2199 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2200 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2201 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2202 WorkList.push_back(Temp.Val); 2203 break; 2204 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2205 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2206 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2207 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2208 WorkList.push_back(Temp.Val); 2209 break; 2210 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2211 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2212 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2213 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2214 WorkList.push_back(Temp.Val); 2215 break; 2216 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2217 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2218 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2219 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2220 break; 2221 } 2222 if (VT != MVT::i1) { 2223 WorkList.push_back(N0.Val); 2224 // FIXME: If running after legalize, we probably can't do this. 2225 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2226 } 2227 return N0; 2228 } 2229 2230 // Could not fold it. 2231 return SDOperand(); 2232} 2233 2234// SelectionDAG::Combine - This is the entry point for the file. 2235// 2236void SelectionDAG::Combine(bool RunningAfterLegalize) { 2237 /// run - This is the main entry point to this class. 2238 /// 2239 DAGCombiner(*this).Run(RunningAfterLegalize); 2240} 2241