DAGCombiner.cpp revision 6dfabb6cc72118e046d2a466aa6adcec4c4923db
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue SimplifyVUnaryOp(SDNode *N); 198 SDValue visitSHL(SDNode *N); 199 SDValue visitSRA(SDNode *N); 200 SDValue visitSRL(SDNode *N); 201 SDValue visitCTLZ(SDNode *N); 202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 203 SDValue visitCTTZ(SDNode *N); 204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 205 SDValue visitCTPOP(SDNode *N); 206 SDValue visitSELECT(SDNode *N); 207 SDValue visitSELECT_CC(SDNode *N); 208 SDValue visitSETCC(SDNode *N); 209 SDValue visitSIGN_EXTEND(SDNode *N); 210 SDValue visitZERO_EXTEND(SDNode *N); 211 SDValue visitANY_EXTEND(SDNode *N); 212 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 213 SDValue visitTRUNCATE(SDNode *N); 214 SDValue visitBITCAST(SDNode *N); 215 SDValue visitBUILD_PAIR(SDNode *N); 216 SDValue visitFADD(SDNode *N); 217 SDValue visitFSUB(SDNode *N); 218 SDValue visitFMUL(SDNode *N); 219 SDValue visitFMA(SDNode *N); 220 SDValue visitFDIV(SDNode *N); 221 SDValue visitFREM(SDNode *N); 222 SDValue visitFCOPYSIGN(SDNode *N); 223 SDValue visitSINT_TO_FP(SDNode *N); 224 SDValue visitUINT_TO_FP(SDNode *N); 225 SDValue visitFP_TO_SINT(SDNode *N); 226 SDValue visitFP_TO_UINT(SDNode *N); 227 SDValue visitFP_ROUND(SDNode *N); 228 SDValue visitFP_ROUND_INREG(SDNode *N); 229 SDValue visitFP_EXTEND(SDNode *N); 230 SDValue visitFNEG(SDNode *N); 231 SDValue visitFABS(SDNode *N); 232 SDValue visitFCEIL(SDNode *N); 233 SDValue visitFTRUNC(SDNode *N); 234 SDValue visitFFLOOR(SDNode *N); 235 SDValue visitBRCOND(SDNode *N); 236 SDValue visitBR_CC(SDNode *N); 237 SDValue visitLOAD(SDNode *N); 238 SDValue visitSTORE(SDNode *N); 239 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 241 SDValue visitBUILD_VECTOR(SDNode *N); 242 SDValue visitCONCAT_VECTORS(SDNode *N); 243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 244 SDValue visitVECTOR_SHUFFLE(SDNode *N); 245 SDValue visitMEMBARRIER(SDNode *N); 246 247 SDValue XformToShuffleWithZero(SDNode *N); 248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 249 250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 251 252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 256 SDValue N3, ISD::CondCode CC, 257 bool NotExtCompare = false); 258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 259 DebugLoc DL, bool foldBooleans = true); 260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 261 unsigned HiOp); 262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 264 SDValue BuildSDIV(SDNode *N); 265 SDValue BuildUDIV(SDNode *N); 266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 267 bool DemandHighBits = true); 268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 270 SDValue ReduceLoadWidth(SDNode *N); 271 SDValue ReduceLoadOpStoreWidth(SDNode *N); 272 SDValue TransformFPLoadStorePair(SDNode *N); 273 274 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 275 276 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 277 /// looking for aliasing nodes and adding them to the Aliases vector. 278 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 279 SmallVector<SDValue, 8> &Aliases); 280 281 /// isAlias - Return true if there is any possibility that the two addresses 282 /// overlap. 283 bool isAlias(SDValue Ptr1, int64_t Size1, 284 const Value *SrcValue1, int SrcValueOffset1, 285 unsigned SrcValueAlign1, 286 const MDNode *TBAAInfo1, 287 SDValue Ptr2, int64_t Size2, 288 const Value *SrcValue2, int SrcValueOffset2, 289 unsigned SrcValueAlign2, 290 const MDNode *TBAAInfo2) const; 291 292 /// FindAliasInfo - Extracts the relevant alias information from the memory 293 /// node. Returns true if the operand was a load. 294 bool FindAliasInfo(SDNode *N, 295 SDValue &Ptr, int64_t &Size, 296 const Value *&SrcValue, int &SrcValueOffset, 297 unsigned &SrcValueAlignment, 298 const MDNode *&TBAAInfo) const; 299 300 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 301 /// looking for a better chain (aliasing node.) 302 SDValue FindBetterChain(SDNode *N, SDValue Chain); 303 304 public: 305 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 306 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 307 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 308 309 /// Run - runs the dag combiner on all nodes in the work list 310 void Run(CombineLevel AtLevel); 311 312 SelectionDAG &getDAG() const { return DAG; } 313 314 /// getShiftAmountTy - Returns a type large enough to hold any valid 315 /// shift amount - before type legalization these can be huge. 316 EVT getShiftAmountTy(EVT LHSTy) { 317 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 318 } 319 320 /// isTypeLegal - This method returns true if we are running before type 321 /// legalization or if the specified VT is legal. 322 bool isTypeLegal(const EVT &VT) { 323 if (!LegalTypes) return true; 324 return TLI.isTypeLegal(VT); 325 } 326 }; 327} 328 329 330namespace { 331/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 332/// nodes from the worklist. 333class WorkListRemover : public SelectionDAG::DAGUpdateListener { 334 DAGCombiner &DC; 335public: 336 explicit WorkListRemover(DAGCombiner &dc) 337 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 338 339 virtual void NodeDeleted(SDNode *N, SDNode *E) { 340 DC.removeFromWorkList(N); 341 } 342}; 343} 344 345//===----------------------------------------------------------------------===// 346// TargetLowering::DAGCombinerInfo implementation 347//===----------------------------------------------------------------------===// 348 349void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 350 ((DAGCombiner*)DC)->AddToWorkList(N); 351} 352 353void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 354 ((DAGCombiner*)DC)->removeFromWorkList(N); 355} 356 357SDValue TargetLowering::DAGCombinerInfo:: 358CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 359 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 360} 361 362SDValue TargetLowering::DAGCombinerInfo:: 363CombineTo(SDNode *N, SDValue Res, bool AddTo) { 364 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 365} 366 367 368SDValue TargetLowering::DAGCombinerInfo:: 369CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 370 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 371} 372 373void TargetLowering::DAGCombinerInfo:: 374CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 375 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 376} 377 378//===----------------------------------------------------------------------===// 379// Helper Functions 380//===----------------------------------------------------------------------===// 381 382/// isNegatibleForFree - Return 1 if we can compute the negated form of the 383/// specified expression for the same cost as the expression itself, or 2 if we 384/// can compute the negated form more cheaply than the expression itself. 385static char isNegatibleForFree(SDValue Op, bool LegalOperations, 386 const TargetLowering &TLI, 387 const TargetOptions *Options, 388 unsigned Depth = 0) { 389 // No compile time optimizations on this type. 390 if (Op.getValueType() == MVT::ppcf128) 391 return 0; 392 393 // fneg is removable even if it has multiple uses. 394 if (Op.getOpcode() == ISD::FNEG) return 2; 395 396 // Don't allow anything with multiple uses. 397 if (!Op.hasOneUse()) return 0; 398 399 // Don't recurse exponentially. 400 if (Depth > 6) return 0; 401 402 switch (Op.getOpcode()) { 403 default: return false; 404 case ISD::ConstantFP: 405 // Don't invert constant FP values after legalize. The negated constant 406 // isn't necessarily legal. 407 return LegalOperations ? 0 : 1; 408 case ISD::FADD: 409 // FIXME: determine better conditions for this xform. 410 if (!Options->UnsafeFPMath) return 0; 411 412 // After operation legalization, it might not be legal to create new FSUBs. 413 if (LegalOperations && 414 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 415 return 0; 416 417 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 418 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 419 Options, Depth + 1)) 420 return V; 421 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 422 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 423 Depth + 1); 424 case ISD::FSUB: 425 // We can't turn -(A-B) into B-A when we honor signed zeros. 426 if (!Options->UnsafeFPMath) return 0; 427 428 // fold (fneg (fsub A, B)) -> (fsub B, A) 429 return 1; 430 431 case ISD::FMUL: 432 case ISD::FDIV: 433 if (Options->HonorSignDependentRoundingFPMath()) return 0; 434 435 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 436 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 437 Options, Depth + 1)) 438 return V; 439 440 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 441 Depth + 1); 442 443 case ISD::FP_EXTEND: 444 case ISD::FP_ROUND: 445 case ISD::FSIN: 446 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 447 Depth + 1); 448 } 449} 450 451/// GetNegatedExpression - If isNegatibleForFree returns true, this function 452/// returns the newly negated expression. 453static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 454 bool LegalOperations, unsigned Depth = 0) { 455 // fneg is removable even if it has multiple uses. 456 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 457 458 // Don't allow anything with multiple uses. 459 assert(Op.hasOneUse() && "Unknown reuse!"); 460 461 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 462 switch (Op.getOpcode()) { 463 default: llvm_unreachable("Unknown code"); 464 case ISD::ConstantFP: { 465 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 466 V.changeSign(); 467 return DAG.getConstantFP(V, Op.getValueType()); 468 } 469 case ISD::FADD: 470 // FIXME: determine better conditions for this xform. 471 assert(DAG.getTarget().Options.UnsafeFPMath); 472 473 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 474 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 475 DAG.getTargetLoweringInfo(), 476 &DAG.getTarget().Options, Depth+1)) 477 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 478 GetNegatedExpression(Op.getOperand(0), DAG, 479 LegalOperations, Depth+1), 480 Op.getOperand(1)); 481 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 482 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 483 GetNegatedExpression(Op.getOperand(1), DAG, 484 LegalOperations, Depth+1), 485 Op.getOperand(0)); 486 case ISD::FSUB: 487 // We can't turn -(A-B) into B-A when we honor signed zeros. 488 assert(DAG.getTarget().Options.UnsafeFPMath); 489 490 // fold (fneg (fsub 0, B)) -> B 491 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 492 if (N0CFP->getValueAPF().isZero()) 493 return Op.getOperand(1); 494 495 // fold (fneg (fsub A, B)) -> (fsub B, A) 496 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 497 Op.getOperand(1), Op.getOperand(0)); 498 499 case ISD::FMUL: 500 case ISD::FDIV: 501 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 502 503 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 504 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 505 DAG.getTargetLoweringInfo(), 506 &DAG.getTarget().Options, Depth+1)) 507 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 508 GetNegatedExpression(Op.getOperand(0), DAG, 509 LegalOperations, Depth+1), 510 Op.getOperand(1)); 511 512 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 513 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 514 Op.getOperand(0), 515 GetNegatedExpression(Op.getOperand(1), DAG, 516 LegalOperations, Depth+1)); 517 518 case ISD::FP_EXTEND: 519 case ISD::FSIN: 520 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 521 GetNegatedExpression(Op.getOperand(0), DAG, 522 LegalOperations, Depth+1)); 523 case ISD::FP_ROUND: 524 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 525 GetNegatedExpression(Op.getOperand(0), DAG, 526 LegalOperations, Depth+1), 527 Op.getOperand(1)); 528 } 529} 530 531 532// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 533// that selects between the values 1 and 0, making it equivalent to a setcc. 534// Also, set the incoming LHS, RHS, and CC references to the appropriate 535// nodes based on the type of node we are checking. This simplifies life a 536// bit for the callers. 537static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 538 SDValue &CC) { 539 if (N.getOpcode() == ISD::SETCC) { 540 LHS = N.getOperand(0); 541 RHS = N.getOperand(1); 542 CC = N.getOperand(2); 543 return true; 544 } 545 if (N.getOpcode() == ISD::SELECT_CC && 546 N.getOperand(2).getOpcode() == ISD::Constant && 547 N.getOperand(3).getOpcode() == ISD::Constant && 548 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 549 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 550 LHS = N.getOperand(0); 551 RHS = N.getOperand(1); 552 CC = N.getOperand(4); 553 return true; 554 } 555 return false; 556} 557 558// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 559// one use. If this is true, it allows the users to invert the operation for 560// free when it is profitable to do so. 561static bool isOneUseSetCC(SDValue N) { 562 SDValue N0, N1, N2; 563 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 564 return true; 565 return false; 566} 567 568SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 569 SDValue N0, SDValue N1) { 570 EVT VT = N0.getValueType(); 571 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 572 if (isa<ConstantSDNode>(N1)) { 573 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 574 SDValue OpNode = 575 DAG.FoldConstantArithmetic(Opc, VT, 576 cast<ConstantSDNode>(N0.getOperand(1)), 577 cast<ConstantSDNode>(N1)); 578 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 579 } 580 if (N0.hasOneUse()) { 581 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 582 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 583 N0.getOperand(0), N1); 584 AddToWorkList(OpNode.getNode()); 585 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 586 } 587 } 588 589 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 590 if (isa<ConstantSDNode>(N0)) { 591 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 592 SDValue OpNode = 593 DAG.FoldConstantArithmetic(Opc, VT, 594 cast<ConstantSDNode>(N1.getOperand(1)), 595 cast<ConstantSDNode>(N0)); 596 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 597 } 598 if (N1.hasOneUse()) { 599 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 600 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 601 N1.getOperand(0), N0); 602 AddToWorkList(OpNode.getNode()); 603 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 604 } 605 } 606 607 return SDValue(); 608} 609 610SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 611 bool AddTo) { 612 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 613 ++NodesCombined; 614 DEBUG(dbgs() << "\nReplacing.1 "; 615 N->dump(&DAG); 616 dbgs() << "\nWith: "; 617 To[0].getNode()->dump(&DAG); 618 dbgs() << " and " << NumTo-1 << " other values\n"; 619 for (unsigned i = 0, e = NumTo; i != e; ++i) 620 assert((!To[i].getNode() || 621 N->getValueType(i) == To[i].getValueType()) && 622 "Cannot combine value to value of different type!")); 623 WorkListRemover DeadNodes(*this); 624 DAG.ReplaceAllUsesWith(N, To); 625 if (AddTo) { 626 // Push the new nodes and any users onto the worklist 627 for (unsigned i = 0, e = NumTo; i != e; ++i) { 628 if (To[i].getNode()) { 629 AddToWorkList(To[i].getNode()); 630 AddUsersToWorkList(To[i].getNode()); 631 } 632 } 633 } 634 635 // Finally, if the node is now dead, remove it from the graph. The node 636 // may not be dead if the replacement process recursively simplified to 637 // something else needing this node. 638 if (N->use_empty()) { 639 // Nodes can be reintroduced into the worklist. Make sure we do not 640 // process a node that has been replaced. 641 removeFromWorkList(N); 642 643 // Finally, since the node is now dead, remove it from the graph. 644 DAG.DeleteNode(N); 645 } 646 return SDValue(N, 0); 647} 648 649void DAGCombiner:: 650CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 651 // Replace all uses. If any nodes become isomorphic to other nodes and 652 // are deleted, make sure to remove them from our worklist. 653 WorkListRemover DeadNodes(*this); 654 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 655 656 // Push the new node and any (possibly new) users onto the worklist. 657 AddToWorkList(TLO.New.getNode()); 658 AddUsersToWorkList(TLO.New.getNode()); 659 660 // Finally, if the node is now dead, remove it from the graph. The node 661 // may not be dead if the replacement process recursively simplified to 662 // something else needing this node. 663 if (TLO.Old.getNode()->use_empty()) { 664 removeFromWorkList(TLO.Old.getNode()); 665 666 // If the operands of this node are only used by the node, they will now 667 // be dead. Make sure to visit them first to delete dead nodes early. 668 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 669 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 670 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 671 672 DAG.DeleteNode(TLO.Old.getNode()); 673 } 674} 675 676/// SimplifyDemandedBits - Check the specified integer node value to see if 677/// it can be simplified or if things it uses can be simplified by bit 678/// propagation. If so, return true. 679bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 680 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 681 APInt KnownZero, KnownOne; 682 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 683 return false; 684 685 // Revisit the node. 686 AddToWorkList(Op.getNode()); 687 688 // Replace the old value with the new one. 689 ++NodesCombined; 690 DEBUG(dbgs() << "\nReplacing.2 "; 691 TLO.Old.getNode()->dump(&DAG); 692 dbgs() << "\nWith: "; 693 TLO.New.getNode()->dump(&DAG); 694 dbgs() << '\n'); 695 696 CommitTargetLoweringOpt(TLO); 697 return true; 698} 699 700void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 701 DebugLoc dl = Load->getDebugLoc(); 702 EVT VT = Load->getValueType(0); 703 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 704 705 DEBUG(dbgs() << "\nReplacing.9 "; 706 Load->dump(&DAG); 707 dbgs() << "\nWith: "; 708 Trunc.getNode()->dump(&DAG); 709 dbgs() << '\n'); 710 WorkListRemover DeadNodes(*this); 711 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 712 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 713 removeFromWorkList(Load); 714 DAG.DeleteNode(Load); 715 AddToWorkList(Trunc.getNode()); 716} 717 718SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 719 Replace = false; 720 DebugLoc dl = Op.getDebugLoc(); 721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 722 EVT MemVT = LD->getMemoryVT(); 723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 725 : ISD::EXTLOAD) 726 : LD->getExtensionType(); 727 Replace = true; 728 return DAG.getExtLoad(ExtType, dl, PVT, 729 LD->getChain(), LD->getBasePtr(), 730 LD->getPointerInfo(), 731 MemVT, LD->isVolatile(), 732 LD->isNonTemporal(), LD->getAlignment()); 733 } 734 735 unsigned Opc = Op.getOpcode(); 736 switch (Opc) { 737 default: break; 738 case ISD::AssertSext: 739 return DAG.getNode(ISD::AssertSext, dl, PVT, 740 SExtPromoteOperand(Op.getOperand(0), PVT), 741 Op.getOperand(1)); 742 case ISD::AssertZext: 743 return DAG.getNode(ISD::AssertZext, dl, PVT, 744 ZExtPromoteOperand(Op.getOperand(0), PVT), 745 Op.getOperand(1)); 746 case ISD::Constant: { 747 unsigned ExtOpc = 748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 749 return DAG.getNode(ExtOpc, dl, PVT, Op); 750 } 751 } 752 753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 754 return SDValue(); 755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 756} 757 758SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 760 return SDValue(); 761 EVT OldVT = Op.getValueType(); 762 DebugLoc dl = Op.getDebugLoc(); 763 bool Replace = false; 764 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 765 if (NewOp.getNode() == 0) 766 return SDValue(); 767 AddToWorkList(NewOp.getNode()); 768 769 if (Replace) 770 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 772 DAG.getValueType(OldVT)); 773} 774 775SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 776 EVT OldVT = Op.getValueType(); 777 DebugLoc dl = Op.getDebugLoc(); 778 bool Replace = false; 779 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 780 if (NewOp.getNode() == 0) 781 return SDValue(); 782 AddToWorkList(NewOp.getNode()); 783 784 if (Replace) 785 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 786 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 787} 788 789/// PromoteIntBinOp - Promote the specified integer binary operation if the 790/// target indicates it is beneficial. e.g. On x86, it's usually better to 791/// promote i16 operations to i32 since i16 instructions are longer. 792SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 793 if (!LegalOperations) 794 return SDValue(); 795 796 EVT VT = Op.getValueType(); 797 if (VT.isVector() || !VT.isInteger()) 798 return SDValue(); 799 800 // If operation type is 'undesirable', e.g. i16 on x86, consider 801 // promoting it. 802 unsigned Opc = Op.getOpcode(); 803 if (TLI.isTypeDesirableForOp(Opc, VT)) 804 return SDValue(); 805 806 EVT PVT = VT; 807 // Consult target whether it is a good idea to promote this operation and 808 // what's the right type to promote it to. 809 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 810 assert(PVT != VT && "Don't know what type to promote to!"); 811 812 bool Replace0 = false; 813 SDValue N0 = Op.getOperand(0); 814 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 815 if (NN0.getNode() == 0) 816 return SDValue(); 817 818 bool Replace1 = false; 819 SDValue N1 = Op.getOperand(1); 820 SDValue NN1; 821 if (N0 == N1) 822 NN1 = NN0; 823 else { 824 NN1 = PromoteOperand(N1, PVT, Replace1); 825 if (NN1.getNode() == 0) 826 return SDValue(); 827 } 828 829 AddToWorkList(NN0.getNode()); 830 if (NN1.getNode()) 831 AddToWorkList(NN1.getNode()); 832 833 if (Replace0) 834 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 835 if (Replace1) 836 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 837 838 DEBUG(dbgs() << "\nPromoting "; 839 Op.getNode()->dump(&DAG)); 840 DebugLoc dl = Op.getDebugLoc(); 841 return DAG.getNode(ISD::TRUNCATE, dl, VT, 842 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 843 } 844 return SDValue(); 845} 846 847/// PromoteIntShiftOp - Promote the specified integer shift operation if the 848/// target indicates it is beneficial. e.g. On x86, it's usually better to 849/// promote i16 operations to i32 since i16 instructions are longer. 850SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 851 if (!LegalOperations) 852 return SDValue(); 853 854 EVT VT = Op.getValueType(); 855 if (VT.isVector() || !VT.isInteger()) 856 return SDValue(); 857 858 // If operation type is 'undesirable', e.g. i16 on x86, consider 859 // promoting it. 860 unsigned Opc = Op.getOpcode(); 861 if (TLI.isTypeDesirableForOp(Opc, VT)) 862 return SDValue(); 863 864 EVT PVT = VT; 865 // Consult target whether it is a good idea to promote this operation and 866 // what's the right type to promote it to. 867 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 868 assert(PVT != VT && "Don't know what type to promote to!"); 869 870 bool Replace = false; 871 SDValue N0 = Op.getOperand(0); 872 if (Opc == ISD::SRA) 873 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 874 else if (Opc == ISD::SRL) 875 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 876 else 877 N0 = PromoteOperand(N0, PVT, Replace); 878 if (N0.getNode() == 0) 879 return SDValue(); 880 881 AddToWorkList(N0.getNode()); 882 if (Replace) 883 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 884 885 DEBUG(dbgs() << "\nPromoting "; 886 Op.getNode()->dump(&DAG)); 887 DebugLoc dl = Op.getDebugLoc(); 888 return DAG.getNode(ISD::TRUNCATE, dl, VT, 889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 890 } 891 return SDValue(); 892} 893 894SDValue DAGCombiner::PromoteExtend(SDValue Op) { 895 if (!LegalOperations) 896 return SDValue(); 897 898 EVT VT = Op.getValueType(); 899 if (VT.isVector() || !VT.isInteger()) 900 return SDValue(); 901 902 // If operation type is 'undesirable', e.g. i16 on x86, consider 903 // promoting it. 904 unsigned Opc = Op.getOpcode(); 905 if (TLI.isTypeDesirableForOp(Opc, VT)) 906 return SDValue(); 907 908 EVT PVT = VT; 909 // Consult target whether it is a good idea to promote this operation and 910 // what's the right type to promote it to. 911 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 912 assert(PVT != VT && "Don't know what type to promote to!"); 913 // fold (aext (aext x)) -> (aext x) 914 // fold (aext (zext x)) -> (zext x) 915 // fold (aext (sext x)) -> (sext x) 916 DEBUG(dbgs() << "\nPromoting "; 917 Op.getNode()->dump(&DAG)); 918 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 919 } 920 return SDValue(); 921} 922 923bool DAGCombiner::PromoteLoad(SDValue Op) { 924 if (!LegalOperations) 925 return false; 926 927 EVT VT = Op.getValueType(); 928 if (VT.isVector() || !VT.isInteger()) 929 return false; 930 931 // If operation type is 'undesirable', e.g. i16 on x86, consider 932 // promoting it. 933 unsigned Opc = Op.getOpcode(); 934 if (TLI.isTypeDesirableForOp(Opc, VT)) 935 return false; 936 937 EVT PVT = VT; 938 // Consult target whether it is a good idea to promote this operation and 939 // what's the right type to promote it to. 940 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 941 assert(PVT != VT && "Don't know what type to promote to!"); 942 943 DebugLoc dl = Op.getDebugLoc(); 944 SDNode *N = Op.getNode(); 945 LoadSDNode *LD = cast<LoadSDNode>(N); 946 EVT MemVT = LD->getMemoryVT(); 947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 949 : ISD::EXTLOAD) 950 : LD->getExtensionType(); 951 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 952 LD->getChain(), LD->getBasePtr(), 953 LD->getPointerInfo(), 954 MemVT, LD->isVolatile(), 955 LD->isNonTemporal(), LD->getAlignment()); 956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 957 958 DEBUG(dbgs() << "\nPromoting "; 959 N->dump(&DAG); 960 dbgs() << "\nTo: "; 961 Result.getNode()->dump(&DAG); 962 dbgs() << '\n'); 963 WorkListRemover DeadNodes(*this); 964 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 965 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 966 removeFromWorkList(N); 967 DAG.DeleteNode(N); 968 AddToWorkList(Result.getNode()); 969 return true; 970 } 971 return false; 972} 973 974 975//===----------------------------------------------------------------------===// 976// Main DAG Combiner implementation 977//===----------------------------------------------------------------------===// 978 979void DAGCombiner::Run(CombineLevel AtLevel) { 980 // set the instance variables, so that the various visit routines may use it. 981 Level = AtLevel; 982 LegalOperations = Level >= AfterLegalizeVectorOps; 983 LegalTypes = Level >= AfterLegalizeTypes; 984 985 // Add all the dag nodes to the worklist. 986 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 987 E = DAG.allnodes_end(); I != E; ++I) 988 AddToWorkList(I); 989 990 // Create a dummy node (which is not added to allnodes), that adds a reference 991 // to the root node, preventing it from being deleted, and tracking any 992 // changes of the root. 993 HandleSDNode Dummy(DAG.getRoot()); 994 995 // The root of the dag may dangle to deleted nodes until the dag combiner is 996 // done. Set it to null to avoid confusion. 997 DAG.setRoot(SDValue()); 998 999 // while the worklist isn't empty, find a node and 1000 // try and combine it. 1001 while (!WorkListContents.empty()) { 1002 SDNode *N; 1003 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1004 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1005 // worklist *should* contain, and check the node we want to visit is should 1006 // actually be visited. 1007 do { 1008 N = WorkListOrder.pop_back_val(); 1009 } while (!WorkListContents.erase(N)); 1010 1011 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1012 // N is deleted from the DAG, since they too may now be dead or may have a 1013 // reduced number of uses, allowing other xforms. 1014 if (N->use_empty() && N != &Dummy) { 1015 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1016 AddToWorkList(N->getOperand(i).getNode()); 1017 1018 DAG.DeleteNode(N); 1019 continue; 1020 } 1021 1022 SDValue RV = combine(N); 1023 1024 if (RV.getNode() == 0) 1025 continue; 1026 1027 ++NodesCombined; 1028 1029 // If we get back the same node we passed in, rather than a new node or 1030 // zero, we know that the node must have defined multiple values and 1031 // CombineTo was used. Since CombineTo takes care of the worklist 1032 // mechanics for us, we have no work to do in this case. 1033 if (RV.getNode() == N) 1034 continue; 1035 1036 assert(N->getOpcode() != ISD::DELETED_NODE && 1037 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1038 "Node was deleted but visit returned new node!"); 1039 1040 DEBUG(dbgs() << "\nReplacing.3 "; 1041 N->dump(&DAG); 1042 dbgs() << "\nWith: "; 1043 RV.getNode()->dump(&DAG); 1044 dbgs() << '\n'); 1045 1046 // Transfer debug value. 1047 DAG.TransferDbgValues(SDValue(N, 0), RV); 1048 WorkListRemover DeadNodes(*this); 1049 if (N->getNumValues() == RV.getNode()->getNumValues()) 1050 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1051 else { 1052 assert(N->getValueType(0) == RV.getValueType() && 1053 N->getNumValues() == 1 && "Type mismatch"); 1054 SDValue OpV = RV; 1055 DAG.ReplaceAllUsesWith(N, &OpV); 1056 } 1057 1058 // Push the new node and any users onto the worklist 1059 AddToWorkList(RV.getNode()); 1060 AddUsersToWorkList(RV.getNode()); 1061 1062 // Add any uses of the old node to the worklist in case this node is the 1063 // last one that uses them. They may become dead after this node is 1064 // deleted. 1065 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1066 AddToWorkList(N->getOperand(i).getNode()); 1067 1068 // Finally, if the node is now dead, remove it from the graph. The node 1069 // may not be dead if the replacement process recursively simplified to 1070 // something else needing this node. 1071 if (N->use_empty()) { 1072 // Nodes can be reintroduced into the worklist. Make sure we do not 1073 // process a node that has been replaced. 1074 removeFromWorkList(N); 1075 1076 // Finally, since the node is now dead, remove it from the graph. 1077 DAG.DeleteNode(N); 1078 } 1079 } 1080 1081 // If the root changed (e.g. it was a dead load, update the root). 1082 DAG.setRoot(Dummy.getValue()); 1083 DAG.RemoveDeadNodes(); 1084} 1085 1086SDValue DAGCombiner::visit(SDNode *N) { 1087 switch (N->getOpcode()) { 1088 default: break; 1089 case ISD::TokenFactor: return visitTokenFactor(N); 1090 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1091 case ISD::ADD: return visitADD(N); 1092 case ISD::SUB: return visitSUB(N); 1093 case ISD::ADDC: return visitADDC(N); 1094 case ISD::SUBC: return visitSUBC(N); 1095 case ISD::ADDE: return visitADDE(N); 1096 case ISD::SUBE: return visitSUBE(N); 1097 case ISD::MUL: return visitMUL(N); 1098 case ISD::SDIV: return visitSDIV(N); 1099 case ISD::UDIV: return visitUDIV(N); 1100 case ISD::SREM: return visitSREM(N); 1101 case ISD::UREM: return visitUREM(N); 1102 case ISD::MULHU: return visitMULHU(N); 1103 case ISD::MULHS: return visitMULHS(N); 1104 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1105 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1106 case ISD::SMULO: return visitSMULO(N); 1107 case ISD::UMULO: return visitUMULO(N); 1108 case ISD::SDIVREM: return visitSDIVREM(N); 1109 case ISD::UDIVREM: return visitUDIVREM(N); 1110 case ISD::AND: return visitAND(N); 1111 case ISD::OR: return visitOR(N); 1112 case ISD::XOR: return visitXOR(N); 1113 case ISD::SHL: return visitSHL(N); 1114 case ISD::SRA: return visitSRA(N); 1115 case ISD::SRL: return visitSRL(N); 1116 case ISD::CTLZ: return visitCTLZ(N); 1117 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1118 case ISD::CTTZ: return visitCTTZ(N); 1119 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1120 case ISD::CTPOP: return visitCTPOP(N); 1121 case ISD::SELECT: return visitSELECT(N); 1122 case ISD::SELECT_CC: return visitSELECT_CC(N); 1123 case ISD::SETCC: return visitSETCC(N); 1124 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1125 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1126 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1127 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1128 case ISD::TRUNCATE: return visitTRUNCATE(N); 1129 case ISD::BITCAST: return visitBITCAST(N); 1130 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1131 case ISD::FADD: return visitFADD(N); 1132 case ISD::FSUB: return visitFSUB(N); 1133 case ISD::FMUL: return visitFMUL(N); 1134 case ISD::FMA: return visitFMA(N); 1135 case ISD::FDIV: return visitFDIV(N); 1136 case ISD::FREM: return visitFREM(N); 1137 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1138 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1139 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1140 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1141 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1142 case ISD::FP_ROUND: return visitFP_ROUND(N); 1143 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1144 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1145 case ISD::FNEG: return visitFNEG(N); 1146 case ISD::FABS: return visitFABS(N); 1147 case ISD::FFLOOR: return visitFFLOOR(N); 1148 case ISD::FCEIL: return visitFCEIL(N); 1149 case ISD::FTRUNC: return visitFTRUNC(N); 1150 case ISD::BRCOND: return visitBRCOND(N); 1151 case ISD::BR_CC: return visitBR_CC(N); 1152 case ISD::LOAD: return visitLOAD(N); 1153 case ISD::STORE: return visitSTORE(N); 1154 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1155 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1156 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1157 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1158 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1159 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1160 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1161 } 1162 return SDValue(); 1163} 1164 1165SDValue DAGCombiner::combine(SDNode *N) { 1166 SDValue RV = visit(N); 1167 1168 // If nothing happened, try a target-specific DAG combine. 1169 if (RV.getNode() == 0) { 1170 assert(N->getOpcode() != ISD::DELETED_NODE && 1171 "Node was deleted but visit returned NULL!"); 1172 1173 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1174 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1175 1176 // Expose the DAG combiner to the target combiner impls. 1177 TargetLowering::DAGCombinerInfo 1178 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1179 1180 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1181 } 1182 } 1183 1184 // If nothing happened still, try promoting the operation. 1185 if (RV.getNode() == 0) { 1186 switch (N->getOpcode()) { 1187 default: break; 1188 case ISD::ADD: 1189 case ISD::SUB: 1190 case ISD::MUL: 1191 case ISD::AND: 1192 case ISD::OR: 1193 case ISD::XOR: 1194 RV = PromoteIntBinOp(SDValue(N, 0)); 1195 break; 1196 case ISD::SHL: 1197 case ISD::SRA: 1198 case ISD::SRL: 1199 RV = PromoteIntShiftOp(SDValue(N, 0)); 1200 break; 1201 case ISD::SIGN_EXTEND: 1202 case ISD::ZERO_EXTEND: 1203 case ISD::ANY_EXTEND: 1204 RV = PromoteExtend(SDValue(N, 0)); 1205 break; 1206 case ISD::LOAD: 1207 if (PromoteLoad(SDValue(N, 0))) 1208 RV = SDValue(N, 0); 1209 break; 1210 } 1211 } 1212 1213 // If N is a commutative binary node, try commuting it to enable more 1214 // sdisel CSE. 1215 if (RV.getNode() == 0 && 1216 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1217 N->getNumValues() == 1) { 1218 SDValue N0 = N->getOperand(0); 1219 SDValue N1 = N->getOperand(1); 1220 1221 // Constant operands are canonicalized to RHS. 1222 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1223 SDValue Ops[] = { N1, N0 }; 1224 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1225 Ops, 2); 1226 if (CSENode) 1227 return SDValue(CSENode, 0); 1228 } 1229 } 1230 1231 return RV; 1232} 1233 1234/// getInputChainForNode - Given a node, return its input chain if it has one, 1235/// otherwise return a null sd operand. 1236static SDValue getInputChainForNode(SDNode *N) { 1237 if (unsigned NumOps = N->getNumOperands()) { 1238 if (N->getOperand(0).getValueType() == MVT::Other) 1239 return N->getOperand(0); 1240 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1241 return N->getOperand(NumOps-1); 1242 for (unsigned i = 1; i < NumOps-1; ++i) 1243 if (N->getOperand(i).getValueType() == MVT::Other) 1244 return N->getOperand(i); 1245 } 1246 return SDValue(); 1247} 1248 1249SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1250 // If N has two operands, where one has an input chain equal to the other, 1251 // the 'other' chain is redundant. 1252 if (N->getNumOperands() == 2) { 1253 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1254 return N->getOperand(0); 1255 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1256 return N->getOperand(1); 1257 } 1258 1259 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1260 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1261 SmallPtrSet<SDNode*, 16> SeenOps; 1262 bool Changed = false; // If we should replace this token factor. 1263 1264 // Start out with this token factor. 1265 TFs.push_back(N); 1266 1267 // Iterate through token factors. The TFs grows when new token factors are 1268 // encountered. 1269 for (unsigned i = 0; i < TFs.size(); ++i) { 1270 SDNode *TF = TFs[i]; 1271 1272 // Check each of the operands. 1273 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1274 SDValue Op = TF->getOperand(i); 1275 1276 switch (Op.getOpcode()) { 1277 case ISD::EntryToken: 1278 // Entry tokens don't need to be added to the list. They are 1279 // rededundant. 1280 Changed = true; 1281 break; 1282 1283 case ISD::TokenFactor: 1284 if (Op.hasOneUse() && 1285 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1286 // Queue up for processing. 1287 TFs.push_back(Op.getNode()); 1288 // Clean up in case the token factor is removed. 1289 AddToWorkList(Op.getNode()); 1290 Changed = true; 1291 break; 1292 } 1293 // Fall thru 1294 1295 default: 1296 // Only add if it isn't already in the list. 1297 if (SeenOps.insert(Op.getNode())) 1298 Ops.push_back(Op); 1299 else 1300 Changed = true; 1301 break; 1302 } 1303 } 1304 } 1305 1306 SDValue Result; 1307 1308 // If we've change things around then replace token factor. 1309 if (Changed) { 1310 if (Ops.empty()) { 1311 // The entry token is the only possible outcome. 1312 Result = DAG.getEntryNode(); 1313 } else { 1314 // New and improved token factor. 1315 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1316 MVT::Other, &Ops[0], Ops.size()); 1317 } 1318 1319 // Don't add users to work list. 1320 return CombineTo(N, Result, false); 1321 } 1322 1323 return Result; 1324} 1325 1326/// MERGE_VALUES can always be eliminated. 1327SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1328 WorkListRemover DeadNodes(*this); 1329 // Replacing results may cause a different MERGE_VALUES to suddenly 1330 // be CSE'd with N, and carry its uses with it. Iterate until no 1331 // uses remain, to ensure that the node can be safely deleted. 1332 // First add the users of this node to the work list so that they 1333 // can be tried again once they have new operands. 1334 AddUsersToWorkList(N); 1335 do { 1336 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1337 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1338 } while (!N->use_empty()); 1339 removeFromWorkList(N); 1340 DAG.DeleteNode(N); 1341 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1342} 1343 1344static 1345SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1346 SelectionDAG &DAG) { 1347 EVT VT = N0.getValueType(); 1348 SDValue N00 = N0.getOperand(0); 1349 SDValue N01 = N0.getOperand(1); 1350 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1351 1352 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1353 isa<ConstantSDNode>(N00.getOperand(1))) { 1354 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1355 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1356 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1357 N00.getOperand(0), N01), 1358 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1359 N00.getOperand(1), N01)); 1360 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1361 } 1362 1363 return SDValue(); 1364} 1365 1366SDValue DAGCombiner::visitADD(SDNode *N) { 1367 SDValue N0 = N->getOperand(0); 1368 SDValue N1 = N->getOperand(1); 1369 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1370 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1371 EVT VT = N0.getValueType(); 1372 1373 // fold vector ops 1374 if (VT.isVector()) { 1375 SDValue FoldedVOp = SimplifyVBinOp(N); 1376 if (FoldedVOp.getNode()) return FoldedVOp; 1377 } 1378 1379 // fold (add x, undef) -> undef 1380 if (N0.getOpcode() == ISD::UNDEF) 1381 return N0; 1382 if (N1.getOpcode() == ISD::UNDEF) 1383 return N1; 1384 // fold (add c1, c2) -> c1+c2 1385 if (N0C && N1C) 1386 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1387 // canonicalize constant to RHS 1388 if (N0C && !N1C) 1389 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1390 // fold (add x, 0) -> x 1391 if (N1C && N1C->isNullValue()) 1392 return N0; 1393 // fold (add Sym, c) -> Sym+c 1394 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1395 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1396 GA->getOpcode() == ISD::GlobalAddress) 1397 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1398 GA->getOffset() + 1399 (uint64_t)N1C->getSExtValue()); 1400 // fold ((c1-A)+c2) -> (c1+c2)-A 1401 if (N1C && N0.getOpcode() == ISD::SUB) 1402 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1403 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1404 DAG.getConstant(N1C->getAPIntValue()+ 1405 N0C->getAPIntValue(), VT), 1406 N0.getOperand(1)); 1407 // reassociate add 1408 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1409 if (RADD.getNode() != 0) 1410 return RADD; 1411 // fold ((0-A) + B) -> B-A 1412 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1413 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1414 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1415 // fold (A + (0-B)) -> A-B 1416 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1417 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1418 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1419 // fold (A+(B-A)) -> B 1420 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1421 return N1.getOperand(0); 1422 // fold ((B-A)+A) -> B 1423 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1424 return N0.getOperand(0); 1425 // fold (A+(B-(A+C))) to (B-C) 1426 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1427 N0 == N1.getOperand(1).getOperand(0)) 1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1429 N1.getOperand(1).getOperand(1)); 1430 // fold (A+(B-(C+A))) to (B-C) 1431 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1432 N0 == N1.getOperand(1).getOperand(1)) 1433 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1434 N1.getOperand(1).getOperand(0)); 1435 // fold (A+((B-A)+or-C)) to (B+or-C) 1436 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1437 N1.getOperand(0).getOpcode() == ISD::SUB && 1438 N0 == N1.getOperand(0).getOperand(1)) 1439 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1440 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1441 1442 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1443 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1444 SDValue N00 = N0.getOperand(0); 1445 SDValue N01 = N0.getOperand(1); 1446 SDValue N10 = N1.getOperand(0); 1447 SDValue N11 = N1.getOperand(1); 1448 1449 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1450 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1451 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1452 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1453 } 1454 1455 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1456 return SDValue(N, 0); 1457 1458 // fold (a+b) -> (a|b) iff a and b share no bits. 1459 if (VT.isInteger() && !VT.isVector()) { 1460 APInt LHSZero, LHSOne; 1461 APInt RHSZero, RHSOne; 1462 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1463 1464 if (LHSZero.getBoolValue()) { 1465 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1466 1467 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1468 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1469 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1470 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1471 } 1472 } 1473 1474 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1475 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1476 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1477 if (Result.getNode()) return Result; 1478 } 1479 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1480 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1481 if (Result.getNode()) return Result; 1482 } 1483 1484 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1485 if (N1.getOpcode() == ISD::SHL && 1486 N1.getOperand(0).getOpcode() == ISD::SUB) 1487 if (ConstantSDNode *C = 1488 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1489 if (C->getAPIntValue() == 0) 1490 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1491 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1492 N1.getOperand(0).getOperand(1), 1493 N1.getOperand(1))); 1494 if (N0.getOpcode() == ISD::SHL && 1495 N0.getOperand(0).getOpcode() == ISD::SUB) 1496 if (ConstantSDNode *C = 1497 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1498 if (C->getAPIntValue() == 0) 1499 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1500 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1501 N0.getOperand(0).getOperand(1), 1502 N0.getOperand(1))); 1503 1504 if (N1.getOpcode() == ISD::AND) { 1505 SDValue AndOp0 = N1.getOperand(0); 1506 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1507 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1508 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1509 1510 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1511 // and similar xforms where the inner op is either ~0 or 0. 1512 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1513 DebugLoc DL = N->getDebugLoc(); 1514 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1515 } 1516 } 1517 1518 // add (sext i1), X -> sub X, (zext i1) 1519 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1520 N0.getOperand(0).getValueType() == MVT::i1 && 1521 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1522 DebugLoc DL = N->getDebugLoc(); 1523 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1524 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1525 } 1526 1527 return SDValue(); 1528} 1529 1530SDValue DAGCombiner::visitADDC(SDNode *N) { 1531 SDValue N0 = N->getOperand(0); 1532 SDValue N1 = N->getOperand(1); 1533 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1534 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1535 EVT VT = N0.getValueType(); 1536 1537 // If the flag result is dead, turn this into an ADD. 1538 if (!N->hasAnyUseOfValue(1)) 1539 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1540 DAG.getNode(ISD::CARRY_FALSE, 1541 N->getDebugLoc(), MVT::Glue)); 1542 1543 // canonicalize constant to RHS. 1544 if (N0C && !N1C) 1545 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1546 1547 // fold (addc x, 0) -> x + no carry out 1548 if (N1C && N1C->isNullValue()) 1549 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1550 N->getDebugLoc(), MVT::Glue)); 1551 1552 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1553 APInt LHSZero, LHSOne; 1554 APInt RHSZero, RHSOne; 1555 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1556 1557 if (LHSZero.getBoolValue()) { 1558 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1559 1560 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1561 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1562 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1563 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1564 DAG.getNode(ISD::CARRY_FALSE, 1565 N->getDebugLoc(), MVT::Glue)); 1566 } 1567 1568 return SDValue(); 1569} 1570 1571SDValue DAGCombiner::visitADDE(SDNode *N) { 1572 SDValue N0 = N->getOperand(0); 1573 SDValue N1 = N->getOperand(1); 1574 SDValue CarryIn = N->getOperand(2); 1575 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1576 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1577 1578 // canonicalize constant to RHS 1579 if (N0C && !N1C) 1580 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1581 N1, N0, CarryIn); 1582 1583 // fold (adde x, y, false) -> (addc x, y) 1584 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1585 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1586 1587 return SDValue(); 1588} 1589 1590// Since it may not be valid to emit a fold to zero for vector initializers 1591// check if we can before folding. 1592static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1593 SelectionDAG &DAG, bool LegalOperations) { 1594 if (!VT.isVector()) { 1595 return DAG.getConstant(0, VT); 1596 } 1597 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1598 // Produce a vector of zeros. 1599 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1600 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1601 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1602 &Ops[0], Ops.size()); 1603 } 1604 return SDValue(); 1605} 1606 1607SDValue DAGCombiner::visitSUB(SDNode *N) { 1608 SDValue N0 = N->getOperand(0); 1609 SDValue N1 = N->getOperand(1); 1610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1612 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1613 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1614 EVT VT = N0.getValueType(); 1615 1616 // fold vector ops 1617 if (VT.isVector()) { 1618 SDValue FoldedVOp = SimplifyVBinOp(N); 1619 if (FoldedVOp.getNode()) return FoldedVOp; 1620 } 1621 1622 // fold (sub x, x) -> 0 1623 // FIXME: Refactor this and xor and other similar operations together. 1624 if (N0 == N1) 1625 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1626 // fold (sub c1, c2) -> c1-c2 1627 if (N0C && N1C) 1628 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1629 // fold (sub x, c) -> (add x, -c) 1630 if (N1C) 1631 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1632 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1633 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1634 if (N0C && N0C->isAllOnesValue()) 1635 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1636 // fold A-(A-B) -> B 1637 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1638 return N1.getOperand(1); 1639 // fold (A+B)-A -> B 1640 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1641 return N0.getOperand(1); 1642 // fold (A+B)-B -> A 1643 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1644 return N0.getOperand(0); 1645 // fold C2-(A+C1) -> (C2-C1)-A 1646 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1647 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), 1648 VT); 1649 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1650 N1.getOperand(0)); 1651 } 1652 // fold ((A+(B+or-C))-B) -> A+or-C 1653 if (N0.getOpcode() == ISD::ADD && 1654 (N0.getOperand(1).getOpcode() == ISD::SUB || 1655 N0.getOperand(1).getOpcode() == ISD::ADD) && 1656 N0.getOperand(1).getOperand(0) == N1) 1657 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1658 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1659 // fold ((A+(C+B))-B) -> A+C 1660 if (N0.getOpcode() == ISD::ADD && 1661 N0.getOperand(1).getOpcode() == ISD::ADD && 1662 N0.getOperand(1).getOperand(1) == N1) 1663 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1664 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1665 // fold ((A-(B-C))-C) -> A-B 1666 if (N0.getOpcode() == ISD::SUB && 1667 N0.getOperand(1).getOpcode() == ISD::SUB && 1668 N0.getOperand(1).getOperand(1) == N1) 1669 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1670 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1671 1672 // If either operand of a sub is undef, the result is undef 1673 if (N0.getOpcode() == ISD::UNDEF) 1674 return N0; 1675 if (N1.getOpcode() == ISD::UNDEF) 1676 return N1; 1677 1678 // If the relocation model supports it, consider symbol offsets. 1679 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1680 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1681 // fold (sub Sym, c) -> Sym-c 1682 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1683 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1684 GA->getOffset() - 1685 (uint64_t)N1C->getSExtValue()); 1686 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1687 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1688 if (GA->getGlobal() == GB->getGlobal()) 1689 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1690 VT); 1691 } 1692 1693 return SDValue(); 1694} 1695 1696SDValue DAGCombiner::visitSUBC(SDNode *N) { 1697 SDValue N0 = N->getOperand(0); 1698 SDValue N1 = N->getOperand(1); 1699 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1700 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1701 EVT VT = N0.getValueType(); 1702 1703 // If the flag result is dead, turn this into an SUB. 1704 if (!N->hasAnyUseOfValue(1)) 1705 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1706 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1707 MVT::Glue)); 1708 1709 // fold (subc x, x) -> 0 + no borrow 1710 if (N0 == N1) 1711 return CombineTo(N, DAG.getConstant(0, VT), 1712 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1713 MVT::Glue)); 1714 1715 // fold (subc x, 0) -> x + no borrow 1716 if (N1C && N1C->isNullValue()) 1717 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1718 MVT::Glue)); 1719 1720 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1721 if (N0C && N0C->isAllOnesValue()) 1722 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1723 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1724 MVT::Glue)); 1725 1726 return SDValue(); 1727} 1728 1729SDValue DAGCombiner::visitSUBE(SDNode *N) { 1730 SDValue N0 = N->getOperand(0); 1731 SDValue N1 = N->getOperand(1); 1732 SDValue CarryIn = N->getOperand(2); 1733 1734 // fold (sube x, y, false) -> (subc x, y) 1735 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1736 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1737 1738 return SDValue(); 1739} 1740 1741SDValue DAGCombiner::visitMUL(SDNode *N) { 1742 SDValue N0 = N->getOperand(0); 1743 SDValue N1 = N->getOperand(1); 1744 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1745 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1746 EVT VT = N0.getValueType(); 1747 1748 // fold vector ops 1749 if (VT.isVector()) { 1750 SDValue FoldedVOp = SimplifyVBinOp(N); 1751 if (FoldedVOp.getNode()) return FoldedVOp; 1752 } 1753 1754 // fold (mul x, undef) -> 0 1755 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1756 return DAG.getConstant(0, VT); 1757 // fold (mul c1, c2) -> c1*c2 1758 if (N0C && N1C) 1759 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1760 // canonicalize constant to RHS 1761 if (N0C && !N1C) 1762 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1763 // fold (mul x, 0) -> 0 1764 if (N1C && N1C->isNullValue()) 1765 return N1; 1766 // fold (mul x, -1) -> 0-x 1767 if (N1C && N1C->isAllOnesValue()) 1768 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1769 DAG.getConstant(0, VT), N0); 1770 // fold (mul x, (1 << c)) -> x << c 1771 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1772 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1773 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1774 getShiftAmountTy(N0.getValueType()))); 1775 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1776 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1777 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1778 // FIXME: If the input is something that is easily negated (e.g. a 1779 // single-use add), we should put the negate there. 1780 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1781 DAG.getConstant(0, VT), 1782 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1783 DAG.getConstant(Log2Val, 1784 getShiftAmountTy(N0.getValueType())))); 1785 } 1786 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1787 if (N1C && N0.getOpcode() == ISD::SHL && 1788 isa<ConstantSDNode>(N0.getOperand(1))) { 1789 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1790 N1, N0.getOperand(1)); 1791 AddToWorkList(C3.getNode()); 1792 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1793 N0.getOperand(0), C3); 1794 } 1795 1796 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1797 // use. 1798 { 1799 SDValue Sh(0,0), Y(0,0); 1800 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1801 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1802 N0.getNode()->hasOneUse()) { 1803 Sh = N0; Y = N1; 1804 } else if (N1.getOpcode() == ISD::SHL && 1805 isa<ConstantSDNode>(N1.getOperand(1)) && 1806 N1.getNode()->hasOneUse()) { 1807 Sh = N1; Y = N0; 1808 } 1809 1810 if (Sh.getNode()) { 1811 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1812 Sh.getOperand(0), Y); 1813 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1814 Mul, Sh.getOperand(1)); 1815 } 1816 } 1817 1818 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1819 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1820 isa<ConstantSDNode>(N0.getOperand(1))) 1821 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1822 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1823 N0.getOperand(0), N1), 1824 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1825 N0.getOperand(1), N1)); 1826 1827 // reassociate mul 1828 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1829 if (RMUL.getNode() != 0) 1830 return RMUL; 1831 1832 return SDValue(); 1833} 1834 1835SDValue DAGCombiner::visitSDIV(SDNode *N) { 1836 SDValue N0 = N->getOperand(0); 1837 SDValue N1 = N->getOperand(1); 1838 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1839 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1840 EVT VT = N->getValueType(0); 1841 1842 // fold vector ops 1843 if (VT.isVector()) { 1844 SDValue FoldedVOp = SimplifyVBinOp(N); 1845 if (FoldedVOp.getNode()) return FoldedVOp; 1846 } 1847 1848 // fold (sdiv c1, c2) -> c1/c2 1849 if (N0C && N1C && !N1C->isNullValue()) 1850 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1851 // fold (sdiv X, 1) -> X 1852 if (N1C && N1C->getAPIntValue() == 1LL) 1853 return N0; 1854 // fold (sdiv X, -1) -> 0-X 1855 if (N1C && N1C->isAllOnesValue()) 1856 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1857 DAG.getConstant(0, VT), N0); 1858 // If we know the sign bits of both operands are zero, strength reduce to a 1859 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1860 if (!VT.isVector()) { 1861 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1862 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1863 N0, N1); 1864 } 1865 // fold (sdiv X, pow2) -> simple ops after legalize 1866 if (N1C && !N1C->isNullValue() && 1867 (N1C->getAPIntValue().isPowerOf2() || 1868 (-N1C->getAPIntValue()).isPowerOf2())) { 1869 // If dividing by powers of two is cheap, then don't perform the following 1870 // fold. 1871 if (TLI.isPow2DivCheap()) 1872 return SDValue(); 1873 1874 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1875 1876 // Splat the sign bit into the register 1877 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1878 DAG.getConstant(VT.getSizeInBits()-1, 1879 getShiftAmountTy(N0.getValueType()))); 1880 AddToWorkList(SGN.getNode()); 1881 1882 // Add (N0 < 0) ? abs2 - 1 : 0; 1883 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1884 DAG.getConstant(VT.getSizeInBits() - lg2, 1885 getShiftAmountTy(SGN.getValueType()))); 1886 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1887 AddToWorkList(SRL.getNode()); 1888 AddToWorkList(ADD.getNode()); // Divide by pow2 1889 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1890 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1891 1892 // If we're dividing by a positive value, we're done. Otherwise, we must 1893 // negate the result. 1894 if (N1C->getAPIntValue().isNonNegative()) 1895 return SRA; 1896 1897 AddToWorkList(SRA.getNode()); 1898 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1899 DAG.getConstant(0, VT), SRA); 1900 } 1901 1902 // if integer divide is expensive and we satisfy the requirements, emit an 1903 // alternate sequence. 1904 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1905 SDValue Op = BuildSDIV(N); 1906 if (Op.getNode()) return Op; 1907 } 1908 1909 // undef / X -> 0 1910 if (N0.getOpcode() == ISD::UNDEF) 1911 return DAG.getConstant(0, VT); 1912 // X / undef -> undef 1913 if (N1.getOpcode() == ISD::UNDEF) 1914 return N1; 1915 1916 return SDValue(); 1917} 1918 1919SDValue DAGCombiner::visitUDIV(SDNode *N) { 1920 SDValue N0 = N->getOperand(0); 1921 SDValue N1 = N->getOperand(1); 1922 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1923 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1924 EVT VT = N->getValueType(0); 1925 1926 // fold vector ops 1927 if (VT.isVector()) { 1928 SDValue FoldedVOp = SimplifyVBinOp(N); 1929 if (FoldedVOp.getNode()) return FoldedVOp; 1930 } 1931 1932 // fold (udiv c1, c2) -> c1/c2 1933 if (N0C && N1C && !N1C->isNullValue()) 1934 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1935 // fold (udiv x, (1 << c)) -> x >>u c 1936 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1937 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1938 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1939 getShiftAmountTy(N0.getValueType()))); 1940 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1941 if (N1.getOpcode() == ISD::SHL) { 1942 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1943 if (SHC->getAPIntValue().isPowerOf2()) { 1944 EVT ADDVT = N1.getOperand(1).getValueType(); 1945 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1946 N1.getOperand(1), 1947 DAG.getConstant(SHC->getAPIntValue() 1948 .logBase2(), 1949 ADDVT)); 1950 AddToWorkList(Add.getNode()); 1951 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1952 } 1953 } 1954 } 1955 // fold (udiv x, c) -> alternate 1956 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1957 SDValue Op = BuildUDIV(N); 1958 if (Op.getNode()) return Op; 1959 } 1960 1961 // undef / X -> 0 1962 if (N0.getOpcode() == ISD::UNDEF) 1963 return DAG.getConstant(0, VT); 1964 // X / undef -> undef 1965 if (N1.getOpcode() == ISD::UNDEF) 1966 return N1; 1967 1968 return SDValue(); 1969} 1970 1971SDValue DAGCombiner::visitSREM(SDNode *N) { 1972 SDValue N0 = N->getOperand(0); 1973 SDValue N1 = N->getOperand(1); 1974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1976 EVT VT = N->getValueType(0); 1977 1978 // fold (srem c1, c2) -> c1%c2 1979 if (N0C && N1C && !N1C->isNullValue()) 1980 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1981 // If we know the sign bits of both operands are zero, strength reduce to a 1982 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1983 if (!VT.isVector()) { 1984 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1985 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1986 } 1987 1988 // If X/C can be simplified by the division-by-constant logic, lower 1989 // X%C to the equivalent of X-X/C*C. 1990 if (N1C && !N1C->isNullValue()) { 1991 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1992 AddToWorkList(Div.getNode()); 1993 SDValue OptimizedDiv = combine(Div.getNode()); 1994 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1995 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1996 OptimizedDiv, N1); 1997 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1998 AddToWorkList(Mul.getNode()); 1999 return Sub; 2000 } 2001 } 2002 2003 // undef % X -> 0 2004 if (N0.getOpcode() == ISD::UNDEF) 2005 return DAG.getConstant(0, VT); 2006 // X % undef -> undef 2007 if (N1.getOpcode() == ISD::UNDEF) 2008 return N1; 2009 2010 return SDValue(); 2011} 2012 2013SDValue DAGCombiner::visitUREM(SDNode *N) { 2014 SDValue N0 = N->getOperand(0); 2015 SDValue N1 = N->getOperand(1); 2016 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2017 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2018 EVT VT = N->getValueType(0); 2019 2020 // fold (urem c1, c2) -> c1%c2 2021 if (N0C && N1C && !N1C->isNullValue()) 2022 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2023 // fold (urem x, pow2) -> (and x, pow2-1) 2024 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2025 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2026 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2027 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2028 if (N1.getOpcode() == ISD::SHL) { 2029 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2030 if (SHC->getAPIntValue().isPowerOf2()) { 2031 SDValue Add = 2032 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2033 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2034 VT)); 2035 AddToWorkList(Add.getNode()); 2036 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2037 } 2038 } 2039 } 2040 2041 // If X/C can be simplified by the division-by-constant logic, lower 2042 // X%C to the equivalent of X-X/C*C. 2043 if (N1C && !N1C->isNullValue()) { 2044 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2045 AddToWorkList(Div.getNode()); 2046 SDValue OptimizedDiv = combine(Div.getNode()); 2047 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2048 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2049 OptimizedDiv, N1); 2050 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2051 AddToWorkList(Mul.getNode()); 2052 return Sub; 2053 } 2054 } 2055 2056 // undef % X -> 0 2057 if (N0.getOpcode() == ISD::UNDEF) 2058 return DAG.getConstant(0, VT); 2059 // X % undef -> undef 2060 if (N1.getOpcode() == ISD::UNDEF) 2061 return N1; 2062 2063 return SDValue(); 2064} 2065 2066SDValue DAGCombiner::visitMULHS(SDNode *N) { 2067 SDValue N0 = N->getOperand(0); 2068 SDValue N1 = N->getOperand(1); 2069 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2070 EVT VT = N->getValueType(0); 2071 DebugLoc DL = N->getDebugLoc(); 2072 2073 // fold (mulhs x, 0) -> 0 2074 if (N1C && N1C->isNullValue()) 2075 return N1; 2076 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2077 if (N1C && N1C->getAPIntValue() == 1) 2078 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2079 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2080 getShiftAmountTy(N0.getValueType()))); 2081 // fold (mulhs x, undef) -> 0 2082 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2083 return DAG.getConstant(0, VT); 2084 2085 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2086 // plus a shift. 2087 if (VT.isSimple() && !VT.isVector()) { 2088 MVT Simple = VT.getSimpleVT(); 2089 unsigned SimpleSize = Simple.getSizeInBits(); 2090 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2091 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2092 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2093 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2094 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2095 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2096 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2097 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2098 } 2099 } 2100 2101 return SDValue(); 2102} 2103 2104SDValue DAGCombiner::visitMULHU(SDNode *N) { 2105 SDValue N0 = N->getOperand(0); 2106 SDValue N1 = N->getOperand(1); 2107 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2108 EVT VT = N->getValueType(0); 2109 DebugLoc DL = N->getDebugLoc(); 2110 2111 // fold (mulhu x, 0) -> 0 2112 if (N1C && N1C->isNullValue()) 2113 return N1; 2114 // fold (mulhu x, 1) -> 0 2115 if (N1C && N1C->getAPIntValue() == 1) 2116 return DAG.getConstant(0, N0.getValueType()); 2117 // fold (mulhu x, undef) -> 0 2118 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2119 return DAG.getConstant(0, VT); 2120 2121 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2122 // plus a shift. 2123 if (VT.isSimple() && !VT.isVector()) { 2124 MVT Simple = VT.getSimpleVT(); 2125 unsigned SimpleSize = Simple.getSizeInBits(); 2126 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2127 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2128 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2129 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2130 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2131 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2132 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2133 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2134 } 2135 } 2136 2137 return SDValue(); 2138} 2139 2140/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2141/// compute two values. LoOp and HiOp give the opcodes for the two computations 2142/// that are being performed. Return true if a simplification was made. 2143/// 2144SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2145 unsigned HiOp) { 2146 // If the high half is not needed, just compute the low half. 2147 bool HiExists = N->hasAnyUseOfValue(1); 2148 if (!HiExists && 2149 (!LegalOperations || 2150 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2151 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2152 N->op_begin(), N->getNumOperands()); 2153 return CombineTo(N, Res, Res); 2154 } 2155 2156 // If the low half is not needed, just compute the high half. 2157 bool LoExists = N->hasAnyUseOfValue(0); 2158 if (!LoExists && 2159 (!LegalOperations || 2160 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2161 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2162 N->op_begin(), N->getNumOperands()); 2163 return CombineTo(N, Res, Res); 2164 } 2165 2166 // If both halves are used, return as it is. 2167 if (LoExists && HiExists) 2168 return SDValue(); 2169 2170 // If the two computed results can be simplified separately, separate them. 2171 if (LoExists) { 2172 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2173 N->op_begin(), N->getNumOperands()); 2174 AddToWorkList(Lo.getNode()); 2175 SDValue LoOpt = combine(Lo.getNode()); 2176 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2177 (!LegalOperations || 2178 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2179 return CombineTo(N, LoOpt, LoOpt); 2180 } 2181 2182 if (HiExists) { 2183 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2184 N->op_begin(), N->getNumOperands()); 2185 AddToWorkList(Hi.getNode()); 2186 SDValue HiOpt = combine(Hi.getNode()); 2187 if (HiOpt.getNode() && HiOpt != Hi && 2188 (!LegalOperations || 2189 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2190 return CombineTo(N, HiOpt, HiOpt); 2191 } 2192 2193 return SDValue(); 2194} 2195 2196SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2197 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2198 if (Res.getNode()) return Res; 2199 2200 EVT VT = N->getValueType(0); 2201 DebugLoc DL = N->getDebugLoc(); 2202 2203 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2204 // plus a shift. 2205 if (VT.isSimple() && !VT.isVector()) { 2206 MVT Simple = VT.getSimpleVT(); 2207 unsigned SimpleSize = Simple.getSizeInBits(); 2208 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2209 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2210 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2211 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2212 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2213 // Compute the high part as N1. 2214 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2215 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2216 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2217 // Compute the low part as N0. 2218 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2219 return CombineTo(N, Lo, Hi); 2220 } 2221 } 2222 2223 return SDValue(); 2224} 2225 2226SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2227 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2228 if (Res.getNode()) return Res; 2229 2230 EVT VT = N->getValueType(0); 2231 DebugLoc DL = N->getDebugLoc(); 2232 2233 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2234 // plus a shift. 2235 if (VT.isSimple() && !VT.isVector()) { 2236 MVT Simple = VT.getSimpleVT(); 2237 unsigned SimpleSize = Simple.getSizeInBits(); 2238 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2239 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2240 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2241 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2242 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2243 // Compute the high part as N1. 2244 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2245 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2246 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2247 // Compute the low part as N0. 2248 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2249 return CombineTo(N, Lo, Hi); 2250 } 2251 } 2252 2253 return SDValue(); 2254} 2255 2256SDValue DAGCombiner::visitSMULO(SDNode *N) { 2257 // (smulo x, 2) -> (saddo x, x) 2258 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2259 if (C2->getAPIntValue() == 2) 2260 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2261 N->getOperand(0), N->getOperand(0)); 2262 2263 return SDValue(); 2264} 2265 2266SDValue DAGCombiner::visitUMULO(SDNode *N) { 2267 // (umulo x, 2) -> (uaddo x, x) 2268 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2269 if (C2->getAPIntValue() == 2) 2270 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2271 N->getOperand(0), N->getOperand(0)); 2272 2273 return SDValue(); 2274} 2275 2276SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2277 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2278 if (Res.getNode()) return Res; 2279 2280 return SDValue(); 2281} 2282 2283SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2284 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2285 if (Res.getNode()) return Res; 2286 2287 return SDValue(); 2288} 2289 2290/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2291/// two operands of the same opcode, try to simplify it. 2292SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2293 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2294 EVT VT = N0.getValueType(); 2295 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2296 2297 // Bail early if none of these transforms apply. 2298 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2299 2300 // For each of OP in AND/OR/XOR: 2301 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2302 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2303 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2304 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2305 // 2306 // do not sink logical op inside of a vector extend, since it may combine 2307 // into a vsetcc. 2308 EVT Op0VT = N0.getOperand(0).getValueType(); 2309 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2310 N0.getOpcode() == ISD::SIGN_EXTEND || 2311 // Avoid infinite looping with PromoteIntBinOp. 2312 (N0.getOpcode() == ISD::ANY_EXTEND && 2313 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2314 (N0.getOpcode() == ISD::TRUNCATE && 2315 (!TLI.isZExtFree(VT, Op0VT) || 2316 !TLI.isTruncateFree(Op0VT, VT)) && 2317 TLI.isTypeLegal(Op0VT))) && 2318 !VT.isVector() && 2319 Op0VT == N1.getOperand(0).getValueType() && 2320 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2321 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2322 N0.getOperand(0).getValueType(), 2323 N0.getOperand(0), N1.getOperand(0)); 2324 AddToWorkList(ORNode.getNode()); 2325 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2326 } 2327 2328 // For each of OP in SHL/SRL/SRA/AND... 2329 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2330 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2331 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2332 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2333 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2334 N0.getOperand(1) == N1.getOperand(1)) { 2335 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2336 N0.getOperand(0).getValueType(), 2337 N0.getOperand(0), N1.getOperand(0)); 2338 AddToWorkList(ORNode.getNode()); 2339 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2340 ORNode, N0.getOperand(1)); 2341 } 2342 2343 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2344 // Only perform this optimization after type legalization and before 2345 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2346 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2347 // we don't want to undo this promotion. 2348 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2349 // on scalars. 2350 if ((N0.getOpcode() == ISD::BITCAST || 2351 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && 2352 Level == AfterLegalizeTypes) { 2353 SDValue In0 = N0.getOperand(0); 2354 SDValue In1 = N1.getOperand(0); 2355 EVT In0Ty = In0.getValueType(); 2356 EVT In1Ty = In1.getValueType(); 2357 DebugLoc DL = N->getDebugLoc(); 2358 // If both incoming values are integers, and the original types are the 2359 // same. 2360 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2361 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1); 2362 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op); 2363 AddToWorkList(Op.getNode()); 2364 return BC; 2365 } 2366 } 2367 2368 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2369 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2370 // If both shuffles use the same mask, and both shuffle within a single 2371 // vector, then it is worthwhile to move the swizzle after the operation. 2372 // The type-legalizer generates this pattern when loading illegal 2373 // vector types from memory. In many cases this allows additional shuffle 2374 // optimizations. 2375 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2376 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2377 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2378 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2379 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2380 2381 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2382 "Inputs to shuffles are not the same type"); 2383 2384 unsigned NumElts = VT.getVectorNumElements(); 2385 2386 // Check that both shuffles use the same mask. The masks are known to be of 2387 // the same length because the result vector type is the same. 2388 bool SameMask = true; 2389 for (unsigned i = 0; i != NumElts; ++i) { 2390 int Idx0 = SVN0->getMaskElt(i); 2391 int Idx1 = SVN1->getMaskElt(i); 2392 if (Idx0 != Idx1) { 2393 SameMask = false; 2394 break; 2395 } 2396 } 2397 2398 if (SameMask) { 2399 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2400 N0.getOperand(0), N1.getOperand(0)); 2401 AddToWorkList(Op.getNode()); 2402 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2403 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2404 } 2405 } 2406 2407 return SDValue(); 2408} 2409 2410SDValue DAGCombiner::visitAND(SDNode *N) { 2411 SDValue N0 = N->getOperand(0); 2412 SDValue N1 = N->getOperand(1); 2413 SDValue LL, LR, RL, RR, CC0, CC1; 2414 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2415 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2416 EVT VT = N1.getValueType(); 2417 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2418 2419 // fold vector ops 2420 if (VT.isVector()) { 2421 SDValue FoldedVOp = SimplifyVBinOp(N); 2422 if (FoldedVOp.getNode()) return FoldedVOp; 2423 } 2424 2425 // fold (and x, undef) -> 0 2426 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2427 return DAG.getConstant(0, VT); 2428 // fold (and c1, c2) -> c1&c2 2429 if (N0C && N1C) 2430 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2431 // canonicalize constant to RHS 2432 if (N0C && !N1C) 2433 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2434 // fold (and x, -1) -> x 2435 if (N1C && N1C->isAllOnesValue()) 2436 return N0; 2437 // if (and x, c) is known to be zero, return 0 2438 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2439 APInt::getAllOnesValue(BitWidth))) 2440 return DAG.getConstant(0, VT); 2441 // reassociate and 2442 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2443 if (RAND.getNode() != 0) 2444 return RAND; 2445 // fold (and (or x, C), D) -> D if (C & D) == D 2446 if (N1C && N0.getOpcode() == ISD::OR) 2447 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2448 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2449 return N1; 2450 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2451 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2452 SDValue N0Op0 = N0.getOperand(0); 2453 APInt Mask = ~N1C->getAPIntValue(); 2454 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2455 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2456 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2457 N0.getValueType(), N0Op0); 2458 2459 // Replace uses of the AND with uses of the Zero extend node. 2460 CombineTo(N, Zext); 2461 2462 // We actually want to replace all uses of the any_extend with the 2463 // zero_extend, to avoid duplicating things. This will later cause this 2464 // AND to be folded. 2465 CombineTo(N0.getNode(), Zext); 2466 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2467 } 2468 } 2469 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2470 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2471 // already be zero by virtue of the width of the base type of the load. 2472 // 2473 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2474 // more cases. 2475 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2476 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2477 N0.getOpcode() == ISD::LOAD) { 2478 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2479 N0 : N0.getOperand(0) ); 2480 2481 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2482 // This can be a pure constant or a vector splat, in which case we treat the 2483 // vector as a scalar and use the splat value. 2484 APInt Constant = APInt::getNullValue(1); 2485 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2486 Constant = C->getAPIntValue(); 2487 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2488 APInt SplatValue, SplatUndef; 2489 unsigned SplatBitSize; 2490 bool HasAnyUndefs; 2491 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2492 SplatBitSize, HasAnyUndefs); 2493 if (IsSplat) { 2494 // Undef bits can contribute to a possible optimisation if set, so 2495 // set them. 2496 SplatValue |= SplatUndef; 2497 2498 // The splat value may be something like "0x00FFFFFF", which means 0 for 2499 // the first vector value and FF for the rest, repeating. We need a mask 2500 // that will apply equally to all members of the vector, so AND all the 2501 // lanes of the constant together. 2502 EVT VT = Vector->getValueType(0); 2503 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2504 2505 // If the splat value has been compressed to a bitlength lower 2506 // than the size of the vector lane, we need to re-expand it to 2507 // the lane size. 2508 if (BitWidth > SplatBitSize) 2509 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2510 SplatBitSize < BitWidth; 2511 SplatBitSize = SplatBitSize * 2) 2512 SplatValue |= SplatValue.shl(SplatBitSize); 2513 2514 Constant = APInt::getAllOnesValue(BitWidth); 2515 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2516 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2517 } 2518 } 2519 2520 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2521 // actually legal and isn't going to get expanded, else this is a false 2522 // optimisation. 2523 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2524 Load->getMemoryVT()); 2525 2526 // Resize the constant to the same size as the original memory access before 2527 // extension. If it is still the AllOnesValue then this AND is completely 2528 // unneeded. 2529 Constant = 2530 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2531 2532 bool B; 2533 switch (Load->getExtensionType()) { 2534 default: B = false; break; 2535 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2536 case ISD::ZEXTLOAD: 2537 case ISD::NON_EXTLOAD: B = true; break; 2538 } 2539 2540 if (B && Constant.isAllOnesValue()) { 2541 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2542 // preserve semantics once we get rid of the AND. 2543 SDValue NewLoad(Load, 0); 2544 if (Load->getExtensionType() == ISD::EXTLOAD) { 2545 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2546 Load->getValueType(0), Load->getDebugLoc(), 2547 Load->getChain(), Load->getBasePtr(), 2548 Load->getOffset(), Load->getMemoryVT(), 2549 Load->getMemOperand()); 2550 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2551 if (Load->getNumValues() == 3) { 2552 // PRE/POST_INC loads have 3 values. 2553 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2554 NewLoad.getValue(2) }; 2555 CombineTo(Load, To, 3, true); 2556 } else { 2557 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2558 } 2559 } 2560 2561 // Fold the AND away, taking care not to fold to the old load node if we 2562 // replaced it. 2563 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2564 2565 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2566 } 2567 } 2568 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2569 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2570 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2571 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2572 2573 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2574 LL.getValueType().isInteger()) { 2575 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2576 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2577 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2578 LR.getValueType(), LL, RL); 2579 AddToWorkList(ORNode.getNode()); 2580 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2581 } 2582 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2583 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2584 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2585 LR.getValueType(), LL, RL); 2586 AddToWorkList(ANDNode.getNode()); 2587 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2588 } 2589 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2590 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2591 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2592 LR.getValueType(), LL, RL); 2593 AddToWorkList(ORNode.getNode()); 2594 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2595 } 2596 } 2597 // canonicalize equivalent to ll == rl 2598 if (LL == RR && LR == RL) { 2599 Op1 = ISD::getSetCCSwappedOperands(Op1); 2600 std::swap(RL, RR); 2601 } 2602 if (LL == RL && LR == RR) { 2603 bool isInteger = LL.getValueType().isInteger(); 2604 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2605 if (Result != ISD::SETCC_INVALID && 2606 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2607 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2608 LL, LR, Result); 2609 } 2610 } 2611 2612 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2613 if (N0.getOpcode() == N1.getOpcode()) { 2614 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2615 if (Tmp.getNode()) return Tmp; 2616 } 2617 2618 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2619 // fold (and (sra)) -> (and (srl)) when possible. 2620 if (!VT.isVector() && 2621 SimplifyDemandedBits(SDValue(N, 0))) 2622 return SDValue(N, 0); 2623 2624 // fold (zext_inreg (extload x)) -> (zextload x) 2625 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2626 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2627 EVT MemVT = LN0->getMemoryVT(); 2628 // If we zero all the possible extended bits, then we can turn this into 2629 // a zextload if we are running before legalize or the operation is legal. 2630 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2631 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2632 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2633 ((!LegalOperations && !LN0->isVolatile()) || 2634 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2635 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2636 LN0->getChain(), LN0->getBasePtr(), 2637 LN0->getPointerInfo(), MemVT, 2638 LN0->isVolatile(), LN0->isNonTemporal(), 2639 LN0->getAlignment()); 2640 AddToWorkList(N); 2641 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2642 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2643 } 2644 } 2645 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2646 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2647 N0.hasOneUse()) { 2648 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2649 EVT MemVT = LN0->getMemoryVT(); 2650 // If we zero all the possible extended bits, then we can turn this into 2651 // a zextload if we are running before legalize or the operation is legal. 2652 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2653 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2654 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2655 ((!LegalOperations && !LN0->isVolatile()) || 2656 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2657 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2658 LN0->getChain(), 2659 LN0->getBasePtr(), LN0->getPointerInfo(), 2660 MemVT, 2661 LN0->isVolatile(), LN0->isNonTemporal(), 2662 LN0->getAlignment()); 2663 AddToWorkList(N); 2664 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2665 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2666 } 2667 } 2668 2669 // fold (and (load x), 255) -> (zextload x, i8) 2670 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2671 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2672 if (N1C && (N0.getOpcode() == ISD::LOAD || 2673 (N0.getOpcode() == ISD::ANY_EXTEND && 2674 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2675 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2676 LoadSDNode *LN0 = HasAnyExt 2677 ? cast<LoadSDNode>(N0.getOperand(0)) 2678 : cast<LoadSDNode>(N0); 2679 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2680 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2681 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2682 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2683 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2684 EVT LoadedVT = LN0->getMemoryVT(); 2685 2686 if (ExtVT == LoadedVT && 2687 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2688 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2689 2690 SDValue NewLoad = 2691 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2692 LN0->getChain(), LN0->getBasePtr(), 2693 LN0->getPointerInfo(), 2694 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2695 LN0->getAlignment()); 2696 AddToWorkList(N); 2697 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2698 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2699 } 2700 2701 // Do not change the width of a volatile load. 2702 // Do not generate loads of non-round integer types since these can 2703 // be expensive (and would be wrong if the type is not byte sized). 2704 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2705 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2706 EVT PtrType = LN0->getOperand(1).getValueType(); 2707 2708 unsigned Alignment = LN0->getAlignment(); 2709 SDValue NewPtr = LN0->getBasePtr(); 2710 2711 // For big endian targets, we need to add an offset to the pointer 2712 // to load the correct bytes. For little endian systems, we merely 2713 // need to read fewer bytes from the same pointer. 2714 if (TLI.isBigEndian()) { 2715 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2716 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2717 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2718 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2719 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2720 Alignment = MinAlign(Alignment, PtrOff); 2721 } 2722 2723 AddToWorkList(NewPtr.getNode()); 2724 2725 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2726 SDValue Load = 2727 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2728 LN0->getChain(), NewPtr, 2729 LN0->getPointerInfo(), 2730 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2731 Alignment); 2732 AddToWorkList(N); 2733 CombineTo(LN0, Load, Load.getValue(1)); 2734 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2735 } 2736 } 2737 } 2738 } 2739 2740 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2741 VT.getSizeInBits() <= 64) { 2742 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2743 APInt ADDC = ADDI->getAPIntValue(); 2744 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2745 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2746 // immediate for an add, but it is legal if its top c2 bits are set, 2747 // transform the ADD so the immediate doesn't need to be materialized 2748 // in a register. 2749 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2750 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2751 SRLI->getZExtValue()); 2752 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2753 ADDC |= Mask; 2754 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2755 SDValue NewAdd = 2756 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 2757 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2758 CombineTo(N0.getNode(), NewAdd); 2759 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2760 } 2761 } 2762 } 2763 } 2764 } 2765 } 2766 2767 2768 return SDValue(); 2769} 2770 2771/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2772/// 2773SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2774 bool DemandHighBits) { 2775 if (!LegalOperations) 2776 return SDValue(); 2777 2778 EVT VT = N->getValueType(0); 2779 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2780 return SDValue(); 2781 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2782 return SDValue(); 2783 2784 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2785 bool LookPassAnd0 = false; 2786 bool LookPassAnd1 = false; 2787 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2788 std::swap(N0, N1); 2789 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2790 std::swap(N0, N1); 2791 if (N0.getOpcode() == ISD::AND) { 2792 if (!N0.getNode()->hasOneUse()) 2793 return SDValue(); 2794 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2795 if (!N01C || N01C->getZExtValue() != 0xFF00) 2796 return SDValue(); 2797 N0 = N0.getOperand(0); 2798 LookPassAnd0 = true; 2799 } 2800 2801 if (N1.getOpcode() == ISD::AND) { 2802 if (!N1.getNode()->hasOneUse()) 2803 return SDValue(); 2804 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2805 if (!N11C || N11C->getZExtValue() != 0xFF) 2806 return SDValue(); 2807 N1 = N1.getOperand(0); 2808 LookPassAnd1 = true; 2809 } 2810 2811 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2812 std::swap(N0, N1); 2813 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2814 return SDValue(); 2815 if (!N0.getNode()->hasOneUse() || 2816 !N1.getNode()->hasOneUse()) 2817 return SDValue(); 2818 2819 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2820 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2821 if (!N01C || !N11C) 2822 return SDValue(); 2823 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2824 return SDValue(); 2825 2826 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2827 SDValue N00 = N0->getOperand(0); 2828 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2829 if (!N00.getNode()->hasOneUse()) 2830 return SDValue(); 2831 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2832 if (!N001C || N001C->getZExtValue() != 0xFF) 2833 return SDValue(); 2834 N00 = N00.getOperand(0); 2835 LookPassAnd0 = true; 2836 } 2837 2838 SDValue N10 = N1->getOperand(0); 2839 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2840 if (!N10.getNode()->hasOneUse()) 2841 return SDValue(); 2842 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2843 if (!N101C || N101C->getZExtValue() != 0xFF00) 2844 return SDValue(); 2845 N10 = N10.getOperand(0); 2846 LookPassAnd1 = true; 2847 } 2848 2849 if (N00 != N10) 2850 return SDValue(); 2851 2852 // Make sure everything beyond the low halfword is zero since the SRL 16 2853 // will clear the top bits. 2854 unsigned OpSizeInBits = VT.getSizeInBits(); 2855 if (DemandHighBits && OpSizeInBits > 16 && 2856 (!LookPassAnd0 || !LookPassAnd1) && 2857 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2858 return SDValue(); 2859 2860 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2861 if (OpSizeInBits > 16) 2862 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2863 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2864 return Res; 2865} 2866 2867/// isBSwapHWordElement - Return true if the specified node is an element 2868/// that makes up a 32-bit packed halfword byteswap. i.e. 2869/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2870static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2871 if (!N.getNode()->hasOneUse()) 2872 return false; 2873 2874 unsigned Opc = N.getOpcode(); 2875 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2876 return false; 2877 2878 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2879 if (!N1C) 2880 return false; 2881 2882 unsigned Num; 2883 switch (N1C->getZExtValue()) { 2884 default: 2885 return false; 2886 case 0xFF: Num = 0; break; 2887 case 0xFF00: Num = 1; break; 2888 case 0xFF0000: Num = 2; break; 2889 case 0xFF000000: Num = 3; break; 2890 } 2891 2892 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2893 SDValue N0 = N.getOperand(0); 2894 if (Opc == ISD::AND) { 2895 if (Num == 0 || Num == 2) { 2896 // (x >> 8) & 0xff 2897 // (x >> 8) & 0xff0000 2898 if (N0.getOpcode() != ISD::SRL) 2899 return false; 2900 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2901 if (!C || C->getZExtValue() != 8) 2902 return false; 2903 } else { 2904 // (x << 8) & 0xff00 2905 // (x << 8) & 0xff000000 2906 if (N0.getOpcode() != ISD::SHL) 2907 return false; 2908 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2909 if (!C || C->getZExtValue() != 8) 2910 return false; 2911 } 2912 } else if (Opc == ISD::SHL) { 2913 // (x & 0xff) << 8 2914 // (x & 0xff0000) << 8 2915 if (Num != 0 && Num != 2) 2916 return false; 2917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2918 if (!C || C->getZExtValue() != 8) 2919 return false; 2920 } else { // Opc == ISD::SRL 2921 // (x & 0xff00) >> 8 2922 // (x & 0xff000000) >> 8 2923 if (Num != 1 && Num != 3) 2924 return false; 2925 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2926 if (!C || C->getZExtValue() != 8) 2927 return false; 2928 } 2929 2930 if (Parts[Num]) 2931 return false; 2932 2933 Parts[Num] = N0.getOperand(0).getNode(); 2934 return true; 2935} 2936 2937/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2938/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2939/// => (rotl (bswap x), 16) 2940SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2941 if (!LegalOperations) 2942 return SDValue(); 2943 2944 EVT VT = N->getValueType(0); 2945 if (VT != MVT::i32) 2946 return SDValue(); 2947 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2948 return SDValue(); 2949 2950 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2951 // Look for either 2952 // (or (or (and), (and)), (or (and), (and))) 2953 // (or (or (or (and), (and)), (and)), (and)) 2954 if (N0.getOpcode() != ISD::OR) 2955 return SDValue(); 2956 SDValue N00 = N0.getOperand(0); 2957 SDValue N01 = N0.getOperand(1); 2958 2959 if (N1.getOpcode() == ISD::OR) { 2960 // (or (or (and), (and)), (or (and), (and))) 2961 SDValue N000 = N00.getOperand(0); 2962 if (!isBSwapHWordElement(N000, Parts)) 2963 return SDValue(); 2964 2965 SDValue N001 = N00.getOperand(1); 2966 if (!isBSwapHWordElement(N001, Parts)) 2967 return SDValue(); 2968 SDValue N010 = N01.getOperand(0); 2969 if (!isBSwapHWordElement(N010, Parts)) 2970 return SDValue(); 2971 SDValue N011 = N01.getOperand(1); 2972 if (!isBSwapHWordElement(N011, Parts)) 2973 return SDValue(); 2974 } else { 2975 // (or (or (or (and), (and)), (and)), (and)) 2976 if (!isBSwapHWordElement(N1, Parts)) 2977 return SDValue(); 2978 if (!isBSwapHWordElement(N01, Parts)) 2979 return SDValue(); 2980 if (N00.getOpcode() != ISD::OR) 2981 return SDValue(); 2982 SDValue N000 = N00.getOperand(0); 2983 if (!isBSwapHWordElement(N000, Parts)) 2984 return SDValue(); 2985 SDValue N001 = N00.getOperand(1); 2986 if (!isBSwapHWordElement(N001, Parts)) 2987 return SDValue(); 2988 } 2989 2990 // Make sure the parts are all coming from the same node. 2991 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2992 return SDValue(); 2993 2994 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2995 SDValue(Parts[0],0)); 2996 2997 // Result of the bswap should be rotated by 16. If it's not legal, than 2998 // do (x << 16) | (x >> 16). 2999 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 3000 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3001 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 3002 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3003 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 3004 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 3005 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 3006 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 3007} 3008 3009SDValue DAGCombiner::visitOR(SDNode *N) { 3010 SDValue N0 = N->getOperand(0); 3011 SDValue N1 = N->getOperand(1); 3012 SDValue LL, LR, RL, RR, CC0, CC1; 3013 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3015 EVT VT = N1.getValueType(); 3016 3017 // fold vector ops 3018 if (VT.isVector()) { 3019 SDValue FoldedVOp = SimplifyVBinOp(N); 3020 if (FoldedVOp.getNode()) return FoldedVOp; 3021 } 3022 3023 // fold (or x, undef) -> -1 3024 if (!LegalOperations && 3025 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3026 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3027 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3028 } 3029 // fold (or c1, c2) -> c1|c2 3030 if (N0C && N1C) 3031 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3032 // canonicalize constant to RHS 3033 if (N0C && !N1C) 3034 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 3035 // fold (or x, 0) -> x 3036 if (N1C && N1C->isNullValue()) 3037 return N0; 3038 // fold (or x, -1) -> -1 3039 if (N1C && N1C->isAllOnesValue()) 3040 return N1; 3041 // fold (or x, c) -> c iff (x & ~c) == 0 3042 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3043 return N1; 3044 3045 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3046 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3047 if (BSwap.getNode() != 0) 3048 return BSwap; 3049 BSwap = MatchBSwapHWordLow(N, N0, N1); 3050 if (BSwap.getNode() != 0) 3051 return BSwap; 3052 3053 // reassociate or 3054 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3055 if (ROR.getNode() != 0) 3056 return ROR; 3057 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3058 // iff (c1 & c2) == 0. 3059 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3060 isa<ConstantSDNode>(N0.getOperand(1))) { 3061 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3062 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3063 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3064 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3065 N0.getOperand(0), N1), 3066 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3067 } 3068 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3069 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3070 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3071 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3072 3073 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3074 LL.getValueType().isInteger()) { 3075 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3076 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3077 if (cast<ConstantSDNode>(LR)->isNullValue() && 3078 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3079 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3080 LR.getValueType(), LL, RL); 3081 AddToWorkList(ORNode.getNode()); 3082 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3083 } 3084 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3085 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3086 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3087 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3088 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3089 LR.getValueType(), LL, RL); 3090 AddToWorkList(ANDNode.getNode()); 3091 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3092 } 3093 } 3094 // canonicalize equivalent to ll == rl 3095 if (LL == RR && LR == RL) { 3096 Op1 = ISD::getSetCCSwappedOperands(Op1); 3097 std::swap(RL, RR); 3098 } 3099 if (LL == RL && LR == RR) { 3100 bool isInteger = LL.getValueType().isInteger(); 3101 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3102 if (Result != ISD::SETCC_INVALID && 3103 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3104 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3105 LL, LR, Result); 3106 } 3107 } 3108 3109 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3110 if (N0.getOpcode() == N1.getOpcode()) { 3111 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3112 if (Tmp.getNode()) return Tmp; 3113 } 3114 3115 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3116 if (N0.getOpcode() == ISD::AND && 3117 N1.getOpcode() == ISD::AND && 3118 N0.getOperand(1).getOpcode() == ISD::Constant && 3119 N1.getOperand(1).getOpcode() == ISD::Constant && 3120 // Don't increase # computations. 3121 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3122 // We can only do this xform if we know that bits from X that are set in C2 3123 // but not in C1 are already zero. Likewise for Y. 3124 const APInt &LHSMask = 3125 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3126 const APInt &RHSMask = 3127 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3128 3129 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3130 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3131 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3132 N0.getOperand(0), N1.getOperand(0)); 3133 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3134 DAG.getConstant(LHSMask | RHSMask, VT)); 3135 } 3136 } 3137 3138 // See if this is some rotate idiom. 3139 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3140 return SDValue(Rot, 0); 3141 3142 // Simplify the operands using demanded-bits information. 3143 if (!VT.isVector() && 3144 SimplifyDemandedBits(SDValue(N, 0))) 3145 return SDValue(N, 0); 3146 3147 return SDValue(); 3148} 3149 3150/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3151static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3152 if (Op.getOpcode() == ISD::AND) { 3153 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3154 Mask = Op.getOperand(1); 3155 Op = Op.getOperand(0); 3156 } else { 3157 return false; 3158 } 3159 } 3160 3161 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3162 Shift = Op; 3163 return true; 3164 } 3165 3166 return false; 3167} 3168 3169// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3170// idioms for rotate, and if the target supports rotation instructions, generate 3171// a rot[lr]. 3172SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3173 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3174 EVT VT = LHS.getValueType(); 3175 if (!TLI.isTypeLegal(VT)) return 0; 3176 3177 // The target must have at least one rotate flavor. 3178 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3179 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3180 if (!HasROTL && !HasROTR) return 0; 3181 3182 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3183 SDValue LHSShift; // The shift. 3184 SDValue LHSMask; // AND value if any. 3185 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3186 return 0; // Not part of a rotate. 3187 3188 SDValue RHSShift; // The shift. 3189 SDValue RHSMask; // AND value if any. 3190 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3191 return 0; // Not part of a rotate. 3192 3193 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3194 return 0; // Not shifting the same value. 3195 3196 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3197 return 0; // Shifts must disagree. 3198 3199 // Canonicalize shl to left side in a shl/srl pair. 3200 if (RHSShift.getOpcode() == ISD::SHL) { 3201 std::swap(LHS, RHS); 3202 std::swap(LHSShift, RHSShift); 3203 std::swap(LHSMask , RHSMask ); 3204 } 3205 3206 unsigned OpSizeInBits = VT.getSizeInBits(); 3207 SDValue LHSShiftArg = LHSShift.getOperand(0); 3208 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3209 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3210 3211 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3212 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3213 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3214 RHSShiftAmt.getOpcode() == ISD::Constant) { 3215 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3216 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3217 if ((LShVal + RShVal) != OpSizeInBits) 3218 return 0; 3219 3220 SDValue Rot; 3221 if (HasROTL) 3222 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 3223 else 3224 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 3225 3226 // If there is an AND of either shifted operand, apply it to the result. 3227 if (LHSMask.getNode() || RHSMask.getNode()) { 3228 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3229 3230 if (LHSMask.getNode()) { 3231 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3232 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3233 } 3234 if (RHSMask.getNode()) { 3235 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3236 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3237 } 3238 3239 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3240 } 3241 3242 return Rot.getNode(); 3243 } 3244 3245 // If there is a mask here, and we have a variable shift, we can't be sure 3246 // that we're masking out the right stuff. 3247 if (LHSMask.getNode() || RHSMask.getNode()) 3248 return 0; 3249 3250 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3251 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3252 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3253 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3254 if (ConstantSDNode *SUBC = 3255 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3256 if (SUBC->getAPIntValue() == OpSizeInBits) { 3257 if (HasROTL) 3258 return DAG.getNode(ISD::ROTL, DL, VT, 3259 LHSShiftArg, LHSShiftAmt).getNode(); 3260 else 3261 return DAG.getNode(ISD::ROTR, DL, VT, 3262 LHSShiftArg, RHSShiftAmt).getNode(); 3263 } 3264 } 3265 } 3266 3267 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3268 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3269 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3270 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3271 if (ConstantSDNode *SUBC = 3272 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3273 if (SUBC->getAPIntValue() == OpSizeInBits) { 3274 if (HasROTR) 3275 return DAG.getNode(ISD::ROTR, DL, VT, 3276 LHSShiftArg, RHSShiftAmt).getNode(); 3277 else 3278 return DAG.getNode(ISD::ROTL, DL, VT, 3279 LHSShiftArg, LHSShiftAmt).getNode(); 3280 } 3281 } 3282 } 3283 3284 // Look for sign/zext/any-extended or truncate cases: 3285 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3286 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3287 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3288 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3289 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3290 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3291 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3292 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3293 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3294 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3295 if (RExtOp0.getOpcode() == ISD::SUB && 3296 RExtOp0.getOperand(1) == LExtOp0) { 3297 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3298 // (rotl x, y) 3299 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3300 // (rotr x, (sub 32, y)) 3301 if (ConstantSDNode *SUBC = 3302 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3303 if (SUBC->getAPIntValue() == OpSizeInBits) { 3304 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3305 LHSShiftArg, 3306 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3307 } 3308 } 3309 } else if (LExtOp0.getOpcode() == ISD::SUB && 3310 RExtOp0 == LExtOp0.getOperand(1)) { 3311 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3312 // (rotr x, y) 3313 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3314 // (rotl x, (sub 32, y)) 3315 if (ConstantSDNode *SUBC = 3316 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3317 if (SUBC->getAPIntValue() == OpSizeInBits) { 3318 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3319 LHSShiftArg, 3320 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3321 } 3322 } 3323 } 3324 } 3325 3326 return 0; 3327} 3328 3329SDValue DAGCombiner::visitXOR(SDNode *N) { 3330 SDValue N0 = N->getOperand(0); 3331 SDValue N1 = N->getOperand(1); 3332 SDValue LHS, RHS, CC; 3333 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3334 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3335 EVT VT = N0.getValueType(); 3336 3337 // fold vector ops 3338 if (VT.isVector()) { 3339 SDValue FoldedVOp = SimplifyVBinOp(N); 3340 if (FoldedVOp.getNode()) return FoldedVOp; 3341 } 3342 3343 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3344 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3345 return DAG.getConstant(0, VT); 3346 // fold (xor x, undef) -> undef 3347 if (N0.getOpcode() == ISD::UNDEF) 3348 return N0; 3349 if (N1.getOpcode() == ISD::UNDEF) 3350 return N1; 3351 // fold (xor c1, c2) -> c1^c2 3352 if (N0C && N1C) 3353 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3354 // canonicalize constant to RHS 3355 if (N0C && !N1C) 3356 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3357 // fold (xor x, 0) -> x 3358 if (N1C && N1C->isNullValue()) 3359 return N0; 3360 // reassociate xor 3361 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3362 if (RXOR.getNode() != 0) 3363 return RXOR; 3364 3365 // fold !(x cc y) -> (x !cc y) 3366 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3367 bool isInt = LHS.getValueType().isInteger(); 3368 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3369 isInt); 3370 3371 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3372 switch (N0.getOpcode()) { 3373 default: 3374 llvm_unreachable("Unhandled SetCC Equivalent!"); 3375 case ISD::SETCC: 3376 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3377 case ISD::SELECT_CC: 3378 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3379 N0.getOperand(3), NotCC); 3380 } 3381 } 3382 } 3383 3384 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3385 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3386 N0.getNode()->hasOneUse() && 3387 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3388 SDValue V = N0.getOperand(0); 3389 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3390 DAG.getConstant(1, V.getValueType())); 3391 AddToWorkList(V.getNode()); 3392 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3393 } 3394 3395 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3396 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3397 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3398 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3399 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3400 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3401 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3402 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3403 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3404 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3405 } 3406 } 3407 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3408 if (N1C && N1C->isAllOnesValue() && 3409 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3410 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3411 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3412 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3413 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3414 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3415 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3416 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3417 } 3418 } 3419 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3420 if (N1C && N0.getOpcode() == ISD::XOR) { 3421 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3422 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3423 if (N00C) 3424 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3425 DAG.getConstant(N1C->getAPIntValue() ^ 3426 N00C->getAPIntValue(), VT)); 3427 if (N01C) 3428 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3429 DAG.getConstant(N1C->getAPIntValue() ^ 3430 N01C->getAPIntValue(), VT)); 3431 } 3432 // fold (xor x, x) -> 0 3433 if (N0 == N1) 3434 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3435 3436 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3437 if (N0.getOpcode() == N1.getOpcode()) { 3438 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3439 if (Tmp.getNode()) return Tmp; 3440 } 3441 3442 // Simplify the expression using non-local knowledge. 3443 if (!VT.isVector() && 3444 SimplifyDemandedBits(SDValue(N, 0))) 3445 return SDValue(N, 0); 3446 3447 return SDValue(); 3448} 3449 3450/// visitShiftByConstant - Handle transforms common to the three shifts, when 3451/// the shift amount is a constant. 3452SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3453 SDNode *LHS = N->getOperand(0).getNode(); 3454 if (!LHS->hasOneUse()) return SDValue(); 3455 3456 // We want to pull some binops through shifts, so that we have (and (shift)) 3457 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3458 // thing happens with address calculations, so it's important to canonicalize 3459 // it. 3460 bool HighBitSet = false; // Can we transform this if the high bit is set? 3461 3462 switch (LHS->getOpcode()) { 3463 default: return SDValue(); 3464 case ISD::OR: 3465 case ISD::XOR: 3466 HighBitSet = false; // We can only transform sra if the high bit is clear. 3467 break; 3468 case ISD::AND: 3469 HighBitSet = true; // We can only transform sra if the high bit is set. 3470 break; 3471 case ISD::ADD: 3472 if (N->getOpcode() != ISD::SHL) 3473 return SDValue(); // only shl(add) not sr[al](add). 3474 HighBitSet = false; // We can only transform sra if the high bit is clear. 3475 break; 3476 } 3477 3478 // We require the RHS of the binop to be a constant as well. 3479 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3480 if (!BinOpCst) return SDValue(); 3481 3482 // FIXME: disable this unless the input to the binop is a shift by a constant. 3483 // If it is not a shift, it pessimizes some common cases like: 3484 // 3485 // void foo(int *X, int i) { X[i & 1235] = 1; } 3486 // int bar(int *X, int i) { return X[i & 255]; } 3487 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3488 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3489 BinOpLHSVal->getOpcode() != ISD::SRA && 3490 BinOpLHSVal->getOpcode() != ISD::SRL) || 3491 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3492 return SDValue(); 3493 3494 EVT VT = N->getValueType(0); 3495 3496 // If this is a signed shift right, and the high bit is modified by the 3497 // logical operation, do not perform the transformation. The highBitSet 3498 // boolean indicates the value of the high bit of the constant which would 3499 // cause it to be modified for this operation. 3500 if (N->getOpcode() == ISD::SRA) { 3501 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3502 if (BinOpRHSSignSet != HighBitSet) 3503 return SDValue(); 3504 } 3505 3506 // Fold the constants, shifting the binop RHS by the shift amount. 3507 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3508 N->getValueType(0), 3509 LHS->getOperand(1), N->getOperand(1)); 3510 3511 // Create the new shift. 3512 SDValue NewShift = DAG.getNode(N->getOpcode(), 3513 LHS->getOperand(0).getDebugLoc(), 3514 VT, LHS->getOperand(0), N->getOperand(1)); 3515 3516 // Create the new binop. 3517 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3518} 3519 3520SDValue DAGCombiner::visitSHL(SDNode *N) { 3521 SDValue N0 = N->getOperand(0); 3522 SDValue N1 = N->getOperand(1); 3523 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3524 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3525 EVT VT = N0.getValueType(); 3526 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3527 3528 // fold (shl c1, c2) -> c1<<c2 3529 if (N0C && N1C) 3530 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3531 // fold (shl 0, x) -> 0 3532 if (N0C && N0C->isNullValue()) 3533 return N0; 3534 // fold (shl x, c >= size(x)) -> undef 3535 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3536 return DAG.getUNDEF(VT); 3537 // fold (shl x, 0) -> x 3538 if (N1C && N1C->isNullValue()) 3539 return N0; 3540 // fold (shl undef, x) -> 0 3541 if (N0.getOpcode() == ISD::UNDEF) 3542 return DAG.getConstant(0, VT); 3543 // if (shl x, c) is known to be zero, return 0 3544 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3545 APInt::getAllOnesValue(OpSizeInBits))) 3546 return DAG.getConstant(0, VT); 3547 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3548 if (N1.getOpcode() == ISD::TRUNCATE && 3549 N1.getOperand(0).getOpcode() == ISD::AND && 3550 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3551 SDValue N101 = N1.getOperand(0).getOperand(1); 3552 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3553 EVT TruncVT = N1.getValueType(); 3554 SDValue N100 = N1.getOperand(0).getOperand(0); 3555 APInt TruncC = N101C->getAPIntValue(); 3556 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3557 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3558 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3559 DAG.getNode(ISD::TRUNCATE, 3560 N->getDebugLoc(), 3561 TruncVT, N100), 3562 DAG.getConstant(TruncC, TruncVT))); 3563 } 3564 } 3565 3566 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3567 return SDValue(N, 0); 3568 3569 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3570 if (N1C && N0.getOpcode() == ISD::SHL && 3571 N0.getOperand(1).getOpcode() == ISD::Constant) { 3572 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3573 uint64_t c2 = N1C->getZExtValue(); 3574 if (c1 + c2 >= OpSizeInBits) 3575 return DAG.getConstant(0, VT); 3576 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3577 DAG.getConstant(c1 + c2, N1.getValueType())); 3578 } 3579 3580 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3581 // For this to be valid, the second form must not preserve any of the bits 3582 // that are shifted out by the inner shift in the first form. This means 3583 // the outer shift size must be >= the number of bits added by the ext. 3584 // As a corollary, we don't care what kind of ext it is. 3585 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3586 N0.getOpcode() == ISD::ANY_EXTEND || 3587 N0.getOpcode() == ISD::SIGN_EXTEND) && 3588 N0.getOperand(0).getOpcode() == ISD::SHL && 3589 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3590 uint64_t c1 = 3591 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3592 uint64_t c2 = N1C->getZExtValue(); 3593 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3594 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3595 if (c2 >= OpSizeInBits - InnerShiftSize) { 3596 if (c1 + c2 >= OpSizeInBits) 3597 return DAG.getConstant(0, VT); 3598 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3599 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3600 N0.getOperand(0)->getOperand(0)), 3601 DAG.getConstant(c1 + c2, N1.getValueType())); 3602 } 3603 } 3604 3605 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3606 // (and (srl x, (sub c1, c2), MASK) 3607 // Only fold this if the inner shift has no other uses -- if it does, folding 3608 // this will increase the total number of instructions. 3609 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3610 N0.getOperand(1).getOpcode() == ISD::Constant) { 3611 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3612 if (c1 < VT.getSizeInBits()) { 3613 uint64_t c2 = N1C->getZExtValue(); 3614 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3615 VT.getSizeInBits() - c1); 3616 SDValue Shift; 3617 if (c2 > c1) { 3618 Mask = Mask.shl(c2-c1); 3619 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3620 DAG.getConstant(c2-c1, N1.getValueType())); 3621 } else { 3622 Mask = Mask.lshr(c1-c2); 3623 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3624 DAG.getConstant(c1-c2, N1.getValueType())); 3625 } 3626 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3627 DAG.getConstant(Mask, VT)); 3628 } 3629 } 3630 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3631 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3632 SDValue HiBitsMask = 3633 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3634 VT.getSizeInBits() - 3635 N1C->getZExtValue()), 3636 VT); 3637 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3638 HiBitsMask); 3639 } 3640 3641 if (N1C) { 3642 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3643 if (NewSHL.getNode()) 3644 return NewSHL; 3645 } 3646 3647 return SDValue(); 3648} 3649 3650SDValue DAGCombiner::visitSRA(SDNode *N) { 3651 SDValue N0 = N->getOperand(0); 3652 SDValue N1 = N->getOperand(1); 3653 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3654 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3655 EVT VT = N0.getValueType(); 3656 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3657 3658 // fold (sra c1, c2) -> (sra c1, c2) 3659 if (N0C && N1C) 3660 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3661 // fold (sra 0, x) -> 0 3662 if (N0C && N0C->isNullValue()) 3663 return N0; 3664 // fold (sra -1, x) -> -1 3665 if (N0C && N0C->isAllOnesValue()) 3666 return N0; 3667 // fold (sra x, (setge c, size(x))) -> undef 3668 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3669 return DAG.getUNDEF(VT); 3670 // fold (sra x, 0) -> x 3671 if (N1C && N1C->isNullValue()) 3672 return N0; 3673 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3674 // sext_inreg. 3675 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3676 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3677 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3678 if (VT.isVector()) 3679 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3680 ExtVT, VT.getVectorNumElements()); 3681 if ((!LegalOperations || 3682 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3683 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3684 N0.getOperand(0), DAG.getValueType(ExtVT)); 3685 } 3686 3687 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3688 if (N1C && N0.getOpcode() == ISD::SRA) { 3689 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3690 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3691 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3692 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3693 DAG.getConstant(Sum, N1C->getValueType(0))); 3694 } 3695 } 3696 3697 // fold (sra (shl X, m), (sub result_size, n)) 3698 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3699 // result_size - n != m. 3700 // If truncate is free for the target sext(shl) is likely to result in better 3701 // code. 3702 if (N0.getOpcode() == ISD::SHL) { 3703 // Get the two constanst of the shifts, CN0 = m, CN = n. 3704 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3705 if (N01C && N1C) { 3706 // Determine what the truncate's result bitsize and type would be. 3707 EVT TruncVT = 3708 EVT::getIntegerVT(*DAG.getContext(), 3709 OpSizeInBits - N1C->getZExtValue()); 3710 // Determine the residual right-shift amount. 3711 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3712 3713 // If the shift is not a no-op (in which case this should be just a sign 3714 // extend already), the truncated to type is legal, sign_extend is legal 3715 // on that type, and the truncate to that type is both legal and free, 3716 // perform the transform. 3717 if ((ShiftAmt > 0) && 3718 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3719 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3720 TLI.isTruncateFree(VT, TruncVT)) { 3721 3722 SDValue Amt = DAG.getConstant(ShiftAmt, 3723 getShiftAmountTy(N0.getOperand(0).getValueType())); 3724 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3725 N0.getOperand(0), Amt); 3726 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3727 Shift); 3728 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3729 N->getValueType(0), Trunc); 3730 } 3731 } 3732 } 3733 3734 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3735 if (N1.getOpcode() == ISD::TRUNCATE && 3736 N1.getOperand(0).getOpcode() == ISD::AND && 3737 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3738 SDValue N101 = N1.getOperand(0).getOperand(1); 3739 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3740 EVT TruncVT = N1.getValueType(); 3741 SDValue N100 = N1.getOperand(0).getOperand(0); 3742 APInt TruncC = N101C->getAPIntValue(); 3743 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3744 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3745 DAG.getNode(ISD::AND, N->getDebugLoc(), 3746 TruncVT, 3747 DAG.getNode(ISD::TRUNCATE, 3748 N->getDebugLoc(), 3749 TruncVT, N100), 3750 DAG.getConstant(TruncC, TruncVT))); 3751 } 3752 } 3753 3754 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3755 // if c1 is equal to the number of bits the trunc removes 3756 if (N0.getOpcode() == ISD::TRUNCATE && 3757 (N0.getOperand(0).getOpcode() == ISD::SRL || 3758 N0.getOperand(0).getOpcode() == ISD::SRA) && 3759 N0.getOperand(0).hasOneUse() && 3760 N0.getOperand(0).getOperand(1).hasOneUse() && 3761 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3762 EVT LargeVT = N0.getOperand(0).getValueType(); 3763 ConstantSDNode *LargeShiftAmt = 3764 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3765 3766 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3767 LargeShiftAmt->getZExtValue()) { 3768 SDValue Amt = 3769 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3770 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3771 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3772 N0.getOperand(0).getOperand(0), Amt); 3773 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3774 } 3775 } 3776 3777 // Simplify, based on bits shifted out of the LHS. 3778 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3779 return SDValue(N, 0); 3780 3781 3782 // If the sign bit is known to be zero, switch this to a SRL. 3783 if (DAG.SignBitIsZero(N0)) 3784 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3785 3786 if (N1C) { 3787 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3788 if (NewSRA.getNode()) 3789 return NewSRA; 3790 } 3791 3792 return SDValue(); 3793} 3794 3795SDValue DAGCombiner::visitSRL(SDNode *N) { 3796 SDValue N0 = N->getOperand(0); 3797 SDValue N1 = N->getOperand(1); 3798 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3799 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3800 EVT VT = N0.getValueType(); 3801 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3802 3803 // fold (srl c1, c2) -> c1 >>u c2 3804 if (N0C && N1C) 3805 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3806 // fold (srl 0, x) -> 0 3807 if (N0C && N0C->isNullValue()) 3808 return N0; 3809 // fold (srl x, c >= size(x)) -> undef 3810 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3811 return DAG.getUNDEF(VT); 3812 // fold (srl x, 0) -> x 3813 if (N1C && N1C->isNullValue()) 3814 return N0; 3815 // if (srl x, c) is known to be zero, return 0 3816 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3817 APInt::getAllOnesValue(OpSizeInBits))) 3818 return DAG.getConstant(0, VT); 3819 3820 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3821 if (N1C && N0.getOpcode() == ISD::SRL && 3822 N0.getOperand(1).getOpcode() == ISD::Constant) { 3823 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3824 uint64_t c2 = N1C->getZExtValue(); 3825 if (c1 + c2 >= OpSizeInBits) 3826 return DAG.getConstant(0, VT); 3827 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3828 DAG.getConstant(c1 + c2, N1.getValueType())); 3829 } 3830 3831 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3832 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3833 N0.getOperand(0).getOpcode() == ISD::SRL && 3834 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3835 uint64_t c1 = 3836 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3837 uint64_t c2 = N1C->getZExtValue(); 3838 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3839 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3840 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3841 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3842 if (c1 + OpSizeInBits == InnerShiftSize) { 3843 if (c1 + c2 >= InnerShiftSize) 3844 return DAG.getConstant(0, VT); 3845 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3846 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3847 N0.getOperand(0)->getOperand(0), 3848 DAG.getConstant(c1 + c2, ShiftCountVT))); 3849 } 3850 } 3851 3852 // fold (srl (shl x, c), c) -> (and x, cst2) 3853 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3854 N0.getValueSizeInBits() <= 64) { 3855 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3856 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3857 DAG.getConstant(~0ULL >> ShAmt, VT)); 3858 } 3859 3860 3861 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3862 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3863 // Shifting in all undef bits? 3864 EVT SmallVT = N0.getOperand(0).getValueType(); 3865 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3866 return DAG.getUNDEF(VT); 3867 3868 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3869 uint64_t ShiftAmt = N1C->getZExtValue(); 3870 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3871 N0.getOperand(0), 3872 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3873 AddToWorkList(SmallShift.getNode()); 3874 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3875 } 3876 } 3877 3878 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3879 // bit, which is unmodified by sra. 3880 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3881 if (N0.getOpcode() == ISD::SRA) 3882 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3883 } 3884 3885 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3886 if (N1C && N0.getOpcode() == ISD::CTLZ && 3887 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3888 APInt KnownZero, KnownOne; 3889 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3890 3891 // If any of the input bits are KnownOne, then the input couldn't be all 3892 // zeros, thus the result of the srl will always be zero. 3893 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3894 3895 // If all of the bits input the to ctlz node are known to be zero, then 3896 // the result of the ctlz is "32" and the result of the shift is one. 3897 APInt UnknownBits = ~KnownZero; 3898 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3899 3900 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3901 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3902 // Okay, we know that only that the single bit specified by UnknownBits 3903 // could be set on input to the CTLZ node. If this bit is set, the SRL 3904 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3905 // to an SRL/XOR pair, which is likely to simplify more. 3906 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3907 SDValue Op = N0.getOperand(0); 3908 3909 if (ShAmt) { 3910 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3911 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3912 AddToWorkList(Op.getNode()); 3913 } 3914 3915 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3916 Op, DAG.getConstant(1, VT)); 3917 } 3918 } 3919 3920 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3921 if (N1.getOpcode() == ISD::TRUNCATE && 3922 N1.getOperand(0).getOpcode() == ISD::AND && 3923 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3924 SDValue N101 = N1.getOperand(0).getOperand(1); 3925 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3926 EVT TruncVT = N1.getValueType(); 3927 SDValue N100 = N1.getOperand(0).getOperand(0); 3928 APInt TruncC = N101C->getAPIntValue(); 3929 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3930 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3931 DAG.getNode(ISD::AND, N->getDebugLoc(), 3932 TruncVT, 3933 DAG.getNode(ISD::TRUNCATE, 3934 N->getDebugLoc(), 3935 TruncVT, N100), 3936 DAG.getConstant(TruncC, TruncVT))); 3937 } 3938 } 3939 3940 // fold operands of srl based on knowledge that the low bits are not 3941 // demanded. 3942 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3943 return SDValue(N, 0); 3944 3945 if (N1C) { 3946 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3947 if (NewSRL.getNode()) 3948 return NewSRL; 3949 } 3950 3951 // Attempt to convert a srl of a load into a narrower zero-extending load. 3952 SDValue NarrowLoad = ReduceLoadWidth(N); 3953 if (NarrowLoad.getNode()) 3954 return NarrowLoad; 3955 3956 // Here is a common situation. We want to optimize: 3957 // 3958 // %a = ... 3959 // %b = and i32 %a, 2 3960 // %c = srl i32 %b, 1 3961 // brcond i32 %c ... 3962 // 3963 // into 3964 // 3965 // %a = ... 3966 // %b = and %a, 2 3967 // %c = setcc eq %b, 0 3968 // brcond %c ... 3969 // 3970 // However when after the source operand of SRL is optimized into AND, the SRL 3971 // itself may not be optimized further. Look for it and add the BRCOND into 3972 // the worklist. 3973 if (N->hasOneUse()) { 3974 SDNode *Use = *N->use_begin(); 3975 if (Use->getOpcode() == ISD::BRCOND) 3976 AddToWorkList(Use); 3977 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3978 // Also look pass the truncate. 3979 Use = *Use->use_begin(); 3980 if (Use->getOpcode() == ISD::BRCOND) 3981 AddToWorkList(Use); 3982 } 3983 } 3984 3985 return SDValue(); 3986} 3987 3988SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3989 SDValue N0 = N->getOperand(0); 3990 EVT VT = N->getValueType(0); 3991 3992 // fold (ctlz c1) -> c2 3993 if (isa<ConstantSDNode>(N0)) 3994 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3995 return SDValue(); 3996} 3997 3998SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3999 SDValue N0 = N->getOperand(0); 4000 EVT VT = N->getValueType(0); 4001 4002 // fold (ctlz_zero_undef c1) -> c2 4003 if (isa<ConstantSDNode>(N0)) 4004 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4005 return SDValue(); 4006} 4007 4008SDValue DAGCombiner::visitCTTZ(SDNode *N) { 4009 SDValue N0 = N->getOperand(0); 4010 EVT VT = N->getValueType(0); 4011 4012 // fold (cttz c1) -> c2 4013 if (isa<ConstantSDNode>(N0)) 4014 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 4015 return SDValue(); 4016} 4017 4018SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4019 SDValue N0 = N->getOperand(0); 4020 EVT VT = N->getValueType(0); 4021 4022 // fold (cttz_zero_undef c1) -> c2 4023 if (isa<ConstantSDNode>(N0)) 4024 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4025 return SDValue(); 4026} 4027 4028SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4029 SDValue N0 = N->getOperand(0); 4030 EVT VT = N->getValueType(0); 4031 4032 // fold (ctpop c1) -> c2 4033 if (isa<ConstantSDNode>(N0)) 4034 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 4035 return SDValue(); 4036} 4037 4038SDValue DAGCombiner::visitSELECT(SDNode *N) { 4039 SDValue N0 = N->getOperand(0); 4040 SDValue N1 = N->getOperand(1); 4041 SDValue N2 = N->getOperand(2); 4042 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4043 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4044 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4045 EVT VT = N->getValueType(0); 4046 EVT VT0 = N0.getValueType(); 4047 4048 // fold (select C, X, X) -> X 4049 if (N1 == N2) 4050 return N1; 4051 // fold (select true, X, Y) -> X 4052 if (N0C && !N0C->isNullValue()) 4053 return N1; 4054 // fold (select false, X, Y) -> Y 4055 if (N0C && N0C->isNullValue()) 4056 return N2; 4057 // fold (select C, 1, X) -> (or C, X) 4058 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4059 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4060 // fold (select C, 0, 1) -> (xor C, 1) 4061 if (VT.isInteger() && 4062 (VT0 == MVT::i1 || 4063 (VT0.isInteger() && 4064 TLI.getBooleanContents(false) == 4065 TargetLowering::ZeroOrOneBooleanContent)) && 4066 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4067 SDValue XORNode; 4068 if (VT == VT0) 4069 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4070 N0, DAG.getConstant(1, VT0)); 4071 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4072 N0, DAG.getConstant(1, VT0)); 4073 AddToWorkList(XORNode.getNode()); 4074 if (VT.bitsGT(VT0)) 4075 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4076 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4077 } 4078 // fold (select C, 0, X) -> (and (not C), X) 4079 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4080 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4081 AddToWorkList(NOTNode.getNode()); 4082 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4083 } 4084 // fold (select C, X, 1) -> (or (not C), X) 4085 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4086 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4087 AddToWorkList(NOTNode.getNode()); 4088 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4089 } 4090 // fold (select C, X, 0) -> (and C, X) 4091 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4092 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4093 // fold (select X, X, Y) -> (or X, Y) 4094 // fold (select X, 1, Y) -> (or X, Y) 4095 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4096 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4097 // fold (select X, Y, X) -> (and X, Y) 4098 // fold (select X, Y, 0) -> (and X, Y) 4099 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4100 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4101 4102 // If we can fold this based on the true/false value, do so. 4103 if (SimplifySelectOps(N, N1, N2)) 4104 return SDValue(N, 0); // Don't revisit N. 4105 4106 // fold selects based on a setcc into other things, such as min/max/abs 4107 if (N0.getOpcode() == ISD::SETCC) { 4108 // FIXME: 4109 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4110 // having to say they don't support SELECT_CC on every type the DAG knows 4111 // about, since there is no way to mark an opcode illegal at all value types 4112 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4113 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4114 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4115 N0.getOperand(0), N0.getOperand(1), 4116 N1, N2, N0.getOperand(2)); 4117 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4118 } 4119 4120 return SDValue(); 4121} 4122 4123SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4124 SDValue N0 = N->getOperand(0); 4125 SDValue N1 = N->getOperand(1); 4126 SDValue N2 = N->getOperand(2); 4127 SDValue N3 = N->getOperand(3); 4128 SDValue N4 = N->getOperand(4); 4129 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4130 4131 // fold select_cc lhs, rhs, x, x, cc -> x 4132 if (N2 == N3) 4133 return N2; 4134 4135 // Determine if the condition we're dealing with is constant 4136 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4137 N0, N1, CC, N->getDebugLoc(), false); 4138 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4139 4140 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4141 if (!SCCC->isNullValue()) 4142 return N2; // cond always true -> true val 4143 else 4144 return N3; // cond always false -> false val 4145 } 4146 4147 // Fold to a simpler select_cc 4148 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4149 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4150 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4151 SCC.getOperand(2)); 4152 4153 // If we can fold this based on the true/false value, do so. 4154 if (SimplifySelectOps(N, N2, N3)) 4155 return SDValue(N, 0); // Don't revisit N. 4156 4157 // fold select_cc into other things, such as min/max/abs 4158 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4159} 4160 4161SDValue DAGCombiner::visitSETCC(SDNode *N) { 4162 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4163 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4164 N->getDebugLoc()); 4165} 4166 4167// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4168// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4169// transformation. Returns true if extension are possible and the above 4170// mentioned transformation is profitable. 4171static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4172 unsigned ExtOpc, 4173 SmallVector<SDNode*, 4> &ExtendNodes, 4174 const TargetLowering &TLI) { 4175 bool HasCopyToRegUses = false; 4176 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4177 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4178 UE = N0.getNode()->use_end(); 4179 UI != UE; ++UI) { 4180 SDNode *User = *UI; 4181 if (User == N) 4182 continue; 4183 if (UI.getUse().getResNo() != N0.getResNo()) 4184 continue; 4185 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4186 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4187 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4188 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4189 // Sign bits will be lost after a zext. 4190 return false; 4191 bool Add = false; 4192 for (unsigned i = 0; i != 2; ++i) { 4193 SDValue UseOp = User->getOperand(i); 4194 if (UseOp == N0) 4195 continue; 4196 if (!isa<ConstantSDNode>(UseOp)) 4197 return false; 4198 Add = true; 4199 } 4200 if (Add) 4201 ExtendNodes.push_back(User); 4202 continue; 4203 } 4204 // If truncates aren't free and there are users we can't 4205 // extend, it isn't worthwhile. 4206 if (!isTruncFree) 4207 return false; 4208 // Remember if this value is live-out. 4209 if (User->getOpcode() == ISD::CopyToReg) 4210 HasCopyToRegUses = true; 4211 } 4212 4213 if (HasCopyToRegUses) { 4214 bool BothLiveOut = false; 4215 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4216 UI != UE; ++UI) { 4217 SDUse &Use = UI.getUse(); 4218 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4219 BothLiveOut = true; 4220 break; 4221 } 4222 } 4223 if (BothLiveOut) 4224 // Both unextended and extended values are live out. There had better be 4225 // a good reason for the transformation. 4226 return ExtendNodes.size(); 4227 } 4228 return true; 4229} 4230 4231void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4232 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4233 ISD::NodeType ExtType) { 4234 // Extend SetCC uses if necessary. 4235 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4236 SDNode *SetCC = SetCCs[i]; 4237 SmallVector<SDValue, 4> Ops; 4238 4239 for (unsigned j = 0; j != 2; ++j) { 4240 SDValue SOp = SetCC->getOperand(j); 4241 if (SOp == Trunc) 4242 Ops.push_back(ExtLoad); 4243 else 4244 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4245 } 4246 4247 Ops.push_back(SetCC->getOperand(2)); 4248 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4249 &Ops[0], Ops.size())); 4250 } 4251} 4252 4253SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4254 SDValue N0 = N->getOperand(0); 4255 EVT VT = N->getValueType(0); 4256 4257 // fold (sext c1) -> c1 4258 if (isa<ConstantSDNode>(N0)) 4259 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4260 4261 // fold (sext (sext x)) -> (sext x) 4262 // fold (sext (aext x)) -> (sext x) 4263 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4264 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4265 N0.getOperand(0)); 4266 4267 if (N0.getOpcode() == ISD::TRUNCATE) { 4268 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4269 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4270 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4271 if (NarrowLoad.getNode()) { 4272 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4273 if (NarrowLoad.getNode() != N0.getNode()) { 4274 CombineTo(N0.getNode(), NarrowLoad); 4275 // CombineTo deleted the truncate, if needed, but not what's under it. 4276 AddToWorkList(oye); 4277 } 4278 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4279 } 4280 4281 // See if the value being truncated is already sign extended. If so, just 4282 // eliminate the trunc/sext pair. 4283 SDValue Op = N0.getOperand(0); 4284 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4285 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4286 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4287 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4288 4289 if (OpBits == DestBits) { 4290 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4291 // bits, it is already ready. 4292 if (NumSignBits > DestBits-MidBits) 4293 return Op; 4294 } else if (OpBits < DestBits) { 4295 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4296 // bits, just sext from i32. 4297 if (NumSignBits > OpBits-MidBits) 4298 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4299 } else { 4300 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4301 // bits, just truncate to i32. 4302 if (NumSignBits > OpBits-MidBits) 4303 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4304 } 4305 4306 // fold (sext (truncate x)) -> (sextinreg x). 4307 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4308 N0.getValueType())) { 4309 if (OpBits < DestBits) 4310 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4311 else if (OpBits > DestBits) 4312 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4313 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4314 DAG.getValueType(N0.getValueType())); 4315 } 4316 } 4317 4318 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4319 // None of the supported targets knows how to perform load and sign extend 4320 // on vectors in one instruction. We only perform this transformation on 4321 // scalars. 4322 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4323 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4324 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4325 bool DoXform = true; 4326 SmallVector<SDNode*, 4> SetCCs; 4327 if (!N0.hasOneUse()) 4328 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4329 if (DoXform) { 4330 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4331 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4332 LN0->getChain(), 4333 LN0->getBasePtr(), LN0->getPointerInfo(), 4334 N0.getValueType(), 4335 LN0->isVolatile(), LN0->isNonTemporal(), 4336 LN0->getAlignment()); 4337 CombineTo(N, ExtLoad); 4338 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4339 N0.getValueType(), ExtLoad); 4340 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4341 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4342 ISD::SIGN_EXTEND); 4343 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4344 } 4345 } 4346 4347 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4348 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4349 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4350 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4351 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4352 EVT MemVT = LN0->getMemoryVT(); 4353 if ((!LegalOperations && !LN0->isVolatile()) || 4354 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4355 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4356 LN0->getChain(), 4357 LN0->getBasePtr(), LN0->getPointerInfo(), 4358 MemVT, 4359 LN0->isVolatile(), LN0->isNonTemporal(), 4360 LN0->getAlignment()); 4361 CombineTo(N, ExtLoad); 4362 CombineTo(N0.getNode(), 4363 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4364 N0.getValueType(), ExtLoad), 4365 ExtLoad.getValue(1)); 4366 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4367 } 4368 } 4369 4370 // fold (sext (and/or/xor (load x), cst)) -> 4371 // (and/or/xor (sextload x), (sext cst)) 4372 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4373 N0.getOpcode() == ISD::XOR) && 4374 isa<LoadSDNode>(N0.getOperand(0)) && 4375 N0.getOperand(1).getOpcode() == ISD::Constant && 4376 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4377 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4378 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4379 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4380 bool DoXform = true; 4381 SmallVector<SDNode*, 4> SetCCs; 4382 if (!N0.hasOneUse()) 4383 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4384 SetCCs, TLI); 4385 if (DoXform) { 4386 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4387 LN0->getChain(), LN0->getBasePtr(), 4388 LN0->getPointerInfo(), 4389 LN0->getMemoryVT(), 4390 LN0->isVolatile(), 4391 LN0->isNonTemporal(), 4392 LN0->getAlignment()); 4393 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4394 Mask = Mask.sext(VT.getSizeInBits()); 4395 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4396 ExtLoad, DAG.getConstant(Mask, VT)); 4397 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4398 N0.getOperand(0).getDebugLoc(), 4399 N0.getOperand(0).getValueType(), ExtLoad); 4400 CombineTo(N, And); 4401 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4402 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4403 ISD::SIGN_EXTEND); 4404 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4405 } 4406 } 4407 } 4408 4409 if (N0.getOpcode() == ISD::SETCC) { 4410 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4411 // Only do this before legalize for now. 4412 if (VT.isVector() && !LegalOperations) { 4413 EVT N0VT = N0.getOperand(0).getValueType(); 4414 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4415 // of the same size as the compared operands. Only optimize sext(setcc()) 4416 // if this is the case. 4417 EVT SVT = TLI.getSetCCResultType(N0VT); 4418 4419 // We know that the # elements of the results is the same as the 4420 // # elements of the compare (and the # elements of the compare result 4421 // for that matter). Check to see that they are the same size. If so, 4422 // we know that the element size of the sext'd result matches the 4423 // element size of the compare operands. 4424 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4425 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4426 N0.getOperand(1), 4427 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4428 // If the desired elements are smaller or larger than the source 4429 // elements we can use a matching integer vector type and then 4430 // truncate/sign extend 4431 else { 4432 EVT MatchingElementType = 4433 EVT::getIntegerVT(*DAG.getContext(), 4434 N0VT.getScalarType().getSizeInBits()); 4435 EVT MatchingVectorType = 4436 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4437 N0VT.getVectorNumElements()); 4438 4439 if (SVT == MatchingVectorType) { 4440 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4441 N0.getOperand(0), N0.getOperand(1), 4442 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4443 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4444 } 4445 } 4446 } 4447 4448 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4449 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4450 SDValue NegOne = 4451 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4452 SDValue SCC = 4453 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4454 NegOne, DAG.getConstant(0, VT), 4455 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4456 if (SCC.getNode()) return SCC; 4457 if (!LegalOperations || 4458 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4459 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4460 DAG.getSetCC(N->getDebugLoc(), 4461 TLI.getSetCCResultType(VT), 4462 N0.getOperand(0), N0.getOperand(1), 4463 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4464 NegOne, DAG.getConstant(0, VT)); 4465 } 4466 4467 // fold (sext x) -> (zext x) if the sign bit is known zero. 4468 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4469 DAG.SignBitIsZero(N0)) 4470 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4471 4472 return SDValue(); 4473} 4474 4475// isTruncateOf - If N is a truncate of some other value, return true, record 4476// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4477// This function computes KnownZero to avoid a duplicated call to 4478// ComputeMaskedBits in the caller. 4479static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4480 APInt &KnownZero) { 4481 APInt KnownOne; 4482 if (N->getOpcode() == ISD::TRUNCATE) { 4483 Op = N->getOperand(0); 4484 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4485 return true; 4486 } 4487 4488 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4489 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4490 return false; 4491 4492 SDValue Op0 = N->getOperand(0); 4493 SDValue Op1 = N->getOperand(1); 4494 assert(Op0.getValueType() == Op1.getValueType()); 4495 4496 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4497 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4498 if (COp0 && COp0->isNullValue()) 4499 Op = Op1; 4500 else if (COp1 && COp1->isNullValue()) 4501 Op = Op0; 4502 else 4503 return false; 4504 4505 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4506 4507 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4508 return false; 4509 4510 return true; 4511} 4512 4513SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4514 SDValue N0 = N->getOperand(0); 4515 EVT VT = N->getValueType(0); 4516 4517 // fold (zext c1) -> c1 4518 if (isa<ConstantSDNode>(N0)) 4519 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4520 // fold (zext (zext x)) -> (zext x) 4521 // fold (zext (aext x)) -> (zext x) 4522 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4523 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4524 N0.getOperand(0)); 4525 4526 // fold (zext (truncate x)) -> (zext x) or 4527 // (zext (truncate x)) -> (truncate x) 4528 // This is valid when the truncated bits of x are already zero. 4529 // FIXME: We should extend this to work for vectors too. 4530 SDValue Op; 4531 APInt KnownZero; 4532 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4533 APInt TruncatedBits = 4534 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4535 APInt(Op.getValueSizeInBits(), 0) : 4536 APInt::getBitsSet(Op.getValueSizeInBits(), 4537 N0.getValueSizeInBits(), 4538 std::min(Op.getValueSizeInBits(), 4539 VT.getSizeInBits())); 4540 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4541 if (VT.bitsGT(Op.getValueType())) 4542 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4543 if (VT.bitsLT(Op.getValueType())) 4544 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4545 4546 return Op; 4547 } 4548 } 4549 4550 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4551 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4552 if (N0.getOpcode() == ISD::TRUNCATE) { 4553 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4554 if (NarrowLoad.getNode()) { 4555 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4556 if (NarrowLoad.getNode() != N0.getNode()) { 4557 CombineTo(N0.getNode(), NarrowLoad); 4558 // CombineTo deleted the truncate, if needed, but not what's under it. 4559 AddToWorkList(oye); 4560 } 4561 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4562 } 4563 } 4564 4565 // fold (zext (truncate x)) -> (and x, mask) 4566 if (N0.getOpcode() == ISD::TRUNCATE && 4567 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4568 4569 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4570 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4571 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4572 if (NarrowLoad.getNode()) { 4573 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4574 if (NarrowLoad.getNode() != N0.getNode()) { 4575 CombineTo(N0.getNode(), NarrowLoad); 4576 // CombineTo deleted the truncate, if needed, but not what's under it. 4577 AddToWorkList(oye); 4578 } 4579 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4580 } 4581 4582 SDValue Op = N0.getOperand(0); 4583 if (Op.getValueType().bitsLT(VT)) { 4584 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4585 AddToWorkList(Op.getNode()); 4586 } else if (Op.getValueType().bitsGT(VT)) { 4587 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4588 AddToWorkList(Op.getNode()); 4589 } 4590 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4591 N0.getValueType().getScalarType()); 4592 } 4593 4594 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4595 // if either of the casts is not free. 4596 if (N0.getOpcode() == ISD::AND && 4597 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4598 N0.getOperand(1).getOpcode() == ISD::Constant && 4599 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4600 N0.getValueType()) || 4601 !TLI.isZExtFree(N0.getValueType(), VT))) { 4602 SDValue X = N0.getOperand(0).getOperand(0); 4603 if (X.getValueType().bitsLT(VT)) { 4604 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4605 } else if (X.getValueType().bitsGT(VT)) { 4606 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4607 } 4608 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4609 Mask = Mask.zext(VT.getSizeInBits()); 4610 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4611 X, DAG.getConstant(Mask, VT)); 4612 } 4613 4614 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4615 // None of the supported targets knows how to perform load and vector_zext 4616 // on vectors in one instruction. We only perform this transformation on 4617 // scalars. 4618 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4619 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4620 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4621 bool DoXform = true; 4622 SmallVector<SDNode*, 4> SetCCs; 4623 if (!N0.hasOneUse()) 4624 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4625 if (DoXform) { 4626 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4627 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4628 LN0->getChain(), 4629 LN0->getBasePtr(), LN0->getPointerInfo(), 4630 N0.getValueType(), 4631 LN0->isVolatile(), LN0->isNonTemporal(), 4632 LN0->getAlignment()); 4633 CombineTo(N, ExtLoad); 4634 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4635 N0.getValueType(), ExtLoad); 4636 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4637 4638 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4639 ISD::ZERO_EXTEND); 4640 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4641 } 4642 } 4643 4644 // fold (zext (and/or/xor (load x), cst)) -> 4645 // (and/or/xor (zextload x), (zext cst)) 4646 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4647 N0.getOpcode() == ISD::XOR) && 4648 isa<LoadSDNode>(N0.getOperand(0)) && 4649 N0.getOperand(1).getOpcode() == ISD::Constant && 4650 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4651 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4652 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4653 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4654 bool DoXform = true; 4655 SmallVector<SDNode*, 4> SetCCs; 4656 if (!N0.hasOneUse()) 4657 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4658 SetCCs, TLI); 4659 if (DoXform) { 4660 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4661 LN0->getChain(), LN0->getBasePtr(), 4662 LN0->getPointerInfo(), 4663 LN0->getMemoryVT(), 4664 LN0->isVolatile(), 4665 LN0->isNonTemporal(), 4666 LN0->getAlignment()); 4667 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4668 Mask = Mask.zext(VT.getSizeInBits()); 4669 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4670 ExtLoad, DAG.getConstant(Mask, VT)); 4671 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4672 N0.getOperand(0).getDebugLoc(), 4673 N0.getOperand(0).getValueType(), ExtLoad); 4674 CombineTo(N, And); 4675 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4676 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4677 ISD::ZERO_EXTEND); 4678 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4679 } 4680 } 4681 } 4682 4683 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4684 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4685 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4686 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4687 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4688 EVT MemVT = LN0->getMemoryVT(); 4689 if ((!LegalOperations && !LN0->isVolatile()) || 4690 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4691 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4692 LN0->getChain(), 4693 LN0->getBasePtr(), LN0->getPointerInfo(), 4694 MemVT, 4695 LN0->isVolatile(), LN0->isNonTemporal(), 4696 LN0->getAlignment()); 4697 CombineTo(N, ExtLoad); 4698 CombineTo(N0.getNode(), 4699 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4700 ExtLoad), 4701 ExtLoad.getValue(1)); 4702 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4703 } 4704 } 4705 4706 if (N0.getOpcode() == ISD::SETCC) { 4707 if (!LegalOperations && VT.isVector()) { 4708 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4709 // Only do this before legalize for now. 4710 EVT N0VT = N0.getOperand(0).getValueType(); 4711 EVT EltVT = VT.getVectorElementType(); 4712 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4713 DAG.getConstant(1, EltVT)); 4714 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4715 // We know that the # elements of the results is the same as the 4716 // # elements of the compare (and the # elements of the compare result 4717 // for that matter). Check to see that they are the same size. If so, 4718 // we know that the element size of the sext'd result matches the 4719 // element size of the compare operands. 4720 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4721 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4722 N0.getOperand(1), 4723 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4724 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4725 &OneOps[0], OneOps.size())); 4726 4727 // If the desired elements are smaller or larger than the source 4728 // elements we can use a matching integer vector type and then 4729 // truncate/sign extend 4730 EVT MatchingElementType = 4731 EVT::getIntegerVT(*DAG.getContext(), 4732 N0VT.getScalarType().getSizeInBits()); 4733 EVT MatchingVectorType = 4734 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4735 N0VT.getVectorNumElements()); 4736 SDValue VsetCC = 4737 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4738 N0.getOperand(1), 4739 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4740 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4741 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4742 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4743 &OneOps[0], OneOps.size())); 4744 } 4745 4746 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4747 SDValue SCC = 4748 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4749 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4750 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4751 if (SCC.getNode()) return SCC; 4752 } 4753 4754 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4755 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4756 isa<ConstantSDNode>(N0.getOperand(1)) && 4757 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4758 N0.hasOneUse()) { 4759 SDValue ShAmt = N0.getOperand(1); 4760 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4761 if (N0.getOpcode() == ISD::SHL) { 4762 SDValue InnerZExt = N0.getOperand(0); 4763 // If the original shl may be shifting out bits, do not perform this 4764 // transformation. 4765 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4766 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4767 if (ShAmtVal > KnownZeroBits) 4768 return SDValue(); 4769 } 4770 4771 DebugLoc DL = N->getDebugLoc(); 4772 4773 // Ensure that the shift amount is wide enough for the shifted value. 4774 if (VT.getSizeInBits() >= 256) 4775 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4776 4777 return DAG.getNode(N0.getOpcode(), DL, VT, 4778 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4779 ShAmt); 4780 } 4781 4782 return SDValue(); 4783} 4784 4785SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4786 SDValue N0 = N->getOperand(0); 4787 EVT VT = N->getValueType(0); 4788 4789 // fold (aext c1) -> c1 4790 if (isa<ConstantSDNode>(N0)) 4791 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4792 // fold (aext (aext x)) -> (aext x) 4793 // fold (aext (zext x)) -> (zext x) 4794 // fold (aext (sext x)) -> (sext x) 4795 if (N0.getOpcode() == ISD::ANY_EXTEND || 4796 N0.getOpcode() == ISD::ZERO_EXTEND || 4797 N0.getOpcode() == ISD::SIGN_EXTEND) 4798 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4799 4800 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4801 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4802 if (N0.getOpcode() == ISD::TRUNCATE) { 4803 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4804 if (NarrowLoad.getNode()) { 4805 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4806 if (NarrowLoad.getNode() != N0.getNode()) { 4807 CombineTo(N0.getNode(), NarrowLoad); 4808 // CombineTo deleted the truncate, if needed, but not what's under it. 4809 AddToWorkList(oye); 4810 } 4811 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4812 } 4813 } 4814 4815 // fold (aext (truncate x)) 4816 if (N0.getOpcode() == ISD::TRUNCATE) { 4817 SDValue TruncOp = N0.getOperand(0); 4818 if (TruncOp.getValueType() == VT) 4819 return TruncOp; // x iff x size == zext size. 4820 if (TruncOp.getValueType().bitsGT(VT)) 4821 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4822 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4823 } 4824 4825 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4826 // if the trunc is not free. 4827 if (N0.getOpcode() == ISD::AND && 4828 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4829 N0.getOperand(1).getOpcode() == ISD::Constant && 4830 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4831 N0.getValueType())) { 4832 SDValue X = N0.getOperand(0).getOperand(0); 4833 if (X.getValueType().bitsLT(VT)) { 4834 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4835 } else if (X.getValueType().bitsGT(VT)) { 4836 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4837 } 4838 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4839 Mask = Mask.zext(VT.getSizeInBits()); 4840 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4841 X, DAG.getConstant(Mask, VT)); 4842 } 4843 4844 // fold (aext (load x)) -> (aext (truncate (extload x))) 4845 // None of the supported targets knows how to perform load and any_ext 4846 // on vectors in one instruction. We only perform this transformation on 4847 // scalars. 4848 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4849 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4850 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4851 bool DoXform = true; 4852 SmallVector<SDNode*, 4> SetCCs; 4853 if (!N0.hasOneUse()) 4854 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4855 if (DoXform) { 4856 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4857 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4858 LN0->getChain(), 4859 LN0->getBasePtr(), LN0->getPointerInfo(), 4860 N0.getValueType(), 4861 LN0->isVolatile(), LN0->isNonTemporal(), 4862 LN0->getAlignment()); 4863 CombineTo(N, ExtLoad); 4864 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4865 N0.getValueType(), ExtLoad); 4866 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4867 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4868 ISD::ANY_EXTEND); 4869 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4870 } 4871 } 4872 4873 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4874 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4875 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4876 if (N0.getOpcode() == ISD::LOAD && 4877 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4878 N0.hasOneUse()) { 4879 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4880 EVT MemVT = LN0->getMemoryVT(); 4881 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4882 VT, LN0->getChain(), LN0->getBasePtr(), 4883 LN0->getPointerInfo(), MemVT, 4884 LN0->isVolatile(), LN0->isNonTemporal(), 4885 LN0->getAlignment()); 4886 CombineTo(N, ExtLoad); 4887 CombineTo(N0.getNode(), 4888 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4889 N0.getValueType(), ExtLoad), 4890 ExtLoad.getValue(1)); 4891 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4892 } 4893 4894 if (N0.getOpcode() == ISD::SETCC) { 4895 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4896 // Only do this before legalize for now. 4897 if (VT.isVector() && !LegalOperations) { 4898 EVT N0VT = N0.getOperand(0).getValueType(); 4899 // We know that the # elements of the results is the same as the 4900 // # elements of the compare (and the # elements of the compare result 4901 // for that matter). Check to see that they are the same size. If so, 4902 // we know that the element size of the sext'd result matches the 4903 // element size of the compare operands. 4904 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4905 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4906 N0.getOperand(1), 4907 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4908 // If the desired elements are smaller or larger than the source 4909 // elements we can use a matching integer vector type and then 4910 // truncate/sign extend 4911 else { 4912 EVT MatchingElementType = 4913 EVT::getIntegerVT(*DAG.getContext(), 4914 N0VT.getScalarType().getSizeInBits()); 4915 EVT MatchingVectorType = 4916 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4917 N0VT.getVectorNumElements()); 4918 SDValue VsetCC = 4919 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4920 N0.getOperand(1), 4921 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4922 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4923 } 4924 } 4925 4926 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4927 SDValue SCC = 4928 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4929 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4930 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4931 if (SCC.getNode()) 4932 return SCC; 4933 } 4934 4935 return SDValue(); 4936} 4937 4938/// GetDemandedBits - See if the specified operand can be simplified with the 4939/// knowledge that only the bits specified by Mask are used. If so, return the 4940/// simpler operand, otherwise return a null SDValue. 4941SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4942 switch (V.getOpcode()) { 4943 default: break; 4944 case ISD::Constant: { 4945 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4946 assert(CV != 0 && "Const value should be ConstSDNode."); 4947 const APInt &CVal = CV->getAPIntValue(); 4948 APInt NewVal = CVal & Mask; 4949 if (NewVal != CVal) { 4950 return DAG.getConstant(NewVal, V.getValueType()); 4951 } 4952 break; 4953 } 4954 case ISD::OR: 4955 case ISD::XOR: 4956 // If the LHS or RHS don't contribute bits to the or, drop them. 4957 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4958 return V.getOperand(1); 4959 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4960 return V.getOperand(0); 4961 break; 4962 case ISD::SRL: 4963 // Only look at single-use SRLs. 4964 if (!V.getNode()->hasOneUse()) 4965 break; 4966 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4967 // See if we can recursively simplify the LHS. 4968 unsigned Amt = RHSC->getZExtValue(); 4969 4970 // Watch out for shift count overflow though. 4971 if (Amt >= Mask.getBitWidth()) break; 4972 APInt NewMask = Mask << Amt; 4973 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4974 if (SimplifyLHS.getNode()) 4975 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4976 SimplifyLHS, V.getOperand(1)); 4977 } 4978 } 4979 return SDValue(); 4980} 4981 4982/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4983/// bits and then truncated to a narrower type and where N is a multiple 4984/// of number of bits of the narrower type, transform it to a narrower load 4985/// from address + N / num of bits of new type. If the result is to be 4986/// extended, also fold the extension to form a extending load. 4987SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4988 unsigned Opc = N->getOpcode(); 4989 4990 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4991 SDValue N0 = N->getOperand(0); 4992 EVT VT = N->getValueType(0); 4993 EVT ExtVT = VT; 4994 4995 // This transformation isn't valid for vector loads. 4996 if (VT.isVector()) 4997 return SDValue(); 4998 4999 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 5000 // extended to VT. 5001 if (Opc == ISD::SIGN_EXTEND_INREG) { 5002 ExtType = ISD::SEXTLOAD; 5003 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5004 } else if (Opc == ISD::SRL) { 5005 // Another special-case: SRL is basically zero-extending a narrower value. 5006 ExtType = ISD::ZEXTLOAD; 5007 N0 = SDValue(N, 0); 5008 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 5009 if (!N01) return SDValue(); 5010 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 5011 VT.getSizeInBits() - N01->getZExtValue()); 5012 } 5013 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5014 return SDValue(); 5015 5016 unsigned EVTBits = ExtVT.getSizeInBits(); 5017 5018 // Do not generate loads of non-round integer types since these can 5019 // be expensive (and would be wrong if the type is not byte sized). 5020 if (!ExtVT.isRound()) 5021 return SDValue(); 5022 5023 unsigned ShAmt = 0; 5024 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5025 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5026 ShAmt = N01->getZExtValue(); 5027 // Is the shift amount a multiple of size of VT? 5028 if ((ShAmt & (EVTBits-1)) == 0) { 5029 N0 = N0.getOperand(0); 5030 // Is the load width a multiple of size of VT? 5031 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5032 return SDValue(); 5033 } 5034 5035 // At this point, we must have a load or else we can't do the transform. 5036 if (!isa<LoadSDNode>(N0)) return SDValue(); 5037 5038 // If the shift amount is larger than the input type then we're not 5039 // accessing any of the loaded bytes. If the load was a zextload/extload 5040 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5041 // If the load was a sextload then the result is a splat of the sign bit 5042 // of the extended byte. This is not worth optimizing for. 5043 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5044 return SDValue(); 5045 } 5046 } 5047 5048 // If the load is shifted left (and the result isn't shifted back right), 5049 // we can fold the truncate through the shift. 5050 unsigned ShLeftAmt = 0; 5051 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5052 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5053 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5054 ShLeftAmt = N01->getZExtValue(); 5055 N0 = N0.getOperand(0); 5056 } 5057 } 5058 5059 // If we haven't found a load, we can't narrow it. Don't transform one with 5060 // multiple uses, this would require adding a new load. 5061 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 5062 // Don't change the width of a volatile load. 5063 cast<LoadSDNode>(N0)->isVolatile()) 5064 return SDValue(); 5065 5066 // Verify that we are actually reducing a load width here. 5067 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 5068 return SDValue(); 5069 5070 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5071 EVT PtrType = N0.getOperand(1).getValueType(); 5072 5073 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5074 // It's not possible to generate a constant of extended or untyped type. 5075 return SDValue(); 5076 5077 // For big endian targets, we need to adjust the offset to the pointer to 5078 // load the correct bytes. 5079 if (TLI.isBigEndian()) { 5080 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5081 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5082 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5083 } 5084 5085 uint64_t PtrOff = ShAmt / 8; 5086 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5087 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5088 PtrType, LN0->getBasePtr(), 5089 DAG.getConstant(PtrOff, PtrType)); 5090 AddToWorkList(NewPtr.getNode()); 5091 5092 SDValue Load; 5093 if (ExtType == ISD::NON_EXTLOAD) 5094 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5095 LN0->getPointerInfo().getWithOffset(PtrOff), 5096 LN0->isVolatile(), LN0->isNonTemporal(), 5097 LN0->isInvariant(), NewAlign); 5098 else 5099 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5100 LN0->getPointerInfo().getWithOffset(PtrOff), 5101 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5102 NewAlign); 5103 5104 // Replace the old load's chain with the new load's chain. 5105 WorkListRemover DeadNodes(*this); 5106 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5107 5108 // Shift the result left, if we've swallowed a left shift. 5109 SDValue Result = Load; 5110 if (ShLeftAmt != 0) { 5111 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5112 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5113 ShImmTy = VT; 5114 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5115 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5116 } 5117 5118 // Return the new loaded value. 5119 return Result; 5120} 5121 5122SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5123 SDValue N0 = N->getOperand(0); 5124 SDValue N1 = N->getOperand(1); 5125 EVT VT = N->getValueType(0); 5126 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5127 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5128 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5129 5130 // fold (sext_in_reg c1) -> c1 5131 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5132 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5133 5134 // If the input is already sign extended, just drop the extension. 5135 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5136 return N0; 5137 5138 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5139 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5140 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5141 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5142 N0.getOperand(0), N1); 5143 } 5144 5145 // fold (sext_in_reg (sext x)) -> (sext x) 5146 // fold (sext_in_reg (aext x)) -> (sext x) 5147 // if x is small enough. 5148 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5149 SDValue N00 = N0.getOperand(0); 5150 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5151 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5152 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5153 } 5154 5155 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5156 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5157 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5158 5159 // fold operands of sext_in_reg based on knowledge that the top bits are not 5160 // demanded. 5161 if (SimplifyDemandedBits(SDValue(N, 0))) 5162 return SDValue(N, 0); 5163 5164 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5165 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5166 SDValue NarrowLoad = ReduceLoadWidth(N); 5167 if (NarrowLoad.getNode()) 5168 return NarrowLoad; 5169 5170 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5171 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5172 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5173 if (N0.getOpcode() == ISD::SRL) { 5174 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5175 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5176 // We can turn this into an SRA iff the input to the SRL is already sign 5177 // extended enough. 5178 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5179 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5180 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5181 N0.getOperand(0), N0.getOperand(1)); 5182 } 5183 } 5184 5185 // fold (sext_inreg (extload x)) -> (sextload x) 5186 if (ISD::isEXTLoad(N0.getNode()) && 5187 ISD::isUNINDEXEDLoad(N0.getNode()) && 5188 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5189 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5190 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5191 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5192 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5193 LN0->getChain(), 5194 LN0->getBasePtr(), LN0->getPointerInfo(), 5195 EVT, 5196 LN0->isVolatile(), LN0->isNonTemporal(), 5197 LN0->getAlignment()); 5198 CombineTo(N, ExtLoad); 5199 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5200 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5201 } 5202 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5203 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5204 N0.hasOneUse() && 5205 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5206 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5207 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5208 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5209 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5210 LN0->getChain(), 5211 LN0->getBasePtr(), LN0->getPointerInfo(), 5212 EVT, 5213 LN0->isVolatile(), LN0->isNonTemporal(), 5214 LN0->getAlignment()); 5215 CombineTo(N, ExtLoad); 5216 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5217 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5218 } 5219 5220 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5221 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5222 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5223 N0.getOperand(1), false); 5224 if (BSwap.getNode() != 0) 5225 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5226 BSwap, N1); 5227 } 5228 5229 return SDValue(); 5230} 5231 5232SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5233 SDValue N0 = N->getOperand(0); 5234 EVT VT = N->getValueType(0); 5235 bool isLE = TLI.isLittleEndian(); 5236 5237 // noop truncate 5238 if (N0.getValueType() == N->getValueType(0)) 5239 return N0; 5240 // fold (truncate c1) -> c1 5241 if (isa<ConstantSDNode>(N0)) 5242 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5243 // fold (truncate (truncate x)) -> (truncate x) 5244 if (N0.getOpcode() == ISD::TRUNCATE) 5245 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5246 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5247 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5248 N0.getOpcode() == ISD::SIGN_EXTEND || 5249 N0.getOpcode() == ISD::ANY_EXTEND) { 5250 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5251 // if the source is smaller than the dest, we still need an extend 5252 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5253 N0.getOperand(0)); 5254 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 5255 // if the source is larger than the dest, than we just need the truncate 5256 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5257 else 5258 // if the source and dest are the same type, we can drop both the extend 5259 // and the truncate. 5260 return N0.getOperand(0); 5261 } 5262 5263 // Fold extract-and-trunc into a narrow extract. For example: 5264 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5265 // i32 y = TRUNCATE(i64 x) 5266 // -- becomes -- 5267 // v16i8 b = BITCAST (v2i64 val) 5268 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5269 // 5270 // Note: We only run this optimization after type legalization (which often 5271 // creates this pattern) and before operation legalization after which 5272 // we need to be more careful about the vector instructions that we generate. 5273 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5274 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5275 5276 EVT VecTy = N0.getOperand(0).getValueType(); 5277 EVT ExTy = N0.getValueType(); 5278 EVT TrTy = N->getValueType(0); 5279 5280 unsigned NumElem = VecTy.getVectorNumElements(); 5281 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5282 5283 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5284 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5285 5286 SDValue EltNo = N0->getOperand(1); 5287 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5288 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5289 EVT IndexTy = N0->getOperand(1).getValueType(); 5290 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5291 5292 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5293 NVT, N0.getOperand(0)); 5294 5295 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5296 N->getDebugLoc(), TrTy, V, 5297 DAG.getConstant(Index, IndexTy)); 5298 } 5299 } 5300 5301 // See if we can simplify the input to this truncate through knowledge that 5302 // only the low bits are being used. 5303 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5304 // Currently we only perform this optimization on scalars because vectors 5305 // may have different active low bits. 5306 if (!VT.isVector()) { 5307 SDValue Shorter = 5308 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5309 VT.getSizeInBits())); 5310 if (Shorter.getNode()) 5311 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5312 } 5313 // fold (truncate (load x)) -> (smaller load x) 5314 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5315 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5316 SDValue Reduced = ReduceLoadWidth(N); 5317 if (Reduced.getNode()) 5318 return Reduced; 5319 } 5320 5321 // Simplify the operands using demanded-bits information. 5322 if (!VT.isVector() && 5323 SimplifyDemandedBits(SDValue(N, 0))) 5324 return SDValue(N, 0); 5325 5326 return SDValue(); 5327} 5328 5329static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5330 SDValue Elt = N->getOperand(i); 5331 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5332 return Elt.getNode(); 5333 return Elt.getOperand(Elt.getResNo()).getNode(); 5334} 5335 5336/// CombineConsecutiveLoads - build_pair (load, load) -> load 5337/// if load locations are consecutive. 5338SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5339 assert(N->getOpcode() == ISD::BUILD_PAIR); 5340 5341 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5342 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5343 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5344 LD1->getPointerInfo().getAddrSpace() != 5345 LD2->getPointerInfo().getAddrSpace()) 5346 return SDValue(); 5347 EVT LD1VT = LD1->getValueType(0); 5348 5349 if (ISD::isNON_EXTLoad(LD2) && 5350 LD2->hasOneUse() && 5351 // If both are volatile this would reduce the number of volatile loads. 5352 // If one is volatile it might be ok, but play conservative and bail out. 5353 !LD1->isVolatile() && 5354 !LD2->isVolatile() && 5355 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5356 unsigned Align = LD1->getAlignment(); 5357 unsigned NewAlign = TLI.getTargetData()-> 5358 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5359 5360 if (NewAlign <= Align && 5361 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5362 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5363 LD1->getBasePtr(), LD1->getPointerInfo(), 5364 false, false, false, Align); 5365 } 5366 5367 return SDValue(); 5368} 5369 5370SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5371 SDValue N0 = N->getOperand(0); 5372 EVT VT = N->getValueType(0); 5373 5374 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5375 // Only do this before legalize, since afterward the target may be depending 5376 // on the bitconvert. 5377 // First check to see if this is all constant. 5378 if (!LegalTypes && 5379 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5380 VT.isVector()) { 5381 bool isSimple = true; 5382 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5383 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5384 N0.getOperand(i).getOpcode() != ISD::Constant && 5385 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5386 isSimple = false; 5387 break; 5388 } 5389 5390 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5391 assert(!DestEltVT.isVector() && 5392 "Element type of vector ValueType must not be vector!"); 5393 if (isSimple) 5394 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5395 } 5396 5397 // If the input is a constant, let getNode fold it. 5398 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5399 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5400 if (Res.getNode() != N) { 5401 if (!LegalOperations || 5402 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5403 return Res; 5404 5405 // Folding it resulted in an illegal node, and it's too late to 5406 // do that. Clean up the old node and forego the transformation. 5407 // Ideally this won't happen very often, because instcombine 5408 // and the earlier dagcombine runs (where illegal nodes are 5409 // permitted) should have folded most of them already. 5410 DAG.DeleteNode(Res.getNode()); 5411 } 5412 } 5413 5414 // (conv (conv x, t1), t2) -> (conv x, t2) 5415 if (N0.getOpcode() == ISD::BITCAST) 5416 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5417 N0.getOperand(0)); 5418 5419 // fold (conv (load x)) -> (load (conv*)x) 5420 // If the resultant load doesn't need a higher alignment than the original! 5421 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5422 // Do not change the width of a volatile load. 5423 !cast<LoadSDNode>(N0)->isVolatile() && 5424 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5425 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5426 unsigned Align = TLI.getTargetData()-> 5427 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5428 unsigned OrigAlign = LN0->getAlignment(); 5429 5430 if (Align <= OrigAlign) { 5431 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5432 LN0->getBasePtr(), LN0->getPointerInfo(), 5433 LN0->isVolatile(), LN0->isNonTemporal(), 5434 LN0->isInvariant(), OrigAlign); 5435 AddToWorkList(N); 5436 CombineTo(N0.getNode(), 5437 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5438 N0.getValueType(), Load), 5439 Load.getValue(1)); 5440 return Load; 5441 } 5442 } 5443 5444 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5445 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5446 // This often reduces constant pool loads. 5447 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5448 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5449 N0.getNode()->hasOneUse() && VT.isInteger() && 5450 !VT.isVector() && !N0.getValueType().isVector()) { 5451 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5452 N0.getOperand(0)); 5453 AddToWorkList(NewConv.getNode()); 5454 5455 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5456 if (N0.getOpcode() == ISD::FNEG) 5457 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5458 NewConv, DAG.getConstant(SignBit, VT)); 5459 assert(N0.getOpcode() == ISD::FABS); 5460 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5461 NewConv, DAG.getConstant(~SignBit, VT)); 5462 } 5463 5464 // fold (bitconvert (fcopysign cst, x)) -> 5465 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5466 // Note that we don't handle (copysign x, cst) because this can always be 5467 // folded to an fneg or fabs. 5468 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5469 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5470 VT.isInteger() && !VT.isVector()) { 5471 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5472 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5473 if (isTypeLegal(IntXVT)) { 5474 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5475 IntXVT, N0.getOperand(1)); 5476 AddToWorkList(X.getNode()); 5477 5478 // If X has a different width than the result/lhs, sext it or truncate it. 5479 unsigned VTWidth = VT.getSizeInBits(); 5480 if (OrigXWidth < VTWidth) { 5481 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5482 AddToWorkList(X.getNode()); 5483 } else if (OrigXWidth > VTWidth) { 5484 // To get the sign bit in the right place, we have to shift it right 5485 // before truncating. 5486 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5487 X.getValueType(), X, 5488 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5489 AddToWorkList(X.getNode()); 5490 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5491 AddToWorkList(X.getNode()); 5492 } 5493 5494 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5495 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5496 X, DAG.getConstant(SignBit, VT)); 5497 AddToWorkList(X.getNode()); 5498 5499 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5500 VT, N0.getOperand(0)); 5501 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5502 Cst, DAG.getConstant(~SignBit, VT)); 5503 AddToWorkList(Cst.getNode()); 5504 5505 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5506 } 5507 } 5508 5509 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5510 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5511 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5512 if (CombineLD.getNode()) 5513 return CombineLD; 5514 } 5515 5516 return SDValue(); 5517} 5518 5519SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5520 EVT VT = N->getValueType(0); 5521 return CombineConsecutiveLoads(N, VT); 5522} 5523 5524/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5525/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5526/// destination element value type. 5527SDValue DAGCombiner:: 5528ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5529 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5530 5531 // If this is already the right type, we're done. 5532 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5533 5534 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5535 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5536 5537 // If this is a conversion of N elements of one type to N elements of another 5538 // type, convert each element. This handles FP<->INT cases. 5539 if (SrcBitSize == DstBitSize) { 5540 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5541 BV->getValueType(0).getVectorNumElements()); 5542 5543 // Due to the FP element handling below calling this routine recursively, 5544 // we can end up with a scalar-to-vector node here. 5545 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5546 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5547 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5548 DstEltVT, BV->getOperand(0))); 5549 5550 SmallVector<SDValue, 8> Ops; 5551 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5552 SDValue Op = BV->getOperand(i); 5553 // If the vector element type is not legal, the BUILD_VECTOR operands 5554 // are promoted and implicitly truncated. Make that explicit here. 5555 if (Op.getValueType() != SrcEltVT) 5556 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5557 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5558 DstEltVT, Op)); 5559 AddToWorkList(Ops.back().getNode()); 5560 } 5561 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5562 &Ops[0], Ops.size()); 5563 } 5564 5565 // Otherwise, we're growing or shrinking the elements. To avoid having to 5566 // handle annoying details of growing/shrinking FP values, we convert them to 5567 // int first. 5568 if (SrcEltVT.isFloatingPoint()) { 5569 // Convert the input float vector to a int vector where the elements are the 5570 // same sizes. 5571 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5572 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5573 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5574 SrcEltVT = IntVT; 5575 } 5576 5577 // Now we know the input is an integer vector. If the output is a FP type, 5578 // convert to integer first, then to FP of the right size. 5579 if (DstEltVT.isFloatingPoint()) { 5580 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5581 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5582 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5583 5584 // Next, convert to FP elements of the same size. 5585 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5586 } 5587 5588 // Okay, we know the src/dst types are both integers of differing types. 5589 // Handling growing first. 5590 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5591 if (SrcBitSize < DstBitSize) { 5592 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5593 5594 SmallVector<SDValue, 8> Ops; 5595 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5596 i += NumInputsPerOutput) { 5597 bool isLE = TLI.isLittleEndian(); 5598 APInt NewBits = APInt(DstBitSize, 0); 5599 bool EltIsUndef = true; 5600 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5601 // Shift the previously computed bits over. 5602 NewBits <<= SrcBitSize; 5603 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5604 if (Op.getOpcode() == ISD::UNDEF) continue; 5605 EltIsUndef = false; 5606 5607 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5608 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5609 } 5610 5611 if (EltIsUndef) 5612 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5613 else 5614 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5615 } 5616 5617 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5618 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5619 &Ops[0], Ops.size()); 5620 } 5621 5622 // Finally, this must be the case where we are shrinking elements: each input 5623 // turns into multiple outputs. 5624 bool isS2V = ISD::isScalarToVector(BV); 5625 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5626 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5627 NumOutputsPerInput*BV->getNumOperands()); 5628 SmallVector<SDValue, 8> Ops; 5629 5630 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5631 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5632 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5633 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5634 continue; 5635 } 5636 5637 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5638 getAPIntValue().zextOrTrunc(SrcBitSize); 5639 5640 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5641 APInt ThisVal = OpVal.trunc(DstBitSize); 5642 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5643 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5644 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5645 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5646 Ops[0]); 5647 OpVal = OpVal.lshr(DstBitSize); 5648 } 5649 5650 // For big endian targets, swap the order of the pieces of each element. 5651 if (TLI.isBigEndian()) 5652 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5653 } 5654 5655 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5656 &Ops[0], Ops.size()); 5657} 5658 5659SDValue DAGCombiner::visitFADD(SDNode *N) { 5660 SDValue N0 = N->getOperand(0); 5661 SDValue N1 = N->getOperand(1); 5662 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5663 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5664 EVT VT = N->getValueType(0); 5665 5666 // fold vector ops 5667 if (VT.isVector()) { 5668 SDValue FoldedVOp = SimplifyVBinOp(N); 5669 if (FoldedVOp.getNode()) return FoldedVOp; 5670 } 5671 5672 // fold (fadd c1, c2) -> c1 + c2 5673 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5674 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5675 // canonicalize constant to RHS 5676 if (N0CFP && !N1CFP) 5677 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5678 // fold (fadd A, 0) -> A 5679 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5680 N1CFP->getValueAPF().isZero()) 5681 return N0; 5682 // fold (fadd A, (fneg B)) -> (fsub A, B) 5683 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5684 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5685 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5686 GetNegatedExpression(N1, DAG, LegalOperations)); 5687 // fold (fadd (fneg A), B) -> (fsub B, A) 5688 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5689 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5690 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5691 GetNegatedExpression(N0, DAG, LegalOperations)); 5692 5693 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5694 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5695 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5696 isa<ConstantFPSDNode>(N0.getOperand(1))) 5697 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5698 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5699 N0.getOperand(1), N1)); 5700 5701 // In unsafe math mode, we can fold chains of FADD's of the same value 5702 // into multiplications. This transform is not safe in general because 5703 // we are reducing the number of rounding steps. 5704 if (DAG.getTarget().Options.UnsafeFPMath && 5705 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5706 !N0CFP && !N1CFP) { 5707 if (N0.getOpcode() == ISD::FMUL) { 5708 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5709 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 5710 5711 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5712 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 5713 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5714 SDValue(CFP00, 0), 5715 DAG.getConstantFP(1.0, VT)); 5716 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5717 N1, NewCFP); 5718 } 5719 5720 // (fadd (fmul x, c), x) -> (fmul c+1, x) 5721 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 5722 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5723 SDValue(CFP01, 0), 5724 DAG.getConstantFP(1.0, VT)); 5725 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5726 N1, NewCFP); 5727 } 5728 5729 // (fadd (fadd x, x), x) -> (fmul 3.0, x) 5730 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) && 5731 N0.getOperand(0) == N1) { 5732 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5733 N1, DAG.getConstantFP(3.0, VT)); 5734 } 5735 5736 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x) 5737 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 5738 N1.getOperand(0) == N1.getOperand(1) && 5739 N0.getOperand(1) == N1.getOperand(0)) { 5740 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5741 SDValue(CFP00, 0), 5742 DAG.getConstantFP(2.0, VT)); 5743 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5744 N0.getOperand(1), NewCFP); 5745 } 5746 5747 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x) 5748 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 5749 N1.getOperand(0) == N1.getOperand(1) && 5750 N0.getOperand(0) == N1.getOperand(0)) { 5751 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5752 SDValue(CFP01, 0), 5753 DAG.getConstantFP(2.0, VT)); 5754 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5755 N0.getOperand(0), NewCFP); 5756 } 5757 } 5758 5759 if (N1.getOpcode() == ISD::FMUL) { 5760 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5761 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 5762 5763 // (fadd x, (fmul c, x)) -> (fmul c+1, x) 5764 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 5765 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5766 SDValue(CFP10, 0), 5767 DAG.getConstantFP(1.0, VT)); 5768 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5769 N0, NewCFP); 5770 } 5771 5772 // (fadd x, (fmul x, c)) -> (fmul c+1, x) 5773 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 5774 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5775 SDValue(CFP11, 0), 5776 DAG.getConstantFP(1.0, VT)); 5777 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5778 N0, NewCFP); 5779 } 5780 5781 // (fadd x, (fadd x, x)) -> (fmul 3.0, x) 5782 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) && 5783 N1.getOperand(0) == N0) { 5784 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5785 N0, DAG.getConstantFP(3.0, VT)); 5786 } 5787 5788 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x) 5789 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD && 5790 N1.getOperand(0) == N1.getOperand(1) && 5791 N0.getOperand(1) == N1.getOperand(0)) { 5792 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5793 SDValue(CFP10, 0), 5794 DAG.getConstantFP(2.0, VT)); 5795 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5796 N0.getOperand(1), NewCFP); 5797 } 5798 5799 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x) 5800 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD && 5801 N1.getOperand(0) == N1.getOperand(1) && 5802 N0.getOperand(0) == N1.getOperand(0)) { 5803 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5804 SDValue(CFP11, 0), 5805 DAG.getConstantFP(2.0, VT)); 5806 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5807 N0.getOperand(0), NewCFP); 5808 } 5809 } 5810 5811 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x) 5812 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 5813 N0.getOperand(0) == N0.getOperand(1) && 5814 N1.getOperand(0) == N1.getOperand(1) && 5815 N0.getOperand(0) == N1.getOperand(0)) { 5816 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5817 N0.getOperand(0), 5818 DAG.getConstantFP(4.0, VT)); 5819 } 5820 } 5821 5822 // FADD -> FMA combines: 5823 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5824 DAG.getTarget().Options.UnsafeFPMath) && 5825 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5826 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5827 5828 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 5829 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5830 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5831 N0.getOperand(0), N0.getOperand(1), N1); 5832 } 5833 5834 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 5835 // Note: Commutes FADD operands. 5836 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5837 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5838 N1.getOperand(0), N1.getOperand(1), N0); 5839 } 5840 } 5841 5842 return SDValue(); 5843} 5844 5845SDValue DAGCombiner::visitFSUB(SDNode *N) { 5846 SDValue N0 = N->getOperand(0); 5847 SDValue N1 = N->getOperand(1); 5848 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5849 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5850 EVT VT = N->getValueType(0); 5851 DebugLoc dl = N->getDebugLoc(); 5852 5853 // fold vector ops 5854 if (VT.isVector()) { 5855 SDValue FoldedVOp = SimplifyVBinOp(N); 5856 if (FoldedVOp.getNode()) return FoldedVOp; 5857 } 5858 5859 // fold (fsub c1, c2) -> c1-c2 5860 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5861 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5862 // fold (fsub A, 0) -> A 5863 if (DAG.getTarget().Options.UnsafeFPMath && 5864 N1CFP && N1CFP->getValueAPF().isZero()) 5865 return N0; 5866 // fold (fsub 0, B) -> -B 5867 if (DAG.getTarget().Options.UnsafeFPMath && 5868 N0CFP && N0CFP->getValueAPF().isZero()) { 5869 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5870 return GetNegatedExpression(N1, DAG, LegalOperations); 5871 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5872 return DAG.getNode(ISD::FNEG, dl, VT, N1); 5873 } 5874 // fold (fsub A, (fneg B)) -> (fadd A, B) 5875 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5876 return DAG.getNode(ISD::FADD, dl, VT, N0, 5877 GetNegatedExpression(N1, DAG, LegalOperations)); 5878 5879 // If 'unsafe math' is enabled, fold 5880 // (fsub x, x) -> 0.0 & 5881 // (fsub x, (fadd x, y)) -> (fneg y) & 5882 // (fsub x, (fadd y, x)) -> (fneg y) 5883 if (DAG.getTarget().Options.UnsafeFPMath) { 5884 if (N0 == N1) 5885 return DAG.getConstantFP(0.0f, VT); 5886 5887 if (N1.getOpcode() == ISD::FADD) { 5888 SDValue N10 = N1->getOperand(0); 5889 SDValue N11 = N1->getOperand(1); 5890 5891 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5892 &DAG.getTarget().Options)) 5893 return GetNegatedExpression(N11, DAG, LegalOperations); 5894 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5895 &DAG.getTarget().Options)) 5896 return GetNegatedExpression(N10, DAG, LegalOperations); 5897 } 5898 } 5899 5900 // FSUB -> FMA combines: 5901 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5902 DAG.getTarget().Options.UnsafeFPMath) && 5903 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5904 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5905 5906 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 5907 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5908 return DAG.getNode(ISD::FMA, dl, VT, 5909 N0.getOperand(0), N0.getOperand(1), 5910 DAG.getNode(ISD::FNEG, dl, VT, N1)); 5911 } 5912 5913 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 5914 // Note: Commutes FSUB operands. 5915 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5916 return DAG.getNode(ISD::FMA, dl, VT, 5917 DAG.getNode(ISD::FNEG, dl, VT, 5918 N1.getOperand(0)), 5919 N1.getOperand(1), N0); 5920 } 5921 5922 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 5923 if (N0.getOpcode() == ISD::FNEG && 5924 N0.getOperand(0).getOpcode() == ISD::FMUL && 5925 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 5926 SDValue N00 = N0.getOperand(0).getOperand(0); 5927 SDValue N01 = N0.getOperand(0).getOperand(1); 5928 return DAG.getNode(ISD::FMA, dl, VT, 5929 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 5930 DAG.getNode(ISD::FNEG, dl, VT, N1)); 5931 } 5932 } 5933 5934 return SDValue(); 5935} 5936 5937SDValue DAGCombiner::visitFMUL(SDNode *N) { 5938 SDValue N0 = N->getOperand(0); 5939 SDValue N1 = N->getOperand(1); 5940 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5941 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5942 EVT VT = N->getValueType(0); 5943 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5944 5945 // fold vector ops 5946 if (VT.isVector()) { 5947 SDValue FoldedVOp = SimplifyVBinOp(N); 5948 if (FoldedVOp.getNode()) return FoldedVOp; 5949 } 5950 5951 // fold (fmul c1, c2) -> c1*c2 5952 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5953 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5954 // canonicalize constant to RHS 5955 if (N0CFP && !N1CFP) 5956 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5957 // fold (fmul A, 0) -> 0 5958 if (DAG.getTarget().Options.UnsafeFPMath && 5959 N1CFP && N1CFP->getValueAPF().isZero()) 5960 return N1; 5961 // fold (fmul A, 0) -> 0, vector edition. 5962 if (DAG.getTarget().Options.UnsafeFPMath && 5963 ISD::isBuildVectorAllZeros(N1.getNode())) 5964 return N1; 5965 // fold (fmul A, 1.0) -> A 5966 if (N1CFP && N1CFP->isExactlyValue(1.0)) 5967 return N0; 5968 // fold (fmul X, 2.0) -> (fadd X, X) 5969 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5970 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5971 // fold (fmul X, -1.0) -> (fneg X) 5972 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5973 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5974 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5975 5976 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5977 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5978 &DAG.getTarget().Options)) { 5979 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5980 &DAG.getTarget().Options)) { 5981 // Both can be negated for free, check to see if at least one is cheaper 5982 // negated. 5983 if (LHSNeg == 2 || RHSNeg == 2) 5984 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5985 GetNegatedExpression(N0, DAG, LegalOperations), 5986 GetNegatedExpression(N1, DAG, LegalOperations)); 5987 } 5988 } 5989 5990 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5991 if (DAG.getTarget().Options.UnsafeFPMath && 5992 N1CFP && N0.getOpcode() == ISD::FMUL && 5993 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5994 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5995 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5996 N0.getOperand(1), N1)); 5997 5998 return SDValue(); 5999} 6000 6001SDValue DAGCombiner::visitFMA(SDNode *N) { 6002 SDValue N0 = N->getOperand(0); 6003 SDValue N1 = N->getOperand(1); 6004 SDValue N2 = N->getOperand(2); 6005 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6006 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6007 EVT VT = N->getValueType(0); 6008 DebugLoc dl = N->getDebugLoc(); 6009 6010 if (N0CFP && N0CFP->isExactlyValue(1.0)) 6011 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); 6012 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6013 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); 6014 6015 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6016 if (N0CFP && !N1CFP) 6017 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); 6018 6019 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6020 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6021 N2.getOpcode() == ISD::FMUL && 6022 N0 == N2.getOperand(0) && 6023 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6024 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6025 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6026 } 6027 6028 6029 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6030 if (DAG.getTarget().Options.UnsafeFPMath && 6031 N0.getOpcode() == ISD::FMUL && N1CFP && 6032 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6033 return DAG.getNode(ISD::FMA, dl, VT, 6034 N0.getOperand(0), 6035 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6036 N2); 6037 } 6038 6039 // (fma x, 1, y) -> (fadd x, y) 6040 // (fma x, -1, y) -> (fadd (fneg x), y) 6041 if (N1CFP) { 6042 if (N1CFP->isExactlyValue(1.0)) 6043 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6044 6045 if (N1CFP->isExactlyValue(-1.0) && 6046 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6047 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6048 AddToWorkList(RHSNeg.getNode()); 6049 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6050 } 6051 } 6052 6053 // (fma x, c, x) -> (fmul x, (c+1)) 6054 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) { 6055 return DAG.getNode(ISD::FMUL, dl, VT, 6056 N0, 6057 DAG.getNode(ISD::FADD, dl, VT, 6058 N1, DAG.getConstantFP(1.0, VT))); 6059 } 6060 6061 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6062 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6063 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { 6064 return DAG.getNode(ISD::FMUL, dl, VT, 6065 N0, 6066 DAG.getNode(ISD::FADD, dl, VT, 6067 N1, DAG.getConstantFP(-1.0, VT))); 6068 } 6069 6070 6071 return SDValue(); 6072} 6073 6074SDValue DAGCombiner::visitFDIV(SDNode *N) { 6075 SDValue N0 = N->getOperand(0); 6076 SDValue N1 = N->getOperand(1); 6077 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6078 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6079 EVT VT = N->getValueType(0); 6080 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6081 6082 // fold vector ops 6083 if (VT.isVector()) { 6084 SDValue FoldedVOp = SimplifyVBinOp(N); 6085 if (FoldedVOp.getNode()) return FoldedVOp; 6086 } 6087 6088 // fold (fdiv c1, c2) -> c1/c2 6089 if (N0CFP && N1CFP && VT != MVT::ppcf128) 6090 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 6091 6092 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6093 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) { 6094 // Compute the reciprocal 1.0 / c2. 6095 APFloat N1APF = N1CFP->getValueAPF(); 6096 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6097 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6098 // Only do the transform if the reciprocal is a legal fp immediate that 6099 // isn't too nasty (eg NaN, denormal, ...). 6100 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6101 (!LegalOperations || 6102 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6103 // backend)... we should handle this gracefully after Legalize. 6104 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6105 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6106 TLI.isFPImmLegal(Recip, VT))) 6107 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 6108 DAG.getConstantFP(Recip, VT)); 6109 } 6110 6111 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6112 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6113 &DAG.getTarget().Options)) { 6114 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6115 &DAG.getTarget().Options)) { 6116 // Both can be negated for free, check to see if at least one is cheaper 6117 // negated. 6118 if (LHSNeg == 2 || RHSNeg == 2) 6119 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 6120 GetNegatedExpression(N0, DAG, LegalOperations), 6121 GetNegatedExpression(N1, DAG, LegalOperations)); 6122 } 6123 } 6124 6125 return SDValue(); 6126} 6127 6128SDValue DAGCombiner::visitFREM(SDNode *N) { 6129 SDValue N0 = N->getOperand(0); 6130 SDValue N1 = N->getOperand(1); 6131 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6132 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6133 EVT VT = N->getValueType(0); 6134 6135 // fold (frem c1, c2) -> fmod(c1,c2) 6136 if (N0CFP && N1CFP && VT != MVT::ppcf128) 6137 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 6138 6139 return SDValue(); 6140} 6141 6142SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6143 SDValue N0 = N->getOperand(0); 6144 SDValue N1 = N->getOperand(1); 6145 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6146 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6147 EVT VT = N->getValueType(0); 6148 6149 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 6150 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 6151 6152 if (N1CFP) { 6153 const APFloat& V = N1CFP->getValueAPF(); 6154 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6155 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6156 if (!V.isNegative()) { 6157 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6158 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6159 } else { 6160 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6161 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6162 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 6163 } 6164 } 6165 6166 // copysign(fabs(x), y) -> copysign(x, y) 6167 // copysign(fneg(x), y) -> copysign(x, y) 6168 // copysign(copysign(x,z), y) -> copysign(x, y) 6169 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6170 N0.getOpcode() == ISD::FCOPYSIGN) 6171 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6172 N0.getOperand(0), N1); 6173 6174 // copysign(x, abs(y)) -> abs(x) 6175 if (N1.getOpcode() == ISD::FABS) 6176 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6177 6178 // copysign(x, copysign(y,z)) -> copysign(x, z) 6179 if (N1.getOpcode() == ISD::FCOPYSIGN) 6180 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6181 N0, N1.getOperand(1)); 6182 6183 // copysign(x, fp_extend(y)) -> copysign(x, y) 6184 // copysign(x, fp_round(y)) -> copysign(x, y) 6185 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6186 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6187 N0, N1.getOperand(0)); 6188 6189 return SDValue(); 6190} 6191 6192SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6193 SDValue N0 = N->getOperand(0); 6194 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6195 EVT VT = N->getValueType(0); 6196 EVT OpVT = N0.getValueType(); 6197 6198 // fold (sint_to_fp c1) -> c1fp 6199 if (N0C && OpVT != MVT::ppcf128 && 6200 // ...but only if the target supports immediate floating-point values 6201 (!LegalOperations || 6202 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6203 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6204 6205 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6206 // but UINT_TO_FP is legal on this target, try to convert. 6207 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6208 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6209 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6210 if (DAG.SignBitIsZero(N0)) 6211 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6212 } 6213 6214 // The next optimizations are desireable only if SELECT_CC can be lowered. 6215 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6216 // having to say they don't support SELECT_CC on every type the DAG knows 6217 // about, since there is no way to mark an opcode illegal at all value types 6218 // (See also visitSELECT) 6219 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6220 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6221 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6222 !VT.isVector() && 6223 (!LegalOperations || 6224 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6225 SDValue Ops[] = 6226 { N0.getOperand(0), N0.getOperand(1), 6227 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6228 N0.getOperand(2) }; 6229 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6230 } 6231 6232 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6233 // (select_cc x, y, 1.0, 0.0,, cc) 6234 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6235 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6236 (!LegalOperations || 6237 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6238 SDValue Ops[] = 6239 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6240 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6241 N0.getOperand(0).getOperand(2) }; 6242 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6243 } 6244 } 6245 6246 return SDValue(); 6247} 6248 6249SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6250 SDValue N0 = N->getOperand(0); 6251 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6252 EVT VT = N->getValueType(0); 6253 EVT OpVT = N0.getValueType(); 6254 6255 // fold (uint_to_fp c1) -> c1fp 6256 if (N0C && OpVT != MVT::ppcf128 && 6257 // ...but only if the target supports immediate floating-point values 6258 (!LegalOperations || 6259 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6260 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6261 6262 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6263 // but SINT_TO_FP is legal on this target, try to convert. 6264 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6265 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6266 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6267 if (DAG.SignBitIsZero(N0)) 6268 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6269 } 6270 6271 // The next optimizations are desireable only if SELECT_CC can be lowered. 6272 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6273 // having to say they don't support SELECT_CC on every type the DAG knows 6274 // about, since there is no way to mark an opcode illegal at all value types 6275 // (See also visitSELECT) 6276 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6277 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6278 6279 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6280 (!LegalOperations || 6281 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6282 SDValue Ops[] = 6283 { N0.getOperand(0), N0.getOperand(1), 6284 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6285 N0.getOperand(2) }; 6286 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6287 } 6288 } 6289 6290 return SDValue(); 6291} 6292 6293SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6294 SDValue N0 = N->getOperand(0); 6295 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6296 EVT VT = N->getValueType(0); 6297 6298 // fold (fp_to_sint c1fp) -> c1 6299 if (N0CFP) 6300 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 6301 6302 return SDValue(); 6303} 6304 6305SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6306 SDValue N0 = N->getOperand(0); 6307 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6308 EVT VT = N->getValueType(0); 6309 6310 // fold (fp_to_uint c1fp) -> c1 6311 if (N0CFP && VT != MVT::ppcf128) 6312 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 6313 6314 return SDValue(); 6315} 6316 6317SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6318 SDValue N0 = N->getOperand(0); 6319 SDValue N1 = N->getOperand(1); 6320 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6321 EVT VT = N->getValueType(0); 6322 6323 // fold (fp_round c1fp) -> c1fp 6324 if (N0CFP && N0.getValueType() != MVT::ppcf128) 6325 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 6326 6327 // fold (fp_round (fp_extend x)) -> x 6328 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6329 return N0.getOperand(0); 6330 6331 // fold (fp_round (fp_round x)) -> (fp_round x) 6332 if (N0.getOpcode() == ISD::FP_ROUND) { 6333 // This is a value preserving truncation if both round's are. 6334 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6335 N0.getNode()->getConstantOperandVal(1) == 1; 6336 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 6337 DAG.getIntPtrConstant(IsTrunc)); 6338 } 6339 6340 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6341 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6342 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 6343 N0.getOperand(0), N1); 6344 AddToWorkList(Tmp.getNode()); 6345 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6346 Tmp, N0.getOperand(1)); 6347 } 6348 6349 return SDValue(); 6350} 6351 6352SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6353 SDValue N0 = N->getOperand(0); 6354 EVT VT = N->getValueType(0); 6355 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6356 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6357 6358 // fold (fp_round_inreg c1fp) -> c1fp 6359 if (N0CFP && isTypeLegal(EVT)) { 6360 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6361 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 6362 } 6363 6364 return SDValue(); 6365} 6366 6367SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6368 SDValue N0 = N->getOperand(0); 6369 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6370 EVT VT = N->getValueType(0); 6371 6372 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6373 if (N->hasOneUse() && 6374 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6375 return SDValue(); 6376 6377 // fold (fp_extend c1fp) -> c1fp 6378 if (N0CFP && VT != MVT::ppcf128) 6379 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6380 6381 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6382 // value of X. 6383 if (N0.getOpcode() == ISD::FP_ROUND 6384 && N0.getNode()->getConstantOperandVal(1) == 1) { 6385 SDValue In = N0.getOperand(0); 6386 if (In.getValueType() == VT) return In; 6387 if (VT.bitsLT(In.getValueType())) 6388 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6389 In, N0.getOperand(1)); 6390 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6391 } 6392 6393 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6394 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6395 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6396 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6397 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6398 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6399 LN0->getChain(), 6400 LN0->getBasePtr(), LN0->getPointerInfo(), 6401 N0.getValueType(), 6402 LN0->isVolatile(), LN0->isNonTemporal(), 6403 LN0->getAlignment()); 6404 CombineTo(N, ExtLoad); 6405 CombineTo(N0.getNode(), 6406 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6407 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6408 ExtLoad.getValue(1)); 6409 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6410 } 6411 6412 return SDValue(); 6413} 6414 6415SDValue DAGCombiner::visitFNEG(SDNode *N) { 6416 SDValue N0 = N->getOperand(0); 6417 EVT VT = N->getValueType(0); 6418 6419 if (VT.isVector()) { 6420 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6421 if (FoldedVOp.getNode()) return FoldedVOp; 6422 } 6423 6424 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6425 &DAG.getTarget().Options)) 6426 return GetNegatedExpression(N0, DAG, LegalOperations); 6427 6428 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6429 // constant pool values. 6430 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6431 !VT.isVector() && 6432 N0.getNode()->hasOneUse() && 6433 N0.getOperand(0).getValueType().isInteger()) { 6434 SDValue Int = N0.getOperand(0); 6435 EVT IntVT = Int.getValueType(); 6436 if (IntVT.isInteger() && !IntVT.isVector()) { 6437 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6438 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6439 AddToWorkList(Int.getNode()); 6440 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6441 VT, Int); 6442 } 6443 } 6444 6445 // (fneg (fmul c, x)) -> (fmul -c, x) 6446 if (N0.getOpcode() == ISD::FMUL) { 6447 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6448 if (CFP1) { 6449 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6450 N0.getOperand(0), 6451 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6452 N0.getOperand(1))); 6453 } 6454 } 6455 6456 return SDValue(); 6457} 6458 6459SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6460 SDValue N0 = N->getOperand(0); 6461 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6462 EVT VT = N->getValueType(0); 6463 6464 // fold (fceil c1) -> fceil(c1) 6465 if (N0CFP && VT != MVT::ppcf128) 6466 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0); 6467 6468 return SDValue(); 6469} 6470 6471SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6472 SDValue N0 = N->getOperand(0); 6473 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6474 EVT VT = N->getValueType(0); 6475 6476 // fold (ftrunc c1) -> ftrunc(c1) 6477 if (N0CFP && VT != MVT::ppcf128) 6478 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0); 6479 6480 return SDValue(); 6481} 6482 6483SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6484 SDValue N0 = N->getOperand(0); 6485 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6486 EVT VT = N->getValueType(0); 6487 6488 // fold (ffloor c1) -> ffloor(c1) 6489 if (N0CFP && VT != MVT::ppcf128) 6490 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0); 6491 6492 return SDValue(); 6493} 6494 6495SDValue DAGCombiner::visitFABS(SDNode *N) { 6496 SDValue N0 = N->getOperand(0); 6497 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6498 EVT VT = N->getValueType(0); 6499 6500 if (VT.isVector()) { 6501 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6502 if (FoldedVOp.getNode()) return FoldedVOp; 6503 } 6504 6505 // fold (fabs c1) -> fabs(c1) 6506 if (N0CFP && VT != MVT::ppcf128) 6507 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6508 // fold (fabs (fabs x)) -> (fabs x) 6509 if (N0.getOpcode() == ISD::FABS) 6510 return N->getOperand(0); 6511 // fold (fabs (fneg x)) -> (fabs x) 6512 // fold (fabs (fcopysign x, y)) -> (fabs x) 6513 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6514 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6515 6516 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6517 // constant pool values. 6518 if (!TLI.isFAbsFree(VT) && 6519 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6520 N0.getOperand(0).getValueType().isInteger() && 6521 !N0.getOperand(0).getValueType().isVector()) { 6522 SDValue Int = N0.getOperand(0); 6523 EVT IntVT = Int.getValueType(); 6524 if (IntVT.isInteger() && !IntVT.isVector()) { 6525 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6526 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6527 AddToWorkList(Int.getNode()); 6528 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6529 N->getValueType(0), Int); 6530 } 6531 } 6532 6533 return SDValue(); 6534} 6535 6536SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6537 SDValue Chain = N->getOperand(0); 6538 SDValue N1 = N->getOperand(1); 6539 SDValue N2 = N->getOperand(2); 6540 6541 // If N is a constant we could fold this into a fallthrough or unconditional 6542 // branch. However that doesn't happen very often in normal code, because 6543 // Instcombine/SimplifyCFG should have handled the available opportunities. 6544 // If we did this folding here, it would be necessary to update the 6545 // MachineBasicBlock CFG, which is awkward. 6546 6547 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6548 // on the target. 6549 if (N1.getOpcode() == ISD::SETCC && 6550 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6551 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6552 Chain, N1.getOperand(2), 6553 N1.getOperand(0), N1.getOperand(1), N2); 6554 } 6555 6556 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6557 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6558 (N1.getOperand(0).hasOneUse() && 6559 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6560 SDNode *Trunc = 0; 6561 if (N1.getOpcode() == ISD::TRUNCATE) { 6562 // Look pass the truncate. 6563 Trunc = N1.getNode(); 6564 N1 = N1.getOperand(0); 6565 } 6566 6567 // Match this pattern so that we can generate simpler code: 6568 // 6569 // %a = ... 6570 // %b = and i32 %a, 2 6571 // %c = srl i32 %b, 1 6572 // brcond i32 %c ... 6573 // 6574 // into 6575 // 6576 // %a = ... 6577 // %b = and i32 %a, 2 6578 // %c = setcc eq %b, 0 6579 // brcond %c ... 6580 // 6581 // This applies only when the AND constant value has one bit set and the 6582 // SRL constant is equal to the log2 of the AND constant. The back-end is 6583 // smart enough to convert the result into a TEST/JMP sequence. 6584 SDValue Op0 = N1.getOperand(0); 6585 SDValue Op1 = N1.getOperand(1); 6586 6587 if (Op0.getOpcode() == ISD::AND && 6588 Op1.getOpcode() == ISD::Constant) { 6589 SDValue AndOp1 = Op0.getOperand(1); 6590 6591 if (AndOp1.getOpcode() == ISD::Constant) { 6592 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6593 6594 if (AndConst.isPowerOf2() && 6595 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6596 SDValue SetCC = 6597 DAG.getSetCC(N->getDebugLoc(), 6598 TLI.getSetCCResultType(Op0.getValueType()), 6599 Op0, DAG.getConstant(0, Op0.getValueType()), 6600 ISD::SETNE); 6601 6602 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6603 MVT::Other, Chain, SetCC, N2); 6604 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6605 // will convert it back to (X & C1) >> C2. 6606 CombineTo(N, NewBRCond, false); 6607 // Truncate is dead. 6608 if (Trunc) { 6609 removeFromWorkList(Trunc); 6610 DAG.DeleteNode(Trunc); 6611 } 6612 // Replace the uses of SRL with SETCC 6613 WorkListRemover DeadNodes(*this); 6614 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6615 removeFromWorkList(N1.getNode()); 6616 DAG.DeleteNode(N1.getNode()); 6617 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6618 } 6619 } 6620 } 6621 6622 if (Trunc) 6623 // Restore N1 if the above transformation doesn't match. 6624 N1 = N->getOperand(1); 6625 } 6626 6627 // Transform br(xor(x, y)) -> br(x != y) 6628 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6629 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6630 SDNode *TheXor = N1.getNode(); 6631 SDValue Op0 = TheXor->getOperand(0); 6632 SDValue Op1 = TheXor->getOperand(1); 6633 if (Op0.getOpcode() == Op1.getOpcode()) { 6634 // Avoid missing important xor optimizations. 6635 SDValue Tmp = visitXOR(TheXor); 6636 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6637 DEBUG(dbgs() << "\nReplacing.8 "; 6638 TheXor->dump(&DAG); 6639 dbgs() << "\nWith: "; 6640 Tmp.getNode()->dump(&DAG); 6641 dbgs() << '\n'); 6642 WorkListRemover DeadNodes(*this); 6643 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6644 removeFromWorkList(TheXor); 6645 DAG.DeleteNode(TheXor); 6646 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6647 MVT::Other, Chain, Tmp, N2); 6648 } 6649 } 6650 6651 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6652 bool Equal = false; 6653 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6654 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6655 Op0.getOpcode() == ISD::XOR) { 6656 TheXor = Op0.getNode(); 6657 Equal = true; 6658 } 6659 6660 EVT SetCCVT = N1.getValueType(); 6661 if (LegalTypes) 6662 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6663 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6664 SetCCVT, 6665 Op0, Op1, 6666 Equal ? ISD::SETEQ : ISD::SETNE); 6667 // Replace the uses of XOR with SETCC 6668 WorkListRemover DeadNodes(*this); 6669 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6670 removeFromWorkList(N1.getNode()); 6671 DAG.DeleteNode(N1.getNode()); 6672 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6673 MVT::Other, Chain, SetCC, N2); 6674 } 6675 } 6676 6677 return SDValue(); 6678} 6679 6680// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6681// 6682SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6683 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6684 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6685 6686 // If N is a constant we could fold this into a fallthrough or unconditional 6687 // branch. However that doesn't happen very often in normal code, because 6688 // Instcombine/SimplifyCFG should have handled the available opportunities. 6689 // If we did this folding here, it would be necessary to update the 6690 // MachineBasicBlock CFG, which is awkward. 6691 6692 // Use SimplifySetCC to simplify SETCC's. 6693 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6694 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6695 false); 6696 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6697 6698 // fold to a simpler setcc 6699 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6700 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6701 N->getOperand(0), Simp.getOperand(2), 6702 Simp.getOperand(0), Simp.getOperand(1), 6703 N->getOperand(4)); 6704 6705 return SDValue(); 6706} 6707 6708/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6709/// uses N as its base pointer and that N may be folded in the load / store 6710/// addressing mode. 6711static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6712 SelectionDAG &DAG, 6713 const TargetLowering &TLI) { 6714 EVT VT; 6715 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6716 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6717 return false; 6718 VT = Use->getValueType(0); 6719 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6720 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6721 return false; 6722 VT = ST->getValue().getValueType(); 6723 } else 6724 return false; 6725 6726 TargetLowering::AddrMode AM; 6727 if (N->getOpcode() == ISD::ADD) { 6728 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6729 if (Offset) 6730 // [reg +/- imm] 6731 AM.BaseOffs = Offset->getSExtValue(); 6732 else 6733 // [reg +/- reg] 6734 AM.Scale = 1; 6735 } else if (N->getOpcode() == ISD::SUB) { 6736 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6737 if (Offset) 6738 // [reg +/- imm] 6739 AM.BaseOffs = -Offset->getSExtValue(); 6740 else 6741 // [reg +/- reg] 6742 AM.Scale = 1; 6743 } else 6744 return false; 6745 6746 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6747} 6748 6749/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6750/// pre-indexed load / store when the base pointer is an add or subtract 6751/// and it has other uses besides the load / store. After the 6752/// transformation, the new indexed load / store has effectively folded 6753/// the add / subtract in and all of its other uses are redirected to the 6754/// new load / store. 6755bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6756 if (Level < AfterLegalizeDAG) 6757 return false; 6758 6759 bool isLoad = true; 6760 SDValue Ptr; 6761 EVT VT; 6762 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6763 if (LD->isIndexed()) 6764 return false; 6765 VT = LD->getMemoryVT(); 6766 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6767 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6768 return false; 6769 Ptr = LD->getBasePtr(); 6770 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6771 if (ST->isIndexed()) 6772 return false; 6773 VT = ST->getMemoryVT(); 6774 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6775 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6776 return false; 6777 Ptr = ST->getBasePtr(); 6778 isLoad = false; 6779 } else { 6780 return false; 6781 } 6782 6783 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6784 // out. There is no reason to make this a preinc/predec. 6785 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6786 Ptr.getNode()->hasOneUse()) 6787 return false; 6788 6789 // Ask the target to do addressing mode selection. 6790 SDValue BasePtr; 6791 SDValue Offset; 6792 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6793 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6794 return false; 6795 // Don't create a indexed load / store with zero offset. 6796 if (isa<ConstantSDNode>(Offset) && 6797 cast<ConstantSDNode>(Offset)->isNullValue()) 6798 return false; 6799 6800 // Try turning it into a pre-indexed load / store except when: 6801 // 1) The new base ptr is a frame index. 6802 // 2) If N is a store and the new base ptr is either the same as or is a 6803 // predecessor of the value being stored. 6804 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6805 // that would create a cycle. 6806 // 4) All uses are load / store ops that use it as old base ptr. 6807 6808 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6809 // (plus the implicit offset) to a register to preinc anyway. 6810 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6811 return false; 6812 6813 // Check #2. 6814 if (!isLoad) { 6815 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6816 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6817 return false; 6818 } 6819 6820 // Now check for #3 and #4. 6821 bool RealUse = false; 6822 6823 // Caches for hasPredecessorHelper 6824 SmallPtrSet<const SDNode *, 32> Visited; 6825 SmallVector<const SDNode *, 16> Worklist; 6826 6827 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6828 E = Ptr.getNode()->use_end(); I != E; ++I) { 6829 SDNode *Use = *I; 6830 if (Use == N) 6831 continue; 6832 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6833 return false; 6834 6835 // If Ptr may be folded in addressing mode of other use, then it's 6836 // not profitable to do this transformation. 6837 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6838 RealUse = true; 6839 } 6840 6841 if (!RealUse) 6842 return false; 6843 6844 SDValue Result; 6845 if (isLoad) 6846 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6847 BasePtr, Offset, AM); 6848 else 6849 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6850 BasePtr, Offset, AM); 6851 ++PreIndexedNodes; 6852 ++NodesCombined; 6853 DEBUG(dbgs() << "\nReplacing.4 "; 6854 N->dump(&DAG); 6855 dbgs() << "\nWith: "; 6856 Result.getNode()->dump(&DAG); 6857 dbgs() << '\n'); 6858 WorkListRemover DeadNodes(*this); 6859 if (isLoad) { 6860 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6861 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6862 } else { 6863 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6864 } 6865 6866 // Finally, since the node is now dead, remove it from the graph. 6867 DAG.DeleteNode(N); 6868 6869 // Replace the uses of Ptr with uses of the updated base value. 6870 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 6871 removeFromWorkList(Ptr.getNode()); 6872 DAG.DeleteNode(Ptr.getNode()); 6873 6874 return true; 6875} 6876 6877/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6878/// add / sub of the base pointer node into a post-indexed load / store. 6879/// The transformation folded the add / subtract into the new indexed 6880/// load / store effectively and all of its uses are redirected to the 6881/// new load / store. 6882bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6883 if (Level < AfterLegalizeDAG) 6884 return false; 6885 6886 bool isLoad = true; 6887 SDValue Ptr; 6888 EVT VT; 6889 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6890 if (LD->isIndexed()) 6891 return false; 6892 VT = LD->getMemoryVT(); 6893 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6894 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6895 return false; 6896 Ptr = LD->getBasePtr(); 6897 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6898 if (ST->isIndexed()) 6899 return false; 6900 VT = ST->getMemoryVT(); 6901 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6902 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6903 return false; 6904 Ptr = ST->getBasePtr(); 6905 isLoad = false; 6906 } else { 6907 return false; 6908 } 6909 6910 if (Ptr.getNode()->hasOneUse()) 6911 return false; 6912 6913 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6914 E = Ptr.getNode()->use_end(); I != E; ++I) { 6915 SDNode *Op = *I; 6916 if (Op == N || 6917 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6918 continue; 6919 6920 SDValue BasePtr; 6921 SDValue Offset; 6922 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6923 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6924 // Don't create a indexed load / store with zero offset. 6925 if (isa<ConstantSDNode>(Offset) && 6926 cast<ConstantSDNode>(Offset)->isNullValue()) 6927 continue; 6928 6929 // Try turning it into a post-indexed load / store except when 6930 // 1) All uses are load / store ops that use it as base ptr (and 6931 // it may be folded as addressing mmode). 6932 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6933 // nor a successor of N. Otherwise, if Op is folded that would 6934 // create a cycle. 6935 6936 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6937 continue; 6938 6939 // Check for #1. 6940 bool TryNext = false; 6941 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6942 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6943 SDNode *Use = *II; 6944 if (Use == Ptr.getNode()) 6945 continue; 6946 6947 // If all the uses are load / store addresses, then don't do the 6948 // transformation. 6949 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6950 bool RealUse = false; 6951 for (SDNode::use_iterator III = Use->use_begin(), 6952 EEE = Use->use_end(); III != EEE; ++III) { 6953 SDNode *UseUse = *III; 6954 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6955 RealUse = true; 6956 } 6957 6958 if (!RealUse) { 6959 TryNext = true; 6960 break; 6961 } 6962 } 6963 } 6964 6965 if (TryNext) 6966 continue; 6967 6968 // Check for #2 6969 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6970 SDValue Result = isLoad 6971 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6972 BasePtr, Offset, AM) 6973 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6974 BasePtr, Offset, AM); 6975 ++PostIndexedNodes; 6976 ++NodesCombined; 6977 DEBUG(dbgs() << "\nReplacing.5 "; 6978 N->dump(&DAG); 6979 dbgs() << "\nWith: "; 6980 Result.getNode()->dump(&DAG); 6981 dbgs() << '\n'); 6982 WorkListRemover DeadNodes(*this); 6983 if (isLoad) { 6984 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6985 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6986 } else { 6987 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6988 } 6989 6990 // Finally, since the node is now dead, remove it from the graph. 6991 DAG.DeleteNode(N); 6992 6993 // Replace the uses of Use with uses of the updated base value. 6994 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6995 Result.getValue(isLoad ? 1 : 0)); 6996 removeFromWorkList(Op); 6997 DAG.DeleteNode(Op); 6998 return true; 6999 } 7000 } 7001 } 7002 7003 return false; 7004} 7005 7006SDValue DAGCombiner::visitLOAD(SDNode *N) { 7007 LoadSDNode *LD = cast<LoadSDNode>(N); 7008 SDValue Chain = LD->getChain(); 7009 SDValue Ptr = LD->getBasePtr(); 7010 7011 // If load is not volatile and there are no uses of the loaded value (and 7012 // the updated indexed value in case of indexed loads), change uses of the 7013 // chain value into uses of the chain input (i.e. delete the dead load). 7014 if (!LD->isVolatile()) { 7015 if (N->getValueType(1) == MVT::Other) { 7016 // Unindexed loads. 7017 if (!N->hasAnyUseOfValue(0)) { 7018 // It's not safe to use the two value CombineTo variant here. e.g. 7019 // v1, chain2 = load chain1, loc 7020 // v2, chain3 = load chain2, loc 7021 // v3 = add v2, c 7022 // Now we replace use of chain2 with chain1. This makes the second load 7023 // isomorphic to the one we are deleting, and thus makes this load live. 7024 DEBUG(dbgs() << "\nReplacing.6 "; 7025 N->dump(&DAG); 7026 dbgs() << "\nWith chain: "; 7027 Chain.getNode()->dump(&DAG); 7028 dbgs() << "\n"); 7029 WorkListRemover DeadNodes(*this); 7030 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7031 7032 if (N->use_empty()) { 7033 removeFromWorkList(N); 7034 DAG.DeleteNode(N); 7035 } 7036 7037 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7038 } 7039 } else { 7040 // Indexed loads. 7041 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7042 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7043 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7044 DEBUG(dbgs() << "\nReplacing.7 "; 7045 N->dump(&DAG); 7046 dbgs() << "\nWith: "; 7047 Undef.getNode()->dump(&DAG); 7048 dbgs() << " and 2 other values\n"); 7049 WorkListRemover DeadNodes(*this); 7050 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7051 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7052 DAG.getUNDEF(N->getValueType(1))); 7053 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7054 removeFromWorkList(N); 7055 DAG.DeleteNode(N); 7056 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7057 } 7058 } 7059 } 7060 7061 // If this load is directly stored, replace the load value with the stored 7062 // value. 7063 // TODO: Handle store large -> read small portion. 7064 // TODO: Handle TRUNCSTORE/LOADEXT 7065 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7066 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7067 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7068 if (PrevST->getBasePtr() == Ptr && 7069 PrevST->getValue().getValueType() == N->getValueType(0)) 7070 return CombineTo(N, Chain.getOperand(1), Chain); 7071 } 7072 } 7073 7074 // Try to infer better alignment information than the load already has. 7075 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7076 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7077 if (Align > LD->getAlignment()) 7078 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 7079 LD->getValueType(0), 7080 Chain, Ptr, LD->getPointerInfo(), 7081 LD->getMemoryVT(), 7082 LD->isVolatile(), LD->isNonTemporal(), Align); 7083 } 7084 } 7085 7086 if (CombinerAA) { 7087 // Walk up chain skipping non-aliasing memory nodes. 7088 SDValue BetterChain = FindBetterChain(N, Chain); 7089 7090 // If there is a better chain. 7091 if (Chain != BetterChain) { 7092 SDValue ReplLoad; 7093 7094 // Replace the chain to void dependency. 7095 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7096 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 7097 BetterChain, Ptr, LD->getPointerInfo(), 7098 LD->isVolatile(), LD->isNonTemporal(), 7099 LD->isInvariant(), LD->getAlignment()); 7100 } else { 7101 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 7102 LD->getValueType(0), 7103 BetterChain, Ptr, LD->getPointerInfo(), 7104 LD->getMemoryVT(), 7105 LD->isVolatile(), 7106 LD->isNonTemporal(), 7107 LD->getAlignment()); 7108 } 7109 7110 // Create token factor to keep old chain connected. 7111 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7112 MVT::Other, Chain, ReplLoad.getValue(1)); 7113 7114 // Make sure the new and old chains are cleaned up. 7115 AddToWorkList(Token.getNode()); 7116 7117 // Replace uses with load result and token factor. Don't add users 7118 // to work list. 7119 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7120 } 7121 } 7122 7123 // Try transforming N to an indexed load. 7124 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7125 return SDValue(N, 0); 7126 7127 return SDValue(); 7128} 7129 7130/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 7131/// load is having specific bytes cleared out. If so, return the byte size 7132/// being masked out and the shift amount. 7133static std::pair<unsigned, unsigned> 7134CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 7135 std::pair<unsigned, unsigned> Result(0, 0); 7136 7137 // Check for the structure we're looking for. 7138 if (V->getOpcode() != ISD::AND || 7139 !isa<ConstantSDNode>(V->getOperand(1)) || 7140 !ISD::isNormalLoad(V->getOperand(0).getNode())) 7141 return Result; 7142 7143 // Check the chain and pointer. 7144 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 7145 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 7146 7147 // The store should be chained directly to the load or be an operand of a 7148 // tokenfactor. 7149 if (LD == Chain.getNode()) 7150 ; // ok. 7151 else if (Chain->getOpcode() != ISD::TokenFactor) 7152 return Result; // Fail. 7153 else { 7154 bool isOk = false; 7155 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 7156 if (Chain->getOperand(i).getNode() == LD) { 7157 isOk = true; 7158 break; 7159 } 7160 if (!isOk) return Result; 7161 } 7162 7163 // This only handles simple types. 7164 if (V.getValueType() != MVT::i16 && 7165 V.getValueType() != MVT::i32 && 7166 V.getValueType() != MVT::i64) 7167 return Result; 7168 7169 // Check the constant mask. Invert it so that the bits being masked out are 7170 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 7171 // follow the sign bit for uniformity. 7172 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 7173 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 7174 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 7175 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 7176 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 7177 if (NotMaskLZ == 64) return Result; // All zero mask. 7178 7179 // See if we have a continuous run of bits. If so, we have 0*1+0* 7180 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 7181 return Result; 7182 7183 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 7184 if (V.getValueType() != MVT::i64 && NotMaskLZ) 7185 NotMaskLZ -= 64-V.getValueSizeInBits(); 7186 7187 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 7188 switch (MaskedBytes) { 7189 case 1: 7190 case 2: 7191 case 4: break; 7192 default: return Result; // All one mask, or 5-byte mask. 7193 } 7194 7195 // Verify that the first bit starts at a multiple of mask so that the access 7196 // is aligned the same as the access width. 7197 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 7198 7199 Result.first = MaskedBytes; 7200 Result.second = NotMaskTZ/8; 7201 return Result; 7202} 7203 7204 7205/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 7206/// provides a value as specified by MaskInfo. If so, replace the specified 7207/// store with a narrower store of truncated IVal. 7208static SDNode * 7209ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 7210 SDValue IVal, StoreSDNode *St, 7211 DAGCombiner *DC) { 7212 unsigned NumBytes = MaskInfo.first; 7213 unsigned ByteShift = MaskInfo.second; 7214 SelectionDAG &DAG = DC->getDAG(); 7215 7216 // Check to see if IVal is all zeros in the part being masked in by the 'or' 7217 // that uses this. If not, this is not a replacement. 7218 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 7219 ByteShift*8, (ByteShift+NumBytes)*8); 7220 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 7221 7222 // Check that it is legal on the target to do this. It is legal if the new 7223 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 7224 // legalization. 7225 MVT VT = MVT::getIntegerVT(NumBytes*8); 7226 if (!DC->isTypeLegal(VT)) 7227 return 0; 7228 7229 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 7230 // shifted by ByteShift and truncated down to NumBytes. 7231 if (ByteShift) 7232 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 7233 DAG.getConstant(ByteShift*8, 7234 DC->getShiftAmountTy(IVal.getValueType()))); 7235 7236 // Figure out the offset for the store and the alignment of the access. 7237 unsigned StOffset; 7238 unsigned NewAlign = St->getAlignment(); 7239 7240 if (DAG.getTargetLoweringInfo().isLittleEndian()) 7241 StOffset = ByteShift; 7242 else 7243 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 7244 7245 SDValue Ptr = St->getBasePtr(); 7246 if (StOffset) { 7247 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 7248 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 7249 NewAlign = MinAlign(NewAlign, StOffset); 7250 } 7251 7252 // Truncate down to the new size. 7253 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 7254 7255 ++OpsNarrowed; 7256 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 7257 St->getPointerInfo().getWithOffset(StOffset), 7258 false, false, NewAlign).getNode(); 7259} 7260 7261 7262/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 7263/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 7264/// of the loaded bits, try narrowing the load and store if it would end up 7265/// being a win for performance or code size. 7266SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 7267 StoreSDNode *ST = cast<StoreSDNode>(N); 7268 if (ST->isVolatile()) 7269 return SDValue(); 7270 7271 SDValue Chain = ST->getChain(); 7272 SDValue Value = ST->getValue(); 7273 SDValue Ptr = ST->getBasePtr(); 7274 EVT VT = Value.getValueType(); 7275 7276 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 7277 return SDValue(); 7278 7279 unsigned Opc = Value.getOpcode(); 7280 7281 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 7282 // is a byte mask indicating a consecutive number of bytes, check to see if 7283 // Y is known to provide just those bytes. If so, we try to replace the 7284 // load + replace + store sequence with a single (narrower) store, which makes 7285 // the load dead. 7286 if (Opc == ISD::OR) { 7287 std::pair<unsigned, unsigned> MaskedLoad; 7288 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 7289 if (MaskedLoad.first) 7290 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7291 Value.getOperand(1), ST,this)) 7292 return SDValue(NewST, 0); 7293 7294 // Or is commutative, so try swapping X and Y. 7295 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 7296 if (MaskedLoad.first) 7297 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7298 Value.getOperand(0), ST,this)) 7299 return SDValue(NewST, 0); 7300 } 7301 7302 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 7303 Value.getOperand(1).getOpcode() != ISD::Constant) 7304 return SDValue(); 7305 7306 SDValue N0 = Value.getOperand(0); 7307 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 7308 Chain == SDValue(N0.getNode(), 1)) { 7309 LoadSDNode *LD = cast<LoadSDNode>(N0); 7310 if (LD->getBasePtr() != Ptr || 7311 LD->getPointerInfo().getAddrSpace() != 7312 ST->getPointerInfo().getAddrSpace()) 7313 return SDValue(); 7314 7315 // Find the type to narrow it the load / op / store to. 7316 SDValue N1 = Value.getOperand(1); 7317 unsigned BitWidth = N1.getValueSizeInBits(); 7318 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 7319 if (Opc == ISD::AND) 7320 Imm ^= APInt::getAllOnesValue(BitWidth); 7321 if (Imm == 0 || Imm.isAllOnesValue()) 7322 return SDValue(); 7323 unsigned ShAmt = Imm.countTrailingZeros(); 7324 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 7325 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 7326 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7327 while (NewBW < BitWidth && 7328 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 7329 TLI.isNarrowingProfitable(VT, NewVT))) { 7330 NewBW = NextPowerOf2(NewBW); 7331 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7332 } 7333 if (NewBW >= BitWidth) 7334 return SDValue(); 7335 7336 // If the lsb changed does not start at the type bitwidth boundary, 7337 // start at the previous one. 7338 if (ShAmt % NewBW) 7339 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 7340 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 7341 if ((Imm & Mask) == Imm) { 7342 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 7343 if (Opc == ISD::AND) 7344 NewImm ^= APInt::getAllOnesValue(NewBW); 7345 uint64_t PtrOff = ShAmt / 8; 7346 // For big endian targets, we need to adjust the offset to the pointer to 7347 // load the correct bytes. 7348 if (TLI.isBigEndian()) 7349 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 7350 7351 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 7352 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 7353 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 7354 return SDValue(); 7355 7356 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 7357 Ptr.getValueType(), Ptr, 7358 DAG.getConstant(PtrOff, Ptr.getValueType())); 7359 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 7360 LD->getChain(), NewPtr, 7361 LD->getPointerInfo().getWithOffset(PtrOff), 7362 LD->isVolatile(), LD->isNonTemporal(), 7363 LD->isInvariant(), NewAlign); 7364 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 7365 DAG.getConstant(NewImm, NewVT)); 7366 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 7367 NewVal, NewPtr, 7368 ST->getPointerInfo().getWithOffset(PtrOff), 7369 false, false, NewAlign); 7370 7371 AddToWorkList(NewPtr.getNode()); 7372 AddToWorkList(NewLD.getNode()); 7373 AddToWorkList(NewVal.getNode()); 7374 WorkListRemover DeadNodes(*this); 7375 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7376 ++OpsNarrowed; 7377 return NewST; 7378 } 7379 } 7380 7381 return SDValue(); 7382} 7383 7384/// TransformFPLoadStorePair - For a given floating point load / store pair, 7385/// if the load value isn't used by any other operations, then consider 7386/// transforming the pair to integer load / store operations if the target 7387/// deems the transformation profitable. 7388SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7389 StoreSDNode *ST = cast<StoreSDNode>(N); 7390 SDValue Chain = ST->getChain(); 7391 SDValue Value = ST->getValue(); 7392 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7393 Value.hasOneUse() && 7394 Chain == SDValue(Value.getNode(), 1)) { 7395 LoadSDNode *LD = cast<LoadSDNode>(Value); 7396 EVT VT = LD->getMemoryVT(); 7397 if (!VT.isFloatingPoint() || 7398 VT != ST->getMemoryVT() || 7399 LD->isNonTemporal() || 7400 ST->isNonTemporal() || 7401 LD->getPointerInfo().getAddrSpace() != 0 || 7402 ST->getPointerInfo().getAddrSpace() != 0) 7403 return SDValue(); 7404 7405 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7406 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7407 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7408 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7409 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7410 return SDValue(); 7411 7412 unsigned LDAlign = LD->getAlignment(); 7413 unsigned STAlign = ST->getAlignment(); 7414 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7415 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 7416 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7417 return SDValue(); 7418 7419 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 7420 LD->getChain(), LD->getBasePtr(), 7421 LD->getPointerInfo(), 7422 false, false, false, LDAlign); 7423 7424 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 7425 NewLD, ST->getBasePtr(), 7426 ST->getPointerInfo(), 7427 false, false, STAlign); 7428 7429 AddToWorkList(NewLD.getNode()); 7430 AddToWorkList(NewST.getNode()); 7431 WorkListRemover DeadNodes(*this); 7432 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7433 ++LdStFP2Int; 7434 return NewST; 7435 } 7436 7437 return SDValue(); 7438} 7439 7440SDValue DAGCombiner::visitSTORE(SDNode *N) { 7441 StoreSDNode *ST = cast<StoreSDNode>(N); 7442 SDValue Chain = ST->getChain(); 7443 SDValue Value = ST->getValue(); 7444 SDValue Ptr = ST->getBasePtr(); 7445 7446 // If this is a store of a bit convert, store the input value if the 7447 // resultant store does not need a higher alignment than the original. 7448 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 7449 ST->isUnindexed()) { 7450 unsigned OrigAlign = ST->getAlignment(); 7451 EVT SVT = Value.getOperand(0).getValueType(); 7452 unsigned Align = TLI.getTargetData()-> 7453 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 7454 if (Align <= OrigAlign && 7455 ((!LegalOperations && !ST->isVolatile()) || 7456 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 7457 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7458 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7459 ST->isNonTemporal(), OrigAlign); 7460 } 7461 7462 // Turn 'store undef, Ptr' -> nothing. 7463 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 7464 return Chain; 7465 7466 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 7467 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 7468 // NOTE: If the original store is volatile, this transform must not increase 7469 // the number of stores. For example, on x86-32 an f64 can be stored in one 7470 // processor operation but an i64 (which is not legal) requires two. So the 7471 // transform should not be done in this case. 7472 if (Value.getOpcode() != ISD::TargetConstantFP) { 7473 SDValue Tmp; 7474 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 7475 default: llvm_unreachable("Unknown FP type"); 7476 case MVT::f16: // We don't do this for these yet. 7477 case MVT::f80: 7478 case MVT::f128: 7479 case MVT::ppcf128: 7480 break; 7481 case MVT::f32: 7482 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 7483 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7484 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 7485 bitcastToAPInt().getZExtValue(), MVT::i32); 7486 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7487 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7488 ST->isNonTemporal(), ST->getAlignment()); 7489 } 7490 break; 7491 case MVT::f64: 7492 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 7493 !ST->isVolatile()) || 7494 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 7495 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 7496 getZExtValue(), MVT::i64); 7497 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7498 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7499 ST->isNonTemporal(), ST->getAlignment()); 7500 } 7501 7502 if (!ST->isVolatile() && 7503 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7504 // Many FP stores are not made apparent until after legalize, e.g. for 7505 // argument passing. Since this is so common, custom legalize the 7506 // 64-bit integer store into two 32-bit stores. 7507 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 7508 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 7509 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 7510 if (TLI.isBigEndian()) std::swap(Lo, Hi); 7511 7512 unsigned Alignment = ST->getAlignment(); 7513 bool isVolatile = ST->isVolatile(); 7514 bool isNonTemporal = ST->isNonTemporal(); 7515 7516 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 7517 Ptr, ST->getPointerInfo(), 7518 isVolatile, isNonTemporal, 7519 ST->getAlignment()); 7520 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 7521 DAG.getConstant(4, Ptr.getValueType())); 7522 Alignment = MinAlign(Alignment, 4U); 7523 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 7524 Ptr, ST->getPointerInfo().getWithOffset(4), 7525 isVolatile, isNonTemporal, 7526 Alignment); 7527 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7528 St0, St1); 7529 } 7530 7531 break; 7532 } 7533 } 7534 } 7535 7536 // Try to infer better alignment information than the store already has. 7537 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 7538 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7539 if (Align > ST->getAlignment()) 7540 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 7541 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7542 ST->isVolatile(), ST->isNonTemporal(), Align); 7543 } 7544 } 7545 7546 // Try transforming a pair floating point load / store ops to integer 7547 // load / store ops. 7548 SDValue NewST = TransformFPLoadStorePair(N); 7549 if (NewST.getNode()) 7550 return NewST; 7551 7552 if (CombinerAA) { 7553 // Walk up chain skipping non-aliasing memory nodes. 7554 SDValue BetterChain = FindBetterChain(N, Chain); 7555 7556 // If there is a better chain. 7557 if (Chain != BetterChain) { 7558 SDValue ReplStore; 7559 7560 // Replace the chain to avoid dependency. 7561 if (ST->isTruncatingStore()) { 7562 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7563 ST->getPointerInfo(), 7564 ST->getMemoryVT(), ST->isVolatile(), 7565 ST->isNonTemporal(), ST->getAlignment()); 7566 } else { 7567 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7568 ST->getPointerInfo(), 7569 ST->isVolatile(), ST->isNonTemporal(), 7570 ST->getAlignment()); 7571 } 7572 7573 // Create token to keep both nodes around. 7574 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7575 MVT::Other, Chain, ReplStore); 7576 7577 // Make sure the new and old chains are cleaned up. 7578 AddToWorkList(Token.getNode()); 7579 7580 // Don't add users to work list. 7581 return CombineTo(N, Token, false); 7582 } 7583 } 7584 7585 // Try transforming N to an indexed store. 7586 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7587 return SDValue(N, 0); 7588 7589 // FIXME: is there such a thing as a truncating indexed store? 7590 if (ST->isTruncatingStore() && ST->isUnindexed() && 7591 Value.getValueType().isInteger()) { 7592 // See if we can simplify the input to this truncstore with knowledge that 7593 // only the low bits are being used. For example: 7594 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 7595 SDValue Shorter = 7596 GetDemandedBits(Value, 7597 APInt::getLowBitsSet( 7598 Value.getValueType().getScalarType().getSizeInBits(), 7599 ST->getMemoryVT().getScalarType().getSizeInBits())); 7600 AddToWorkList(Value.getNode()); 7601 if (Shorter.getNode()) 7602 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 7603 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7604 ST->isVolatile(), ST->isNonTemporal(), 7605 ST->getAlignment()); 7606 7607 // Otherwise, see if we can simplify the operation with 7608 // SimplifyDemandedBits, which only works if the value has a single use. 7609 if (SimplifyDemandedBits(Value, 7610 APInt::getLowBitsSet( 7611 Value.getValueType().getScalarType().getSizeInBits(), 7612 ST->getMemoryVT().getScalarType().getSizeInBits()))) 7613 return SDValue(N, 0); 7614 } 7615 7616 // If this is a load followed by a store to the same location, then the store 7617 // is dead/noop. 7618 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 7619 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 7620 ST->isUnindexed() && !ST->isVolatile() && 7621 // There can't be any side effects between the load and store, such as 7622 // a call or store. 7623 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 7624 // The store is dead, remove it. 7625 return Chain; 7626 } 7627 } 7628 7629 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 7630 // truncating store. We can do this even if this is already a truncstore. 7631 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 7632 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 7633 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 7634 ST->getMemoryVT())) { 7635 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7636 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7637 ST->isVolatile(), ST->isNonTemporal(), 7638 ST->getAlignment()); 7639 } 7640 7641 return ReduceLoadOpStoreWidth(N); 7642} 7643 7644SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 7645 SDValue InVec = N->getOperand(0); 7646 SDValue InVal = N->getOperand(1); 7647 SDValue EltNo = N->getOperand(2); 7648 DebugLoc dl = N->getDebugLoc(); 7649 7650 // If the inserted element is an UNDEF, just use the input vector. 7651 if (InVal.getOpcode() == ISD::UNDEF) 7652 return InVec; 7653 7654 EVT VT = InVec.getValueType(); 7655 7656 // If we can't generate a legal BUILD_VECTOR, exit 7657 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 7658 return SDValue(); 7659 7660 // Check that we know which element is being inserted 7661 if (!isa<ConstantSDNode>(EltNo)) 7662 return SDValue(); 7663 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7664 7665 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 7666 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 7667 // vector elements. 7668 SmallVector<SDValue, 8> Ops; 7669 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 7670 Ops.append(InVec.getNode()->op_begin(), 7671 InVec.getNode()->op_end()); 7672 } else if (InVec.getOpcode() == ISD::UNDEF) { 7673 unsigned NElts = VT.getVectorNumElements(); 7674 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 7675 } else { 7676 return SDValue(); 7677 } 7678 7679 // Insert the element 7680 if (Elt < Ops.size()) { 7681 // All the operands of BUILD_VECTOR must have the same type; 7682 // we enforce that here. 7683 EVT OpVT = Ops[0].getValueType(); 7684 if (InVal.getValueType() != OpVT) 7685 InVal = OpVT.bitsGT(InVal.getValueType()) ? 7686 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 7687 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 7688 Ops[Elt] = InVal; 7689 } 7690 7691 // Return the new vector 7692 return DAG.getNode(ISD::BUILD_VECTOR, dl, 7693 VT, &Ops[0], Ops.size()); 7694} 7695 7696SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 7697 // (vextract (scalar_to_vector val, 0) -> val 7698 SDValue InVec = N->getOperand(0); 7699 EVT VT = InVec.getValueType(); 7700 EVT NVT = N->getValueType(0); 7701 7702 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 7703 // Check if the result type doesn't match the inserted element type. A 7704 // SCALAR_TO_VECTOR may truncate the inserted element and the 7705 // EXTRACT_VECTOR_ELT may widen the extracted vector. 7706 SDValue InOp = InVec.getOperand(0); 7707 if (InOp.getValueType() != NVT) { 7708 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 7709 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 7710 } 7711 return InOp; 7712 } 7713 7714 SDValue EltNo = N->getOperand(1); 7715 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 7716 7717 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 7718 // We only perform this optimization before the op legalization phase because 7719 // we may introduce new vector instructions which are not backed by TD 7720 // patterns. For example on AVX, extracting elements from a wide vector 7721 // without using extract_subvector. 7722 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 7723 && ConstEltNo && !LegalOperations) { 7724 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7725 int NumElem = VT.getVectorNumElements(); 7726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 7727 // Find the new index to extract from. 7728 int OrigElt = SVOp->getMaskElt(Elt); 7729 7730 // Extracting an undef index is undef. 7731 if (OrigElt == -1) 7732 return DAG.getUNDEF(NVT); 7733 7734 // Select the right vector half to extract from. 7735 if (OrigElt < NumElem) { 7736 InVec = InVec->getOperand(0); 7737 } else { 7738 InVec = InVec->getOperand(1); 7739 OrigElt -= NumElem; 7740 } 7741 7742 EVT IndexTy = N->getOperand(1).getValueType(); 7743 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 7744 InVec, DAG.getConstant(OrigElt, IndexTy)); 7745 } 7746 7747 // Perform only after legalization to ensure build_vector / vector_shuffle 7748 // optimizations have already been done. 7749 if (!LegalOperations) return SDValue(); 7750 7751 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 7752 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 7753 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 7754 7755 if (ConstEltNo) { 7756 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7757 bool NewLoad = false; 7758 bool BCNumEltsChanged = false; 7759 EVT ExtVT = VT.getVectorElementType(); 7760 EVT LVT = ExtVT; 7761 7762 // If the result of load has to be truncated, then it's not necessarily 7763 // profitable. 7764 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 7765 return SDValue(); 7766 7767 if (InVec.getOpcode() == ISD::BITCAST) { 7768 // Don't duplicate a load with other uses. 7769 if (!InVec.hasOneUse()) 7770 return SDValue(); 7771 7772 EVT BCVT = InVec.getOperand(0).getValueType(); 7773 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 7774 return SDValue(); 7775 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 7776 BCNumEltsChanged = true; 7777 InVec = InVec.getOperand(0); 7778 ExtVT = BCVT.getVectorElementType(); 7779 NewLoad = true; 7780 } 7781 7782 LoadSDNode *LN0 = NULL; 7783 const ShuffleVectorSDNode *SVN = NULL; 7784 if (ISD::isNormalLoad(InVec.getNode())) { 7785 LN0 = cast<LoadSDNode>(InVec); 7786 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 7787 InVec.getOperand(0).getValueType() == ExtVT && 7788 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 7789 // Don't duplicate a load with other uses. 7790 if (!InVec.hasOneUse()) 7791 return SDValue(); 7792 7793 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 7794 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 7795 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 7796 // => 7797 // (load $addr+1*size) 7798 7799 // Don't duplicate a load with other uses. 7800 if (!InVec.hasOneUse()) 7801 return SDValue(); 7802 7803 // If the bit convert changed the number of elements, it is unsafe 7804 // to examine the mask. 7805 if (BCNumEltsChanged) 7806 return SDValue(); 7807 7808 // Select the input vector, guarding against out of range extract vector. 7809 unsigned NumElems = VT.getVectorNumElements(); 7810 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7811 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7812 7813 if (InVec.getOpcode() == ISD::BITCAST) { 7814 // Don't duplicate a load with other uses. 7815 if (!InVec.hasOneUse()) 7816 return SDValue(); 7817 7818 InVec = InVec.getOperand(0); 7819 } 7820 if (ISD::isNormalLoad(InVec.getNode())) { 7821 LN0 = cast<LoadSDNode>(InVec); 7822 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7823 } 7824 } 7825 7826 // Make sure we found a non-volatile load and the extractelement is 7827 // the only use. 7828 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7829 return SDValue(); 7830 7831 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7832 if (Elt == -1) 7833 return DAG.getUNDEF(LVT); 7834 7835 unsigned Align = LN0->getAlignment(); 7836 if (NewLoad) { 7837 // Check the resultant load doesn't need a higher alignment than the 7838 // original load. 7839 unsigned NewAlign = 7840 TLI.getTargetData() 7841 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7842 7843 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7844 return SDValue(); 7845 7846 Align = NewAlign; 7847 } 7848 7849 SDValue NewPtr = LN0->getBasePtr(); 7850 unsigned PtrOff = 0; 7851 7852 if (Elt) { 7853 PtrOff = LVT.getSizeInBits() * Elt / 8; 7854 EVT PtrType = NewPtr.getValueType(); 7855 if (TLI.isBigEndian()) 7856 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7857 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7858 DAG.getConstant(PtrOff, PtrType)); 7859 } 7860 7861 // The replacement we need to do here is a little tricky: we need to 7862 // replace an extractelement of a load with a load. 7863 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7864 // Note that this replacement assumes that the extractvalue is the only 7865 // use of the load; that's okay because we don't want to perform this 7866 // transformation in other cases anyway. 7867 SDValue Load; 7868 SDValue Chain; 7869 if (NVT.bitsGT(LVT)) { 7870 // If the result type of vextract is wider than the load, then issue an 7871 // extending load instead. 7872 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 7873 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 7874 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 7875 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 7876 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 7877 Chain = Load.getValue(1); 7878 } else { 7879 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7880 LN0->getPointerInfo().getWithOffset(PtrOff), 7881 LN0->isVolatile(), LN0->isNonTemporal(), 7882 LN0->isInvariant(), Align); 7883 Chain = Load.getValue(1); 7884 if (NVT.bitsLT(LVT)) 7885 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 7886 else 7887 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 7888 } 7889 WorkListRemover DeadNodes(*this); 7890 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7891 SDValue To[] = { Load, Chain }; 7892 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 7893 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7894 // worklist explicitly as well. 7895 AddToWorkList(Load.getNode()); 7896 AddUsersToWorkList(Load.getNode()); // Add users too 7897 // Make sure to revisit this node to clean it up; it will usually be dead. 7898 AddToWorkList(N); 7899 return SDValue(N, 0); 7900 } 7901 7902 return SDValue(); 7903} 7904 7905SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7906 unsigned NumInScalars = N->getNumOperands(); 7907 DebugLoc dl = N->getDebugLoc(); 7908 EVT VT = N->getValueType(0); 7909 7910 // A vector built entirely of undefs is undef. 7911 if (ISD::allOperandsUndef(N)) 7912 return DAG.getUNDEF(VT); 7913 7914 // Check to see if this is a BUILD_VECTOR of a bunch of values 7915 // which come from any_extend or zero_extend nodes. If so, we can create 7916 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7917 // optimizations. We do not handle sign-extend because we can't fill the sign 7918 // using shuffles. 7919 EVT SourceType = MVT::Other; 7920 bool AllAnyExt = true; 7921 7922 for (unsigned i = 0; i != NumInScalars; ++i) { 7923 SDValue In = N->getOperand(i); 7924 // Ignore undef inputs. 7925 if (In.getOpcode() == ISD::UNDEF) continue; 7926 7927 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7928 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7929 7930 // Abort if the element is not an extension. 7931 if (!ZeroExt && !AnyExt) { 7932 SourceType = MVT::Other; 7933 break; 7934 } 7935 7936 // The input is a ZeroExt or AnyExt. Check the original type. 7937 EVT InTy = In.getOperand(0).getValueType(); 7938 7939 // Check that all of the widened source types are the same. 7940 if (SourceType == MVT::Other) 7941 // First time. 7942 SourceType = InTy; 7943 else if (InTy != SourceType) { 7944 // Multiple income types. Abort. 7945 SourceType = MVT::Other; 7946 break; 7947 } 7948 7949 // Check if all of the extends are ANY_EXTENDs. 7950 AllAnyExt &= AnyExt; 7951 } 7952 7953 // In order to have valid types, all of the inputs must be extended from the 7954 // same source type and all of the inputs must be any or zero extend. 7955 // Scalar sizes must be a power of two. 7956 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7957 bool ValidTypes = SourceType != MVT::Other && 7958 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7959 isPowerOf2_32(SourceType.getSizeInBits()); 7960 7961 // We perform this optimization post type-legalization because 7962 // the type-legalizer often scalarizes integer-promoted vectors. 7963 // Performing this optimization before may create bit-casts which 7964 // will be type-legalized to complex code sequences. 7965 // We perform this optimization only before the operation legalizer because we 7966 // may introduce illegal operations. 7967 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 7968 // turn into a single shuffle instruction. 7969 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 7970 ValidTypes) { 7971 bool isLE = TLI.isLittleEndian(); 7972 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7973 assert(ElemRatio > 1 && "Invalid element size ratio"); 7974 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 7975 DAG.getConstant(0, SourceType); 7976 7977 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7978 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7979 7980 // Populate the new build_vector 7981 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7982 SDValue Cast = N->getOperand(i); 7983 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7984 Cast.getOpcode() == ISD::ZERO_EXTEND || 7985 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7986 SDValue In; 7987 if (Cast.getOpcode() == ISD::UNDEF) 7988 In = DAG.getUNDEF(SourceType); 7989 else 7990 In = Cast->getOperand(0); 7991 unsigned Index = isLE ? (i * ElemRatio) : 7992 (i * ElemRatio + (ElemRatio - 1)); 7993 7994 assert(Index < Ops.size() && "Invalid index"); 7995 Ops[Index] = In; 7996 } 7997 7998 // The type of the new BUILD_VECTOR node. 7999 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 8000 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 8001 "Invalid vector size"); 8002 // Check if the new vector type is legal. 8003 if (!isTypeLegal(VecVT)) return SDValue(); 8004 8005 // Make the new BUILD_VECTOR. 8006 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8007 VecVT, &Ops[0], Ops.size()); 8008 8009 // The new BUILD_VECTOR node has the potential to be further optimized. 8010 AddToWorkList(BV.getNode()); 8011 // Bitcast to the desired type. 8012 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 8013 } 8014 8015 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 8016 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 8017 // at most two distinct vectors, turn this into a shuffle node. 8018 8019 // May only combine to shuffle after legalize if shuffle is legal. 8020 if (LegalOperations && 8021 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 8022 return SDValue(); 8023 8024 SDValue VecIn1, VecIn2; 8025 for (unsigned i = 0; i != NumInScalars; ++i) { 8026 // Ignore undef inputs. 8027 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 8028 8029 // If this input is something other than a EXTRACT_VECTOR_ELT with a 8030 // constant index, bail out. 8031 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 8032 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 8033 VecIn1 = VecIn2 = SDValue(0, 0); 8034 break; 8035 } 8036 8037 // We allow up to two distinct input vectors. 8038 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 8039 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 8040 continue; 8041 8042 if (VecIn1.getNode() == 0) { 8043 VecIn1 = ExtractedFromVec; 8044 } else if (VecIn2.getNode() == 0) { 8045 VecIn2 = ExtractedFromVec; 8046 } else { 8047 // Too many inputs. 8048 VecIn1 = VecIn2 = SDValue(0, 0); 8049 break; 8050 } 8051 } 8052 8053 // If everything is good, we can make a shuffle operation. 8054 if (VecIn1.getNode()) { 8055 SmallVector<int, 8> Mask; 8056 for (unsigned i = 0; i != NumInScalars; ++i) { 8057 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 8058 Mask.push_back(-1); 8059 continue; 8060 } 8061 8062 // If extracting from the first vector, just use the index directly. 8063 SDValue Extract = N->getOperand(i); 8064 SDValue ExtVal = Extract.getOperand(1); 8065 if (Extract.getOperand(0) == VecIn1) { 8066 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8067 if (ExtIndex > VT.getVectorNumElements()) 8068 return SDValue(); 8069 8070 Mask.push_back(ExtIndex); 8071 continue; 8072 } 8073 8074 // Otherwise, use InIdx + VecSize 8075 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8076 Mask.push_back(Idx+NumInScalars); 8077 } 8078 8079 // We can't generate a shuffle node with mismatched input and output types. 8080 // Attempt to transform a single input vector to the correct type. 8081 if ((VT != VecIn1.getValueType())) { 8082 // We don't support shuffeling between TWO values of different types. 8083 if (VecIn2.getNode() != 0) 8084 return SDValue(); 8085 8086 // We only support widening of vectors which are half the size of the 8087 // output registers. For example XMM->YMM widening on X86 with AVX. 8088 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 8089 return SDValue(); 8090 8091 // If the input vector type has a different base type to the output 8092 // vector type, bail out. 8093 if (VecIn1.getValueType().getVectorElementType() != 8094 VT.getVectorElementType()) 8095 return SDValue(); 8096 8097 // Widen the input vector by adding undef values. 8098 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 8099 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 8100 } 8101 8102 // If VecIn2 is unused then change it to undef. 8103 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 8104 8105 // Check that we were able to transform all incoming values to the same 8106 // type. 8107 if (VecIn2.getValueType() != VecIn1.getValueType() || 8108 VecIn1.getValueType() != VT) 8109 return SDValue(); 8110 8111 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 8112 if (!isTypeLegal(VT)) 8113 return SDValue(); 8114 8115 // Return the new VECTOR_SHUFFLE node. 8116 SDValue Ops[2]; 8117 Ops[0] = VecIn1; 8118 Ops[1] = VecIn2; 8119 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 8120 } 8121 8122 return SDValue(); 8123} 8124 8125SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 8126 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 8127 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 8128 // inputs come from at most two distinct vectors, turn this into a shuffle 8129 // node. 8130 8131 // If we only have one input vector, we don't need to do any concatenation. 8132 if (N->getNumOperands() == 1) 8133 return N->getOperand(0); 8134 8135 // Check if all of the operands are undefs. 8136 if (ISD::allOperandsUndef(N)) 8137 return DAG.getUNDEF(N->getValueType(0)); 8138 8139 return SDValue(); 8140} 8141 8142SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 8143 EVT NVT = N->getValueType(0); 8144 SDValue V = N->getOperand(0); 8145 8146 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 8147 // Handle only simple case where vector being inserted and vector 8148 // being extracted are of same type, and are half size of larger vectors. 8149 EVT BigVT = V->getOperand(0).getValueType(); 8150 EVT SmallVT = V->getOperand(1).getValueType(); 8151 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 8152 return SDValue(); 8153 8154 // Only handle cases where both indexes are constants with the same type. 8155 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8156 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 8157 8158 if (InsIdx && ExtIdx && 8159 InsIdx->getValueType(0).getSizeInBits() <= 64 && 8160 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 8161 // Combine: 8162 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 8163 // Into: 8164 // indices are equal => V1 8165 // otherwise => (extract_subvec V1, ExtIdx) 8166 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 8167 return V->getOperand(1); 8168 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 8169 V->getOperand(0), N->getOperand(1)); 8170 } 8171 } 8172 8173 return SDValue(); 8174} 8175 8176SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 8177 EVT VT = N->getValueType(0); 8178 unsigned NumElts = VT.getVectorNumElements(); 8179 8180 SDValue N0 = N->getOperand(0); 8181 SDValue N1 = N->getOperand(1); 8182 8183 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 8184 8185 // Canonicalize shuffle undef, undef -> undef 8186 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 8187 return DAG.getUNDEF(VT); 8188 8189 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8190 8191 // Canonicalize shuffle v, v -> v, undef 8192 if (N0 == N1) { 8193 SmallVector<int, 8> NewMask; 8194 for (unsigned i = 0; i != NumElts; ++i) { 8195 int Idx = SVN->getMaskElt(i); 8196 if (Idx >= (int)NumElts) Idx -= NumElts; 8197 NewMask.push_back(Idx); 8198 } 8199 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 8200 &NewMask[0]); 8201 } 8202 8203 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 8204 if (N0.getOpcode() == ISD::UNDEF) { 8205 SmallVector<int, 8> NewMask; 8206 for (unsigned i = 0; i != NumElts; ++i) { 8207 int Idx = SVN->getMaskElt(i); 8208 if (Idx >= 0) { 8209 if (Idx < (int)NumElts) 8210 Idx += NumElts; 8211 else 8212 Idx -= NumElts; 8213 } 8214 NewMask.push_back(Idx); 8215 } 8216 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 8217 &NewMask[0]); 8218 } 8219 8220 // Remove references to rhs if it is undef 8221 if (N1.getOpcode() == ISD::UNDEF) { 8222 bool Changed = false; 8223 SmallVector<int, 8> NewMask; 8224 for (unsigned i = 0; i != NumElts; ++i) { 8225 int Idx = SVN->getMaskElt(i); 8226 if (Idx >= (int)NumElts) { 8227 Idx = -1; 8228 Changed = true; 8229 } 8230 NewMask.push_back(Idx); 8231 } 8232 if (Changed) 8233 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 8234 } 8235 8236 // If it is a splat, check if the argument vector is another splat or a 8237 // build_vector with all scalar elements the same. 8238 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 8239 SDNode *V = N0.getNode(); 8240 8241 // If this is a bit convert that changes the element type of the vector but 8242 // not the number of vector elements, look through it. Be careful not to 8243 // look though conversions that change things like v4f32 to v2f64. 8244 if (V->getOpcode() == ISD::BITCAST) { 8245 SDValue ConvInput = V->getOperand(0); 8246 if (ConvInput.getValueType().isVector() && 8247 ConvInput.getValueType().getVectorNumElements() == NumElts) 8248 V = ConvInput.getNode(); 8249 } 8250 8251 if (V->getOpcode() == ISD::BUILD_VECTOR) { 8252 assert(V->getNumOperands() == NumElts && 8253 "BUILD_VECTOR has wrong number of operands"); 8254 SDValue Base; 8255 bool AllSame = true; 8256 for (unsigned i = 0; i != NumElts; ++i) { 8257 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 8258 Base = V->getOperand(i); 8259 break; 8260 } 8261 } 8262 // Splat of <u, u, u, u>, return <u, u, u, u> 8263 if (!Base.getNode()) 8264 return N0; 8265 for (unsigned i = 0; i != NumElts; ++i) { 8266 if (V->getOperand(i) != Base) { 8267 AllSame = false; 8268 break; 8269 } 8270 } 8271 // Splat of <x, x, x, x>, return <x, x, x, x> 8272 if (AllSame) 8273 return N0; 8274 } 8275 } 8276 8277 // If this shuffle node is simply a swizzle of another shuffle node, 8278 // and it reverses the swizzle of the previous shuffle then we can 8279 // optimize shuffle(shuffle(x, undef), undef) -> x. 8280 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 8281 N1.getOpcode() == ISD::UNDEF) { 8282 8283 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 8284 8285 // Shuffle nodes can only reverse shuffles with a single non-undef value. 8286 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 8287 return SDValue(); 8288 8289 // The incoming shuffle must be of the same type as the result of the 8290 // current shuffle. 8291 assert(OtherSV->getOperand(0).getValueType() == VT && 8292 "Shuffle types don't match"); 8293 8294 for (unsigned i = 0; i != NumElts; ++i) { 8295 int Idx = SVN->getMaskElt(i); 8296 assert(Idx < (int)NumElts && "Index references undef operand"); 8297 // Next, this index comes from the first value, which is the incoming 8298 // shuffle. Adopt the incoming index. 8299 if (Idx >= 0) 8300 Idx = OtherSV->getMaskElt(Idx); 8301 8302 // The combined shuffle must map each index to itself. 8303 if (Idx >= 0 && (unsigned)Idx != i) 8304 return SDValue(); 8305 } 8306 8307 return OtherSV->getOperand(0); 8308 } 8309 8310 return SDValue(); 8311} 8312 8313SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 8314 if (!TLI.getShouldFoldAtomicFences()) 8315 return SDValue(); 8316 8317 SDValue atomic = N->getOperand(0); 8318 switch (atomic.getOpcode()) { 8319 case ISD::ATOMIC_CMP_SWAP: 8320 case ISD::ATOMIC_SWAP: 8321 case ISD::ATOMIC_LOAD_ADD: 8322 case ISD::ATOMIC_LOAD_SUB: 8323 case ISD::ATOMIC_LOAD_AND: 8324 case ISD::ATOMIC_LOAD_OR: 8325 case ISD::ATOMIC_LOAD_XOR: 8326 case ISD::ATOMIC_LOAD_NAND: 8327 case ISD::ATOMIC_LOAD_MIN: 8328 case ISD::ATOMIC_LOAD_MAX: 8329 case ISD::ATOMIC_LOAD_UMIN: 8330 case ISD::ATOMIC_LOAD_UMAX: 8331 break; 8332 default: 8333 return SDValue(); 8334 } 8335 8336 SDValue fence = atomic.getOperand(0); 8337 if (fence.getOpcode() != ISD::MEMBARRIER) 8338 return SDValue(); 8339 8340 switch (atomic.getOpcode()) { 8341 case ISD::ATOMIC_CMP_SWAP: 8342 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 8343 fence.getOperand(0), 8344 atomic.getOperand(1), atomic.getOperand(2), 8345 atomic.getOperand(3)), atomic.getResNo()); 8346 case ISD::ATOMIC_SWAP: 8347 case ISD::ATOMIC_LOAD_ADD: 8348 case ISD::ATOMIC_LOAD_SUB: 8349 case ISD::ATOMIC_LOAD_AND: 8350 case ISD::ATOMIC_LOAD_OR: 8351 case ISD::ATOMIC_LOAD_XOR: 8352 case ISD::ATOMIC_LOAD_NAND: 8353 case ISD::ATOMIC_LOAD_MIN: 8354 case ISD::ATOMIC_LOAD_MAX: 8355 case ISD::ATOMIC_LOAD_UMIN: 8356 case ISD::ATOMIC_LOAD_UMAX: 8357 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 8358 fence.getOperand(0), 8359 atomic.getOperand(1), atomic.getOperand(2)), 8360 atomic.getResNo()); 8361 default: 8362 return SDValue(); 8363 } 8364} 8365 8366/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 8367/// an AND to a vector_shuffle with the destination vector and a zero vector. 8368/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 8369/// vector_shuffle V, Zero, <0, 4, 2, 4> 8370SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 8371 EVT VT = N->getValueType(0); 8372 DebugLoc dl = N->getDebugLoc(); 8373 SDValue LHS = N->getOperand(0); 8374 SDValue RHS = N->getOperand(1); 8375 if (N->getOpcode() == ISD::AND) { 8376 if (RHS.getOpcode() == ISD::BITCAST) 8377 RHS = RHS.getOperand(0); 8378 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 8379 SmallVector<int, 8> Indices; 8380 unsigned NumElts = RHS.getNumOperands(); 8381 for (unsigned i = 0; i != NumElts; ++i) { 8382 SDValue Elt = RHS.getOperand(i); 8383 if (!isa<ConstantSDNode>(Elt)) 8384 return SDValue(); 8385 8386 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 8387 Indices.push_back(i); 8388 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 8389 Indices.push_back(NumElts); 8390 else 8391 return SDValue(); 8392 } 8393 8394 // Let's see if the target supports this vector_shuffle. 8395 EVT RVT = RHS.getValueType(); 8396 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 8397 return SDValue(); 8398 8399 // Return the new VECTOR_SHUFFLE node. 8400 EVT EltVT = RVT.getVectorElementType(); 8401 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 8402 DAG.getConstant(0, EltVT)); 8403 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8404 RVT, &ZeroOps[0], ZeroOps.size()); 8405 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 8406 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 8407 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 8408 } 8409 } 8410 8411 return SDValue(); 8412} 8413 8414/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 8415SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 8416 // After legalize, the target may be depending on adds and other 8417 // binary ops to provide legal ways to construct constants or other 8418 // things. Simplifying them may result in a loss of legality. 8419 if (LegalOperations) return SDValue(); 8420 8421 assert(N->getValueType(0).isVector() && 8422 "SimplifyVBinOp only works on vectors!"); 8423 8424 SDValue LHS = N->getOperand(0); 8425 SDValue RHS = N->getOperand(1); 8426 SDValue Shuffle = XformToShuffleWithZero(N); 8427 if (Shuffle.getNode()) return Shuffle; 8428 8429 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 8430 // this operation. 8431 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 8432 RHS.getOpcode() == ISD::BUILD_VECTOR) { 8433 SmallVector<SDValue, 8> Ops; 8434 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 8435 SDValue LHSOp = LHS.getOperand(i); 8436 SDValue RHSOp = RHS.getOperand(i); 8437 // If these two elements can't be folded, bail out. 8438 if ((LHSOp.getOpcode() != ISD::UNDEF && 8439 LHSOp.getOpcode() != ISD::Constant && 8440 LHSOp.getOpcode() != ISD::ConstantFP) || 8441 (RHSOp.getOpcode() != ISD::UNDEF && 8442 RHSOp.getOpcode() != ISD::Constant && 8443 RHSOp.getOpcode() != ISD::ConstantFP)) 8444 break; 8445 8446 // Can't fold divide by zero. 8447 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 8448 N->getOpcode() == ISD::FDIV) { 8449 if ((RHSOp.getOpcode() == ISD::Constant && 8450 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 8451 (RHSOp.getOpcode() == ISD::ConstantFP && 8452 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 8453 break; 8454 } 8455 8456 EVT VT = LHSOp.getValueType(); 8457 EVT RVT = RHSOp.getValueType(); 8458 if (RVT != VT) { 8459 // Integer BUILD_VECTOR operands may have types larger than the element 8460 // size (e.g., when the element type is not legal). Prior to type 8461 // legalization, the types may not match between the two BUILD_VECTORS. 8462 // Truncate one of the operands to make them match. 8463 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 8464 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 8465 } else { 8466 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 8467 VT = RVT; 8468 } 8469 } 8470 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 8471 LHSOp, RHSOp); 8472 if (FoldOp.getOpcode() != ISD::UNDEF && 8473 FoldOp.getOpcode() != ISD::Constant && 8474 FoldOp.getOpcode() != ISD::ConstantFP) 8475 break; 8476 Ops.push_back(FoldOp); 8477 AddToWorkList(FoldOp.getNode()); 8478 } 8479 8480 if (Ops.size() == LHS.getNumOperands()) 8481 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8482 LHS.getValueType(), &Ops[0], Ops.size()); 8483 } 8484 8485 return SDValue(); 8486} 8487 8488/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 8489SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 8490 // After legalize, the target may be depending on adds and other 8491 // binary ops to provide legal ways to construct constants or other 8492 // things. Simplifying them may result in a loss of legality. 8493 if (LegalOperations) return SDValue(); 8494 8495 assert(N->getValueType(0).isVector() && 8496 "SimplifyVUnaryOp only works on vectors!"); 8497 8498 SDValue N0 = N->getOperand(0); 8499 8500 if (N0.getOpcode() != ISD::BUILD_VECTOR) 8501 return SDValue(); 8502 8503 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 8504 SmallVector<SDValue, 8> Ops; 8505 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 8506 SDValue Op = N0.getOperand(i); 8507 if (Op.getOpcode() != ISD::UNDEF && 8508 Op.getOpcode() != ISD::ConstantFP) 8509 break; 8510 EVT EltVT = Op.getValueType(); 8511 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op); 8512 if (FoldOp.getOpcode() != ISD::UNDEF && 8513 FoldOp.getOpcode() != ISD::ConstantFP) 8514 break; 8515 Ops.push_back(FoldOp); 8516 AddToWorkList(FoldOp.getNode()); 8517 } 8518 8519 if (Ops.size() != N0.getNumOperands()) 8520 return SDValue(); 8521 8522 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8523 N0.getValueType(), &Ops[0], Ops.size()); 8524} 8525 8526SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 8527 SDValue N1, SDValue N2){ 8528 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 8529 8530 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 8531 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 8532 8533 // If we got a simplified select_cc node back from SimplifySelectCC, then 8534 // break it down into a new SETCC node, and a new SELECT node, and then return 8535 // the SELECT node, since we were called with a SELECT node. 8536 if (SCC.getNode()) { 8537 // Check to see if we got a select_cc back (to turn into setcc/select). 8538 // Otherwise, just return whatever node we got back, like fabs. 8539 if (SCC.getOpcode() == ISD::SELECT_CC) { 8540 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 8541 N0.getValueType(), 8542 SCC.getOperand(0), SCC.getOperand(1), 8543 SCC.getOperand(4)); 8544 AddToWorkList(SETCC.getNode()); 8545 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 8546 SCC.getOperand(2), SCC.getOperand(3), SETCC); 8547 } 8548 8549 return SCC; 8550 } 8551 return SDValue(); 8552} 8553 8554/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 8555/// are the two values being selected between, see if we can simplify the 8556/// select. Callers of this should assume that TheSelect is deleted if this 8557/// returns true. As such, they should return the appropriate thing (e.g. the 8558/// node) back to the top-level of the DAG combiner loop to avoid it being 8559/// looked at. 8560bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 8561 SDValue RHS) { 8562 8563 // Cannot simplify select with vector condition 8564 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 8565 8566 // If this is a select from two identical things, try to pull the operation 8567 // through the select. 8568 if (LHS.getOpcode() != RHS.getOpcode() || 8569 !LHS.hasOneUse() || !RHS.hasOneUse()) 8570 return false; 8571 8572 // If this is a load and the token chain is identical, replace the select 8573 // of two loads with a load through a select of the address to load from. 8574 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 8575 // constants have been dropped into the constant pool. 8576 if (LHS.getOpcode() == ISD::LOAD) { 8577 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 8578 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 8579 8580 // Token chains must be identical. 8581 if (LHS.getOperand(0) != RHS.getOperand(0) || 8582 // Do not let this transformation reduce the number of volatile loads. 8583 LLD->isVolatile() || RLD->isVolatile() || 8584 // If this is an EXTLOAD, the VT's must match. 8585 LLD->getMemoryVT() != RLD->getMemoryVT() || 8586 // If this is an EXTLOAD, the kind of extension must match. 8587 (LLD->getExtensionType() != RLD->getExtensionType() && 8588 // The only exception is if one of the extensions is anyext. 8589 LLD->getExtensionType() != ISD::EXTLOAD && 8590 RLD->getExtensionType() != ISD::EXTLOAD) || 8591 // FIXME: this discards src value information. This is 8592 // over-conservative. It would be beneficial to be able to remember 8593 // both potential memory locations. Since we are discarding 8594 // src value info, don't do the transformation if the memory 8595 // locations are not in the default address space. 8596 LLD->getPointerInfo().getAddrSpace() != 0 || 8597 RLD->getPointerInfo().getAddrSpace() != 0) 8598 return false; 8599 8600 // Check that the select condition doesn't reach either load. If so, 8601 // folding this will induce a cycle into the DAG. If not, this is safe to 8602 // xform, so create a select of the addresses. 8603 SDValue Addr; 8604 if (TheSelect->getOpcode() == ISD::SELECT) { 8605 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 8606 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 8607 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 8608 return false; 8609 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 8610 LLD->getBasePtr().getValueType(), 8611 TheSelect->getOperand(0), LLD->getBasePtr(), 8612 RLD->getBasePtr()); 8613 } else { // Otherwise SELECT_CC 8614 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 8615 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 8616 8617 if ((LLD->hasAnyUseOfValue(1) && 8618 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 8619 (RLD->hasAnyUseOfValue(1) && 8620 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 8621 return false; 8622 8623 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 8624 LLD->getBasePtr().getValueType(), 8625 TheSelect->getOperand(0), 8626 TheSelect->getOperand(1), 8627 LLD->getBasePtr(), RLD->getBasePtr(), 8628 TheSelect->getOperand(4)); 8629 } 8630 8631 SDValue Load; 8632 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 8633 Load = DAG.getLoad(TheSelect->getValueType(0), 8634 TheSelect->getDebugLoc(), 8635 // FIXME: Discards pointer info. 8636 LLD->getChain(), Addr, MachinePointerInfo(), 8637 LLD->isVolatile(), LLD->isNonTemporal(), 8638 LLD->isInvariant(), LLD->getAlignment()); 8639 } else { 8640 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 8641 RLD->getExtensionType() : LLD->getExtensionType(), 8642 TheSelect->getDebugLoc(), 8643 TheSelect->getValueType(0), 8644 // FIXME: Discards pointer info. 8645 LLD->getChain(), Addr, MachinePointerInfo(), 8646 LLD->getMemoryVT(), LLD->isVolatile(), 8647 LLD->isNonTemporal(), LLD->getAlignment()); 8648 } 8649 8650 // Users of the select now use the result of the load. 8651 CombineTo(TheSelect, Load); 8652 8653 // Users of the old loads now use the new load's chain. We know the 8654 // old-load value is dead now. 8655 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 8656 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 8657 return true; 8658 } 8659 8660 return false; 8661} 8662 8663/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 8664/// where 'cond' is the comparison specified by CC. 8665SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 8666 SDValue N2, SDValue N3, 8667 ISD::CondCode CC, bool NotExtCompare) { 8668 // (x ? y : y) -> y. 8669 if (N2 == N3) return N2; 8670 8671 EVT VT = N2.getValueType(); 8672 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 8673 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 8674 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 8675 8676 // Determine if the condition we're dealing with is constant 8677 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 8678 N0, N1, CC, DL, false); 8679 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 8680 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 8681 8682 // fold select_cc true, x, y -> x 8683 if (SCCC && !SCCC->isNullValue()) 8684 return N2; 8685 // fold select_cc false, x, y -> y 8686 if (SCCC && SCCC->isNullValue()) 8687 return N3; 8688 8689 // Check to see if we can simplify the select into an fabs node 8690 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 8691 // Allow either -0.0 or 0.0 8692 if (CFP->getValueAPF().isZero()) { 8693 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 8694 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 8695 N0 == N2 && N3.getOpcode() == ISD::FNEG && 8696 N2 == N3.getOperand(0)) 8697 return DAG.getNode(ISD::FABS, DL, VT, N0); 8698 8699 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 8700 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 8701 N0 == N3 && N2.getOpcode() == ISD::FNEG && 8702 N2.getOperand(0) == N3) 8703 return DAG.getNode(ISD::FABS, DL, VT, N3); 8704 } 8705 } 8706 8707 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 8708 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 8709 // in it. This is a win when the constant is not otherwise available because 8710 // it replaces two constant pool loads with one. We only do this if the FP 8711 // type is known to be legal, because if it isn't, then we are before legalize 8712 // types an we want the other legalization to happen first (e.g. to avoid 8713 // messing with soft float) and if the ConstantFP is not legal, because if 8714 // it is legal, we may not need to store the FP constant in a constant pool. 8715 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 8716 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 8717 if (TLI.isTypeLegal(N2.getValueType()) && 8718 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 8719 TargetLowering::Legal) && 8720 // If both constants have multiple uses, then we won't need to do an 8721 // extra load, they are likely around in registers for other users. 8722 (TV->hasOneUse() || FV->hasOneUse())) { 8723 Constant *Elts[] = { 8724 const_cast<ConstantFP*>(FV->getConstantFPValue()), 8725 const_cast<ConstantFP*>(TV->getConstantFPValue()) 8726 }; 8727 Type *FPTy = Elts[0]->getType(); 8728 const TargetData &TD = *TLI.getTargetData(); 8729 8730 // Create a ConstantArray of the two constants. 8731 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 8732 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 8733 TD.getPrefTypeAlignment(FPTy)); 8734 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8735 8736 // Get the offsets to the 0 and 1 element of the array so that we can 8737 // select between them. 8738 SDValue Zero = DAG.getIntPtrConstant(0); 8739 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 8740 SDValue One = DAG.getIntPtrConstant(EltSize); 8741 8742 SDValue Cond = DAG.getSetCC(DL, 8743 TLI.getSetCCResultType(N0.getValueType()), 8744 N0, N1, CC); 8745 AddToWorkList(Cond.getNode()); 8746 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 8747 Cond, One, Zero); 8748 AddToWorkList(CstOffset.getNode()); 8749 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 8750 CstOffset); 8751 AddToWorkList(CPIdx.getNode()); 8752 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 8753 MachinePointerInfo::getConstantPool(), false, 8754 false, false, Alignment); 8755 8756 } 8757 } 8758 8759 // Check to see if we can perform the "gzip trick", transforming 8760 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 8761 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 8762 (N1C->isNullValue() || // (a < 0) ? b : 0 8763 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 8764 EVT XType = N0.getValueType(); 8765 EVT AType = N2.getValueType(); 8766 if (XType.bitsGE(AType)) { 8767 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 8768 // single-bit constant. 8769 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 8770 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 8771 ShCtV = XType.getSizeInBits()-ShCtV-1; 8772 SDValue ShCt = DAG.getConstant(ShCtV, 8773 getShiftAmountTy(N0.getValueType())); 8774 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 8775 XType, N0, ShCt); 8776 AddToWorkList(Shift.getNode()); 8777 8778 if (XType.bitsGT(AType)) { 8779 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8780 AddToWorkList(Shift.getNode()); 8781 } 8782 8783 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8784 } 8785 8786 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 8787 XType, N0, 8788 DAG.getConstant(XType.getSizeInBits()-1, 8789 getShiftAmountTy(N0.getValueType()))); 8790 AddToWorkList(Shift.getNode()); 8791 8792 if (XType.bitsGT(AType)) { 8793 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8794 AddToWorkList(Shift.getNode()); 8795 } 8796 8797 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8798 } 8799 } 8800 8801 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 8802 // where y is has a single bit set. 8803 // A plaintext description would be, we can turn the SELECT_CC into an AND 8804 // when the condition can be materialized as an all-ones register. Any 8805 // single bit-test can be materialized as an all-ones register with 8806 // shift-left and shift-right-arith. 8807 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 8808 N0->getValueType(0) == VT && 8809 N1C && N1C->isNullValue() && 8810 N2C && N2C->isNullValue()) { 8811 SDValue AndLHS = N0->getOperand(0); 8812 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 8813 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 8814 // Shift the tested bit over the sign bit. 8815 APInt AndMask = ConstAndRHS->getAPIntValue(); 8816 SDValue ShlAmt = 8817 DAG.getConstant(AndMask.countLeadingZeros(), 8818 getShiftAmountTy(AndLHS.getValueType())); 8819 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 8820 8821 // Now arithmetic right shift it all the way over, so the result is either 8822 // all-ones, or zero. 8823 SDValue ShrAmt = 8824 DAG.getConstant(AndMask.getBitWidth()-1, 8825 getShiftAmountTy(Shl.getValueType())); 8826 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 8827 8828 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 8829 } 8830 } 8831 8832 // fold select C, 16, 0 -> shl C, 4 8833 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 8834 TLI.getBooleanContents(N0.getValueType().isVector()) == 8835 TargetLowering::ZeroOrOneBooleanContent) { 8836 8837 // If the caller doesn't want us to simplify this into a zext of a compare, 8838 // don't do it. 8839 if (NotExtCompare && N2C->getAPIntValue() == 1) 8840 return SDValue(); 8841 8842 // Get a SetCC of the condition 8843 // FIXME: Should probably make sure that setcc is legal if we ever have a 8844 // target where it isn't. 8845 SDValue Temp, SCC; 8846 // cast from setcc result type to select result type 8847 if (LegalTypes) { 8848 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 8849 N0, N1, CC); 8850 if (N2.getValueType().bitsLT(SCC.getValueType())) 8851 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 8852 else 8853 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8854 N2.getValueType(), SCC); 8855 } else { 8856 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 8857 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8858 N2.getValueType(), SCC); 8859 } 8860 8861 AddToWorkList(SCC.getNode()); 8862 AddToWorkList(Temp.getNode()); 8863 8864 if (N2C->getAPIntValue() == 1) 8865 return Temp; 8866 8867 // shl setcc result by log2 n2c 8868 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 8869 DAG.getConstant(N2C->getAPIntValue().logBase2(), 8870 getShiftAmountTy(Temp.getValueType()))); 8871 } 8872 8873 // Check to see if this is the equivalent of setcc 8874 // FIXME: Turn all of these into setcc if setcc if setcc is legal 8875 // otherwise, go ahead with the folds. 8876 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 8877 EVT XType = N0.getValueType(); 8878 if (!LegalOperations || 8879 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 8880 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 8881 if (Res.getValueType() != VT) 8882 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 8883 return Res; 8884 } 8885 8886 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 8887 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 8888 (!LegalOperations || 8889 TLI.isOperationLegal(ISD::CTLZ, XType))) { 8890 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 8891 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 8892 DAG.getConstant(Log2_32(XType.getSizeInBits()), 8893 getShiftAmountTy(Ctlz.getValueType()))); 8894 } 8895 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 8896 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 8897 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 8898 XType, DAG.getConstant(0, XType), N0); 8899 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 8900 return DAG.getNode(ISD::SRL, DL, XType, 8901 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 8902 DAG.getConstant(XType.getSizeInBits()-1, 8903 getShiftAmountTy(XType))); 8904 } 8905 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 8906 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 8907 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 8908 DAG.getConstant(XType.getSizeInBits()-1, 8909 getShiftAmountTy(N0.getValueType()))); 8910 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 8911 } 8912 } 8913 8914 // Check to see if this is an integer abs. 8915 // select_cc setg[te] X, 0, X, -X -> 8916 // select_cc setgt X, -1, X, -X -> 8917 // select_cc setl[te] X, 0, -X, X -> 8918 // select_cc setlt X, 1, -X, X -> 8919 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 8920 if (N1C) { 8921 ConstantSDNode *SubC = NULL; 8922 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8923 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 8924 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 8925 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 8926 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 8927 (N1C->isOne() && CC == ISD::SETLT)) && 8928 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 8929 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 8930 8931 EVT XType = N0.getValueType(); 8932 if (SubC && SubC->isNullValue() && XType.isInteger()) { 8933 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 8934 N0, 8935 DAG.getConstant(XType.getSizeInBits()-1, 8936 getShiftAmountTy(N0.getValueType()))); 8937 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 8938 XType, N0, Shift); 8939 AddToWorkList(Shift.getNode()); 8940 AddToWorkList(Add.getNode()); 8941 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 8942 } 8943 } 8944 8945 return SDValue(); 8946} 8947 8948/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8949SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8950 SDValue N1, ISD::CondCode Cond, 8951 DebugLoc DL, bool foldBooleans) { 8952 TargetLowering::DAGCombinerInfo 8953 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8954 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8955} 8956 8957/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8958/// return a DAG expression to select that will generate the same value by 8959/// multiplying by a magic number. See: 8960/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8961SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8962 std::vector<SDNode*> Built; 8963 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8964 8965 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8966 ii != ee; ++ii) 8967 AddToWorkList(*ii); 8968 return S; 8969} 8970 8971/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8972/// return a DAG expression to select that will generate the same value by 8973/// multiplying by a magic number. See: 8974/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8975SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8976 std::vector<SDNode*> Built; 8977 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8978 8979 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8980 ii != ee; ++ii) 8981 AddToWorkList(*ii); 8982 return S; 8983} 8984 8985/// FindBaseOffset - Return true if base is a frame index, which is known not 8986// to alias with anything but itself. Provides base object and offset as 8987// results. 8988static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8989 const GlobalValue *&GV, const void *&CV) { 8990 // Assume it is a primitive operation. 8991 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8992 8993 // If it's an adding a simple constant then integrate the offset. 8994 if (Base.getOpcode() == ISD::ADD) { 8995 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8996 Base = Base.getOperand(0); 8997 Offset += C->getZExtValue(); 8998 } 8999 } 9000 9001 // Return the underlying GlobalValue, and update the Offset. Return false 9002 // for GlobalAddressSDNode since the same GlobalAddress may be represented 9003 // by multiple nodes with different offsets. 9004 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 9005 GV = G->getGlobal(); 9006 Offset += G->getOffset(); 9007 return false; 9008 } 9009 9010 // Return the underlying Constant value, and update the Offset. Return false 9011 // for ConstantSDNodes since the same constant pool entry may be represented 9012 // by multiple nodes with different offsets. 9013 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 9014 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 9015 : (const void *)C->getConstVal(); 9016 Offset += C->getOffset(); 9017 return false; 9018 } 9019 // If it's any of the following then it can't alias with anything but itself. 9020 return isa<FrameIndexSDNode>(Base); 9021} 9022 9023/// isAlias - Return true if there is any possibility that the two addresses 9024/// overlap. 9025bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 9026 const Value *SrcValue1, int SrcValueOffset1, 9027 unsigned SrcValueAlign1, 9028 const MDNode *TBAAInfo1, 9029 SDValue Ptr2, int64_t Size2, 9030 const Value *SrcValue2, int SrcValueOffset2, 9031 unsigned SrcValueAlign2, 9032 const MDNode *TBAAInfo2) const { 9033 // If they are the same then they must be aliases. 9034 if (Ptr1 == Ptr2) return true; 9035 9036 // Gather base node and offset information. 9037 SDValue Base1, Base2; 9038 int64_t Offset1, Offset2; 9039 const GlobalValue *GV1, *GV2; 9040 const void *CV1, *CV2; 9041 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 9042 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 9043 9044 // If they have a same base address then check to see if they overlap. 9045 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 9046 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9047 9048 // It is possible for different frame indices to alias each other, mostly 9049 // when tail call optimization reuses return address slots for arguments. 9050 // To catch this case, look up the actual index of frame indices to compute 9051 // the real alias relationship. 9052 if (isFrameIndex1 && isFrameIndex2) { 9053 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9054 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 9055 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 9056 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9057 } 9058 9059 // Otherwise, if we know what the bases are, and they aren't identical, then 9060 // we know they cannot alias. 9061 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 9062 return false; 9063 9064 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 9065 // compared to the size and offset of the access, we may be able to prove they 9066 // do not alias. This check is conservative for now to catch cases created by 9067 // splitting vector types. 9068 if ((SrcValueAlign1 == SrcValueAlign2) && 9069 (SrcValueOffset1 != SrcValueOffset2) && 9070 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 9071 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 9072 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 9073 9074 // There is no overlap between these relatively aligned accesses of similar 9075 // size, return no alias. 9076 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 9077 return false; 9078 } 9079 9080 if (CombinerGlobalAA) { 9081 // Use alias analysis information. 9082 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 9083 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 9084 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 9085 AliasAnalysis::AliasResult AAResult = 9086 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 9087 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 9088 if (AAResult == AliasAnalysis::NoAlias) 9089 return false; 9090 } 9091 9092 // Otherwise we have to assume they alias. 9093 return true; 9094} 9095 9096/// FindAliasInfo - Extracts the relevant alias information from the memory 9097/// node. Returns true if the operand was a load. 9098bool DAGCombiner::FindAliasInfo(SDNode *N, 9099 SDValue &Ptr, int64_t &Size, 9100 const Value *&SrcValue, 9101 int &SrcValueOffset, 9102 unsigned &SrcValueAlign, 9103 const MDNode *&TBAAInfo) const { 9104 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 9105 9106 Ptr = LS->getBasePtr(); 9107 Size = LS->getMemoryVT().getSizeInBits() >> 3; 9108 SrcValue = LS->getSrcValue(); 9109 SrcValueOffset = LS->getSrcValueOffset(); 9110 SrcValueAlign = LS->getOriginalAlignment(); 9111 TBAAInfo = LS->getTBAAInfo(); 9112 return isa<LoadSDNode>(LS); 9113} 9114 9115/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 9116/// looking for aliasing nodes and adding them to the Aliases vector. 9117void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 9118 SmallVector<SDValue, 8> &Aliases) { 9119 SmallVector<SDValue, 8> Chains; // List of chains to visit. 9120 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 9121 9122 // Get alias information for node. 9123 SDValue Ptr; 9124 int64_t Size; 9125 const Value *SrcValue; 9126 int SrcValueOffset; 9127 unsigned SrcValueAlign; 9128 const MDNode *SrcTBAAInfo; 9129 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 9130 SrcValueAlign, SrcTBAAInfo); 9131 9132 // Starting off. 9133 Chains.push_back(OriginalChain); 9134 unsigned Depth = 0; 9135 9136 // Look at each chain and determine if it is an alias. If so, add it to the 9137 // aliases list. If not, then continue up the chain looking for the next 9138 // candidate. 9139 while (!Chains.empty()) { 9140 SDValue Chain = Chains.back(); 9141 Chains.pop_back(); 9142 9143 // For TokenFactor nodes, look at each operand and only continue up the 9144 // chain until we find two aliases. If we've seen two aliases, assume we'll 9145 // find more and revert to original chain since the xform is unlikely to be 9146 // profitable. 9147 // 9148 // FIXME: The depth check could be made to return the last non-aliasing 9149 // chain we found before we hit a tokenfactor rather than the original 9150 // chain. 9151 if (Depth > 6 || Aliases.size() == 2) { 9152 Aliases.clear(); 9153 Aliases.push_back(OriginalChain); 9154 break; 9155 } 9156 9157 // Don't bother if we've been before. 9158 if (!Visited.insert(Chain.getNode())) 9159 continue; 9160 9161 switch (Chain.getOpcode()) { 9162 case ISD::EntryToken: 9163 // Entry token is ideal chain operand, but handled in FindBetterChain. 9164 break; 9165 9166 case ISD::LOAD: 9167 case ISD::STORE: { 9168 // Get alias information for Chain. 9169 SDValue OpPtr; 9170 int64_t OpSize; 9171 const Value *OpSrcValue; 9172 int OpSrcValueOffset; 9173 unsigned OpSrcValueAlign; 9174 const MDNode *OpSrcTBAAInfo; 9175 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 9176 OpSrcValue, OpSrcValueOffset, 9177 OpSrcValueAlign, 9178 OpSrcTBAAInfo); 9179 9180 // If chain is alias then stop here. 9181 if (!(IsLoad && IsOpLoad) && 9182 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 9183 SrcTBAAInfo, 9184 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 9185 OpSrcValueAlign, OpSrcTBAAInfo)) { 9186 Aliases.push_back(Chain); 9187 } else { 9188 // Look further up the chain. 9189 Chains.push_back(Chain.getOperand(0)); 9190 ++Depth; 9191 } 9192 break; 9193 } 9194 9195 case ISD::TokenFactor: 9196 // We have to check each of the operands of the token factor for "small" 9197 // token factors, so we queue them up. Adding the operands to the queue 9198 // (stack) in reverse order maintains the original order and increases the 9199 // likelihood that getNode will find a matching token factor (CSE.) 9200 if (Chain.getNumOperands() > 16) { 9201 Aliases.push_back(Chain); 9202 break; 9203 } 9204 for (unsigned n = Chain.getNumOperands(); n;) 9205 Chains.push_back(Chain.getOperand(--n)); 9206 ++Depth; 9207 break; 9208 9209 default: 9210 // For all other instructions we will just have to take what we can get. 9211 Aliases.push_back(Chain); 9212 break; 9213 } 9214 } 9215} 9216 9217/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 9218/// for a better chain (aliasing node.) 9219SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 9220 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 9221 9222 // Accumulate all the aliases to this node. 9223 GatherAllAliases(N, OldChain, Aliases); 9224 9225 // If no operands then chain to entry token. 9226 if (Aliases.size() == 0) 9227 return DAG.getEntryNode(); 9228 9229 // If a single operand then chain to it. We don't need to revisit it. 9230 if (Aliases.size() == 1) 9231 return Aliases[0]; 9232 9233 // Construct a custom tailored token factor. 9234 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 9235 &Aliases[0], Aliases.size()); 9236} 9237 9238// SelectionDAG::Combine - This is the entry point for the file. 9239// 9240void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 9241 CodeGenOpt::Level OptLevel) { 9242 /// run - This is the main entry point to this class. 9243 /// 9244 DAGCombiner(*this, AA, OptLevel).Run(Level); 9245} 9246